1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 13#include <dt-bindings/power/mt8195-power.h> 14 15/ { 16 compatible = "mediatek,mt8195"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a55"; 28 reg = <0x000>; 29 enable-method = "psci"; 30 performance-domains = <&performance 0>; 31 clock-frequency = <1701000000>; 32 capacity-dmips-mhz = <578>; 33 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 34 next-level-cache = <&l2_0>; 35 #cooling-cells = <2>; 36 }; 37 38 cpu1: cpu@100 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a55"; 41 reg = <0x100>; 42 enable-method = "psci"; 43 performance-domains = <&performance 0>; 44 clock-frequency = <1701000000>; 45 capacity-dmips-mhz = <578>; 46 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 47 next-level-cache = <&l2_0>; 48 #cooling-cells = <2>; 49 }; 50 51 cpu2: cpu@200 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a55"; 54 reg = <0x200>; 55 enable-method = "psci"; 56 performance-domains = <&performance 0>; 57 clock-frequency = <1701000000>; 58 capacity-dmips-mhz = <578>; 59 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 60 next-level-cache = <&l2_0>; 61 #cooling-cells = <2>; 62 }; 63 64 cpu3: cpu@300 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a55"; 67 reg = <0x300>; 68 enable-method = "psci"; 69 performance-domains = <&performance 0>; 70 clock-frequency = <1701000000>; 71 capacity-dmips-mhz = <578>; 72 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 73 next-level-cache = <&l2_0>; 74 #cooling-cells = <2>; 75 }; 76 77 cpu4: cpu@400 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a78"; 80 reg = <0x400>; 81 enable-method = "psci"; 82 performance-domains = <&performance 1>; 83 clock-frequency = <2171000000>; 84 capacity-dmips-mhz = <1024>; 85 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 86 next-level-cache = <&l2_1>; 87 #cooling-cells = <2>; 88 }; 89 90 cpu5: cpu@500 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a78"; 93 reg = <0x500>; 94 enable-method = "psci"; 95 performance-domains = <&performance 1>; 96 clock-frequency = <2171000000>; 97 capacity-dmips-mhz = <1024>; 98 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 99 next-level-cache = <&l2_1>; 100 #cooling-cells = <2>; 101 }; 102 103 cpu6: cpu@600 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a78"; 106 reg = <0x600>; 107 enable-method = "psci"; 108 performance-domains = <&performance 1>; 109 clock-frequency = <2171000000>; 110 capacity-dmips-mhz = <1024>; 111 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 112 next-level-cache = <&l2_1>; 113 #cooling-cells = <2>; 114 }; 115 116 cpu7: cpu@700 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a78"; 119 reg = <0x700>; 120 enable-method = "psci"; 121 performance-domains = <&performance 1>; 122 clock-frequency = <2171000000>; 123 capacity-dmips-mhz = <1024>; 124 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 125 next-level-cache = <&l2_1>; 126 #cooling-cells = <2>; 127 }; 128 129 cpu-map { 130 cluster0 { 131 core0 { 132 cpu = <&cpu0>; 133 }; 134 135 core1 { 136 cpu = <&cpu1>; 137 }; 138 139 core2 { 140 cpu = <&cpu2>; 141 }; 142 143 core3 { 144 cpu = <&cpu3>; 145 }; 146 }; 147 148 cluster1 { 149 core0 { 150 cpu = <&cpu4>; 151 }; 152 153 core1 { 154 cpu = <&cpu5>; 155 }; 156 157 core2 { 158 cpu = <&cpu6>; 159 }; 160 161 core3 { 162 cpu = <&cpu7>; 163 }; 164 }; 165 }; 166 167 idle-states { 168 entry-method = "psci"; 169 170 cpu_off_l: cpu-off-l { 171 compatible = "arm,idle-state"; 172 arm,psci-suspend-param = <0x00010001>; 173 local-timer-stop; 174 entry-latency-us = <50>; 175 exit-latency-us = <95>; 176 min-residency-us = <580>; 177 }; 178 179 cpu_off_b: cpu-off-b { 180 compatible = "arm,idle-state"; 181 arm,psci-suspend-param = <0x00010001>; 182 local-timer-stop; 183 entry-latency-us = <45>; 184 exit-latency-us = <140>; 185 min-residency-us = <740>; 186 }; 187 188 cluster_off_l: cluster-off-l { 189 compatible = "arm,idle-state"; 190 arm,psci-suspend-param = <0x01010002>; 191 local-timer-stop; 192 entry-latency-us = <55>; 193 exit-latency-us = <155>; 194 min-residency-us = <840>; 195 }; 196 197 cluster_off_b: cluster-off-b { 198 compatible = "arm,idle-state"; 199 arm,psci-suspend-param = <0x01010002>; 200 local-timer-stop; 201 entry-latency-us = <50>; 202 exit-latency-us = <200>; 203 min-residency-us = <1000>; 204 }; 205 }; 206 207 l2_0: l2-cache0 { 208 compatible = "cache"; 209 next-level-cache = <&l3_0>; 210 }; 211 212 l2_1: l2-cache1 { 213 compatible = "cache"; 214 next-level-cache = <&l3_0>; 215 }; 216 217 l3_0: l3-cache { 218 compatible = "cache"; 219 }; 220 }; 221 222 dsu-pmu { 223 compatible = "arm,dsu-pmu"; 224 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 225 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 226 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 227 }; 228 229 clk26m: oscillator-26m { 230 compatible = "fixed-clock"; 231 #clock-cells = <0>; 232 clock-frequency = <26000000>; 233 clock-output-names = "clk26m"; 234 }; 235 236 clk32k: oscillator-32k { 237 compatible = "fixed-clock"; 238 #clock-cells = <0>; 239 clock-frequency = <32768>; 240 clock-output-names = "clk32k"; 241 }; 242 243 performance: performance-controller@11bc10 { 244 compatible = "mediatek,cpufreq-hw"; 245 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 246 #performance-domain-cells = <1>; 247 }; 248 249 pmu-a55 { 250 compatible = "arm,cortex-a55-pmu"; 251 interrupt-parent = <&gic>; 252 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 253 }; 254 255 pmu-a78 { 256 compatible = "arm,cortex-a78-pmu"; 257 interrupt-parent = <&gic>; 258 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 259 }; 260 261 psci { 262 compatible = "arm,psci-1.0"; 263 method = "smc"; 264 }; 265 266 timer: timer { 267 compatible = "arm,armv8-timer"; 268 interrupt-parent = <&gic>; 269 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 270 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 271 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 272 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 273 }; 274 275 soc { 276 #address-cells = <2>; 277 #size-cells = <2>; 278 compatible = "simple-bus"; 279 ranges; 280 281 gic: interrupt-controller@c000000 { 282 compatible = "arm,gic-v3"; 283 #interrupt-cells = <4>; 284 #redistributor-regions = <1>; 285 interrupt-parent = <&gic>; 286 interrupt-controller; 287 reg = <0 0x0c000000 0 0x40000>, 288 <0 0x0c040000 0 0x200000>; 289 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 290 291 ppi-partitions { 292 ppi_cluster0: interrupt-partition-0 { 293 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 294 }; 295 296 ppi_cluster1: interrupt-partition-1 { 297 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 298 }; 299 }; 300 }; 301 302 topckgen: syscon@10000000 { 303 compatible = "mediatek,mt8195-topckgen", "syscon"; 304 reg = <0 0x10000000 0 0x1000>; 305 #clock-cells = <1>; 306 }; 307 308 infracfg_ao: syscon@10001000 { 309 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; 310 reg = <0 0x10001000 0 0x1000>; 311 #clock-cells = <1>; 312 #reset-cells = <1>; 313 }; 314 315 pericfg: syscon@10003000 { 316 compatible = "mediatek,mt8195-pericfg", "syscon"; 317 reg = <0 0x10003000 0 0x1000>; 318 #clock-cells = <1>; 319 }; 320 321 pio: pinctrl@10005000 { 322 compatible = "mediatek,mt8195-pinctrl"; 323 reg = <0 0x10005000 0 0x1000>, 324 <0 0x11d10000 0 0x1000>, 325 <0 0x11d30000 0 0x1000>, 326 <0 0x11d40000 0 0x1000>, 327 <0 0x11e20000 0 0x1000>, 328 <0 0x11eb0000 0 0x1000>, 329 <0 0x11f40000 0 0x1000>, 330 <0 0x1000b000 0 0x1000>; 331 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 332 "iocfg_br", "iocfg_lm", "iocfg_rb", 333 "iocfg_tl", "eint"; 334 gpio-controller; 335 #gpio-cells = <2>; 336 gpio-ranges = <&pio 0 0 144>; 337 interrupt-controller; 338 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 339 #interrupt-cells = <2>; 340 }; 341 342 scpsys: syscon@10006000 { 343 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; 344 reg = <0 0x10006000 0 0x1000>; 345 346 /* System Power Manager */ 347 spm: power-controller { 348 compatible = "mediatek,mt8195-power-controller"; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 #power-domain-cells = <1>; 352 353 /* power domain of the SoC */ 354 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { 355 reg = <MT8195_POWER_DOMAIN_MFG0>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 #power-domain-cells = <1>; 359 360 power-domain@MT8195_POWER_DOMAIN_MFG1 { 361 reg = <MT8195_POWER_DOMAIN_MFG1>; 362 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>; 363 clock-names = "mfg"; 364 mediatek,infracfg = <&infracfg_ao>; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 #power-domain-cells = <1>; 368 369 power-domain@MT8195_POWER_DOMAIN_MFG2 { 370 reg = <MT8195_POWER_DOMAIN_MFG2>; 371 #power-domain-cells = <0>; 372 }; 373 374 power-domain@MT8195_POWER_DOMAIN_MFG3 { 375 reg = <MT8195_POWER_DOMAIN_MFG3>; 376 #power-domain-cells = <0>; 377 }; 378 379 power-domain@MT8195_POWER_DOMAIN_MFG4 { 380 reg = <MT8195_POWER_DOMAIN_MFG4>; 381 #power-domain-cells = <0>; 382 }; 383 384 power-domain@MT8195_POWER_DOMAIN_MFG5 { 385 reg = <MT8195_POWER_DOMAIN_MFG5>; 386 #power-domain-cells = <0>; 387 }; 388 389 power-domain@MT8195_POWER_DOMAIN_MFG6 { 390 reg = <MT8195_POWER_DOMAIN_MFG6>; 391 #power-domain-cells = <0>; 392 }; 393 }; 394 }; 395 396 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { 397 reg = <MT8195_POWER_DOMAIN_VPPSYS0>; 398 clocks = <&topckgen CLK_TOP_VPP>, 399 <&topckgen CLK_TOP_CAM>, 400 <&topckgen CLK_TOP_CCU>, 401 <&topckgen CLK_TOP_IMG>, 402 <&topckgen CLK_TOP_VENC>, 403 <&topckgen CLK_TOP_VDEC>, 404 <&topckgen CLK_TOP_WPE_VPP>, 405 <&topckgen CLK_TOP_CFG_VPP0>, 406 <&vppsys0 CLK_VPP0_SMI_COMMON>, 407 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, 408 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, 409 <&vppsys0 CLK_VPP0_GALS_VENCSYS>, 410 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, 411 <&vppsys0 CLK_VPP0_GALS_INFRA>, 412 <&vppsys0 CLK_VPP0_GALS_CAMSYS>, 413 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, 414 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, 415 <&vppsys0 CLK_VPP0_SMI_REORDER>, 416 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 417 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 418 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 419 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 420 <&vppsys0 CLK_VPP0_SMI_RSI>, 421 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 422 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 423 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 424 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 425 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", 426 "vppsys4", "vppsys5", "vppsys6", "vppsys7", 427 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", 428 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", 429 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", 430 "vppsys0-12", "vppsys0-13", "vppsys0-14", 431 "vppsys0-15", "vppsys0-16", "vppsys0-17", 432 "vppsys0-18"; 433 mediatek,infracfg = <&infracfg_ao>; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 #power-domain-cells = <1>; 437 438 power-domain@MT8195_POWER_DOMAIN_VDEC1 { 439 reg = <MT8195_POWER_DOMAIN_VDEC1>; 440 clocks = <&vdecsys CLK_VDEC_LARB1>; 441 clock-names = "vdec1-0"; 442 mediatek,infracfg = <&infracfg_ao>; 443 #power-domain-cells = <0>; 444 }; 445 446 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { 447 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; 448 mediatek,infracfg = <&infracfg_ao>; 449 #power-domain-cells = <0>; 450 }; 451 452 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { 453 reg = <MT8195_POWER_DOMAIN_VDOSYS0>; 454 clocks = <&topckgen CLK_TOP_CFG_VDO0>, 455 <&vdosys0 CLK_VDO0_SMI_GALS>, 456 <&vdosys0 CLK_VDO0_SMI_COMMON>, 457 <&vdosys0 CLK_VDO0_SMI_EMI>, 458 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 459 <&vdosys0 CLK_VDO0_SMI_LARB>, 460 <&vdosys0 CLK_VDO0_SMI_RSI>; 461 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", 462 "vdosys0-2", "vdosys0-3", 463 "vdosys0-4", "vdosys0-5"; 464 mediatek,infracfg = <&infracfg_ao>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 #power-domain-cells = <1>; 468 469 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { 470 reg = <MT8195_POWER_DOMAIN_VPPSYS1>; 471 clocks = <&topckgen CLK_TOP_CFG_VPP1>, 472 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 473 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; 474 clock-names = "vppsys1", "vppsys1-0", 475 "vppsys1-1"; 476 mediatek,infracfg = <&infracfg_ao>; 477 #power-domain-cells = <0>; 478 }; 479 480 power-domain@MT8195_POWER_DOMAIN_WPESYS { 481 reg = <MT8195_POWER_DOMAIN_WPESYS>; 482 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 483 <&wpesys CLK_WPE_SMI_LARB8>, 484 <&wpesys CLK_WPE_SMI_LARB7_P>, 485 <&wpesys CLK_WPE_SMI_LARB8_P>; 486 clock-names = "wepsys-0", "wepsys-1", "wepsys-2", 487 "wepsys-3"; 488 mediatek,infracfg = <&infracfg_ao>; 489 #power-domain-cells = <0>; 490 }; 491 492 power-domain@MT8195_POWER_DOMAIN_VDEC0 { 493 reg = <MT8195_POWER_DOMAIN_VDEC0>; 494 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 495 clock-names = "vdec0-0"; 496 mediatek,infracfg = <&infracfg_ao>; 497 #power-domain-cells = <0>; 498 }; 499 500 power-domain@MT8195_POWER_DOMAIN_VDEC2 { 501 reg = <MT8195_POWER_DOMAIN_VDEC2>; 502 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 503 clock-names = "vdec2-0"; 504 mediatek,infracfg = <&infracfg_ao>; 505 #power-domain-cells = <0>; 506 }; 507 508 power-domain@MT8195_POWER_DOMAIN_VENC { 509 reg = <MT8195_POWER_DOMAIN_VENC>; 510 mediatek,infracfg = <&infracfg_ao>; 511 #power-domain-cells = <0>; 512 }; 513 514 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { 515 reg = <MT8195_POWER_DOMAIN_VDOSYS1>; 516 clocks = <&topckgen CLK_TOP_CFG_VDO1>, 517 <&vdosys1 CLK_VDO1_SMI_LARB2>, 518 <&vdosys1 CLK_VDO1_SMI_LARB3>, 519 <&vdosys1 CLK_VDO1_GALS>; 520 clock-names = "vdosys1", "vdosys1-0", 521 "vdosys1-1", "vdosys1-2"; 522 mediatek,infracfg = <&infracfg_ao>; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 #power-domain-cells = <1>; 526 527 power-domain@MT8195_POWER_DOMAIN_DP_TX { 528 reg = <MT8195_POWER_DOMAIN_DP_TX>; 529 mediatek,infracfg = <&infracfg_ao>; 530 #power-domain-cells = <0>; 531 }; 532 533 power-domain@MT8195_POWER_DOMAIN_EPD_TX { 534 reg = <MT8195_POWER_DOMAIN_EPD_TX>; 535 mediatek,infracfg = <&infracfg_ao>; 536 #power-domain-cells = <0>; 537 }; 538 539 power-domain@MT8195_POWER_DOMAIN_HDMI_TX { 540 reg = <MT8195_POWER_DOMAIN_HDMI_TX>; 541 clocks = <&topckgen CLK_TOP_HDMI_APB>; 542 clock-names = "hdmi_tx"; 543 #power-domain-cells = <0>; 544 }; 545 }; 546 547 power-domain@MT8195_POWER_DOMAIN_IMG { 548 reg = <MT8195_POWER_DOMAIN_IMG>; 549 clocks = <&imgsys CLK_IMG_LARB9>, 550 <&imgsys CLK_IMG_GALS>; 551 clock-names = "img-0", "img-1"; 552 mediatek,infracfg = <&infracfg_ao>; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 #power-domain-cells = <1>; 556 557 power-domain@MT8195_POWER_DOMAIN_DIP { 558 reg = <MT8195_POWER_DOMAIN_DIP>; 559 #power-domain-cells = <0>; 560 }; 561 562 power-domain@MT8195_POWER_DOMAIN_IPE { 563 reg = <MT8195_POWER_DOMAIN_IPE>; 564 clocks = <&topckgen CLK_TOP_IPE>, 565 <&imgsys CLK_IMG_IPE>, 566 <&ipesys CLK_IPE_SMI_LARB12>; 567 clock-names = "ipe", "ipe-0", "ipe-1"; 568 mediatek,infracfg = <&infracfg_ao>; 569 #power-domain-cells = <0>; 570 }; 571 }; 572 573 power-domain@MT8195_POWER_DOMAIN_CAM { 574 reg = <MT8195_POWER_DOMAIN_CAM>; 575 clocks = <&camsys CLK_CAM_LARB13>, 576 <&camsys CLK_CAM_LARB14>, 577 <&camsys CLK_CAM_CAM2MM0_GALS>, 578 <&camsys CLK_CAM_CAM2MM1_GALS>, 579 <&camsys CLK_CAM_CAM2SYS_GALS>; 580 clock-names = "cam-0", "cam-1", "cam-2", "cam-3", 581 "cam-4"; 582 mediatek,infracfg = <&infracfg_ao>; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 #power-domain-cells = <1>; 586 587 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { 588 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; 589 #power-domain-cells = <0>; 590 }; 591 592 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { 593 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; 594 #power-domain-cells = <0>; 595 }; 596 597 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { 598 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; 599 #power-domain-cells = <0>; 600 }; 601 }; 602 }; 603 }; 604 605 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { 606 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 607 mediatek,infracfg = <&infracfg_ao>; 608 #power-domain-cells = <0>; 609 }; 610 611 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { 612 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 613 mediatek,infracfg = <&infracfg_ao>; 614 #power-domain-cells = <0>; 615 }; 616 617 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { 618 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; 619 #power-domain-cells = <0>; 620 }; 621 622 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { 623 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 624 #power-domain-cells = <0>; 625 }; 626 627 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { 628 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; 629 clocks = <&topckgen CLK_TOP_SENINF>, 630 <&topckgen CLK_TOP_SENINF2>; 631 clock-names = "csi_rx_top", "csi_rx_top1"; 632 #power-domain-cells = <0>; 633 }; 634 635 power-domain@MT8195_POWER_DOMAIN_ETHER { 636 reg = <MT8195_POWER_DOMAIN_ETHER>; 637 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 638 clock-names = "ether"; 639 #power-domain-cells = <0>; 640 }; 641 642 power-domain@MT8195_POWER_DOMAIN_ADSP { 643 reg = <MT8195_POWER_DOMAIN_ADSP>; 644 clocks = <&topckgen CLK_TOP_ADSP>, 645 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 646 clock-names = "adsp", "adsp1"; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 mediatek,infracfg = <&infracfg_ao>; 650 #power-domain-cells = <1>; 651 652 power-domain@MT8195_POWER_DOMAIN_AUDIO { 653 reg = <MT8195_POWER_DOMAIN_AUDIO>; 654 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 655 <&topckgen CLK_TOP_AUD_INTBUS>, 656 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 657 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; 658 clock-names = "audio", "audio1", "audio2", 659 "audio3"; 660 mediatek,infracfg = <&infracfg_ao>; 661 #power-domain-cells = <0>; 662 }; 663 }; 664 }; 665 }; 666 667 watchdog: watchdog@10007000 { 668 compatible = "mediatek,mt8195-wdt", 669 "mediatek,mt6589-wdt"; 670 mediatek,disable-extrst; 671 reg = <0 0x10007000 0 0x100>; 672 }; 673 674 apmixedsys: syscon@1000c000 { 675 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 676 reg = <0 0x1000c000 0 0x1000>; 677 #clock-cells = <1>; 678 }; 679 680 systimer: timer@10017000 { 681 compatible = "mediatek,mt8195-timer", 682 "mediatek,mt6765-timer"; 683 reg = <0 0x10017000 0 0x1000>; 684 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 685 clocks = <&topckgen CLK_TOP_CLK26M_D2>; 686 }; 687 688 pwrap: pwrap@10024000 { 689 compatible = "mediatek,mt8195-pwrap", "syscon"; 690 reg = <0 0x10024000 0 0x1000>; 691 reg-names = "pwrap"; 692 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 693 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 694 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 695 clock-names = "spi", "wrap"; 696 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 697 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 698 }; 699 700 scp_adsp: clock-controller@10720000 { 701 compatible = "mediatek,mt8195-scp_adsp"; 702 reg = <0 0x10720000 0 0x1000>; 703 #clock-cells = <1>; 704 }; 705 706 uart0: serial@11001100 { 707 compatible = "mediatek,mt8195-uart", 708 "mediatek,mt6577-uart"; 709 reg = <0 0x11001100 0 0x100>; 710 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 711 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 712 clock-names = "baud", "bus"; 713 status = "disabled"; 714 }; 715 716 uart1: serial@11001200 { 717 compatible = "mediatek,mt8195-uart", 718 "mediatek,mt6577-uart"; 719 reg = <0 0x11001200 0 0x100>; 720 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 721 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 722 clock-names = "baud", "bus"; 723 status = "disabled"; 724 }; 725 726 uart2: serial@11001300 { 727 compatible = "mediatek,mt8195-uart", 728 "mediatek,mt6577-uart"; 729 reg = <0 0x11001300 0 0x100>; 730 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 731 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 732 clock-names = "baud", "bus"; 733 status = "disabled"; 734 }; 735 736 uart3: serial@11001400 { 737 compatible = "mediatek,mt8195-uart", 738 "mediatek,mt6577-uart"; 739 reg = <0 0x11001400 0 0x100>; 740 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 741 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 742 clock-names = "baud", "bus"; 743 status = "disabled"; 744 }; 745 746 uart4: serial@11001500 { 747 compatible = "mediatek,mt8195-uart", 748 "mediatek,mt6577-uart"; 749 reg = <0 0x11001500 0 0x100>; 750 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 751 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 752 clock-names = "baud", "bus"; 753 status = "disabled"; 754 }; 755 756 uart5: serial@11001600 { 757 compatible = "mediatek,mt8195-uart", 758 "mediatek,mt6577-uart"; 759 reg = <0 0x11001600 0 0x100>; 760 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 761 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 762 clock-names = "baud", "bus"; 763 status = "disabled"; 764 }; 765 766 auxadc: auxadc@11002000 { 767 compatible = "mediatek,mt8195-auxadc", 768 "mediatek,mt8173-auxadc"; 769 reg = <0 0x11002000 0 0x1000>; 770 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 771 clock-names = "main"; 772 #io-channel-cells = <1>; 773 status = "disabled"; 774 }; 775 776 pericfg_ao: syscon@11003000 { 777 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 778 reg = <0 0x11003000 0 0x1000>; 779 #clock-cells = <1>; 780 }; 781 782 spi0: spi@1100a000 { 783 compatible = "mediatek,mt8195-spi", 784 "mediatek,mt6765-spi"; 785 #address-cells = <1>; 786 #size-cells = <0>; 787 reg = <0 0x1100a000 0 0x1000>; 788 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 789 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 790 <&topckgen CLK_TOP_SPI>, 791 <&infracfg_ao CLK_INFRA_AO_SPI0>; 792 clock-names = "parent-clk", "sel-clk", "spi-clk"; 793 status = "disabled"; 794 }; 795 796 spi1: spi@11010000 { 797 compatible = "mediatek,mt8195-spi", 798 "mediatek,mt6765-spi"; 799 #address-cells = <1>; 800 #size-cells = <0>; 801 reg = <0 0x11010000 0 0x1000>; 802 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 803 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 804 <&topckgen CLK_TOP_SPI>, 805 <&infracfg_ao CLK_INFRA_AO_SPI1>; 806 clock-names = "parent-clk", "sel-clk", "spi-clk"; 807 status = "disabled"; 808 }; 809 810 spi2: spi@11012000 { 811 compatible = "mediatek,mt8195-spi", 812 "mediatek,mt6765-spi"; 813 #address-cells = <1>; 814 #size-cells = <0>; 815 reg = <0 0x11012000 0 0x1000>; 816 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 817 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 818 <&topckgen CLK_TOP_SPI>, 819 <&infracfg_ao CLK_INFRA_AO_SPI2>; 820 clock-names = "parent-clk", "sel-clk", "spi-clk"; 821 status = "disabled"; 822 }; 823 824 spi3: spi@11013000 { 825 compatible = "mediatek,mt8195-spi", 826 "mediatek,mt6765-spi"; 827 #address-cells = <1>; 828 #size-cells = <0>; 829 reg = <0 0x11013000 0 0x1000>; 830 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 831 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 832 <&topckgen CLK_TOP_SPI>, 833 <&infracfg_ao CLK_INFRA_AO_SPI3>; 834 clock-names = "parent-clk", "sel-clk", "spi-clk"; 835 status = "disabled"; 836 }; 837 838 spi4: spi@11018000 { 839 compatible = "mediatek,mt8195-spi", 840 "mediatek,mt6765-spi"; 841 #address-cells = <1>; 842 #size-cells = <0>; 843 reg = <0 0x11018000 0 0x1000>; 844 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 845 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 846 <&topckgen CLK_TOP_SPI>, 847 <&infracfg_ao CLK_INFRA_AO_SPI4>; 848 clock-names = "parent-clk", "sel-clk", "spi-clk"; 849 status = "disabled"; 850 }; 851 852 spi5: spi@11019000 { 853 compatible = "mediatek,mt8195-spi", 854 "mediatek,mt6765-spi"; 855 #address-cells = <1>; 856 #size-cells = <0>; 857 reg = <0 0x11019000 0 0x1000>; 858 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 859 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 860 <&topckgen CLK_TOP_SPI>, 861 <&infracfg_ao CLK_INFRA_AO_SPI5>; 862 clock-names = "parent-clk", "sel-clk", "spi-clk"; 863 status = "disabled"; 864 }; 865 866 spis0: spi@1101d000 { 867 compatible = "mediatek,mt8195-spi-slave"; 868 reg = <0 0x1101d000 0 0x1000>; 869 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 870 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 871 clock-names = "spi"; 872 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 873 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 874 status = "disabled"; 875 }; 876 877 spis1: spi@1101e000 { 878 compatible = "mediatek,mt8195-spi-slave"; 879 reg = <0 0x1101e000 0 0x1000>; 880 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 881 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 882 clock-names = "spi"; 883 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 884 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 885 status = "disabled"; 886 }; 887 888 xhci0: usb@11200000 { 889 compatible = "mediatek,mt8195-xhci", 890 "mediatek,mtk-xhci"; 891 reg = <0 0x11200000 0 0x1000>, 892 <0 0x11203e00 0 0x0100>; 893 reg-names = "mac", "ippc"; 894 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 895 phys = <&u2port0 PHY_TYPE_USB2>, 896 <&u3port0 PHY_TYPE_USB3>; 897 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 898 <&topckgen CLK_TOP_SSUSB_XHCI>; 899 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 900 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 901 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 902 <&topckgen CLK_TOP_SSUSB_REF>, 903 <&apmixedsys CLK_APMIXED_USB1PLL>, 904 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 905 clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck"; 906 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 907 wakeup-source; 908 status = "disabled"; 909 }; 910 911 mmc0: mmc@11230000 { 912 compatible = "mediatek,mt8195-mmc", 913 "mediatek,mt8183-mmc"; 914 reg = <0 0x11230000 0 0x10000>, 915 <0 0x11f50000 0 0x1000>; 916 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 917 clocks = <&topckgen CLK_TOP_MSDC50_0>, 918 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 919 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 920 clock-names = "source", "hclk", "source_cg"; 921 status = "disabled"; 922 }; 923 924 mmc1: mmc@11240000 { 925 compatible = "mediatek,mt8195-mmc", 926 "mediatek,mt8183-mmc"; 927 reg = <0 0x11240000 0 0x1000>, 928 <0 0x11c70000 0 0x1000>; 929 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 930 clocks = <&topckgen CLK_TOP_MSDC30_1>, 931 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 932 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 933 clock-names = "source", "hclk", "source_cg"; 934 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 935 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 936 status = "disabled"; 937 }; 938 939 mmc2: mmc@11250000 { 940 compatible = "mediatek,mt8195-mmc", 941 "mediatek,mt8183-mmc"; 942 reg = <0 0x11250000 0 0x1000>, 943 <0 0x11e60000 0 0x1000>; 944 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 945 clocks = <&topckgen CLK_TOP_MSDC30_2>, 946 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 947 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 948 clock-names = "source", "hclk", "source_cg"; 949 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 950 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 951 status = "disabled"; 952 }; 953 954 xhci1: usb@11290000 { 955 compatible = "mediatek,mt8195-xhci", 956 "mediatek,mtk-xhci"; 957 reg = <0 0x11290000 0 0x1000>, 958 <0 0x11293e00 0 0x0100>; 959 reg-names = "mac", "ippc"; 960 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 961 phys = <&u2port1 PHY_TYPE_USB2>; 962 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 963 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 964 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 965 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 966 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 967 <&topckgen CLK_TOP_SSUSB_P1_REF>, 968 <&apmixedsys CLK_APMIXED_USB1PLL>, 969 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 970 clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck"; 971 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 972 wakeup-source; 973 status = "disabled"; 974 }; 975 976 xhci2: usb@112a0000 { 977 compatible = "mediatek,mt8195-xhci", 978 "mediatek,mtk-xhci"; 979 reg = <0 0x112a0000 0 0x1000>, 980 <0 0x112a3e00 0 0x0100>; 981 reg-names = "mac", "ippc"; 982 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 983 phys = <&u2port2 PHY_TYPE_USB2>; 984 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, 985 <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 986 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 987 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 988 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 989 <&topckgen CLK_TOP_SSUSB_P2_REF>, 990 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 991 clock-names = "sys_ck", "ref_ck", "xhci_ck"; 992 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 993 wakeup-source; 994 status = "disabled"; 995 }; 996 997 xhci3: usb@112b0000 { 998 compatible = "mediatek,mt8195-xhci", 999 "mediatek,mtk-xhci"; 1000 reg = <0 0x112b0000 0 0x1000>, 1001 <0 0x112b3e00 0 0x0100>; 1002 reg-names = "mac", "ippc"; 1003 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1004 phys = <&u2port3 PHY_TYPE_USB2>; 1005 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, 1006 <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1007 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1008 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1009 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1010 <&topckgen CLK_TOP_SSUSB_P3_REF>, 1011 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1012 clock-names = "sys_ck", "ref_ck", "xhci_ck"; 1013 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 1014 wakeup-source; 1015 status = "disabled"; 1016 }; 1017 1018 nor_flash: spi@1132c000 { 1019 compatible = "mediatek,mt8195-nor", 1020 "mediatek,mt8173-nor"; 1021 reg = <0 0x1132c000 0 0x1000>; 1022 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1023 clocks = <&topckgen CLK_TOP_SPINOR>, 1024 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 1025 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1026 clock-names = "spi", "sf", "axi"; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 status = "disabled"; 1030 }; 1031 1032 efuse: efuse@11c10000 { 1033 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 1034 reg = <0 0x11c10000 0 0x1000>; 1035 #address-cells = <1>; 1036 #size-cells = <1>; 1037 u3_tx_imp_p0: usb3-tx-imp@184,1 { 1038 reg = <0x184 0x1>; 1039 bits = <0 5>; 1040 }; 1041 u3_rx_imp_p0: usb3-rx-imp@184,2 { 1042 reg = <0x184 0x2>; 1043 bits = <5 5>; 1044 }; 1045 u3_intr_p0: usb3-intr@185 { 1046 reg = <0x185 0x1>; 1047 bits = <2 6>; 1048 }; 1049 comb_tx_imp_p1: usb3-tx-imp@186,1 { 1050 reg = <0x186 0x1>; 1051 bits = <0 5>; 1052 }; 1053 comb_rx_imp_p1: usb3-rx-imp@186,2 { 1054 reg = <0x186 0x2>; 1055 bits = <5 5>; 1056 }; 1057 comb_intr_p1: usb3-intr@187 { 1058 reg = <0x187 0x1>; 1059 bits = <2 6>; 1060 }; 1061 u2_intr_p0: usb2-intr-p0@188,1 { 1062 reg = <0x188 0x1>; 1063 bits = <0 5>; 1064 }; 1065 u2_intr_p1: usb2-intr-p1@188,2 { 1066 reg = <0x188 0x2>; 1067 bits = <5 5>; 1068 }; 1069 u2_intr_p2: usb2-intr-p2@189,1 { 1070 reg = <0x189 0x1>; 1071 bits = <2 5>; 1072 }; 1073 u2_intr_p3: usb2-intr-p3@189,2 { 1074 reg = <0x189 0x2>; 1075 bits = <7 5>; 1076 }; 1077 }; 1078 1079 u3phy2: t-phy@11c40000 { 1080 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1081 #address-cells = <1>; 1082 #size-cells = <1>; 1083 ranges = <0 0 0x11c40000 0x700>; 1084 status = "disabled"; 1085 1086 u2port2: usb-phy@0 { 1087 reg = <0x0 0x700>; 1088 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 1089 clock-names = "ref"; 1090 #phy-cells = <1>; 1091 }; 1092 }; 1093 1094 u3phy3: t-phy@11c50000 { 1095 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1096 #address-cells = <1>; 1097 #size-cells = <1>; 1098 ranges = <0 0 0x11c50000 0x700>; 1099 status = "disabled"; 1100 1101 u2port3: usb-phy@0 { 1102 reg = <0x0 0x700>; 1103 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 1104 clock-names = "ref"; 1105 #phy-cells = <1>; 1106 }; 1107 }; 1108 1109 i2c5: i2c@11d00000 { 1110 compatible = "mediatek,mt8195-i2c", 1111 "mediatek,mt8192-i2c"; 1112 reg = <0 0x11d00000 0 0x1000>, 1113 <0 0x10220580 0 0x80>; 1114 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 1115 clock-div = <1>; 1116 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 1117 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1118 clock-names = "main", "dma"; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 status = "disabled"; 1122 }; 1123 1124 i2c6: i2c@11d01000 { 1125 compatible = "mediatek,mt8195-i2c", 1126 "mediatek,mt8192-i2c"; 1127 reg = <0 0x11d01000 0 0x1000>, 1128 <0 0x10220600 0 0x80>; 1129 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 1130 clock-div = <1>; 1131 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 1132 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1133 clock-names = "main", "dma"; 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 status = "disabled"; 1137 }; 1138 1139 i2c7: i2c@11d02000 { 1140 compatible = "mediatek,mt8195-i2c", 1141 "mediatek,mt8192-i2c"; 1142 reg = <0 0x11d02000 0 0x1000>, 1143 <0 0x10220680 0 0x80>; 1144 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1145 clock-div = <1>; 1146 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1147 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1148 clock-names = "main", "dma"; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 status = "disabled"; 1152 }; 1153 1154 imp_iic_wrap_s: clock-controller@11d03000 { 1155 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 1156 reg = <0 0x11d03000 0 0x1000>; 1157 #clock-cells = <1>; 1158 }; 1159 1160 i2c0: i2c@11e00000 { 1161 compatible = "mediatek,mt8195-i2c", 1162 "mediatek,mt8192-i2c"; 1163 reg = <0 0x11e00000 0 0x1000>, 1164 <0 0x10220080 0 0x80>; 1165 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 1166 clock-div = <1>; 1167 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 1168 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1169 clock-names = "main", "dma"; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 status = "disabled"; 1173 }; 1174 1175 i2c1: i2c@11e01000 { 1176 compatible = "mediatek,mt8195-i2c", 1177 "mediatek,mt8192-i2c"; 1178 reg = <0 0x11e01000 0 0x1000>, 1179 <0 0x10220200 0 0x80>; 1180 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1181 clock-div = <1>; 1182 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 1183 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1184 clock-names = "main", "dma"; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 status = "disabled"; 1188 }; 1189 1190 i2c2: i2c@11e02000 { 1191 compatible = "mediatek,mt8195-i2c", 1192 "mediatek,mt8192-i2c"; 1193 reg = <0 0x11e02000 0 0x1000>, 1194 <0 0x10220380 0 0x80>; 1195 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1196 clock-div = <1>; 1197 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 1198 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1199 clock-names = "main", "dma"; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 status = "disabled"; 1203 }; 1204 1205 i2c3: i2c@11e03000 { 1206 compatible = "mediatek,mt8195-i2c", 1207 "mediatek,mt8192-i2c"; 1208 reg = <0 0x11e03000 0 0x1000>, 1209 <0 0x10220480 0 0x80>; 1210 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1211 clock-div = <1>; 1212 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 1213 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1214 clock-names = "main", "dma"; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 status = "disabled"; 1218 }; 1219 1220 i2c4: i2c@11e04000 { 1221 compatible = "mediatek,mt8195-i2c", 1222 "mediatek,mt8192-i2c"; 1223 reg = <0 0x11e04000 0 0x1000>, 1224 <0 0x10220500 0 0x80>; 1225 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 1226 clock-div = <1>; 1227 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 1228 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1229 clock-names = "main", "dma"; 1230 #address-cells = <1>; 1231 #size-cells = <0>; 1232 status = "disabled"; 1233 }; 1234 1235 imp_iic_wrap_w: clock-controller@11e05000 { 1236 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 1237 reg = <0 0x11e05000 0 0x1000>; 1238 #clock-cells = <1>; 1239 }; 1240 1241 u3phy1: t-phy@11e30000 { 1242 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1243 #address-cells = <1>; 1244 #size-cells = <1>; 1245 ranges = <0 0 0x11e30000 0xe00>; 1246 status = "disabled"; 1247 1248 u2port1: usb-phy@0 { 1249 reg = <0x0 0x700>; 1250 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 1251 <&clk26m>; 1252 clock-names = "ref", "da_ref"; 1253 #phy-cells = <1>; 1254 }; 1255 1256 u3port1: usb-phy@700 { 1257 reg = <0x700 0x700>; 1258 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1259 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 1260 clock-names = "ref", "da_ref"; 1261 nvmem-cells = <&comb_intr_p1>, 1262 <&comb_rx_imp_p1>, 1263 <&comb_tx_imp_p1>; 1264 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1265 #phy-cells = <1>; 1266 }; 1267 }; 1268 1269 u3phy0: t-phy@11e40000 { 1270 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1271 #address-cells = <1>; 1272 #size-cells = <1>; 1273 ranges = <0 0 0x11e40000 0xe00>; 1274 status = "disabled"; 1275 1276 u2port0: usb-phy@0 { 1277 reg = <0x0 0x700>; 1278 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1279 <&clk26m>; 1280 clock-names = "ref", "da_ref"; 1281 #phy-cells = <1>; 1282 }; 1283 1284 u3port0: usb-phy@700 { 1285 reg = <0x700 0x700>; 1286 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1287 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 1288 clock-names = "ref", "da_ref"; 1289 nvmem-cells = <&u3_intr_p0>, 1290 <&u3_rx_imp_p0>, 1291 <&u3_tx_imp_p0>; 1292 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1293 #phy-cells = <1>; 1294 }; 1295 }; 1296 1297 ufsphy: ufs-phy@11fa0000 { 1298 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 1299 reg = <0 0x11fa0000 0 0xc000>; 1300 clocks = <&clk26m>, <&clk26m>; 1301 clock-names = "unipro", "mp"; 1302 #phy-cells = <0>; 1303 status = "disabled"; 1304 }; 1305 1306 mfgcfg: clock-controller@13fbf000 { 1307 compatible = "mediatek,mt8195-mfgcfg"; 1308 reg = <0 0x13fbf000 0 0x1000>; 1309 #clock-cells = <1>; 1310 }; 1311 1312 vppsys0: clock-controller@14000000 { 1313 compatible = "mediatek,mt8195-vppsys0"; 1314 reg = <0 0x14000000 0 0x1000>; 1315 #clock-cells = <1>; 1316 }; 1317 1318 wpesys: clock-controller@14e00000 { 1319 compatible = "mediatek,mt8195-wpesys"; 1320 reg = <0 0x14e00000 0 0x1000>; 1321 #clock-cells = <1>; 1322 }; 1323 1324 wpesys_vpp0: clock-controller@14e02000 { 1325 compatible = "mediatek,mt8195-wpesys_vpp0"; 1326 reg = <0 0x14e02000 0 0x1000>; 1327 #clock-cells = <1>; 1328 }; 1329 1330 wpesys_vpp1: clock-controller@14e03000 { 1331 compatible = "mediatek,mt8195-wpesys_vpp1"; 1332 reg = <0 0x14e03000 0 0x1000>; 1333 #clock-cells = <1>; 1334 }; 1335 1336 vppsys1: clock-controller@14f00000 { 1337 compatible = "mediatek,mt8195-vppsys1"; 1338 reg = <0 0x14f00000 0 0x1000>; 1339 #clock-cells = <1>; 1340 }; 1341 1342 imgsys: clock-controller@15000000 { 1343 compatible = "mediatek,mt8195-imgsys"; 1344 reg = <0 0x15000000 0 0x1000>; 1345 #clock-cells = <1>; 1346 }; 1347 1348 imgsys1_dip_top: clock-controller@15110000 { 1349 compatible = "mediatek,mt8195-imgsys1_dip_top"; 1350 reg = <0 0x15110000 0 0x1000>; 1351 #clock-cells = <1>; 1352 }; 1353 1354 imgsys1_dip_nr: clock-controller@15130000 { 1355 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 1356 reg = <0 0x15130000 0 0x1000>; 1357 #clock-cells = <1>; 1358 }; 1359 1360 imgsys1_wpe: clock-controller@15220000 { 1361 compatible = "mediatek,mt8195-imgsys1_wpe"; 1362 reg = <0 0x15220000 0 0x1000>; 1363 #clock-cells = <1>; 1364 }; 1365 1366 ipesys: clock-controller@15330000 { 1367 compatible = "mediatek,mt8195-ipesys"; 1368 reg = <0 0x15330000 0 0x1000>; 1369 #clock-cells = <1>; 1370 }; 1371 1372 camsys: clock-controller@16000000 { 1373 compatible = "mediatek,mt8195-camsys"; 1374 reg = <0 0x16000000 0 0x1000>; 1375 #clock-cells = <1>; 1376 }; 1377 1378 camsys_rawa: clock-controller@1604f000 { 1379 compatible = "mediatek,mt8195-camsys_rawa"; 1380 reg = <0 0x1604f000 0 0x1000>; 1381 #clock-cells = <1>; 1382 }; 1383 1384 camsys_yuva: clock-controller@1606f000 { 1385 compatible = "mediatek,mt8195-camsys_yuva"; 1386 reg = <0 0x1606f000 0 0x1000>; 1387 #clock-cells = <1>; 1388 }; 1389 1390 camsys_rawb: clock-controller@1608f000 { 1391 compatible = "mediatek,mt8195-camsys_rawb"; 1392 reg = <0 0x1608f000 0 0x1000>; 1393 #clock-cells = <1>; 1394 }; 1395 1396 camsys_yuvb: clock-controller@160af000 { 1397 compatible = "mediatek,mt8195-camsys_yuvb"; 1398 reg = <0 0x160af000 0 0x1000>; 1399 #clock-cells = <1>; 1400 }; 1401 1402 camsys_mraw: clock-controller@16140000 { 1403 compatible = "mediatek,mt8195-camsys_mraw"; 1404 reg = <0 0x16140000 0 0x1000>; 1405 #clock-cells = <1>; 1406 }; 1407 1408 ccusys: clock-controller@17200000 { 1409 compatible = "mediatek,mt8195-ccusys"; 1410 reg = <0 0x17200000 0 0x1000>; 1411 #clock-cells = <1>; 1412 }; 1413 1414 vdecsys_soc: clock-controller@1800f000 { 1415 compatible = "mediatek,mt8195-vdecsys_soc"; 1416 reg = <0 0x1800f000 0 0x1000>; 1417 #clock-cells = <1>; 1418 }; 1419 1420 vdecsys: clock-controller@1802f000 { 1421 compatible = "mediatek,mt8195-vdecsys"; 1422 reg = <0 0x1802f000 0 0x1000>; 1423 #clock-cells = <1>; 1424 }; 1425 1426 vdecsys_core1: clock-controller@1803f000 { 1427 compatible = "mediatek,mt8195-vdecsys_core1"; 1428 reg = <0 0x1803f000 0 0x1000>; 1429 #clock-cells = <1>; 1430 }; 1431 1432 apusys_pll: clock-controller@190f3000 { 1433 compatible = "mediatek,mt8195-apusys_pll"; 1434 reg = <0 0x190f3000 0 0x1000>; 1435 #clock-cells = <1>; 1436 }; 1437 1438 vencsys: clock-controller@1a000000 { 1439 compatible = "mediatek,mt8195-vencsys"; 1440 reg = <0 0x1a000000 0 0x1000>; 1441 #clock-cells = <1>; 1442 }; 1443 1444 vencsys_core1: clock-controller@1b000000 { 1445 compatible = "mediatek,mt8195-vencsys_core1"; 1446 reg = <0 0x1b000000 0 0x1000>; 1447 #clock-cells = <1>; 1448 }; 1449 1450 vdosys0: syscon@1c01a000 { 1451 compatible = "mediatek,mt8195-mmsys", "syscon"; 1452 reg = <0 0x1c01a000 0 0x1000>; 1453 #clock-cells = <1>; 1454 }; 1455 1456 vdosys1: syscon@1c100000 { 1457 compatible = "mediatek,mt8195-mmsys", "syscon"; 1458 reg = <0 0x1c100000 0 0x1000>; 1459 #clock-cells = <1>; 1460 }; 1461 }; 1462}; 1463