mt8195.dtsi (04cd978316c992711f341b0c91fdb44f2c21836b) mt8195.dtsi (3b5838d1d82e381e31bc3d13398f08d69b98be5d)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/memory/mt8195-memory-port.h>
11#include <dt-bindings/phy/phy.h>
12#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
13#include <dt-bindings/power/mt8195-power.h>
14
15/ {
16 compatible = "mediatek,mt8195";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;

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719 <&topckgen CLK_TOP_SPMI_M_MST>;
720 clock-names = "pmif_sys_ck",
721 "pmif_tmr_ck",
722 "spmimst_clk_mux";
723 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
724 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
725 };
726
12#include <dt-bindings/phy/phy.h>
13#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
14#include <dt-bindings/power/mt8195-power.h>
15
16/ {
17 compatible = "mediatek,mt8195";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;

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720 <&topckgen CLK_TOP_SPMI_M_MST>;
721 clock-names = "pmif_sys_ck",
722 "pmif_tmr_ck",
723 "spmimst_clk_mux";
724 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
725 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
726 };
727
728 iommu_infra: infra-iommu@10315000 {
729 compatible = "mediatek,mt8195-iommu-infra";
730 reg = <0 0x10315000 0 0x5000>;
731 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>,
732 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>,
733 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>,
734 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>,
735 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>;
736 #iommu-cells = <1>;
737 };
738
727 scp: scp@10500000 {
728 compatible = "mediatek,mt8195-scp";
729 reg = <0 0x10500000 0 0x100000>,
730 <0 0x10720000 0 0xe0000>,
731 <0 0x10700000 0 0x8000>;
732 reg-names = "sram", "cfg", "l1tcm";
733 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
734 status = "disabled";

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1433 };
1434
1435 vppsys0: clock-controller@14000000 {
1436 compatible = "mediatek,mt8195-vppsys0";
1437 reg = <0 0x14000000 0 0x1000>;
1438 #clock-cells = <1>;
1439 };
1440
739 scp: scp@10500000 {
740 compatible = "mediatek,mt8195-scp";
741 reg = <0 0x10500000 0 0x100000>,
742 <0 0x10720000 0 0xe0000>,
743 <0 0x10700000 0 0x8000>;
744 reg-names = "sram", "cfg", "l1tcm";
745 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
746 status = "disabled";

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1445 };
1446
1447 vppsys0: clock-controller@14000000 {
1448 compatible = "mediatek,mt8195-vppsys0";
1449 reg = <0 0x14000000 0 0x1000>;
1450 #clock-cells = <1>;
1451 };
1452
1453 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
1454 compatible = "mediatek,mt8195-smi-sub-common";
1455 reg = <0 0x14010000 0 0x1000>;
1456 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
1457 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
1458 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
1459 clock-names = "apb", "smi", "gals0";
1460 mediatek,smi = <&smi_common_vpp>;
1461 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1462 };
1463
1464 smi_sub_common_vdec_vpp0_2x1: smi@14011000 {
1465 compatible = "mediatek,mt8195-smi-sub-common";
1466 reg = <0 0x14011000 0 0x1000>;
1467 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
1468 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
1469 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>;
1470 clock-names = "apb", "smi", "gals0";
1471 mediatek,smi = <&smi_common_vpp>;
1472 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1473 };
1474
1475 smi_common_vpp: smi@14012000 {
1476 compatible = "mediatek,mt8195-smi-common-vpp";
1477 reg = <0 0x14012000 0 0x1000>;
1478 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
1479 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
1480 <&vppsys0 CLK_VPP0_SMI_RSI>,
1481 <&vppsys0 CLK_VPP0_SMI_RSI>;
1482 clock-names = "apb", "smi", "gals0", "gals1";
1483 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1484 };
1485
1486 larb4: larb@14013000 {
1487 compatible = "mediatek,mt8195-smi-larb";
1488 reg = <0 0x14013000 0 0x1000>;
1489 mediatek,larb-id = <4>;
1490 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
1491 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
1492 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
1493 clock-names = "apb", "smi";
1494 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1495 };
1496
1497 iommu_vpp: iommu@14018000 {
1498 compatible = "mediatek,mt8195-iommu-vpp";
1499 reg = <0 0x14018000 0 0x1000>;
1500 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8
1501 &larb12 &larb14 &larb16 &larb18
1502 &larb20 &larb22 &larb23 &larb26
1503 &larb27>;
1504 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>;
1505 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
1506 clock-names = "bclk";
1507 #iommu-cells = <1>;
1508 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1509 };
1510
1441 wpesys: clock-controller@14e00000 {
1442 compatible = "mediatek,mt8195-wpesys";
1443 reg = <0 0x14e00000 0 0x1000>;
1444 #clock-cells = <1>;
1445 };
1446
1447 wpesys_vpp0: clock-controller@14e02000 {
1448 compatible = "mediatek,mt8195-wpesys_vpp0";
1449 reg = <0 0x14e02000 0 0x1000>;
1450 #clock-cells = <1>;
1451 };
1452
1453 wpesys_vpp1: clock-controller@14e03000 {
1454 compatible = "mediatek,mt8195-wpesys_vpp1";
1455 reg = <0 0x14e03000 0 0x1000>;
1456 #clock-cells = <1>;
1457 };
1458
1511 wpesys: clock-controller@14e00000 {
1512 compatible = "mediatek,mt8195-wpesys";
1513 reg = <0 0x14e00000 0 0x1000>;
1514 #clock-cells = <1>;
1515 };
1516
1517 wpesys_vpp0: clock-controller@14e02000 {
1518 compatible = "mediatek,mt8195-wpesys_vpp0";
1519 reg = <0 0x14e02000 0 0x1000>;
1520 #clock-cells = <1>;
1521 };
1522
1523 wpesys_vpp1: clock-controller@14e03000 {
1524 compatible = "mediatek,mt8195-wpesys_vpp1";
1525 reg = <0 0x14e03000 0 0x1000>;
1526 #clock-cells = <1>;
1527 };
1528
1529 larb7: larb@14e04000 {
1530 compatible = "mediatek,mt8195-smi-larb";
1531 reg = <0 0x14e04000 0 0x1000>;
1532 mediatek,larb-id = <7>;
1533 mediatek,smi = <&smi_common_vdo>;
1534 clocks = <&wpesys CLK_WPE_SMI_LARB7>,
1535 <&wpesys CLK_WPE_SMI_LARB7>;
1536 clock-names = "apb", "smi";
1537 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
1538 };
1539
1540 larb8: larb@14e05000 {
1541 compatible = "mediatek,mt8195-smi-larb";
1542 reg = <0 0x14e05000 0 0x1000>;
1543 mediatek,larb-id = <8>;
1544 mediatek,smi = <&smi_common_vpp>;
1545 clocks = <&wpesys CLK_WPE_SMI_LARB8>,
1546 <&wpesys CLK_WPE_SMI_LARB8>,
1547 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
1548 clock-names = "apb", "smi", "gals";
1549 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
1550 };
1551
1459 vppsys1: clock-controller@14f00000 {
1460 compatible = "mediatek,mt8195-vppsys1";
1461 reg = <0 0x14f00000 0 0x1000>;
1462 #clock-cells = <1>;
1463 };
1464
1552 vppsys1: clock-controller@14f00000 {
1553 compatible = "mediatek,mt8195-vppsys1";
1554 reg = <0 0x14f00000 0 0x1000>;
1555 #clock-cells = <1>;
1556 };
1557
1558 larb5: larb@14f02000 {
1559 compatible = "mediatek,mt8195-smi-larb";
1560 reg = <0 0x14f02000 0 0x1000>;
1561 mediatek,larb-id = <5>;
1562 mediatek,smi = <&smi_common_vdo>;
1563 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
1564 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
1565 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;
1566 clock-names = "apb", "smi", "gals";
1567 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
1568 };
1569
1570 larb6: larb@14f03000 {
1571 compatible = "mediatek,mt8195-smi-larb";
1572 reg = <0 0x14f03000 0 0x1000>;
1573 mediatek,larb-id = <6>;
1574 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
1575 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
1576 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
1577 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
1578 clock-names = "apb", "smi", "gals";
1579 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
1580 };
1581
1465 imgsys: clock-controller@15000000 {
1466 compatible = "mediatek,mt8195-imgsys";
1467 reg = <0 0x15000000 0 0x1000>;
1468 #clock-cells = <1>;
1469 };
1470
1582 imgsys: clock-controller@15000000 {
1583 compatible = "mediatek,mt8195-imgsys";
1584 reg = <0 0x15000000 0 0x1000>;
1585 #clock-cells = <1>;
1586 };
1587
1588 larb9: larb@15001000 {
1589 compatible = "mediatek,mt8195-smi-larb";
1590 reg = <0 0x15001000 0 0x1000>;
1591 mediatek,larb-id = <9>;
1592 mediatek,smi = <&smi_sub_common_img1_3x1>;
1593 clocks = <&imgsys CLK_IMG_LARB9>,
1594 <&imgsys CLK_IMG_LARB9>,
1595 <&imgsys CLK_IMG_GALS>;
1596 clock-names = "apb", "smi", "gals";
1597 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
1598 };
1599
1600 smi_sub_common_img0_3x1: smi@15002000 {
1601 compatible = "mediatek,mt8195-smi-sub-common";
1602 reg = <0 0x15002000 0 0x1000>;
1603 clocks = <&imgsys CLK_IMG_IPE>,
1604 <&imgsys CLK_IMG_IPE>,
1605 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
1606 clock-names = "apb", "smi", "gals0";
1607 mediatek,smi = <&smi_common_vpp>;
1608 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
1609 };
1610
1611 smi_sub_common_img1_3x1: smi@15003000 {
1612 compatible = "mediatek,mt8195-smi-sub-common";
1613 reg = <0 0x15003000 0 0x1000>;
1614 clocks = <&imgsys CLK_IMG_LARB9>,
1615 <&imgsys CLK_IMG_LARB9>,
1616 <&imgsys CLK_IMG_GALS>;
1617 clock-names = "apb", "smi", "gals0";
1618 mediatek,smi = <&smi_common_vdo>;
1619 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
1620 };
1621
1471 imgsys1_dip_top: clock-controller@15110000 {
1472 compatible = "mediatek,mt8195-imgsys1_dip_top";
1473 reg = <0 0x15110000 0 0x1000>;
1474 #clock-cells = <1>;
1475 };
1476
1622 imgsys1_dip_top: clock-controller@15110000 {
1623 compatible = "mediatek,mt8195-imgsys1_dip_top";
1624 reg = <0 0x15110000 0 0x1000>;
1625 #clock-cells = <1>;
1626 };
1627
1628 larb10: larb@15120000 {
1629 compatible = "mediatek,mt8195-smi-larb";
1630 reg = <0 0x15120000 0 0x1000>;
1631 mediatek,larb-id = <10>;
1632 mediatek,smi = <&smi_sub_common_img1_3x1>;
1633 clocks = <&imgsys CLK_IMG_DIP0>,
1634 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>;
1635 clock-names = "apb", "smi";
1636 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
1637 };
1638
1477 imgsys1_dip_nr: clock-controller@15130000 {
1478 compatible = "mediatek,mt8195-imgsys1_dip_nr";
1479 reg = <0 0x15130000 0 0x1000>;
1480 #clock-cells = <1>;
1481 };
1482
1483 imgsys1_wpe: clock-controller@15220000 {
1484 compatible = "mediatek,mt8195-imgsys1_wpe";
1485 reg = <0 0x15220000 0 0x1000>;
1486 #clock-cells = <1>;
1487 };
1488
1639 imgsys1_dip_nr: clock-controller@15130000 {
1640 compatible = "mediatek,mt8195-imgsys1_dip_nr";
1641 reg = <0 0x15130000 0 0x1000>;
1642 #clock-cells = <1>;
1643 };
1644
1645 imgsys1_wpe: clock-controller@15220000 {
1646 compatible = "mediatek,mt8195-imgsys1_wpe";
1647 reg = <0 0x15220000 0 0x1000>;
1648 #clock-cells = <1>;
1649 };
1650
1651 larb11: larb@15230000 {
1652 compatible = "mediatek,mt8195-smi-larb";
1653 reg = <0 0x15230000 0 0x1000>;
1654 mediatek,larb-id = <11>;
1655 mediatek,smi = <&smi_sub_common_img1_3x1>;
1656 clocks = <&imgsys CLK_IMG_WPE0>,
1657 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>;
1658 clock-names = "apb", "smi";
1659 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
1660 };
1661
1489 ipesys: clock-controller@15330000 {
1490 compatible = "mediatek,mt8195-ipesys";
1491 reg = <0 0x15330000 0 0x1000>;
1492 #clock-cells = <1>;
1493 };
1494
1662 ipesys: clock-controller@15330000 {
1663 compatible = "mediatek,mt8195-ipesys";
1664 reg = <0 0x15330000 0 0x1000>;
1665 #clock-cells = <1>;
1666 };
1667
1668 larb12: larb@15340000 {
1669 compatible = "mediatek,mt8195-smi-larb";
1670 reg = <0 0x15340000 0 0x1000>;
1671 mediatek,larb-id = <12>;
1672 mediatek,smi = <&smi_sub_common_img0_3x1>;
1673 clocks = <&ipesys CLK_IPE_SMI_LARB12>,
1674 <&ipesys CLK_IPE_SMI_LARB12>;
1675 clock-names = "apb", "smi";
1676 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
1677 };
1678
1495 camsys: clock-controller@16000000 {
1496 compatible = "mediatek,mt8195-camsys";
1497 reg = <0 0x16000000 0 0x1000>;
1498 #clock-cells = <1>;
1499 };
1500
1679 camsys: clock-controller@16000000 {
1680 compatible = "mediatek,mt8195-camsys";
1681 reg = <0 0x16000000 0 0x1000>;
1682 #clock-cells = <1>;
1683 };
1684
1685 larb13: larb@16001000 {
1686 compatible = "mediatek,mt8195-smi-larb";
1687 reg = <0 0x16001000 0 0x1000>;
1688 mediatek,larb-id = <13>;
1689 mediatek,smi = <&smi_sub_common_cam_4x1>;
1690 clocks = <&camsys CLK_CAM_LARB13>,
1691 <&camsys CLK_CAM_LARB13>,
1692 <&camsys CLK_CAM_CAM2MM0_GALS>;
1693 clock-names = "apb", "smi", "gals";
1694 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
1695 };
1696
1697 larb14: larb@16002000 {
1698 compatible = "mediatek,mt8195-smi-larb";
1699 reg = <0 0x16002000 0 0x1000>;
1700 mediatek,larb-id = <14>;
1701 mediatek,smi = <&smi_sub_common_cam_7x1>;
1702 clocks = <&camsys CLK_CAM_LARB14>,
1703 <&camsys CLK_CAM_LARB14>;
1704 clock-names = "apb", "smi";
1705 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
1706 };
1707
1708 smi_sub_common_cam_4x1: smi@16004000 {
1709 compatible = "mediatek,mt8195-smi-sub-common";
1710 reg = <0 0x16004000 0 0x1000>;
1711 clocks = <&camsys CLK_CAM_LARB13>,
1712 <&camsys CLK_CAM_LARB13>,
1713 <&camsys CLK_CAM_CAM2MM0_GALS>;
1714 clock-names = "apb", "smi", "gals0";
1715 mediatek,smi = <&smi_common_vdo>;
1716 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
1717 };
1718
1719 smi_sub_common_cam_7x1: smi@16005000 {
1720 compatible = "mediatek,mt8195-smi-sub-common";
1721 reg = <0 0x16005000 0 0x1000>;
1722 clocks = <&camsys CLK_CAM_LARB14>,
1723 <&camsys CLK_CAM_CAM2MM1_GALS>,
1724 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
1725 clock-names = "apb", "smi", "gals0";
1726 mediatek,smi = <&smi_common_vpp>;
1727 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
1728 };
1729
1730 larb16: larb@16012000 {
1731 compatible = "mediatek,mt8195-smi-larb";
1732 reg = <0 0x16012000 0 0x1000>;
1733 mediatek,larb-id = <16>;
1734 mediatek,smi = <&smi_sub_common_cam_7x1>;
1735 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>,
1736 <&camsys_rawa CLK_CAM_RAWA_LARBX>;
1737 clock-names = "apb", "smi";
1738 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
1739 };
1740
1741 larb17: larb@16013000 {
1742 compatible = "mediatek,mt8195-smi-larb";
1743 reg = <0 0x16013000 0 0x1000>;
1744 mediatek,larb-id = <17>;
1745 mediatek,smi = <&smi_sub_common_cam_4x1>;
1746 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>,
1747 <&camsys_yuva CLK_CAM_YUVA_LARBX>;
1748 clock-names = "apb", "smi";
1749 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
1750 };
1751
1752 larb27: larb@16014000 {
1753 compatible = "mediatek,mt8195-smi-larb";
1754 reg = <0 0x16014000 0 0x1000>;
1755 mediatek,larb-id = <27>;
1756 mediatek,smi = <&smi_sub_common_cam_7x1>;
1757 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>,
1758 <&camsys_rawb CLK_CAM_RAWB_LARBX>;
1759 clock-names = "apb", "smi";
1760 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
1761 };
1762
1763 larb28: larb@16015000 {
1764 compatible = "mediatek,mt8195-smi-larb";
1765 reg = <0 0x16015000 0 0x1000>;
1766 mediatek,larb-id = <28>;
1767 mediatek,smi = <&smi_sub_common_cam_4x1>;
1768 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>,
1769 <&camsys_yuvb CLK_CAM_YUVB_LARBX>;
1770 clock-names = "apb", "smi";
1771 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
1772 };
1773
1501 camsys_rawa: clock-controller@1604f000 {
1502 compatible = "mediatek,mt8195-camsys_rawa";
1503 reg = <0 0x1604f000 0 0x1000>;
1504 #clock-cells = <1>;
1505 };
1506
1507 camsys_yuva: clock-controller@1606f000 {
1508 compatible = "mediatek,mt8195-camsys_yuva";

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1523 };
1524
1525 camsys_mraw: clock-controller@16140000 {
1526 compatible = "mediatek,mt8195-camsys_mraw";
1527 reg = <0 0x16140000 0 0x1000>;
1528 #clock-cells = <1>;
1529 };
1530
1774 camsys_rawa: clock-controller@1604f000 {
1775 compatible = "mediatek,mt8195-camsys_rawa";
1776 reg = <0 0x1604f000 0 0x1000>;
1777 #clock-cells = <1>;
1778 };
1779
1780 camsys_yuva: clock-controller@1606f000 {
1781 compatible = "mediatek,mt8195-camsys_yuva";

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1796 };
1797
1798 camsys_mraw: clock-controller@16140000 {
1799 compatible = "mediatek,mt8195-camsys_mraw";
1800 reg = <0 0x16140000 0 0x1000>;
1801 #clock-cells = <1>;
1802 };
1803
1804 larb25: larb@16141000 {
1805 compatible = "mediatek,mt8195-smi-larb";
1806 reg = <0 0x16141000 0 0x1000>;
1807 mediatek,larb-id = <25>;
1808 mediatek,smi = <&smi_sub_common_cam_4x1>;
1809 clocks = <&camsys CLK_CAM_LARB13>,
1810 <&camsys_mraw CLK_CAM_MRAW_LARBX>,
1811 <&camsys CLK_CAM_CAM2MM0_GALS>;
1812 clock-names = "apb", "smi", "gals";
1813 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
1814 };
1815
1816 larb26: larb@16142000 {
1817 compatible = "mediatek,mt8195-smi-larb";
1818 reg = <0 0x16142000 0 0x1000>;
1819 mediatek,larb-id = <26>;
1820 mediatek,smi = <&smi_sub_common_cam_7x1>;
1821 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>,
1822 <&camsys_mraw CLK_CAM_MRAW_LARBX>;
1823 clock-names = "apb", "smi";
1824 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
1825
1826 };
1827
1531 ccusys: clock-controller@17200000 {
1532 compatible = "mediatek,mt8195-ccusys";
1533 reg = <0 0x17200000 0 0x1000>;
1534 #clock-cells = <1>;
1535 };
1536
1828 ccusys: clock-controller@17200000 {
1829 compatible = "mediatek,mt8195-ccusys";
1830 reg = <0 0x17200000 0 0x1000>;
1831 #clock-cells = <1>;
1832 };
1833
1834 larb18: larb@17201000 {
1835 compatible = "mediatek,mt8195-smi-larb";
1836 reg = <0 0x17201000 0 0x1000>;
1837 mediatek,larb-id = <18>;
1838 mediatek,smi = <&smi_sub_common_cam_7x1>;
1839 clocks = <&ccusys CLK_CCU_LARB18>,
1840 <&ccusys CLK_CCU_LARB18>;
1841 clock-names = "apb", "smi";
1842 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
1843 };
1844
1845 larb24: larb@1800d000 {
1846 compatible = "mediatek,mt8195-smi-larb";
1847 reg = <0 0x1800d000 0 0x1000>;
1848 mediatek,larb-id = <24>;
1849 mediatek,smi = <&smi_common_vdo>;
1850 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
1851 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
1852 clock-names = "apb", "smi";
1853 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
1854 };
1855
1856 larb23: larb@1800e000 {
1857 compatible = "mediatek,mt8195-smi-larb";
1858 reg = <0 0x1800e000 0 0x1000>;
1859 mediatek,larb-id = <23>;
1860 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
1861 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
1862 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
1863 clock-names = "apb", "smi";
1864 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
1865 };
1866
1537 vdecsys_soc: clock-controller@1800f000 {
1538 compatible = "mediatek,mt8195-vdecsys_soc";
1539 reg = <0 0x1800f000 0 0x1000>;
1540 #clock-cells = <1>;
1541 };
1542
1867 vdecsys_soc: clock-controller@1800f000 {
1868 compatible = "mediatek,mt8195-vdecsys_soc";
1869 reg = <0 0x1800f000 0 0x1000>;
1870 #clock-cells = <1>;
1871 };
1872
1873 larb21: larb@1802e000 {
1874 compatible = "mediatek,mt8195-smi-larb";
1875 reg = <0 0x1802e000 0 0x1000>;
1876 mediatek,larb-id = <21>;
1877 mediatek,smi = <&smi_common_vdo>;
1878 clocks = <&vdecsys CLK_VDEC_LARB1>,
1879 <&vdecsys CLK_VDEC_LARB1>;
1880 clock-names = "apb", "smi";
1881 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
1882 };
1883
1543 vdecsys: clock-controller@1802f000 {
1544 compatible = "mediatek,mt8195-vdecsys";
1545 reg = <0 0x1802f000 0 0x1000>;
1546 #clock-cells = <1>;
1547 };
1548
1884 vdecsys: clock-controller@1802f000 {
1885 compatible = "mediatek,mt8195-vdecsys";
1886 reg = <0 0x1802f000 0 0x1000>;
1887 #clock-cells = <1>;
1888 };
1889
1890 larb22: larb@1803e000 {
1891 compatible = "mediatek,mt8195-smi-larb";
1892 reg = <0 0x1803e000 0 0x1000>;
1893 mediatek,larb-id = <22>;
1894 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
1895 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
1896 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
1897 clock-names = "apb", "smi";
1898 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
1899 };
1900
1549 vdecsys_core1: clock-controller@1803f000 {
1550 compatible = "mediatek,mt8195-vdecsys_core1";
1551 reg = <0 0x1803f000 0 0x1000>;
1552 #clock-cells = <1>;
1553 };
1554
1555 apusys_pll: clock-controller@190f3000 {
1556 compatible = "mediatek,mt8195-apusys_pll";
1557 reg = <0 0x190f3000 0 0x1000>;
1558 #clock-cells = <1>;
1559 };
1560
1561 vencsys: clock-controller@1a000000 {
1562 compatible = "mediatek,mt8195-vencsys";
1563 reg = <0 0x1a000000 0 0x1000>;
1564 #clock-cells = <1>;
1565 };
1566
1901 vdecsys_core1: clock-controller@1803f000 {
1902 compatible = "mediatek,mt8195-vdecsys_core1";
1903 reg = <0 0x1803f000 0 0x1000>;
1904 #clock-cells = <1>;
1905 };
1906
1907 apusys_pll: clock-controller@190f3000 {
1908 compatible = "mediatek,mt8195-apusys_pll";
1909 reg = <0 0x190f3000 0 0x1000>;
1910 #clock-cells = <1>;
1911 };
1912
1913 vencsys: clock-controller@1a000000 {
1914 compatible = "mediatek,mt8195-vencsys";
1915 reg = <0 0x1a000000 0 0x1000>;
1916 #clock-cells = <1>;
1917 };
1918
1919 larb19: larb@1a010000 {
1920 compatible = "mediatek,mt8195-smi-larb";
1921 reg = <0 0x1a010000 0 0x1000>;
1922 mediatek,larb-id = <19>;
1923 mediatek,smi = <&smi_common_vdo>;
1924 clocks = <&vencsys CLK_VENC_VENC>,
1925 <&vencsys CLK_VENC_GALS>;
1926 clock-names = "apb", "smi";
1927 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
1928 };
1929
1567 vencsys_core1: clock-controller@1b000000 {
1568 compatible = "mediatek,mt8195-vencsys_core1";
1569 reg = <0 0x1b000000 0 0x1000>;
1570 #clock-cells = <1>;
1571 };
1572
1573 vdosys0: syscon@1c01a000 {
1574 compatible = "mediatek,mt8195-mmsys", "syscon";
1575 reg = <0 0x1c01a000 0 0x1000>;
1576 #clock-cells = <1>;
1577 };
1578
1930 vencsys_core1: clock-controller@1b000000 {
1931 compatible = "mediatek,mt8195-vencsys_core1";
1932 reg = <0 0x1b000000 0 0x1000>;
1933 #clock-cells = <1>;
1934 };
1935
1936 vdosys0: syscon@1c01a000 {
1937 compatible = "mediatek,mt8195-mmsys", "syscon";
1938 reg = <0 0x1c01a000 0 0x1000>;
1939 #clock-cells = <1>;
1940 };
1941
1942 larb20: larb@1b010000 {
1943 compatible = "mediatek,mt8195-smi-larb";
1944 reg = <0 0x1b010000 0 0x1000>;
1945 mediatek,larb-id = <20>;
1946 mediatek,smi = <&smi_common_vpp>;
1947 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>,
1948 <&vencsys_core1 CLK_VENC_CORE1_GALS>,
1949 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
1950 clock-names = "apb", "smi", "gals";
1951 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
1952 };
1953
1954 larb0: larb@1c018000 {
1955 compatible = "mediatek,mt8195-smi-larb";
1956 reg = <0 0x1c018000 0 0x1000>;
1957 mediatek,larb-id = <0>;
1958 mediatek,smi = <&smi_common_vdo>;
1959 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
1960 <&vdosys0 CLK_VDO0_SMI_LARB>,
1961 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;
1962 clock-names = "apb", "smi", "gals";
1963 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1964 };
1965
1966 larb1: larb@1c019000 {
1967 compatible = "mediatek,mt8195-smi-larb";
1968 reg = <0 0x1c019000 0 0x1000>;
1969 mediatek,larb-id = <1>;
1970 mediatek,smi = <&smi_common_vpp>;
1971 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
1972 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
1973 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
1974 clock-names = "apb", "smi", "gals";
1975 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1976 };
1977
1579 vdosys1: syscon@1c100000 {
1580 compatible = "mediatek,mt8195-mmsys", "syscon";
1581 reg = <0 0x1c100000 0 0x1000>;
1582 #clock-cells = <1>;
1583 };
1978 vdosys1: syscon@1c100000 {
1979 compatible = "mediatek,mt8195-mmsys", "syscon";
1980 reg = <0 0x1c100000 0 0x1000>;
1981 #clock-cells = <1>;
1982 };
1983
1984 smi_common_vdo: smi@1c01b000 {
1985 compatible = "mediatek,mt8195-smi-common-vdo";
1986 reg = <0 0x1c01b000 0 0x1000>;
1987 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,
1988 <&vdosys0 CLK_VDO0_SMI_EMI>,
1989 <&vdosys0 CLK_VDO0_SMI_RSI>,
1990 <&vdosys0 CLK_VDO0_SMI_GALS>;
1991 clock-names = "apb", "smi", "gals0", "gals1";
1992 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1993
1994 };
1995
1996 iommu_vdo: iommu@1c01f000 {
1997 compatible = "mediatek,mt8195-iommu-vdo";
1998 reg = <0 0x1c01f000 0 0x1000>;
1999 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9
2000 &larb10 &larb11 &larb13 &larb17
2001 &larb19 &larb21 &larb24 &larb25
2002 &larb28>;
2003 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>;
2004 #iommu-cells = <1>;
2005 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>;
2006 clock-names = "bclk";
2007 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2008 };
2009
2010 larb2: larb@1c102000 {
2011 compatible = "mediatek,mt8195-smi-larb";
2012 reg = <0 0x1c102000 0 0x1000>;
2013 mediatek,larb-id = <2>;
2014 mediatek,smi = <&smi_common_vdo>;
2015 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
2016 <&vdosys1 CLK_VDO1_SMI_LARB2>,
2017 <&vdosys1 CLK_VDO1_GALS>;
2018 clock-names = "apb", "smi", "gals";
2019 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2020 };
2021
2022 larb3: larb@1c103000 {
2023 compatible = "mediatek,mt8195-smi-larb";
2024 reg = <0 0x1c103000 0 0x1000>;
2025 mediatek,larb-id = <3>;
2026 mediatek,smi = <&smi_common_vpp>;
2027 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
2028 <&vdosys1 CLK_VDO1_GALS>,
2029 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
2030 clock-names = "apb", "smi", "gals";
2031 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2032 };
1584 };
1585};
2033 };
2034};