1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/memory/mt8195-memory-port.h> 12#include <dt-bindings/phy/phy.h> 13#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 14#include <dt-bindings/power/mt8195-power.h> 15 16/ { 17 compatible = "mediatek,mt8195"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu0: cpu@0 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a55"; 29 reg = <0x000>; 30 enable-method = "psci"; 31 performance-domains = <&performance 0>; 32 clock-frequency = <1701000000>; 33 capacity-dmips-mhz = <578>; 34 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 35 next-level-cache = <&l2_0>; 36 #cooling-cells = <2>; 37 }; 38 39 cpu1: cpu@100 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a55"; 42 reg = <0x100>; 43 enable-method = "psci"; 44 performance-domains = <&performance 0>; 45 clock-frequency = <1701000000>; 46 capacity-dmips-mhz = <578>; 47 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 48 next-level-cache = <&l2_0>; 49 #cooling-cells = <2>; 50 }; 51 52 cpu2: cpu@200 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x200>; 56 enable-method = "psci"; 57 performance-domains = <&performance 0>; 58 clock-frequency = <1701000000>; 59 capacity-dmips-mhz = <578>; 60 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 61 next-level-cache = <&l2_0>; 62 #cooling-cells = <2>; 63 }; 64 65 cpu3: cpu@300 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a55"; 68 reg = <0x300>; 69 enable-method = "psci"; 70 performance-domains = <&performance 0>; 71 clock-frequency = <1701000000>; 72 capacity-dmips-mhz = <578>; 73 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 74 next-level-cache = <&l2_0>; 75 #cooling-cells = <2>; 76 }; 77 78 cpu4: cpu@400 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a78"; 81 reg = <0x400>; 82 enable-method = "psci"; 83 performance-domains = <&performance 1>; 84 clock-frequency = <2171000000>; 85 capacity-dmips-mhz = <1024>; 86 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 87 next-level-cache = <&l2_1>; 88 #cooling-cells = <2>; 89 }; 90 91 cpu5: cpu@500 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a78"; 94 reg = <0x500>; 95 enable-method = "psci"; 96 performance-domains = <&performance 1>; 97 clock-frequency = <2171000000>; 98 capacity-dmips-mhz = <1024>; 99 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 100 next-level-cache = <&l2_1>; 101 #cooling-cells = <2>; 102 }; 103 104 cpu6: cpu@600 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a78"; 107 reg = <0x600>; 108 enable-method = "psci"; 109 performance-domains = <&performance 1>; 110 clock-frequency = <2171000000>; 111 capacity-dmips-mhz = <1024>; 112 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 113 next-level-cache = <&l2_1>; 114 #cooling-cells = <2>; 115 }; 116 117 cpu7: cpu@700 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a78"; 120 reg = <0x700>; 121 enable-method = "psci"; 122 performance-domains = <&performance 1>; 123 clock-frequency = <2171000000>; 124 capacity-dmips-mhz = <1024>; 125 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 126 next-level-cache = <&l2_1>; 127 #cooling-cells = <2>; 128 }; 129 130 cpu-map { 131 cluster0 { 132 core0 { 133 cpu = <&cpu0>; 134 }; 135 136 core1 { 137 cpu = <&cpu1>; 138 }; 139 140 core2 { 141 cpu = <&cpu2>; 142 }; 143 144 core3 { 145 cpu = <&cpu3>; 146 }; 147 }; 148 149 cluster1 { 150 core0 { 151 cpu = <&cpu4>; 152 }; 153 154 core1 { 155 cpu = <&cpu5>; 156 }; 157 158 core2 { 159 cpu = <&cpu6>; 160 }; 161 162 core3 { 163 cpu = <&cpu7>; 164 }; 165 }; 166 }; 167 168 idle-states { 169 entry-method = "psci"; 170 171 cpu_off_l: cpu-off-l { 172 compatible = "arm,idle-state"; 173 arm,psci-suspend-param = <0x00010001>; 174 local-timer-stop; 175 entry-latency-us = <50>; 176 exit-latency-us = <95>; 177 min-residency-us = <580>; 178 }; 179 180 cpu_off_b: cpu-off-b { 181 compatible = "arm,idle-state"; 182 arm,psci-suspend-param = <0x00010001>; 183 local-timer-stop; 184 entry-latency-us = <45>; 185 exit-latency-us = <140>; 186 min-residency-us = <740>; 187 }; 188 189 cluster_off_l: cluster-off-l { 190 compatible = "arm,idle-state"; 191 arm,psci-suspend-param = <0x01010002>; 192 local-timer-stop; 193 entry-latency-us = <55>; 194 exit-latency-us = <155>; 195 min-residency-us = <840>; 196 }; 197 198 cluster_off_b: cluster-off-b { 199 compatible = "arm,idle-state"; 200 arm,psci-suspend-param = <0x01010002>; 201 local-timer-stop; 202 entry-latency-us = <50>; 203 exit-latency-us = <200>; 204 min-residency-us = <1000>; 205 }; 206 }; 207 208 l2_0: l2-cache0 { 209 compatible = "cache"; 210 next-level-cache = <&l3_0>; 211 }; 212 213 l2_1: l2-cache1 { 214 compatible = "cache"; 215 next-level-cache = <&l3_0>; 216 }; 217 218 l3_0: l3-cache { 219 compatible = "cache"; 220 }; 221 }; 222 223 dsu-pmu { 224 compatible = "arm,dsu-pmu"; 225 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 226 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 227 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 228 }; 229 230 dmic_codec: dmic-codec { 231 compatible = "dmic-codec"; 232 num-channels = <2>; 233 wakeup-delay-ms = <50>; 234 }; 235 236 sound: mt8195-sound { 237 mediatek,platform = <&afe>; 238 status = "disabled"; 239 }; 240 241 clk26m: oscillator-26m { 242 compatible = "fixed-clock"; 243 #clock-cells = <0>; 244 clock-frequency = <26000000>; 245 clock-output-names = "clk26m"; 246 }; 247 248 clk32k: oscillator-32k { 249 compatible = "fixed-clock"; 250 #clock-cells = <0>; 251 clock-frequency = <32768>; 252 clock-output-names = "clk32k"; 253 }; 254 255 performance: performance-controller@11bc10 { 256 compatible = "mediatek,cpufreq-hw"; 257 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 258 #performance-domain-cells = <1>; 259 }; 260 261 pmu-a55 { 262 compatible = "arm,cortex-a55-pmu"; 263 interrupt-parent = <&gic>; 264 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 265 }; 266 267 pmu-a78 { 268 compatible = "arm,cortex-a78-pmu"; 269 interrupt-parent = <&gic>; 270 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 271 }; 272 273 psci { 274 compatible = "arm,psci-1.0"; 275 method = "smc"; 276 }; 277 278 timer: timer { 279 compatible = "arm,armv8-timer"; 280 interrupt-parent = <&gic>; 281 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 282 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 283 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 284 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 285 }; 286 287 soc { 288 #address-cells = <2>; 289 #size-cells = <2>; 290 compatible = "simple-bus"; 291 ranges; 292 293 gic: interrupt-controller@c000000 { 294 compatible = "arm,gic-v3"; 295 #interrupt-cells = <4>; 296 #redistributor-regions = <1>; 297 interrupt-parent = <&gic>; 298 interrupt-controller; 299 reg = <0 0x0c000000 0 0x40000>, 300 <0 0x0c040000 0 0x200000>; 301 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 302 303 ppi-partitions { 304 ppi_cluster0: interrupt-partition-0 { 305 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 306 }; 307 308 ppi_cluster1: interrupt-partition-1 { 309 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 310 }; 311 }; 312 }; 313 314 topckgen: syscon@10000000 { 315 compatible = "mediatek,mt8195-topckgen", "syscon"; 316 reg = <0 0x10000000 0 0x1000>; 317 #clock-cells = <1>; 318 }; 319 320 infracfg_ao: syscon@10001000 { 321 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; 322 reg = <0 0x10001000 0 0x1000>; 323 #clock-cells = <1>; 324 #reset-cells = <1>; 325 }; 326 327 pericfg: syscon@10003000 { 328 compatible = "mediatek,mt8195-pericfg", "syscon"; 329 reg = <0 0x10003000 0 0x1000>; 330 #clock-cells = <1>; 331 }; 332 333 pio: pinctrl@10005000 { 334 compatible = "mediatek,mt8195-pinctrl"; 335 reg = <0 0x10005000 0 0x1000>, 336 <0 0x11d10000 0 0x1000>, 337 <0 0x11d30000 0 0x1000>, 338 <0 0x11d40000 0 0x1000>, 339 <0 0x11e20000 0 0x1000>, 340 <0 0x11eb0000 0 0x1000>, 341 <0 0x11f40000 0 0x1000>, 342 <0 0x1000b000 0 0x1000>; 343 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 344 "iocfg_br", "iocfg_lm", "iocfg_rb", 345 "iocfg_tl", "eint"; 346 gpio-controller; 347 #gpio-cells = <2>; 348 gpio-ranges = <&pio 0 0 144>; 349 interrupt-controller; 350 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 351 #interrupt-cells = <2>; 352 }; 353 354 scpsys: syscon@10006000 { 355 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; 356 reg = <0 0x10006000 0 0x1000>; 357 358 /* System Power Manager */ 359 spm: power-controller { 360 compatible = "mediatek,mt8195-power-controller"; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 #power-domain-cells = <1>; 364 365 /* power domain of the SoC */ 366 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { 367 reg = <MT8195_POWER_DOMAIN_MFG0>; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 #power-domain-cells = <1>; 371 372 power-domain@MT8195_POWER_DOMAIN_MFG1 { 373 reg = <MT8195_POWER_DOMAIN_MFG1>; 374 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>; 375 clock-names = "mfg"; 376 mediatek,infracfg = <&infracfg_ao>; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 #power-domain-cells = <1>; 380 381 power-domain@MT8195_POWER_DOMAIN_MFG2 { 382 reg = <MT8195_POWER_DOMAIN_MFG2>; 383 #power-domain-cells = <0>; 384 }; 385 386 power-domain@MT8195_POWER_DOMAIN_MFG3 { 387 reg = <MT8195_POWER_DOMAIN_MFG3>; 388 #power-domain-cells = <0>; 389 }; 390 391 power-domain@MT8195_POWER_DOMAIN_MFG4 { 392 reg = <MT8195_POWER_DOMAIN_MFG4>; 393 #power-domain-cells = <0>; 394 }; 395 396 power-domain@MT8195_POWER_DOMAIN_MFG5 { 397 reg = <MT8195_POWER_DOMAIN_MFG5>; 398 #power-domain-cells = <0>; 399 }; 400 401 power-domain@MT8195_POWER_DOMAIN_MFG6 { 402 reg = <MT8195_POWER_DOMAIN_MFG6>; 403 #power-domain-cells = <0>; 404 }; 405 }; 406 }; 407 408 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { 409 reg = <MT8195_POWER_DOMAIN_VPPSYS0>; 410 clocks = <&topckgen CLK_TOP_VPP>, 411 <&topckgen CLK_TOP_CAM>, 412 <&topckgen CLK_TOP_CCU>, 413 <&topckgen CLK_TOP_IMG>, 414 <&topckgen CLK_TOP_VENC>, 415 <&topckgen CLK_TOP_VDEC>, 416 <&topckgen CLK_TOP_WPE_VPP>, 417 <&topckgen CLK_TOP_CFG_VPP0>, 418 <&vppsys0 CLK_VPP0_SMI_COMMON>, 419 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, 420 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, 421 <&vppsys0 CLK_VPP0_GALS_VENCSYS>, 422 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, 423 <&vppsys0 CLK_VPP0_GALS_INFRA>, 424 <&vppsys0 CLK_VPP0_GALS_CAMSYS>, 425 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, 426 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, 427 <&vppsys0 CLK_VPP0_SMI_REORDER>, 428 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 429 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 430 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 431 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 432 <&vppsys0 CLK_VPP0_SMI_RSI>, 433 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 434 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 435 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 436 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 437 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", 438 "vppsys4", "vppsys5", "vppsys6", "vppsys7", 439 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", 440 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", 441 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", 442 "vppsys0-12", "vppsys0-13", "vppsys0-14", 443 "vppsys0-15", "vppsys0-16", "vppsys0-17", 444 "vppsys0-18"; 445 mediatek,infracfg = <&infracfg_ao>; 446 #address-cells = <1>; 447 #size-cells = <0>; 448 #power-domain-cells = <1>; 449 450 power-domain@MT8195_POWER_DOMAIN_VDEC1 { 451 reg = <MT8195_POWER_DOMAIN_VDEC1>; 452 clocks = <&vdecsys CLK_VDEC_LARB1>; 453 clock-names = "vdec1-0"; 454 mediatek,infracfg = <&infracfg_ao>; 455 #power-domain-cells = <0>; 456 }; 457 458 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { 459 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; 460 mediatek,infracfg = <&infracfg_ao>; 461 #power-domain-cells = <0>; 462 }; 463 464 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { 465 reg = <MT8195_POWER_DOMAIN_VDOSYS0>; 466 clocks = <&topckgen CLK_TOP_CFG_VDO0>, 467 <&vdosys0 CLK_VDO0_SMI_GALS>, 468 <&vdosys0 CLK_VDO0_SMI_COMMON>, 469 <&vdosys0 CLK_VDO0_SMI_EMI>, 470 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 471 <&vdosys0 CLK_VDO0_SMI_LARB>, 472 <&vdosys0 CLK_VDO0_SMI_RSI>; 473 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", 474 "vdosys0-2", "vdosys0-3", 475 "vdosys0-4", "vdosys0-5"; 476 mediatek,infracfg = <&infracfg_ao>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 #power-domain-cells = <1>; 480 481 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { 482 reg = <MT8195_POWER_DOMAIN_VPPSYS1>; 483 clocks = <&topckgen CLK_TOP_CFG_VPP1>, 484 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 485 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; 486 clock-names = "vppsys1", "vppsys1-0", 487 "vppsys1-1"; 488 mediatek,infracfg = <&infracfg_ao>; 489 #power-domain-cells = <0>; 490 }; 491 492 power-domain@MT8195_POWER_DOMAIN_WPESYS { 493 reg = <MT8195_POWER_DOMAIN_WPESYS>; 494 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 495 <&wpesys CLK_WPE_SMI_LARB8>, 496 <&wpesys CLK_WPE_SMI_LARB7_P>, 497 <&wpesys CLK_WPE_SMI_LARB8_P>; 498 clock-names = "wepsys-0", "wepsys-1", "wepsys-2", 499 "wepsys-3"; 500 mediatek,infracfg = <&infracfg_ao>; 501 #power-domain-cells = <0>; 502 }; 503 504 power-domain@MT8195_POWER_DOMAIN_VDEC0 { 505 reg = <MT8195_POWER_DOMAIN_VDEC0>; 506 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 507 clock-names = "vdec0-0"; 508 mediatek,infracfg = <&infracfg_ao>; 509 #power-domain-cells = <0>; 510 }; 511 512 power-domain@MT8195_POWER_DOMAIN_VDEC2 { 513 reg = <MT8195_POWER_DOMAIN_VDEC2>; 514 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 515 clock-names = "vdec2-0"; 516 mediatek,infracfg = <&infracfg_ao>; 517 #power-domain-cells = <0>; 518 }; 519 520 power-domain@MT8195_POWER_DOMAIN_VENC { 521 reg = <MT8195_POWER_DOMAIN_VENC>; 522 mediatek,infracfg = <&infracfg_ao>; 523 #power-domain-cells = <0>; 524 }; 525 526 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { 527 reg = <MT8195_POWER_DOMAIN_VDOSYS1>; 528 clocks = <&topckgen CLK_TOP_CFG_VDO1>, 529 <&vdosys1 CLK_VDO1_SMI_LARB2>, 530 <&vdosys1 CLK_VDO1_SMI_LARB3>, 531 <&vdosys1 CLK_VDO1_GALS>; 532 clock-names = "vdosys1", "vdosys1-0", 533 "vdosys1-1", "vdosys1-2"; 534 mediatek,infracfg = <&infracfg_ao>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 #power-domain-cells = <1>; 538 539 power-domain@MT8195_POWER_DOMAIN_DP_TX { 540 reg = <MT8195_POWER_DOMAIN_DP_TX>; 541 mediatek,infracfg = <&infracfg_ao>; 542 #power-domain-cells = <0>; 543 }; 544 545 power-domain@MT8195_POWER_DOMAIN_EPD_TX { 546 reg = <MT8195_POWER_DOMAIN_EPD_TX>; 547 mediatek,infracfg = <&infracfg_ao>; 548 #power-domain-cells = <0>; 549 }; 550 551 power-domain@MT8195_POWER_DOMAIN_HDMI_TX { 552 reg = <MT8195_POWER_DOMAIN_HDMI_TX>; 553 clocks = <&topckgen CLK_TOP_HDMI_APB>; 554 clock-names = "hdmi_tx"; 555 #power-domain-cells = <0>; 556 }; 557 }; 558 559 power-domain@MT8195_POWER_DOMAIN_IMG { 560 reg = <MT8195_POWER_DOMAIN_IMG>; 561 clocks = <&imgsys CLK_IMG_LARB9>, 562 <&imgsys CLK_IMG_GALS>; 563 clock-names = "img-0", "img-1"; 564 mediatek,infracfg = <&infracfg_ao>; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 #power-domain-cells = <1>; 568 569 power-domain@MT8195_POWER_DOMAIN_DIP { 570 reg = <MT8195_POWER_DOMAIN_DIP>; 571 #power-domain-cells = <0>; 572 }; 573 574 power-domain@MT8195_POWER_DOMAIN_IPE { 575 reg = <MT8195_POWER_DOMAIN_IPE>; 576 clocks = <&topckgen CLK_TOP_IPE>, 577 <&imgsys CLK_IMG_IPE>, 578 <&ipesys CLK_IPE_SMI_LARB12>; 579 clock-names = "ipe", "ipe-0", "ipe-1"; 580 mediatek,infracfg = <&infracfg_ao>; 581 #power-domain-cells = <0>; 582 }; 583 }; 584 585 power-domain@MT8195_POWER_DOMAIN_CAM { 586 reg = <MT8195_POWER_DOMAIN_CAM>; 587 clocks = <&camsys CLK_CAM_LARB13>, 588 <&camsys CLK_CAM_LARB14>, 589 <&camsys CLK_CAM_CAM2MM0_GALS>, 590 <&camsys CLK_CAM_CAM2MM1_GALS>, 591 <&camsys CLK_CAM_CAM2SYS_GALS>; 592 clock-names = "cam-0", "cam-1", "cam-2", "cam-3", 593 "cam-4"; 594 mediatek,infracfg = <&infracfg_ao>; 595 #address-cells = <1>; 596 #size-cells = <0>; 597 #power-domain-cells = <1>; 598 599 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { 600 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; 601 #power-domain-cells = <0>; 602 }; 603 604 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { 605 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; 606 #power-domain-cells = <0>; 607 }; 608 609 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { 610 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; 611 #power-domain-cells = <0>; 612 }; 613 }; 614 }; 615 }; 616 617 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { 618 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 619 mediatek,infracfg = <&infracfg_ao>; 620 #power-domain-cells = <0>; 621 }; 622 623 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { 624 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 625 mediatek,infracfg = <&infracfg_ao>; 626 #power-domain-cells = <0>; 627 }; 628 629 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { 630 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; 631 #power-domain-cells = <0>; 632 }; 633 634 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { 635 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 636 #power-domain-cells = <0>; 637 }; 638 639 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { 640 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; 641 clocks = <&topckgen CLK_TOP_SENINF>, 642 <&topckgen CLK_TOP_SENINF2>; 643 clock-names = "csi_rx_top", "csi_rx_top1"; 644 #power-domain-cells = <0>; 645 }; 646 647 power-domain@MT8195_POWER_DOMAIN_ETHER { 648 reg = <MT8195_POWER_DOMAIN_ETHER>; 649 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 650 clock-names = "ether"; 651 #power-domain-cells = <0>; 652 }; 653 654 power-domain@MT8195_POWER_DOMAIN_ADSP { 655 reg = <MT8195_POWER_DOMAIN_ADSP>; 656 clocks = <&topckgen CLK_TOP_ADSP>, 657 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 658 clock-names = "adsp", "adsp1"; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 mediatek,infracfg = <&infracfg_ao>; 662 #power-domain-cells = <1>; 663 664 power-domain@MT8195_POWER_DOMAIN_AUDIO { 665 reg = <MT8195_POWER_DOMAIN_AUDIO>; 666 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 667 <&topckgen CLK_TOP_AUD_INTBUS>, 668 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 669 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; 670 clock-names = "audio", "audio1", "audio2", 671 "audio3"; 672 mediatek,infracfg = <&infracfg_ao>; 673 #power-domain-cells = <0>; 674 }; 675 }; 676 }; 677 }; 678 679 watchdog: watchdog@10007000 { 680 compatible = "mediatek,mt8195-wdt", 681 "mediatek,mt6589-wdt"; 682 mediatek,disable-extrst; 683 reg = <0 0x10007000 0 0x100>; 684 #reset-cells = <1>; 685 }; 686 687 apmixedsys: syscon@1000c000 { 688 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 689 reg = <0 0x1000c000 0 0x1000>; 690 #clock-cells = <1>; 691 }; 692 693 systimer: timer@10017000 { 694 compatible = "mediatek,mt8195-timer", 695 "mediatek,mt6765-timer"; 696 reg = <0 0x10017000 0 0x1000>; 697 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 698 clocks = <&topckgen CLK_TOP_CLK26M_D2>; 699 }; 700 701 pwrap: pwrap@10024000 { 702 compatible = "mediatek,mt8195-pwrap", "syscon"; 703 reg = <0 0x10024000 0 0x1000>; 704 reg-names = "pwrap"; 705 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 706 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 707 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 708 clock-names = "spi", "wrap"; 709 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 710 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 711 }; 712 713 spmi: spmi@10027000 { 714 compatible = "mediatek,mt8195-spmi"; 715 reg = <0 0x10027000 0 0x000e00>, 716 <0 0x10029000 0 0x000100>; 717 reg-names = "pmif", "spmimst"; 718 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 719 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 720 <&topckgen CLK_TOP_SPMI_M_MST>; 721 clock-names = "pmif_sys_ck", 722 "pmif_tmr_ck", 723 "spmimst_clk_mux"; 724 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 725 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 726 }; 727 728 iommu_infra: infra-iommu@10315000 { 729 compatible = "mediatek,mt8195-iommu-infra"; 730 reg = <0 0x10315000 0 0x5000>; 731 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>, 732 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>, 733 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>, 734 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>, 735 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>; 736 #iommu-cells = <1>; 737 }; 738 739 scp: scp@10500000 { 740 compatible = "mediatek,mt8195-scp"; 741 reg = <0 0x10500000 0 0x100000>, 742 <0 0x10720000 0 0xe0000>, 743 <0 0x10700000 0 0x8000>; 744 reg-names = "sram", "cfg", "l1tcm"; 745 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 746 status = "disabled"; 747 }; 748 749 scp_adsp: clock-controller@10720000 { 750 compatible = "mediatek,mt8195-scp_adsp"; 751 reg = <0 0x10720000 0 0x1000>; 752 #clock-cells = <1>; 753 }; 754 755 adsp: dsp@10803000 { 756 compatible = "mediatek,mt8195-dsp"; 757 reg = <0 0x10803000 0 0x1000>, 758 <0 0x10840000 0 0x40000>; 759 reg-names = "cfg", "sram"; 760 clocks = <&topckgen CLK_TOP_ADSP>, 761 <&clk26m>, 762 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 763 <&topckgen CLK_TOP_MAINPLL_D7_D2>, 764 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, 765 <&topckgen CLK_TOP_AUDIO_H>; 766 clock-names = "adsp_sel", 767 "clk26m_ck", 768 "audio_local_bus", 769 "mainpll_d7_d2", 770 "scp_adsp_audiodsp", 771 "audio_h"; 772 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; 773 mbox-names = "rx", "tx"; 774 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 775 status = "disabled"; 776 }; 777 778 adsp_mailbox0: mailbox@10816000 { 779 compatible = "mediatek,mt8195-adsp-mbox"; 780 #mbox-cells = <0>; 781 reg = <0 0x10816000 0 0x1000>; 782 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; 783 }; 784 785 adsp_mailbox1: mailbox@10817000 { 786 compatible = "mediatek,mt8195-adsp-mbox"; 787 #mbox-cells = <0>; 788 reg = <0 0x10817000 0 0x1000>; 789 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; 790 }; 791 792 afe: mt8195-afe-pcm@10890000 { 793 compatible = "mediatek,mt8195-audio"; 794 reg = <0 0x10890000 0 0x10000>; 795 mediatek,topckgen = <&topckgen>; 796 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; 797 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 798 resets = <&watchdog 14>; 799 reset-names = "audiosys"; 800 clocks = <&clk26m>, 801 <&apmixedsys CLK_APMIXED_APLL1>, 802 <&apmixedsys CLK_APMIXED_APLL2>, 803 <&topckgen CLK_TOP_APLL12_DIV0>, 804 <&topckgen CLK_TOP_APLL12_DIV1>, 805 <&topckgen CLK_TOP_APLL12_DIV2>, 806 <&topckgen CLK_TOP_APLL12_DIV3>, 807 <&topckgen CLK_TOP_APLL12_DIV9>, 808 <&topckgen CLK_TOP_A1SYS_HP>, 809 <&topckgen CLK_TOP_AUD_INTBUS>, 810 <&topckgen CLK_TOP_AUDIO_H>, 811 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 812 <&topckgen CLK_TOP_DPTX_MCK>, 813 <&topckgen CLK_TOP_I2SO1_MCK>, 814 <&topckgen CLK_TOP_I2SO2_MCK>, 815 <&topckgen CLK_TOP_I2SI1_MCK>, 816 <&topckgen CLK_TOP_I2SI2_MCK>, 817 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, 818 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; 819 clock-names = "clk26m", 820 "apll1_ck", 821 "apll2_ck", 822 "apll12_div0", 823 "apll12_div1", 824 "apll12_div2", 825 "apll12_div3", 826 "apll12_div9", 827 "a1sys_hp_sel", 828 "aud_intbus_sel", 829 "audio_h_sel", 830 "audio_local_bus_sel", 831 "dptx_m_sel", 832 "i2so1_m_sel", 833 "i2so2_m_sel", 834 "i2si1_m_sel", 835 "i2si2_m_sel", 836 "infra_ao_audio_26m_b", 837 "scp_adsp_audiodsp"; 838 status = "disabled"; 839 }; 840 841 uart0: serial@11001100 { 842 compatible = "mediatek,mt8195-uart", 843 "mediatek,mt6577-uart"; 844 reg = <0 0x11001100 0 0x100>; 845 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 846 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 847 clock-names = "baud", "bus"; 848 status = "disabled"; 849 }; 850 851 uart1: serial@11001200 { 852 compatible = "mediatek,mt8195-uart", 853 "mediatek,mt6577-uart"; 854 reg = <0 0x11001200 0 0x100>; 855 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 856 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 857 clock-names = "baud", "bus"; 858 status = "disabled"; 859 }; 860 861 uart2: serial@11001300 { 862 compatible = "mediatek,mt8195-uart", 863 "mediatek,mt6577-uart"; 864 reg = <0 0x11001300 0 0x100>; 865 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 866 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 867 clock-names = "baud", "bus"; 868 status = "disabled"; 869 }; 870 871 uart3: serial@11001400 { 872 compatible = "mediatek,mt8195-uart", 873 "mediatek,mt6577-uart"; 874 reg = <0 0x11001400 0 0x100>; 875 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 876 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 877 clock-names = "baud", "bus"; 878 status = "disabled"; 879 }; 880 881 uart4: serial@11001500 { 882 compatible = "mediatek,mt8195-uart", 883 "mediatek,mt6577-uart"; 884 reg = <0 0x11001500 0 0x100>; 885 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 886 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 887 clock-names = "baud", "bus"; 888 status = "disabled"; 889 }; 890 891 uart5: serial@11001600 { 892 compatible = "mediatek,mt8195-uart", 893 "mediatek,mt6577-uart"; 894 reg = <0 0x11001600 0 0x100>; 895 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 896 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 897 clock-names = "baud", "bus"; 898 status = "disabled"; 899 }; 900 901 auxadc: auxadc@11002000 { 902 compatible = "mediatek,mt8195-auxadc", 903 "mediatek,mt8173-auxadc"; 904 reg = <0 0x11002000 0 0x1000>; 905 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 906 clock-names = "main"; 907 #io-channel-cells = <1>; 908 status = "disabled"; 909 }; 910 911 pericfg_ao: syscon@11003000 { 912 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 913 reg = <0 0x11003000 0 0x1000>; 914 #clock-cells = <1>; 915 }; 916 917 spi0: spi@1100a000 { 918 compatible = "mediatek,mt8195-spi", 919 "mediatek,mt6765-spi"; 920 #address-cells = <1>; 921 #size-cells = <0>; 922 reg = <0 0x1100a000 0 0x1000>; 923 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 924 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 925 <&topckgen CLK_TOP_SPI>, 926 <&infracfg_ao CLK_INFRA_AO_SPI0>; 927 clock-names = "parent-clk", "sel-clk", "spi-clk"; 928 status = "disabled"; 929 }; 930 931 spi1: spi@11010000 { 932 compatible = "mediatek,mt8195-spi", 933 "mediatek,mt6765-spi"; 934 #address-cells = <1>; 935 #size-cells = <0>; 936 reg = <0 0x11010000 0 0x1000>; 937 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 938 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 939 <&topckgen CLK_TOP_SPI>, 940 <&infracfg_ao CLK_INFRA_AO_SPI1>; 941 clock-names = "parent-clk", "sel-clk", "spi-clk"; 942 status = "disabled"; 943 }; 944 945 spi2: spi@11012000 { 946 compatible = "mediatek,mt8195-spi", 947 "mediatek,mt6765-spi"; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 reg = <0 0x11012000 0 0x1000>; 951 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 952 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 953 <&topckgen CLK_TOP_SPI>, 954 <&infracfg_ao CLK_INFRA_AO_SPI2>; 955 clock-names = "parent-clk", "sel-clk", "spi-clk"; 956 status = "disabled"; 957 }; 958 959 spi3: spi@11013000 { 960 compatible = "mediatek,mt8195-spi", 961 "mediatek,mt6765-spi"; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 reg = <0 0x11013000 0 0x1000>; 965 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 966 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 967 <&topckgen CLK_TOP_SPI>, 968 <&infracfg_ao CLK_INFRA_AO_SPI3>; 969 clock-names = "parent-clk", "sel-clk", "spi-clk"; 970 status = "disabled"; 971 }; 972 973 spi4: spi@11018000 { 974 compatible = "mediatek,mt8195-spi", 975 "mediatek,mt6765-spi"; 976 #address-cells = <1>; 977 #size-cells = <0>; 978 reg = <0 0x11018000 0 0x1000>; 979 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 980 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 981 <&topckgen CLK_TOP_SPI>, 982 <&infracfg_ao CLK_INFRA_AO_SPI4>; 983 clock-names = "parent-clk", "sel-clk", "spi-clk"; 984 status = "disabled"; 985 }; 986 987 spi5: spi@11019000 { 988 compatible = "mediatek,mt8195-spi", 989 "mediatek,mt6765-spi"; 990 #address-cells = <1>; 991 #size-cells = <0>; 992 reg = <0 0x11019000 0 0x1000>; 993 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 994 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 995 <&topckgen CLK_TOP_SPI>, 996 <&infracfg_ao CLK_INFRA_AO_SPI5>; 997 clock-names = "parent-clk", "sel-clk", "spi-clk"; 998 status = "disabled"; 999 }; 1000 1001 spis0: spi@1101d000 { 1002 compatible = "mediatek,mt8195-spi-slave"; 1003 reg = <0 0x1101d000 0 0x1000>; 1004 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 1005 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 1006 clock-names = "spi"; 1007 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1008 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1009 status = "disabled"; 1010 }; 1011 1012 spis1: spi@1101e000 { 1013 compatible = "mediatek,mt8195-spi-slave"; 1014 reg = <0 0x1101e000 0 0x1000>; 1015 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 1016 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 1017 clock-names = "spi"; 1018 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1019 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1020 status = "disabled"; 1021 }; 1022 1023 xhci0: usb@11200000 { 1024 compatible = "mediatek,mt8195-xhci", 1025 "mediatek,mtk-xhci"; 1026 reg = <0 0x11200000 0 0x1000>, 1027 <0 0x11203e00 0 0x0100>; 1028 reg-names = "mac", "ippc"; 1029 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1030 phys = <&u2port0 PHY_TYPE_USB2>, 1031 <&u3port0 PHY_TYPE_USB3>; 1032 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1033 <&topckgen CLK_TOP_SSUSB_XHCI>; 1034 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1035 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1036 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1037 <&topckgen CLK_TOP_SSUSB_REF>, 1038 <&apmixedsys CLK_APMIXED_USB1PLL>, 1039 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1040 clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck"; 1041 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 1042 wakeup-source; 1043 status = "disabled"; 1044 }; 1045 1046 mmc0: mmc@11230000 { 1047 compatible = "mediatek,mt8195-mmc", 1048 "mediatek,mt8183-mmc"; 1049 reg = <0 0x11230000 0 0x10000>, 1050 <0 0x11f50000 0 0x1000>; 1051 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1052 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1053 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1054 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 1055 clock-names = "source", "hclk", "source_cg"; 1056 status = "disabled"; 1057 }; 1058 1059 mmc1: mmc@11240000 { 1060 compatible = "mediatek,mt8195-mmc", 1061 "mediatek,mt8183-mmc"; 1062 reg = <0 0x11240000 0 0x1000>, 1063 <0 0x11c70000 0 0x1000>; 1064 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1065 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1066 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1067 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1068 clock-names = "source", "hclk", "source_cg"; 1069 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1070 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1071 status = "disabled"; 1072 }; 1073 1074 mmc2: mmc@11250000 { 1075 compatible = "mediatek,mt8195-mmc", 1076 "mediatek,mt8183-mmc"; 1077 reg = <0 0x11250000 0 0x1000>, 1078 <0 0x11e60000 0 0x1000>; 1079 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1080 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1081 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 1082 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 1083 clock-names = "source", "hclk", "source_cg"; 1084 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1085 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1086 status = "disabled"; 1087 }; 1088 1089 xhci1: usb@11290000 { 1090 compatible = "mediatek,mt8195-xhci", 1091 "mediatek,mtk-xhci"; 1092 reg = <0 0x11290000 0 0x1000>, 1093 <0 0x11293e00 0 0x0100>; 1094 reg-names = "mac", "ippc"; 1095 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1096 phys = <&u2port1 PHY_TYPE_USB2>; 1097 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 1098 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 1099 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1100 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1101 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 1102 <&topckgen CLK_TOP_SSUSB_P1_REF>, 1103 <&apmixedsys CLK_APMIXED_USB1PLL>, 1104 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 1105 clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck"; 1106 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 1107 wakeup-source; 1108 status = "disabled"; 1109 }; 1110 1111 xhci2: usb@112a0000 { 1112 compatible = "mediatek,mt8195-xhci", 1113 "mediatek,mtk-xhci"; 1114 reg = <0 0x112a0000 0 0x1000>, 1115 <0 0x112a3e00 0 0x0100>; 1116 reg-names = "mac", "ippc"; 1117 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1118 phys = <&u2port2 PHY_TYPE_USB2>; 1119 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, 1120 <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1121 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1122 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1123 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1124 <&topckgen CLK_TOP_SSUSB_P2_REF>, 1125 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1126 clock-names = "sys_ck", "ref_ck", "xhci_ck"; 1127 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 1128 wakeup-source; 1129 status = "disabled"; 1130 }; 1131 1132 xhci3: usb@112b0000 { 1133 compatible = "mediatek,mt8195-xhci", 1134 "mediatek,mtk-xhci"; 1135 reg = <0 0x112b0000 0 0x1000>, 1136 <0 0x112b3e00 0 0x0100>; 1137 reg-names = "mac", "ippc"; 1138 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1139 phys = <&u2port3 PHY_TYPE_USB2>; 1140 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, 1141 <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1142 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1143 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1144 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1145 <&topckgen CLK_TOP_SSUSB_P3_REF>, 1146 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1147 clock-names = "sys_ck", "ref_ck", "xhci_ck"; 1148 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 1149 wakeup-source; 1150 status = "disabled"; 1151 }; 1152 1153 nor_flash: spi@1132c000 { 1154 compatible = "mediatek,mt8195-nor", 1155 "mediatek,mt8173-nor"; 1156 reg = <0 0x1132c000 0 0x1000>; 1157 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1158 clocks = <&topckgen CLK_TOP_SPINOR>, 1159 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 1160 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1161 clock-names = "spi", "sf", "axi"; 1162 #address-cells = <1>; 1163 #size-cells = <0>; 1164 status = "disabled"; 1165 }; 1166 1167 efuse: efuse@11c10000 { 1168 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 1169 reg = <0 0x11c10000 0 0x1000>; 1170 #address-cells = <1>; 1171 #size-cells = <1>; 1172 u3_tx_imp_p0: usb3-tx-imp@184,1 { 1173 reg = <0x184 0x1>; 1174 bits = <0 5>; 1175 }; 1176 u3_rx_imp_p0: usb3-rx-imp@184,2 { 1177 reg = <0x184 0x2>; 1178 bits = <5 5>; 1179 }; 1180 u3_intr_p0: usb3-intr@185 { 1181 reg = <0x185 0x1>; 1182 bits = <2 6>; 1183 }; 1184 comb_tx_imp_p1: usb3-tx-imp@186,1 { 1185 reg = <0x186 0x1>; 1186 bits = <0 5>; 1187 }; 1188 comb_rx_imp_p1: usb3-rx-imp@186,2 { 1189 reg = <0x186 0x2>; 1190 bits = <5 5>; 1191 }; 1192 comb_intr_p1: usb3-intr@187 { 1193 reg = <0x187 0x1>; 1194 bits = <2 6>; 1195 }; 1196 u2_intr_p0: usb2-intr-p0@188,1 { 1197 reg = <0x188 0x1>; 1198 bits = <0 5>; 1199 }; 1200 u2_intr_p1: usb2-intr-p1@188,2 { 1201 reg = <0x188 0x2>; 1202 bits = <5 5>; 1203 }; 1204 u2_intr_p2: usb2-intr-p2@189,1 { 1205 reg = <0x189 0x1>; 1206 bits = <2 5>; 1207 }; 1208 u2_intr_p3: usb2-intr-p3@189,2 { 1209 reg = <0x189 0x2>; 1210 bits = <7 5>; 1211 }; 1212 }; 1213 1214 u3phy2: t-phy@11c40000 { 1215 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1216 #address-cells = <1>; 1217 #size-cells = <1>; 1218 ranges = <0 0 0x11c40000 0x700>; 1219 status = "disabled"; 1220 1221 u2port2: usb-phy@0 { 1222 reg = <0x0 0x700>; 1223 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 1224 clock-names = "ref"; 1225 #phy-cells = <1>; 1226 }; 1227 }; 1228 1229 u3phy3: t-phy@11c50000 { 1230 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1231 #address-cells = <1>; 1232 #size-cells = <1>; 1233 ranges = <0 0 0x11c50000 0x700>; 1234 status = "disabled"; 1235 1236 u2port3: usb-phy@0 { 1237 reg = <0x0 0x700>; 1238 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 1239 clock-names = "ref"; 1240 #phy-cells = <1>; 1241 }; 1242 }; 1243 1244 i2c5: i2c@11d00000 { 1245 compatible = "mediatek,mt8195-i2c", 1246 "mediatek,mt8192-i2c"; 1247 reg = <0 0x11d00000 0 0x1000>, 1248 <0 0x10220580 0 0x80>; 1249 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 1250 clock-div = <1>; 1251 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 1252 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1253 clock-names = "main", "dma"; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 status = "disabled"; 1257 }; 1258 1259 i2c6: i2c@11d01000 { 1260 compatible = "mediatek,mt8195-i2c", 1261 "mediatek,mt8192-i2c"; 1262 reg = <0 0x11d01000 0 0x1000>, 1263 <0 0x10220600 0 0x80>; 1264 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 1265 clock-div = <1>; 1266 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 1267 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1268 clock-names = "main", "dma"; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 status = "disabled"; 1272 }; 1273 1274 i2c7: i2c@11d02000 { 1275 compatible = "mediatek,mt8195-i2c", 1276 "mediatek,mt8192-i2c"; 1277 reg = <0 0x11d02000 0 0x1000>, 1278 <0 0x10220680 0 0x80>; 1279 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1280 clock-div = <1>; 1281 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1282 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1283 clock-names = "main", "dma"; 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 status = "disabled"; 1287 }; 1288 1289 imp_iic_wrap_s: clock-controller@11d03000 { 1290 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 1291 reg = <0 0x11d03000 0 0x1000>; 1292 #clock-cells = <1>; 1293 }; 1294 1295 i2c0: i2c@11e00000 { 1296 compatible = "mediatek,mt8195-i2c", 1297 "mediatek,mt8192-i2c"; 1298 reg = <0 0x11e00000 0 0x1000>, 1299 <0 0x10220080 0 0x80>; 1300 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 1301 clock-div = <1>; 1302 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 1303 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1304 clock-names = "main", "dma"; 1305 #address-cells = <1>; 1306 #size-cells = <0>; 1307 status = "disabled"; 1308 }; 1309 1310 i2c1: i2c@11e01000 { 1311 compatible = "mediatek,mt8195-i2c", 1312 "mediatek,mt8192-i2c"; 1313 reg = <0 0x11e01000 0 0x1000>, 1314 <0 0x10220200 0 0x80>; 1315 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1316 clock-div = <1>; 1317 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 1318 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1319 clock-names = "main", "dma"; 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 status = "disabled"; 1323 }; 1324 1325 i2c2: i2c@11e02000 { 1326 compatible = "mediatek,mt8195-i2c", 1327 "mediatek,mt8192-i2c"; 1328 reg = <0 0x11e02000 0 0x1000>, 1329 <0 0x10220380 0 0x80>; 1330 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1331 clock-div = <1>; 1332 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 1333 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1334 clock-names = "main", "dma"; 1335 #address-cells = <1>; 1336 #size-cells = <0>; 1337 status = "disabled"; 1338 }; 1339 1340 i2c3: i2c@11e03000 { 1341 compatible = "mediatek,mt8195-i2c", 1342 "mediatek,mt8192-i2c"; 1343 reg = <0 0x11e03000 0 0x1000>, 1344 <0 0x10220480 0 0x80>; 1345 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1346 clock-div = <1>; 1347 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 1348 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1349 clock-names = "main", "dma"; 1350 #address-cells = <1>; 1351 #size-cells = <0>; 1352 status = "disabled"; 1353 }; 1354 1355 i2c4: i2c@11e04000 { 1356 compatible = "mediatek,mt8195-i2c", 1357 "mediatek,mt8192-i2c"; 1358 reg = <0 0x11e04000 0 0x1000>, 1359 <0 0x10220500 0 0x80>; 1360 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 1361 clock-div = <1>; 1362 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 1363 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1364 clock-names = "main", "dma"; 1365 #address-cells = <1>; 1366 #size-cells = <0>; 1367 status = "disabled"; 1368 }; 1369 1370 imp_iic_wrap_w: clock-controller@11e05000 { 1371 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 1372 reg = <0 0x11e05000 0 0x1000>; 1373 #clock-cells = <1>; 1374 }; 1375 1376 u3phy1: t-phy@11e30000 { 1377 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1378 #address-cells = <1>; 1379 #size-cells = <1>; 1380 ranges = <0 0 0x11e30000 0xe00>; 1381 status = "disabled"; 1382 1383 u2port1: usb-phy@0 { 1384 reg = <0x0 0x700>; 1385 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 1386 <&clk26m>; 1387 clock-names = "ref", "da_ref"; 1388 #phy-cells = <1>; 1389 }; 1390 1391 u3port1: usb-phy@700 { 1392 reg = <0x700 0x700>; 1393 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1394 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 1395 clock-names = "ref", "da_ref"; 1396 nvmem-cells = <&comb_intr_p1>, 1397 <&comb_rx_imp_p1>, 1398 <&comb_tx_imp_p1>; 1399 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1400 #phy-cells = <1>; 1401 }; 1402 }; 1403 1404 u3phy0: t-phy@11e40000 { 1405 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1406 #address-cells = <1>; 1407 #size-cells = <1>; 1408 ranges = <0 0 0x11e40000 0xe00>; 1409 status = "disabled"; 1410 1411 u2port0: usb-phy@0 { 1412 reg = <0x0 0x700>; 1413 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1414 <&clk26m>; 1415 clock-names = "ref", "da_ref"; 1416 #phy-cells = <1>; 1417 }; 1418 1419 u3port0: usb-phy@700 { 1420 reg = <0x700 0x700>; 1421 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1422 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 1423 clock-names = "ref", "da_ref"; 1424 nvmem-cells = <&u3_intr_p0>, 1425 <&u3_rx_imp_p0>, 1426 <&u3_tx_imp_p0>; 1427 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1428 #phy-cells = <1>; 1429 }; 1430 }; 1431 1432 ufsphy: ufs-phy@11fa0000 { 1433 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 1434 reg = <0 0x11fa0000 0 0xc000>; 1435 clocks = <&clk26m>, <&clk26m>; 1436 clock-names = "unipro", "mp"; 1437 #phy-cells = <0>; 1438 status = "disabled"; 1439 }; 1440 1441 mfgcfg: clock-controller@13fbf000 { 1442 compatible = "mediatek,mt8195-mfgcfg"; 1443 reg = <0 0x13fbf000 0 0x1000>; 1444 #clock-cells = <1>; 1445 }; 1446 1447 vppsys0: clock-controller@14000000 { 1448 compatible = "mediatek,mt8195-vppsys0"; 1449 reg = <0 0x14000000 0 0x1000>; 1450 #clock-cells = <1>; 1451 }; 1452 1453 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { 1454 compatible = "mediatek,mt8195-smi-sub-common"; 1455 reg = <0 0x14010000 0 0x1000>; 1456 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1457 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1458 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 1459 clock-names = "apb", "smi", "gals0"; 1460 mediatek,smi = <&smi_common_vpp>; 1461 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1462 }; 1463 1464 smi_sub_common_vdec_vpp0_2x1: smi@14011000 { 1465 compatible = "mediatek,mt8195-smi-sub-common"; 1466 reg = <0 0x14011000 0 0x1000>; 1467 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1468 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1469 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>; 1470 clock-names = "apb", "smi", "gals0"; 1471 mediatek,smi = <&smi_common_vpp>; 1472 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1473 }; 1474 1475 smi_common_vpp: smi@14012000 { 1476 compatible = "mediatek,mt8195-smi-common-vpp"; 1477 reg = <0 0x14012000 0 0x1000>; 1478 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1479 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1480 <&vppsys0 CLK_VPP0_SMI_RSI>, 1481 <&vppsys0 CLK_VPP0_SMI_RSI>; 1482 clock-names = "apb", "smi", "gals0", "gals1"; 1483 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1484 }; 1485 1486 larb4: larb@14013000 { 1487 compatible = "mediatek,mt8195-smi-larb"; 1488 reg = <0 0x14013000 0 0x1000>; 1489 mediatek,larb-id = <4>; 1490 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 1491 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1492 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 1493 clock-names = "apb", "smi"; 1494 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1495 }; 1496 1497 iommu_vpp: iommu@14018000 { 1498 compatible = "mediatek,mt8195-iommu-vpp"; 1499 reg = <0 0x14018000 0 0x1000>; 1500 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8 1501 &larb12 &larb14 &larb16 &larb18 1502 &larb20 &larb22 &larb23 &larb26 1503 &larb27>; 1504 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 1505 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 1506 clock-names = "bclk"; 1507 #iommu-cells = <1>; 1508 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1509 }; 1510 1511 wpesys: clock-controller@14e00000 { 1512 compatible = "mediatek,mt8195-wpesys"; 1513 reg = <0 0x14e00000 0 0x1000>; 1514 #clock-cells = <1>; 1515 }; 1516 1517 wpesys_vpp0: clock-controller@14e02000 { 1518 compatible = "mediatek,mt8195-wpesys_vpp0"; 1519 reg = <0 0x14e02000 0 0x1000>; 1520 #clock-cells = <1>; 1521 }; 1522 1523 wpesys_vpp1: clock-controller@14e03000 { 1524 compatible = "mediatek,mt8195-wpesys_vpp1"; 1525 reg = <0 0x14e03000 0 0x1000>; 1526 #clock-cells = <1>; 1527 }; 1528 1529 larb7: larb@14e04000 { 1530 compatible = "mediatek,mt8195-smi-larb"; 1531 reg = <0 0x14e04000 0 0x1000>; 1532 mediatek,larb-id = <7>; 1533 mediatek,smi = <&smi_common_vdo>; 1534 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 1535 <&wpesys CLK_WPE_SMI_LARB7>; 1536 clock-names = "apb", "smi"; 1537 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 1538 }; 1539 1540 larb8: larb@14e05000 { 1541 compatible = "mediatek,mt8195-smi-larb"; 1542 reg = <0 0x14e05000 0 0x1000>; 1543 mediatek,larb-id = <8>; 1544 mediatek,smi = <&smi_common_vpp>; 1545 clocks = <&wpesys CLK_WPE_SMI_LARB8>, 1546 <&wpesys CLK_WPE_SMI_LARB8>, 1547 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 1548 clock-names = "apb", "smi", "gals"; 1549 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 1550 }; 1551 1552 vppsys1: clock-controller@14f00000 { 1553 compatible = "mediatek,mt8195-vppsys1"; 1554 reg = <0 0x14f00000 0 0x1000>; 1555 #clock-cells = <1>; 1556 }; 1557 1558 larb5: larb@14f02000 { 1559 compatible = "mediatek,mt8195-smi-larb"; 1560 reg = <0 0x14f02000 0 0x1000>; 1561 mediatek,larb-id = <5>; 1562 mediatek,smi = <&smi_common_vdo>; 1563 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 1564 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 1565 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>; 1566 clock-names = "apb", "smi", "gals"; 1567 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 1568 }; 1569 1570 larb6: larb@14f03000 { 1571 compatible = "mediatek,mt8195-smi-larb"; 1572 reg = <0 0x14f03000 0 0x1000>; 1573 mediatek,larb-id = <6>; 1574 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 1575 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 1576 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 1577 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>; 1578 clock-names = "apb", "smi", "gals"; 1579 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 1580 }; 1581 1582 imgsys: clock-controller@15000000 { 1583 compatible = "mediatek,mt8195-imgsys"; 1584 reg = <0 0x15000000 0 0x1000>; 1585 #clock-cells = <1>; 1586 }; 1587 1588 larb9: larb@15001000 { 1589 compatible = "mediatek,mt8195-smi-larb"; 1590 reg = <0 0x15001000 0 0x1000>; 1591 mediatek,larb-id = <9>; 1592 mediatek,smi = <&smi_sub_common_img1_3x1>; 1593 clocks = <&imgsys CLK_IMG_LARB9>, 1594 <&imgsys CLK_IMG_LARB9>, 1595 <&imgsys CLK_IMG_GALS>; 1596 clock-names = "apb", "smi", "gals"; 1597 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1598 }; 1599 1600 smi_sub_common_img0_3x1: smi@15002000 { 1601 compatible = "mediatek,mt8195-smi-sub-common"; 1602 reg = <0 0x15002000 0 0x1000>; 1603 clocks = <&imgsys CLK_IMG_IPE>, 1604 <&imgsys CLK_IMG_IPE>, 1605 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 1606 clock-names = "apb", "smi", "gals0"; 1607 mediatek,smi = <&smi_common_vpp>; 1608 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1609 }; 1610 1611 smi_sub_common_img1_3x1: smi@15003000 { 1612 compatible = "mediatek,mt8195-smi-sub-common"; 1613 reg = <0 0x15003000 0 0x1000>; 1614 clocks = <&imgsys CLK_IMG_LARB9>, 1615 <&imgsys CLK_IMG_LARB9>, 1616 <&imgsys CLK_IMG_GALS>; 1617 clock-names = "apb", "smi", "gals0"; 1618 mediatek,smi = <&smi_common_vdo>; 1619 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1620 }; 1621 1622 imgsys1_dip_top: clock-controller@15110000 { 1623 compatible = "mediatek,mt8195-imgsys1_dip_top"; 1624 reg = <0 0x15110000 0 0x1000>; 1625 #clock-cells = <1>; 1626 }; 1627 1628 larb10: larb@15120000 { 1629 compatible = "mediatek,mt8195-smi-larb"; 1630 reg = <0 0x15120000 0 0x1000>; 1631 mediatek,larb-id = <10>; 1632 mediatek,smi = <&smi_sub_common_img1_3x1>; 1633 clocks = <&imgsys CLK_IMG_DIP0>, 1634 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>; 1635 clock-names = "apb", "smi"; 1636 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 1637 }; 1638 1639 imgsys1_dip_nr: clock-controller@15130000 { 1640 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 1641 reg = <0 0x15130000 0 0x1000>; 1642 #clock-cells = <1>; 1643 }; 1644 1645 imgsys1_wpe: clock-controller@15220000 { 1646 compatible = "mediatek,mt8195-imgsys1_wpe"; 1647 reg = <0 0x15220000 0 0x1000>; 1648 #clock-cells = <1>; 1649 }; 1650 1651 larb11: larb@15230000 { 1652 compatible = "mediatek,mt8195-smi-larb"; 1653 reg = <0 0x15230000 0 0x1000>; 1654 mediatek,larb-id = <11>; 1655 mediatek,smi = <&smi_sub_common_img1_3x1>; 1656 clocks = <&imgsys CLK_IMG_WPE0>, 1657 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>; 1658 clock-names = "apb", "smi"; 1659 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 1660 }; 1661 1662 ipesys: clock-controller@15330000 { 1663 compatible = "mediatek,mt8195-ipesys"; 1664 reg = <0 0x15330000 0 0x1000>; 1665 #clock-cells = <1>; 1666 }; 1667 1668 larb12: larb@15340000 { 1669 compatible = "mediatek,mt8195-smi-larb"; 1670 reg = <0 0x15340000 0 0x1000>; 1671 mediatek,larb-id = <12>; 1672 mediatek,smi = <&smi_sub_common_img0_3x1>; 1673 clocks = <&ipesys CLK_IPE_SMI_LARB12>, 1674 <&ipesys CLK_IPE_SMI_LARB12>; 1675 clock-names = "apb", "smi"; 1676 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>; 1677 }; 1678 1679 camsys: clock-controller@16000000 { 1680 compatible = "mediatek,mt8195-camsys"; 1681 reg = <0 0x16000000 0 0x1000>; 1682 #clock-cells = <1>; 1683 }; 1684 1685 larb13: larb@16001000 { 1686 compatible = "mediatek,mt8195-smi-larb"; 1687 reg = <0 0x16001000 0 0x1000>; 1688 mediatek,larb-id = <13>; 1689 mediatek,smi = <&smi_sub_common_cam_4x1>; 1690 clocks = <&camsys CLK_CAM_LARB13>, 1691 <&camsys CLK_CAM_LARB13>, 1692 <&camsys CLK_CAM_CAM2MM0_GALS>; 1693 clock-names = "apb", "smi", "gals"; 1694 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 1695 }; 1696 1697 larb14: larb@16002000 { 1698 compatible = "mediatek,mt8195-smi-larb"; 1699 reg = <0 0x16002000 0 0x1000>; 1700 mediatek,larb-id = <14>; 1701 mediatek,smi = <&smi_sub_common_cam_7x1>; 1702 clocks = <&camsys CLK_CAM_LARB14>, 1703 <&camsys CLK_CAM_LARB14>; 1704 clock-names = "apb", "smi"; 1705 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 1706 }; 1707 1708 smi_sub_common_cam_4x1: smi@16004000 { 1709 compatible = "mediatek,mt8195-smi-sub-common"; 1710 reg = <0 0x16004000 0 0x1000>; 1711 clocks = <&camsys CLK_CAM_LARB13>, 1712 <&camsys CLK_CAM_LARB13>, 1713 <&camsys CLK_CAM_CAM2MM0_GALS>; 1714 clock-names = "apb", "smi", "gals0"; 1715 mediatek,smi = <&smi_common_vdo>; 1716 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 1717 }; 1718 1719 smi_sub_common_cam_7x1: smi@16005000 { 1720 compatible = "mediatek,mt8195-smi-sub-common"; 1721 reg = <0 0x16005000 0 0x1000>; 1722 clocks = <&camsys CLK_CAM_LARB14>, 1723 <&camsys CLK_CAM_CAM2MM1_GALS>, 1724 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 1725 clock-names = "apb", "smi", "gals0"; 1726 mediatek,smi = <&smi_common_vpp>; 1727 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 1728 }; 1729 1730 larb16: larb@16012000 { 1731 compatible = "mediatek,mt8195-smi-larb"; 1732 reg = <0 0x16012000 0 0x1000>; 1733 mediatek,larb-id = <16>; 1734 mediatek,smi = <&smi_sub_common_cam_7x1>; 1735 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>, 1736 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 1737 clock-names = "apb", "smi"; 1738 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 1739 }; 1740 1741 larb17: larb@16013000 { 1742 compatible = "mediatek,mt8195-smi-larb"; 1743 reg = <0 0x16013000 0 0x1000>; 1744 mediatek,larb-id = <17>; 1745 mediatek,smi = <&smi_sub_common_cam_4x1>; 1746 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>, 1747 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 1748 clock-names = "apb", "smi"; 1749 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 1750 }; 1751 1752 larb27: larb@16014000 { 1753 compatible = "mediatek,mt8195-smi-larb"; 1754 reg = <0 0x16014000 0 0x1000>; 1755 mediatek,larb-id = <27>; 1756 mediatek,smi = <&smi_sub_common_cam_7x1>; 1757 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>, 1758 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 1759 clock-names = "apb", "smi"; 1760 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 1761 }; 1762 1763 larb28: larb@16015000 { 1764 compatible = "mediatek,mt8195-smi-larb"; 1765 reg = <0 0x16015000 0 0x1000>; 1766 mediatek,larb-id = <28>; 1767 mediatek,smi = <&smi_sub_common_cam_4x1>; 1768 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>, 1769 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 1770 clock-names = "apb", "smi"; 1771 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 1772 }; 1773 1774 camsys_rawa: clock-controller@1604f000 { 1775 compatible = "mediatek,mt8195-camsys_rawa"; 1776 reg = <0 0x1604f000 0 0x1000>; 1777 #clock-cells = <1>; 1778 }; 1779 1780 camsys_yuva: clock-controller@1606f000 { 1781 compatible = "mediatek,mt8195-camsys_yuva"; 1782 reg = <0 0x1606f000 0 0x1000>; 1783 #clock-cells = <1>; 1784 }; 1785 1786 camsys_rawb: clock-controller@1608f000 { 1787 compatible = "mediatek,mt8195-camsys_rawb"; 1788 reg = <0 0x1608f000 0 0x1000>; 1789 #clock-cells = <1>; 1790 }; 1791 1792 camsys_yuvb: clock-controller@160af000 { 1793 compatible = "mediatek,mt8195-camsys_yuvb"; 1794 reg = <0 0x160af000 0 0x1000>; 1795 #clock-cells = <1>; 1796 }; 1797 1798 camsys_mraw: clock-controller@16140000 { 1799 compatible = "mediatek,mt8195-camsys_mraw"; 1800 reg = <0 0x16140000 0 0x1000>; 1801 #clock-cells = <1>; 1802 }; 1803 1804 larb25: larb@16141000 { 1805 compatible = "mediatek,mt8195-smi-larb"; 1806 reg = <0 0x16141000 0 0x1000>; 1807 mediatek,larb-id = <25>; 1808 mediatek,smi = <&smi_sub_common_cam_4x1>; 1809 clocks = <&camsys CLK_CAM_LARB13>, 1810 <&camsys_mraw CLK_CAM_MRAW_LARBX>, 1811 <&camsys CLK_CAM_CAM2MM0_GALS>; 1812 clock-names = "apb", "smi", "gals"; 1813 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 1814 }; 1815 1816 larb26: larb@16142000 { 1817 compatible = "mediatek,mt8195-smi-larb"; 1818 reg = <0 0x16142000 0 0x1000>; 1819 mediatek,larb-id = <26>; 1820 mediatek,smi = <&smi_sub_common_cam_7x1>; 1821 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>, 1822 <&camsys_mraw CLK_CAM_MRAW_LARBX>; 1823 clock-names = "apb", "smi"; 1824 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 1825 1826 }; 1827 1828 ccusys: clock-controller@17200000 { 1829 compatible = "mediatek,mt8195-ccusys"; 1830 reg = <0 0x17200000 0 0x1000>; 1831 #clock-cells = <1>; 1832 }; 1833 1834 larb18: larb@17201000 { 1835 compatible = "mediatek,mt8195-smi-larb"; 1836 reg = <0 0x17201000 0 0x1000>; 1837 mediatek,larb-id = <18>; 1838 mediatek,smi = <&smi_sub_common_cam_7x1>; 1839 clocks = <&ccusys CLK_CCU_LARB18>, 1840 <&ccusys CLK_CCU_LARB18>; 1841 clock-names = "apb", "smi"; 1842 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 1843 }; 1844 1845 larb24: larb@1800d000 { 1846 compatible = "mediatek,mt8195-smi-larb"; 1847 reg = <0 0x1800d000 0 0x1000>; 1848 mediatek,larb-id = <24>; 1849 mediatek,smi = <&smi_common_vdo>; 1850 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 1851 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 1852 clock-names = "apb", "smi"; 1853 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 1854 }; 1855 1856 larb23: larb@1800e000 { 1857 compatible = "mediatek,mt8195-smi-larb"; 1858 reg = <0 0x1800e000 0 0x1000>; 1859 mediatek,larb-id = <23>; 1860 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 1861 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1862 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 1863 clock-names = "apb", "smi"; 1864 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 1865 }; 1866 1867 vdecsys_soc: clock-controller@1800f000 { 1868 compatible = "mediatek,mt8195-vdecsys_soc"; 1869 reg = <0 0x1800f000 0 0x1000>; 1870 #clock-cells = <1>; 1871 }; 1872 1873 larb21: larb@1802e000 { 1874 compatible = "mediatek,mt8195-smi-larb"; 1875 reg = <0 0x1802e000 0 0x1000>; 1876 mediatek,larb-id = <21>; 1877 mediatek,smi = <&smi_common_vdo>; 1878 clocks = <&vdecsys CLK_VDEC_LARB1>, 1879 <&vdecsys CLK_VDEC_LARB1>; 1880 clock-names = "apb", "smi"; 1881 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 1882 }; 1883 1884 vdecsys: clock-controller@1802f000 { 1885 compatible = "mediatek,mt8195-vdecsys"; 1886 reg = <0 0x1802f000 0 0x1000>; 1887 #clock-cells = <1>; 1888 }; 1889 1890 larb22: larb@1803e000 { 1891 compatible = "mediatek,mt8195-smi-larb"; 1892 reg = <0 0x1803e000 0 0x1000>; 1893 mediatek,larb-id = <22>; 1894 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 1895 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1896 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 1897 clock-names = "apb", "smi"; 1898 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 1899 }; 1900 1901 vdecsys_core1: clock-controller@1803f000 { 1902 compatible = "mediatek,mt8195-vdecsys_core1"; 1903 reg = <0 0x1803f000 0 0x1000>; 1904 #clock-cells = <1>; 1905 }; 1906 1907 apusys_pll: clock-controller@190f3000 { 1908 compatible = "mediatek,mt8195-apusys_pll"; 1909 reg = <0 0x190f3000 0 0x1000>; 1910 #clock-cells = <1>; 1911 }; 1912 1913 vencsys: clock-controller@1a000000 { 1914 compatible = "mediatek,mt8195-vencsys"; 1915 reg = <0 0x1a000000 0 0x1000>; 1916 #clock-cells = <1>; 1917 }; 1918 1919 larb19: larb@1a010000 { 1920 compatible = "mediatek,mt8195-smi-larb"; 1921 reg = <0 0x1a010000 0 0x1000>; 1922 mediatek,larb-id = <19>; 1923 mediatek,smi = <&smi_common_vdo>; 1924 clocks = <&vencsys CLK_VENC_VENC>, 1925 <&vencsys CLK_VENC_GALS>; 1926 clock-names = "apb", "smi"; 1927 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 1928 }; 1929 1930 vencsys_core1: clock-controller@1b000000 { 1931 compatible = "mediatek,mt8195-vencsys_core1"; 1932 reg = <0 0x1b000000 0 0x1000>; 1933 #clock-cells = <1>; 1934 }; 1935 1936 vdosys0: syscon@1c01a000 { 1937 compatible = "mediatek,mt8195-mmsys", "syscon"; 1938 reg = <0 0x1c01a000 0 0x1000>; 1939 #clock-cells = <1>; 1940 }; 1941 1942 larb20: larb@1b010000 { 1943 compatible = "mediatek,mt8195-smi-larb"; 1944 reg = <0 0x1b010000 0 0x1000>; 1945 mediatek,larb-id = <20>; 1946 mediatek,smi = <&smi_common_vpp>; 1947 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>, 1948 <&vencsys_core1 CLK_VENC_CORE1_GALS>, 1949 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 1950 clock-names = "apb", "smi", "gals"; 1951 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 1952 }; 1953 1954 larb0: larb@1c018000 { 1955 compatible = "mediatek,mt8195-smi-larb"; 1956 reg = <0 0x1c018000 0 0x1000>; 1957 mediatek,larb-id = <0>; 1958 mediatek,smi = <&smi_common_vdo>; 1959 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 1960 <&vdosys0 CLK_VDO0_SMI_LARB>, 1961 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>; 1962 clock-names = "apb", "smi", "gals"; 1963 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 1964 }; 1965 1966 larb1: larb@1c019000 { 1967 compatible = "mediatek,mt8195-smi-larb"; 1968 reg = <0 0x1c019000 0 0x1000>; 1969 mediatek,larb-id = <1>; 1970 mediatek,smi = <&smi_common_vpp>; 1971 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 1972 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, 1973 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>; 1974 clock-names = "apb", "smi", "gals"; 1975 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 1976 }; 1977 1978 vdosys1: syscon@1c100000 { 1979 compatible = "mediatek,mt8195-mmsys", "syscon"; 1980 reg = <0 0x1c100000 0 0x1000>; 1981 #clock-cells = <1>; 1982 }; 1983 1984 smi_common_vdo: smi@1c01b000 { 1985 compatible = "mediatek,mt8195-smi-common-vdo"; 1986 reg = <0 0x1c01b000 0 0x1000>; 1987 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 1988 <&vdosys0 CLK_VDO0_SMI_EMI>, 1989 <&vdosys0 CLK_VDO0_SMI_RSI>, 1990 <&vdosys0 CLK_VDO0_SMI_GALS>; 1991 clock-names = "apb", "smi", "gals0", "gals1"; 1992 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 1993 1994 }; 1995 1996 iommu_vdo: iommu@1c01f000 { 1997 compatible = "mediatek,mt8195-iommu-vdo"; 1998 reg = <0 0x1c01f000 0 0x1000>; 1999 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9 2000 &larb10 &larb11 &larb13 &larb17 2001 &larb19 &larb21 &larb24 &larb25 2002 &larb28>; 2003 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>; 2004 #iommu-cells = <1>; 2005 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 2006 clock-names = "bclk"; 2007 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2008 }; 2009 2010 larb2: larb@1c102000 { 2011 compatible = "mediatek,mt8195-smi-larb"; 2012 reg = <0 0x1c102000 0 0x1000>; 2013 mediatek,larb-id = <2>; 2014 mediatek,smi = <&smi_common_vdo>; 2015 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 2016 <&vdosys1 CLK_VDO1_SMI_LARB2>, 2017 <&vdosys1 CLK_VDO1_GALS>; 2018 clock-names = "apb", "smi", "gals"; 2019 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2020 }; 2021 2022 larb3: larb@1c103000 { 2023 compatible = "mediatek,mt8195-smi-larb"; 2024 reg = <0 0x1c103000 0 0x1000>; 2025 mediatek,larb-id = <3>; 2026 mediatek,smi = <&smi_common_vpp>; 2027 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 2028 <&vdosys1 CLK_VDO1_GALS>, 2029 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2030 clock-names = "apb", "smi", "gals"; 2031 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2032 }; 2033 }; 2034}; 2035