1 #include <sys/mca_x86.h> 2 #include "ao_mca_disp.h" 3 4 static const ao_error_disp_t ao_error_disp_dc[] = { 5 /* Correctable D$ data infill from system memory */ 6 { 7 FM_EREPORT_CPU_AMD_DC_INF_SYS_ECC1, 8 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_INF_SYS_ECC1, 9 ( AMD_BANK_STAT_CECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask */ 10 AMD_BANK_STAT_CECC, /* mask_res */ 11 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 12 0, /* ext code 0000 */ 13 AO_MCA_PP_BIT_SRC, /* pp_bits */ 14 ( AO_MCA_II_BIT_MEM | AO_MCA_II_BIT_IO ), /* ii_bits */ 15 AO_MCA_R4_BIT_DRD, /* r4_bits */ 16 39, /* addr valid hi */ 17 6, /* addr valid lo */ 18 AO_AED_PANIC_NEVER, /* panic_when */ 19 AO_AED_F_PHYSICAL, /* flags */ 20 0, /* errtype */ 21 }, 22 23 /* Correctable D$ data infill from L2$ */ 24 { 25 FM_EREPORT_CPU_AMD_DC_INF_L2_ECC1, 26 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_INF_L2_ECC1, 27 ( AMD_BANK_STAT_CECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask */ 28 AMD_BANK_STAT_CECC, /* mask_res */ 29 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L2), 30 0, /* ext code 0000 */ 31 0, /* pp_bits */ 32 0, /* ii_bits */ 33 AO_MCA_R4_BIT_DRD, /* r4_bits */ 34 39, /* addr valid hi */ 35 6, /* addr valid lo */ 36 AO_AED_PANIC_NEVER, /* panic_when */ 37 AO_AED_F_PHYSICAL, /* flags */ 38 0, /* errtype */ 39 }, 40 41 /* Uncorrectable D$ data infill from system memory */ 42 { 43 FM_EREPORT_CPU_AMD_DC_INF_SYS_ECCM, 44 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_INF_SYS_ECCM, 45 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC | AMD_BANK_STAT_CECC ), /* mask */ 46 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask_res */ 47 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 48 0, /* ext code 0000 */ 49 AO_MCA_PP_BIT_SRC, /* pp_bits */ 50 ( AO_MCA_II_BIT_MEM | AO_MCA_II_BIT_IO ), /* ii_bits */ 51 AO_MCA_R4_BIT_DRD, /* r4_bits */ 52 39, /* addr valid hi */ 53 6, /* addr valid lo */ 54 AO_AED_PANIC_ALWAYS, /* panic_when */ 55 AO_AED_F_PHYSICAL, /* flags */ 56 0, /* errtype */ 57 }, 58 59 /* Uncorrectable D$ data infill from L2$ */ 60 { 61 FM_EREPORT_CPU_AMD_DC_INF_L2_ECCM, 62 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_INF_L2_ECCM, 63 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC | AMD_BANK_STAT_CECC ), /* mask */ 64 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask_res */ 65 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L2), 66 0, /* ext code 0000 */ 67 0, /* pp_bits */ 68 0, /* ii_bits */ 69 AO_MCA_R4_BIT_DRD, /* r4_bits */ 70 39, /* addr valid hi */ 71 6, /* addr valid lo */ 72 AO_AED_PANIC_ALWAYS, /* panic_when */ 73 AO_AED_F_PHYSICAL, /* flags */ 74 0, /* errtype */ 75 }, 76 77 /* Correctable single-bit error in Data Array from scrub */ 78 { 79 FM_EREPORT_CPU_AMD_DC_DATA_ECC1, 80 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_DATA_ECC1, 81 ( AMD_BANK_STAT_CECC | AMD_BANK_STAT_SCRUB | MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask */ 82 ( AMD_BANK_STAT_CECC | AMD_BANK_STAT_SCRUB ), /* mask_res */ 83 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L1), 84 0, /* ext code 0000 */ 85 0, /* pp_bits */ 86 0, /* ii_bits */ 87 AO_MCA_R4_BIT_ERR, /* r4_bits */ 88 11, /* addr valid hi */ 89 3, /* addr valid lo */ 90 AO_AED_PANIC_NEVER, /* panic_when */ 91 AO_AED_F_PHYSICAL, /* flags */ 92 0, /* errtype */ 93 }, 94 95 /* Uncorrectable single-bit error in Data Array */ 96 { 97 FM_EREPORT_CPU_AMD_DC_DATA_ECC1_UC, 98 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_DATA_ECC1_UC, 99 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_SCRUB ), /* mask */ 100 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC ), /* mask_res */ 101 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L1), 102 0, /* ext code 0000 */ 103 0, /* pp_bits */ 104 0, /* ii_bits */ 105 ( AO_MCA_R4_BIT_DRD | AO_MCA_R4_BIT_DWR ), /* r4_bits */ 106 39, /* addr valid hi */ 107 3, /* addr valid lo */ 108 AO_AED_PANIC_ALWAYS, /* panic_when */ 109 AO_AED_F_PHYSICAL, /* flags */ 110 0, /* errtype */ 111 }, 112 113 /* Uncorrectable single-bit error in Data Array */ 114 { 115 FM_EREPORT_CPU_AMD_DC_DATA_ECC1_UC, 116 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_DATA_ECC1_UC, 117 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_SCRUB ), /* mask */ 118 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC ), /* mask_res */ 119 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L1), 120 0, /* ext code 0000 */ 121 0, /* pp_bits */ 122 0, /* ii_bits */ 123 ( AO_MCA_R4_BIT_EVICT | AO_MCA_R4_BIT_SNOOP ), /* r4_bits */ 124 11, /* addr valid hi */ 125 6, /* addr valid lo */ 126 AO_AED_PANIC_ALWAYS, /* panic_when */ 127 AO_AED_F_PHYSICAL, /* flags */ 128 0, /* errtype */ 129 }, 130 131 /* Uncorrectable multi-bit error in Data Array */ 132 { 133 FM_EREPORT_CPU_AMD_DC_DATA_ECCM, 134 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_DATA_ECCM, 135 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_SCRUB ), /* mask */ 136 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask_res */ 137 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L1), 138 0, /* ext code 0000 */ 139 0, /* pp_bits */ 140 0, /* ii_bits */ 141 ( AO_MCA_R4_BIT_DRD | AO_MCA_R4_BIT_DWR ), /* r4_bits */ 142 39, /* addr valid hi */ 143 3, /* addr valid lo */ 144 AO_AED_PANIC_ALWAYS, /* panic_when */ 145 AO_AED_F_PHYSICAL, /* flags */ 146 0, /* errtype */ 147 }, 148 149 /* Uncorrectable multi-bit error in Data Array */ 150 { 151 FM_EREPORT_CPU_AMD_DC_DATA_ECCM, 152 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_DATA_ECCM, 153 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_SCRUB ), /* mask */ 154 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask_res */ 155 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L1), 156 0, /* ext code 0000 */ 157 0, /* pp_bits */ 158 0, /* ii_bits */ 159 ( AO_MCA_R4_BIT_EVICT | AO_MCA_R4_BIT_SNOOP ), /* r4_bits */ 160 11, /* addr valid hi */ 161 6, /* addr valid lo */ 162 AO_AED_PANIC_ALWAYS, /* panic_when */ 163 AO_AED_F_PHYSICAL, /* flags */ 164 0, /* errtype */ 165 }, 166 167 /* Uncorrectable multi-bit error in Data Array from scrub */ 168 { 169 FM_EREPORT_CPU_AMD_DC_DATA_ECCM, 170 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_DATA_ECCM, 171 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC | AMD_BANK_STAT_SCRUB | AMD_BANK_STAT_CECC ), /* mask */ 172 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC | AMD_BANK_STAT_SCRUB ), /* mask_res */ 173 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L1), 174 0, /* ext code 0000 */ 175 0, /* pp_bits */ 176 0, /* ii_bits */ 177 AO_MCA_R4_BIT_ERR, /* r4_bits */ 178 11, /* addr valid hi */ 179 3, /* addr valid lo */ 180 AO_AED_PANIC_ALWAYS, /* panic_when */ 181 AO_AED_F_PHYSICAL, /* flags */ 182 0, /* errtype */ 183 }, 184 185 /* Main Tag Array Parity Error */ 186 { 187 FM_EREPORT_CPU_AMD_DC_TAG_PAR, 188 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_TAG_PAR, 189 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 190 MSR_MC_STATUS_UC, /* mask_res */ 191 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L1), 192 0, /* ext code 0000 */ 193 0, /* pp_bits */ 194 0, /* ii_bits */ 195 ( AO_MCA_R4_BIT_DRD | AO_MCA_R4_BIT_DWR ), /* r4_bits */ 196 39, /* addr valid hi */ 197 3, /* addr valid lo */ 198 AO_AED_PANIC_ALWAYS, /* panic_when */ 199 AO_AED_F_PHYSICAL, /* flags */ 200 0, /* errtype */ 201 }, 202 203 /* Snoop Tag Array Parity Error */ 204 { 205 FM_EREPORT_CPU_AMD_DC_STAG_PAR, 206 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_STAG_PAR, 207 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 208 MSR_MC_STATUS_UC, /* mask_res */ 209 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L1), 210 0, /* ext code 0000 */ 211 0, /* pp_bits */ 212 0, /* ii_bits */ 213 ( AO_MCA_R4_BIT_SNOOP | AO_MCA_R4_BIT_EVICT ), /* r4_bits */ 214 11, /* addr valid hi */ 215 6, /* addr valid lo */ 216 AO_AED_PANIC_ALWAYS, /* panic_when */ 217 AO_AED_F_PHYSICAL, /* flags */ 218 0, /* errtype */ 219 }, 220 221 /* L1 DTLB Parity Error */ 222 { 223 FM_EREPORT_CPU_AMD_DC_L1TLB_PAR, 224 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_L1TLB_PAR, 225 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 226 MSR_MC_STATUS_UC, /* mask_res */ 227 AMD_ERRCODE_MKTLB(MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L1), 228 0, /* ext code 0000 */ 229 0, /* pp_bits */ 230 0, /* ii_bits */ 231 0, /* r4_bits */ 232 47, /* addr valid hi */ 233 12, /* addr valid lo */ 234 AO_AED_PANIC_ALWAYS, /* panic_when */ 235 AO_AED_F_LINEAR, /* flags */ 236 0, /* errtype */ 237 }, 238 239 /* L1 DTLB Parity Error (multimatch) */ 240 { 241 FM_EREPORT_CPU_AMD_DC_L1TLB_PAR, 242 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_L1TLB_PAR, 243 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 244 MSR_MC_STATUS_UC, /* mask_res */ 245 AMD_ERRCODE_MKTLB(MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L1), 246 1, /* ext code 0001 */ 247 0, /* pp_bits */ 248 0, /* ii_bits */ 249 0, /* r4_bits */ 250 47, /* addr valid hi */ 251 12, /* addr valid lo */ 252 AO_AED_PANIC_ALWAYS, /* panic_when */ 253 AO_AED_F_LINEAR, /* flags */ 254 0, /* errtype */ 255 }, 256 257 /* L2 DTLB Parity Error */ 258 { 259 FM_EREPORT_CPU_AMD_DC_L2TLB_PAR, 260 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_L2TLB_PAR, 261 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 262 MSR_MC_STATUS_UC, /* mask_res */ 263 AMD_ERRCODE_MKTLB(MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L2), 264 0, /* ext code 0000 */ 265 0, /* pp_bits */ 266 0, /* ii_bits */ 267 0, /* r4_bits */ 268 47, /* addr valid hi */ 269 12, /* addr valid lo */ 270 AO_AED_PANIC_ALWAYS, /* panic_when */ 271 AO_AED_F_LINEAR, /* flags */ 272 0, /* errtype */ 273 }, 274 275 /* L2 DTLB Parity Error (multimatch) */ 276 { 277 FM_EREPORT_CPU_AMD_DC_L2TLB_PAR, 278 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_L2TLB_PAR, 279 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 280 MSR_MC_STATUS_UC, /* mask_res */ 281 AMD_ERRCODE_MKTLB(MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L2), 282 1, /* ext code 0001 */ 283 0, /* pp_bits */ 284 0, /* ii_bits */ 285 0, /* r4_bits */ 286 47, /* addr valid hi */ 287 12, /* addr valid lo */ 288 AO_AED_PANIC_ALWAYS, /* panic_when */ 289 AO_AED_F_LINEAR, /* flags */ 290 0, /* errtype */ 291 }, 292 293 { NULL } 294 }; 295 296 static const ao_error_disp_t ao_error_disp_ic[] = { 297 /* Correctable I$ data infill from system memory */ 298 { 299 FM_EREPORT_CPU_AMD_IC_INF_SYS_ECC1, 300 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_INF_SYS_ECC1, 301 ( AMD_BANK_STAT_CECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask */ 302 AMD_BANK_STAT_CECC, /* mask_res */ 303 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 304 0, /* ext code 0000 */ 305 AO_MCA_PP_BIT_SRC, /* pp_bits */ 306 AO_MCA_II_BIT_MEM, /* ii_bits */ 307 AO_MCA_R4_BIT_IRD, /* r4_bits */ 308 39, /* addr valid hi */ 309 6, /* addr valid lo */ 310 AO_AED_PANIC_NEVER, /* panic_when */ 311 AO_AED_F_PHYSICAL, /* flags */ 312 0, /* errtype */ 313 }, 314 315 /* Correctable I$ data infill from L2$ */ 316 { 317 FM_EREPORT_CPU_AMD_IC_INF_L2_ECC1, 318 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_INF_L2_ECC1, 319 ( AMD_BANK_STAT_CECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask */ 320 AMD_BANK_STAT_CECC, /* mask_res */ 321 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L2), 322 0, /* ext code 0000 */ 323 0, /* pp_bits */ 324 0, /* ii_bits */ 325 AO_MCA_R4_BIT_IRD, /* r4_bits */ 326 39, /* addr valid hi */ 327 6, /* addr valid lo */ 328 AO_AED_PANIC_NEVER, /* panic_when */ 329 AO_AED_F_PHYSICAL, /* flags */ 330 0, /* errtype */ 331 }, 332 333 /* Uncorrectable I$ data infill from system memory */ 334 { 335 FM_EREPORT_CPU_AMD_IC_INF_SYS_ECCM, 336 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_INF_SYS_ECCM, 337 ( AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC ), /* mask */ 338 ( AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask_res */ 339 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 340 0, /* ext code 0000 */ 341 AO_MCA_PP_BIT_SRC, /* pp_bits */ 342 AO_MCA_II_BIT_MEM, /* ii_bits */ 343 AO_MCA_R4_BIT_IRD, /* r4_bits */ 344 39, /* addr valid hi */ 345 6, /* addr valid lo */ 346 AO_AED_PANIC_ALWAYS, /* panic_when */ 347 AO_AED_F_PHYSICAL, /* flags */ 348 0, /* errtype */ 349 }, 350 351 /* Uncorrectable I$ data infill from L2$ */ 352 { 353 FM_EREPORT_CPU_AMD_IC_INF_L2_ECCM, 354 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_INF_L2_ECCM, 355 ( AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC ), /* mask */ 356 ( AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask_res */ 357 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L2), 358 0, /* ext code 0000 */ 359 0, /* pp_bits */ 360 0, /* ii_bits */ 361 AO_MCA_R4_BIT_IRD, /* r4_bits */ 362 39, /* addr valid hi */ 363 6, /* addr valid lo */ 364 AO_AED_PANIC_ALWAYS, /* panic_when */ 365 AO_AED_F_PHYSICAL, /* flags */ 366 0, /* errtype */ 367 }, 368 369 /* Data Array Parity Error */ 370 { 371 FM_EREPORT_CPU_AMD_IC_DATA_PAR, 372 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_DATA_PAR, 373 ( AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask */ 374 0, /* mask_res */ 375 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L1), 376 0, /* ext code 0000 */ 377 0, /* pp_bits */ 378 0, /* ii_bits */ 379 AO_MCA_R4_BIT_IRD, /* r4_bits */ 380 47, /* addr valid hi */ 381 4, /* addr valid lo */ 382 AO_AED_PANIC_NEVER, /* panic_when */ 383 AO_AED_F_LINEAR, /* flags */ 384 0, /* errtype */ 385 }, 386 387 /* Main Tag Array Parity Error */ 388 { 389 FM_EREPORT_CPU_AMD_IC_TAG_PAR, 390 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_TAG_PAR, 391 ( AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask */ 392 0, /* mask_res */ 393 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L1), 394 0, /* ext code 0000 */ 395 0, /* pp_bits */ 396 0, /* ii_bits */ 397 AO_MCA_R4_BIT_IRD, /* r4_bits */ 398 47, /* addr valid hi */ 399 6, /* addr valid lo */ 400 AO_AED_PANIC_NEVER, /* panic_when */ 401 AO_AED_F_LINEAR, /* flags */ 402 0, /* errtype */ 403 }, 404 405 /* Main Tag Array Parity Error */ 406 { 407 FM_EREPORT_CPU_AMD_IC_TAG_PAR, 408 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_TAG_PAR, 409 ( AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask */ 410 0, /* mask_res */ 411 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L1), 412 0, /* ext code 0000 */ 413 0, /* pp_bits */ 414 0, /* ii_bits */ 415 AO_MCA_R4_BIT_EVICT, /* r4_bits */ 416 0, /* addr valid hi */ 417 0, /* addr valid lo */ 418 AO_AED_PANIC_NEVER, /* panic_when */ 419 AO_AED_F_LINEAR, /* flags */ 420 0, /* errtype */ 421 }, 422 423 /* Snoop Tag Array Parity Error */ 424 { 425 FM_EREPORT_CPU_AMD_IC_STAG_PAR, 426 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_STAG_PAR, 427 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 428 MSR_MC_STATUS_UC, /* mask_res */ 429 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L1), 430 0, /* ext code 0000 */ 431 0, /* pp_bits */ 432 0, /* ii_bits */ 433 AO_MCA_R4_BIT_SNOOP, /* r4_bits */ 434 39, /* addr valid hi */ 435 6, /* addr valid lo */ 436 AO_AED_PANIC_ALWAYS, /* panic_when */ 437 AO_AED_F_PHYSICAL, /* flags */ 438 0, /* errtype */ 439 }, 440 441 /* Snoop Tag Array Parity Error */ 442 { 443 FM_EREPORT_CPU_AMD_IC_STAG_PAR, 444 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_STAG_PAR, 445 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 446 MSR_MC_STATUS_UC, /* mask_res */ 447 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L1), 448 0, /* ext code 0000 */ 449 0, /* pp_bits */ 450 0, /* ii_bits */ 451 AO_MCA_R4_BIT_EVICT, /* r4_bits */ 452 0, /* addr valid hi */ 453 0, /* addr valid lo */ 454 AO_AED_PANIC_ALWAYS, /* panic_when */ 455 AO_AED_F_PHYSICAL, /* flags */ 456 0, /* errtype */ 457 }, 458 459 /* L1 ITLB Parity Error */ 460 { 461 FM_EREPORT_CPU_AMD_IC_L1TLB_PAR, 462 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_L1TLB_PAR, 463 ( AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask */ 464 0, /* mask_res */ 465 AMD_ERRCODE_MKTLB(MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L1), 466 0, /* ext code 0000 */ 467 0, /* pp_bits */ 468 0, /* ii_bits */ 469 0, /* r4_bits */ 470 47, /* addr valid hi */ 471 12, /* addr valid lo */ 472 AO_AED_PANIC_NEVER, /* panic_when */ 473 ( AO_AED_F_LINEAR | AO_AED_F_PAGEALIGNED ), /* flags */ 474 0, /* errtype */ 475 }, 476 477 /* L1 ITLB Parity Error (multimatch) */ 478 { 479 FM_EREPORT_CPU_AMD_IC_L1TLB_PAR, 480 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_L1TLB_PAR, 481 ( AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask */ 482 0, /* mask_res */ 483 AMD_ERRCODE_MKTLB(MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L1), 484 1, /* ext code 0001 */ 485 0, /* pp_bits */ 486 0, /* ii_bits */ 487 0, /* r4_bits */ 488 47, /* addr valid hi */ 489 12, /* addr valid lo */ 490 AO_AED_PANIC_NEVER, /* panic_when */ 491 ( AO_AED_F_LINEAR | AO_AED_F_PAGEALIGNED ), /* flags */ 492 0, /* errtype */ 493 }, 494 495 /* L2 ITLB Parity Error */ 496 { 497 FM_EREPORT_CPU_AMD_IC_L2TLB_PAR, 498 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_L2TLB_PAR, 499 ( AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask */ 500 0, /* mask_res */ 501 AMD_ERRCODE_MKTLB(MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L2), 502 0, /* ext code 0000 */ 503 0, /* pp_bits */ 504 0, /* ii_bits */ 505 0, /* r4_bits */ 506 47, /* addr valid hi */ 507 12, /* addr valid lo */ 508 AO_AED_PANIC_NEVER, /* panic_when */ 509 AO_AED_F_LINEAR, /* flags */ 510 0, /* errtype */ 511 }, 512 513 /* L2 ITLB Parity Error (multimatch) */ 514 { 515 FM_EREPORT_CPU_AMD_IC_L2TLB_PAR, 516 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_L2TLB_PAR, 517 ( AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask */ 518 0, /* mask_res */ 519 AMD_ERRCODE_MKTLB(MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L2), 520 1, /* ext code 0001 */ 521 0, /* pp_bits */ 522 0, /* ii_bits */ 523 0, /* r4_bits */ 524 47, /* addr valid hi */ 525 12, /* addr valid lo */ 526 AO_AED_PANIC_NEVER, /* panic_when */ 527 AO_AED_F_LINEAR, /* flags */ 528 0, /* errtype */ 529 }, 530 531 /* System Data Read Error */ 532 { 533 FM_EREPORT_CPU_AMD_IC_RDDE, 534 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_RDDE, 535 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 536 MSR_MC_STATUS_UC, /* mask_res */ 537 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 538 0, /* ext code 0000 */ 539 AO_MCA_PP_BIT_SRC, /* pp_bits */ 540 AO_MCA_II_BIT_MEM, /* ii_bits */ 541 AO_MCA_R4_BIT_IRD, /* r4_bits */ 542 0, /* addr valid hi */ 543 0, /* addr valid lo */ 544 AO_AED_PANIC_IFMCE, /* panic_when */ 545 0, /* flags */ 546 0, /* errtype */ 547 }, 548 549 { NULL } 550 }; 551 552 static const ao_error_disp_t ao_error_disp_bu[] = { 553 /* L2 data array single-bit ECC during TLB reload, snoop, or copyback */ 554 { 555 FM_EREPORT_CPU_AMD_BU_L2D_ECC1, 556 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2D_ECC1, 557 ( AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask */ 558 AMD_BANK_STAT_CECC, /* mask_res */ 559 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_GEN, MCAX86_ERRCODE_LL_L2), 560 0, /* ext code 0000 */ 561 0, /* pp_bits */ 562 0, /* ii_bits */ 563 ( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_SNOOP | AO_MCA_R4_BIT_EVICT ), /* r4_bits */ 564 39, /* addr valid hi */ 565 6, /* addr valid lo */ 566 AO_AED_PANIC_NEVER, /* panic_when */ 567 AO_AED_F_PHYSICAL, /* flags */ 568 0, /* errtype */ 569 }, 570 571 /* L2 data array multi-bit ECC during TLB reload, snoop, or copyback */ 572 { 573 FM_EREPORT_CPU_AMD_BU_L2D_ECCM, 574 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2D_ECCM, 575 ( AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC ), /* mask */ 576 ( AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask_res */ 577 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_GEN, MCAX86_ERRCODE_LL_L2), 578 0, /* ext code 0000 */ 579 0, /* pp_bits */ 580 0, /* ii_bits */ 581 ( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_SNOOP | AO_MCA_R4_BIT_EVICT ), /* r4_bits */ 582 39, /* addr valid hi */ 583 6, /* addr valid lo */ 584 AO_AED_PANIC_ALWAYS, /* panic_when */ 585 AO_AED_F_PHYSICAL, /* flags */ 586 0, /* errtype */ 587 }, 588 589 /* L2 main tag array single-bit ECC error on scrubber access */ 590 { 591 FM_EREPORT_CPU_AMD_BU_L2T_ECC1, 592 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2T_ECC1, 593 ( AMD_BANK_STAT_CECC | AMD_BANK_STAT_SCRUB | AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask */ 594 ( AMD_BANK_STAT_CECC | AMD_BANK_STAT_SCRUB ), /* mask_res */ 595 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L2), 596 2, /* ext code 0010 */ 597 0, /* pp_bits */ 598 0, /* ii_bits */ 599 AO_MCA_R4_BIT_ERR, /* r4_bits */ 600 15, /* addr valid hi */ 601 0, /* addr valid lo */ 602 AO_AED_PANIC_NEVER, /* panic_when */ 603 ( AO_AED_F_PHYSICAL | AO_AED_F_L2SETWAY ), /* flags */ 604 0, /* errtype */ 605 }, 606 607 /* L2 main tag array multi-bit ECC error on scrubber access */ 608 { 609 FM_EREPORT_CPU_AMD_BU_L2T_ECCM, 610 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2T_ECCM, 611 ( AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_SCRUB | AMD_BANK_STAT_CECC ), /* mask */ 612 ( AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_SCRUB ), /* mask_res */ 613 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L2), 614 2, /* ext code 0010 */ 615 0, /* pp_bits */ 616 0, /* ii_bits */ 617 AO_MCA_R4_BIT_ERR, /* r4_bits */ 618 15, /* addr valid hi */ 619 0, /* addr valid lo */ 620 AO_AED_PANIC_ALWAYS, /* panic_when */ 621 ( AO_AED_F_PHYSICAL | AO_AED_F_L2SETWAY ), /* flags */ 622 0, /* errtype */ 623 }, 624 625 /* L2 main tag array parity error on I$ fetch */ 626 { 627 FM_EREPORT_CPU_AMD_BU_L2T_PAR, 628 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2T_PAR, 629 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 630 MSR_MC_STATUS_UC, /* mask_res */ 631 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L2), 632 2, /* ext code 0010 */ 633 0, /* pp_bits */ 634 0, /* ii_bits */ 635 AO_MCA_R4_BIT_IRD, /* r4_bits */ 636 15, /* addr valid hi */ 637 0, /* addr valid lo */ 638 AO_AED_PANIC_ALWAYS, /* panic_when */ 639 ( AO_AED_F_PHYSICAL | AO_AED_F_L2SETWAY ), /* flags */ 640 0, /* errtype */ 641 }, 642 643 /* L2 main tag array parity error on D$ fetch */ 644 { 645 FM_EREPORT_CPU_AMD_BU_L2T_PAR, 646 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2T_PAR, 647 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 648 MSR_MC_STATUS_UC, /* mask_res */ 649 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L2), 650 2, /* ext code 0010 */ 651 0, /* pp_bits */ 652 0, /* ii_bits */ 653 AO_MCA_R4_BIT_DRD, /* r4_bits */ 654 15, /* addr valid hi */ 655 0, /* addr valid lo */ 656 AO_AED_PANIC_ALWAYS, /* panic_when */ 657 ( AO_AED_F_PHYSICAL | AO_AED_F_L2SETWAY ), /* flags */ 658 0, /* errtype */ 659 }, 660 661 /* L2 main tag array parity error on TLB reload, snoop, or copyback */ 662 { 663 FM_EREPORT_CPU_AMD_BU_L2T_PAR, 664 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2T_PAR, 665 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 666 MSR_MC_STATUS_UC, /* mask_res */ 667 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_GEN, MCAX86_ERRCODE_LL_L2), 668 2, /* ext code 0010 */ 669 0, /* pp_bits */ 670 0, /* ii_bits */ 671 ( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_SNOOP | AO_MCA_R4_BIT_EVICT ), /* r4_bits */ 672 15, /* addr valid hi */ 673 0, /* addr valid lo */ 674 AO_AED_PANIC_ALWAYS, /* panic_when */ 675 ( AO_AED_F_PHYSICAL | AO_AED_F_L2SETWAY ), /* flags */ 676 0, /* errtype */ 677 }, 678 679 /* L2 main tag array parity error on scrubber access */ 680 { 681 FM_EREPORT_CPU_AMD_BU_L2T_PAR, 682 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2T_PAR, 683 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_SCRUB | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 684 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_SCRUB ), /* mask_res */ 685 AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L2), 686 2, /* ext code 0010 */ 687 0, /* pp_bits */ 688 0, /* ii_bits */ 689 AO_MCA_R4_BIT_ERR, /* r4_bits */ 690 15, /* addr valid hi */ 691 0, /* addr valid lo */ 692 AO_AED_PANIC_ALWAYS, /* panic_when */ 693 ( AO_AED_F_PHYSICAL | AO_AED_F_L2SETWAY ), /* flags */ 694 0, /* errtype */ 695 }, 696 697 /* System data single-bit ECC for hardware prefetch or TLB reload */ 698 { 699 FM_EREPORT_CPU_AMD_BU_S_ECC1, 700 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_S_ECC1, 701 ( AMD_BANK_STAT_CECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask */ 702 AMD_BANK_STAT_CECC, /* mask_res */ 703 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 704 0, /* ext code 0000 */ 705 AO_MCA_PP_BIT_SRC, /* pp_bits */ 706 ( AO_MCA_II_BIT_MEM | AO_MCA_II_BIT_IO ), /* ii_bits */ 707 AO_MCA_R4_BIT_RD, /* r4_bits */ 708 39, /* addr valid hi */ 709 6, /* addr valid lo */ 710 AO_AED_PANIC_NEVER, /* panic_when */ 711 AO_AED_F_PHYSICAL, /* flags */ 712 0, /* errtype */ 713 }, 714 715 /* System data single-bit ECC for hardware prefetch or TLB reload */ 716 { 717 FM_EREPORT_CPU_AMD_BU_S_ECC1, 718 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_S_ECC1, 719 ( AMD_BANK_STAT_CECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask */ 720 AMD_BANK_STAT_CECC, /* mask_res */ 721 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 722 0, /* ext code 0000 */ 723 AO_MCA_PP_BIT_SRC, /* pp_bits */ 724 ( AO_MCA_II_BIT_MEM | AO_MCA_II_BIT_IO ), /* ii_bits */ 725 AO_MCA_R4_BIT_PREFETCH, /* r4_bits */ 726 0, /* addr valid hi */ 727 0, /* addr valid lo */ 728 AO_AED_PANIC_NEVER, /* panic_when */ 729 AO_AED_F_PHYSICAL, /* flags */ 730 0, /* errtype */ 731 }, 732 733 /* System data multi-bit ECC for hardware prefetch or TLB reload */ 734 { 735 FM_EREPORT_CPU_AMD_BU_S_ECCM, 736 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_S_ECCM, 737 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC | AMD_BANK_STAT_CECC ), /* mask */ 738 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask_res */ 739 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 740 0, /* ext code 0000 */ 741 AO_MCA_PP_BIT_SRC, /* pp_bits */ 742 ( AO_MCA_II_BIT_MEM | AO_MCA_II_BIT_IO ), /* ii_bits */ 743 AO_MCA_R4_BIT_RD, /* r4_bits */ 744 39, /* addr valid hi */ 745 6, /* addr valid lo */ 746 AO_AED_PANIC_ALWAYS, /* panic_when */ 747 AO_AED_F_PHYSICAL, /* flags */ 748 0, /* errtype */ 749 }, 750 751 /* System data multi-bit ECC for hardware prefetch or TLB reload */ 752 { 753 FM_EREPORT_CPU_AMD_BU_S_ECCM, 754 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_S_ECCM, 755 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC | AMD_BANK_STAT_CECC ), /* mask */ 756 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask_res */ 757 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 758 0, /* ext code 0000 */ 759 AO_MCA_PP_BIT_SRC, /* pp_bits */ 760 ( AO_MCA_II_BIT_MEM | AO_MCA_II_BIT_IO ), /* ii_bits */ 761 AO_MCA_R4_BIT_PREFETCH, /* r4_bits */ 762 0, /* addr valid hi */ 763 0, /* addr valid lo */ 764 AO_AED_PANIC_ALWAYS, /* panic_when */ 765 AO_AED_F_PHYSICAL, /* flags */ 766 0, /* errtype */ 767 }, 768 769 /* System data read error for TLB reload or hardware prefetch */ 770 { 771 FM_EREPORT_CPU_AMD_BU_S_RDE, 772 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_S_RDE, 773 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 774 MSR_MC_STATUS_UC, /* mask_res */ 775 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 776 0, /* ext code 0000 */ 777 AO_MCA_PP_BIT_SRC, /* pp_bits */ 778 ( AO_MCA_II_BIT_MEM | AO_MCA_II_BIT_IO ), /* ii_bits */ 779 ( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_PREFETCH ), /* r4_bits */ 780 39, /* addr valid hi */ 781 6, /* addr valid lo */ 782 AO_AED_PANIC_IFMCE, /* panic_when */ 783 AO_AED_F_PHYSICAL, /* flags */ 784 0, /* errtype */ 785 }, 786 787 { NULL } 788 }; 789 790 static const ao_error_disp_t ao_error_disp_ls[] = { 791 /* System data read error */ 792 { 793 FM_EREPORT_CPU_AMD_LS_S_RDE, 794 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_LS_S_RDE, 795 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 796 MSR_MC_STATUS_UC, /* mask_res */ 797 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 798 0, /* ext code 0000 */ 799 AO_MCA_PP_BIT_SRC, /* pp_bits */ 800 ( AO_MCA_II_BIT_MEM | AO_MCA_II_BIT_IO ), /* ii_bits */ 801 ( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_WR ), /* r4_bits */ 802 39, /* addr valid hi */ 803 6, /* addr valid lo */ 804 AO_AED_PANIC_IFMCE, /* panic_when */ 805 AO_AED_F_PHYSICAL, /* flags */ 806 0, /* errtype */ 807 }, 808 809 { NULL } 810 }; 811 812 static const ao_error_disp_t ao_error_disp_nb[] = { 813 /* Correctable ECC error from Normal ECC */ 814 { 815 FM_EREPORT_CPU_AMD_NB_MEM_CE, 816 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_MEM_CE, 817 ( AMD_BANK_STAT_CECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask */ 818 AMD_BANK_STAT_CECC, /* mask_res */ 819 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 820 0, /* ext code 0000 */ 821 ( AO_MCA_PP_BIT_SRC | AO_MCA_PP_BIT_RES ), /* pp_bits */ 822 AO_MCA_II_BIT_MEM, /* ii_bits */ 823 ( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_WR ), /* r4_bits */ 824 39, /* addr valid hi */ 825 3, /* addr valid lo */ 826 AO_AED_PANIC_NEVER, /* panic_when */ 827 AO_AED_F_PHYSICAL, /* flags */ 828 0, /* errtype */ 829 }, 830 831 /* Uncorrectable ECC error from Normal ECC */ 832 { 833 FM_EREPORT_CPU_AMD_NB_MEM_UE, 834 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_MEM_UE, 835 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC | AMD_BANK_STAT_CECC ), /* mask */ 836 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask_res */ 837 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 838 0, /* ext code 0000 */ 839 ( AO_MCA_PP_BIT_SRC | AO_MCA_PP_BIT_RES ), /* pp_bits */ 840 AO_MCA_II_BIT_MEM, /* ii_bits */ 841 ( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_WR ), /* r4_bits */ 842 39, /* addr valid hi */ 843 3, /* addr valid lo */ 844 AO_AED_PANIC_ALWAYS, /* panic_when */ 845 AO_AED_F_PHYSICAL, /* flags */ 846 0, /* errtype */ 847 }, 848 849 /* Correctable ECC error from ChipKill ECC */ 850 { 851 FM_EREPORT_CPU_AMD_NB_MEM_CE, 852 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_MEM_CE, 853 ( AMD_BANK_STAT_CECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask */ 854 AMD_BANK_STAT_CECC, /* mask_res */ 855 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 856 8, /* ext code 1000 */ 857 ( AO_MCA_PP_BIT_SRC | AO_MCA_PP_BIT_RES ), /* pp_bits */ 858 AO_MCA_II_BIT_MEM, /* ii_bits */ 859 ( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_WR ), /* r4_bits */ 860 39, /* addr valid hi */ 861 3, /* addr valid lo */ 862 AO_AED_PANIC_NEVER, /* panic_when */ 863 AO_AED_F_PHYSICAL, /* flags */ 864 0, /* errtype */ 865 }, 866 867 /* Uncorrectable ECC error from ChipKill ECC */ 868 { 869 FM_EREPORT_CPU_AMD_NB_MEM_UE, 870 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_MEM_UE, 871 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC | AMD_BANK_STAT_CECC ), /* mask */ 872 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask_res */ 873 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 874 8, /* ext code 1000 */ 875 ( AO_MCA_PP_BIT_SRC | AO_MCA_PP_BIT_RES ), /* pp_bits */ 876 AO_MCA_II_BIT_MEM, /* ii_bits */ 877 ( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_WR ), /* r4_bits */ 878 39, /* addr valid hi */ 879 3, /* addr valid lo */ 880 AO_AED_PANIC_ALWAYS, /* panic_when */ 881 AO_AED_F_PHYSICAL, /* flags */ 882 0, /* errtype */ 883 }, 884 885 /* Hypertransport CRC error */ 886 { 887 FM_EREPORT_CPU_AMD_NB_HT_CRC, 888 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_HT_CRC, 889 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 890 MSR_MC_STATUS_UC, /* mask_res */ 891 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 892 1, /* ext code 0001 */ 893 AO_MCA_PP_BIT_OBS, /* pp_bits */ 894 AO_MCA_II_BIT_GEN, /* ii_bits */ 895 AO_MCA_R4_BIT_ERR, /* r4_bits */ 896 0, /* addr valid hi */ 897 0, /* addr valid lo */ 898 AO_AED_PANIC_ALWAYS, /* panic_when */ 899 0, /* flags */ 900 0, /* errtype */ 901 }, 902 903 /* Hypertransport Sync packet error */ 904 { 905 FM_EREPORT_CPU_AMD_NB_HT_SYNC, 906 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_HT_SYNC, 907 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 908 MSR_MC_STATUS_UC, /* mask_res */ 909 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 910 2, /* ext code 0010 */ 911 AO_MCA_PP_BIT_OBS, /* pp_bits */ 912 AO_MCA_II_BIT_GEN, /* ii_bits */ 913 AO_MCA_R4_BIT_ERR, /* r4_bits */ 914 0, /* addr valid hi */ 915 0, /* addr valid lo */ 916 AO_AED_PANIC_ALWAYS, /* panic_when */ 917 0, /* flags */ 918 0, /* errtype */ 919 }, 920 921 /* Master Abort */ 922 { 923 FM_EREPORT_CPU_AMD_NB_MA, 924 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_MA, 925 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 926 MSR_MC_STATUS_UC, /* mask_res */ 927 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 928 3, /* ext code 0011 */ 929 ( AO_MCA_PP_BIT_SRC | AO_MCA_PP_BIT_OBS ), /* pp_bits */ 930 ( AO_MCA_II_BIT_MEM | AO_MCA_II_BIT_IO ), /* ii_bits */ 931 ( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_WR ), /* r4_bits */ 932 39, /* addr valid hi */ 933 3, /* addr valid lo */ 934 AO_AED_PANIC_NEVER, /* panic_when */ 935 AO_AED_F_PHYSICAL, /* flags */ 936 0, /* errtype */ 937 }, 938 939 /* Target Abort */ 940 { 941 FM_EREPORT_CPU_AMD_NB_TA, 942 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_TA, 943 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 944 MSR_MC_STATUS_UC, /* mask_res */ 945 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 946 4, /* ext code 0100 */ 947 ( AO_MCA_PP_BIT_SRC | AO_MCA_PP_BIT_OBS ), /* pp_bits */ 948 ( AO_MCA_II_BIT_MEM | AO_MCA_II_BIT_IO ), /* ii_bits */ 949 ( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_WR ), /* r4_bits */ 950 39, /* addr valid hi */ 951 3, /* addr valid lo */ 952 AO_AED_PANIC_NEVER, /* panic_when */ 953 AO_AED_F_PHYSICAL, /* flags */ 954 0, /* errtype */ 955 }, 956 957 /* GART Table Walk Error */ 958 { 959 FM_EREPORT_CPU_AMD_NB_GART_WALK, 960 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_GART_WALK, 961 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 962 MSR_MC_STATUS_UC, /* mask_res */ 963 AMD_ERRCODE_MKTLB(MCAX86_ERRCODE_TT_GEN, MCAX86_ERRCODE_LL_LG), 964 5, /* ext code 0101 */ 965 0, /* pp_bits */ 966 0, /* ii_bits */ 967 0, /* r4_bits */ 968 39, /* addr valid hi */ 969 3, /* addr valid lo */ 970 AO_AED_PANIC_NEVER, /* panic_when */ 971 AO_AED_F_PHYSICAL, /* flags */ 972 0, /* errtype */ 973 }, 974 975 /* Atomic Read/Modify/Write error */ 976 { 977 FM_EREPORT_CPU_AMD_NB_RMW, 978 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_RMW, 979 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 980 MSR_MC_STATUS_UC, /* mask_res */ 981 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 982 6, /* ext code 0110 */ 983 AO_MCA_PP_BIT_OBS, /* pp_bits */ 984 AO_MCA_II_BIT_IO, /* ii_bits */ 985 AO_MCA_R4_BIT_ERR, /* r4_bits */ 986 39, /* addr valid hi */ 987 3, /* addr valid lo */ 988 AO_AED_PANIC_ALWAYS, /* panic_when */ 989 AO_AED_F_PHYSICAL, /* flags */ 990 0, /* errtype */ 991 }, 992 993 /* Watchdog error (timeout) */ 994 { 995 FM_EREPORT_CPU_AMD_NB_WDOG, 996 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_WDOG, 997 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 998 MSR_MC_STATUS_UC, /* mask_res */ 999 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_TIMEOUT, 0, 0, MCAX86_ERRCODE_LL_LG), 1000 7, /* ext code 0111 */ 1001 AO_MCA_PP_BIT_GEN, /* pp_bits */ 1002 AO_MCA_II_BIT_GEN, /* ii_bits */ 1003 AO_MCA_R4_BIT_ERR, /* r4_bits */ 1004 39, /* addr valid hi */ 1005 3, /* addr valid lo */ 1006 AO_AED_PANIC_ALWAYS, /* panic_when */ 1007 0, /* flags */ 1008 0, /* errtype */ 1009 }, 1010 1011 /* DRAM Address Parity Error */ 1012 { 1013 FM_EREPORT_CPU_AMD_NB_DRAMADDR_PAR, 1014 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_DRAMADDR_PAR, 1015 ( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */ 1016 MSR_MC_STATUS_UC, /* mask_res */ 1017 AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG), 1018 13, /* ext code 1101 */ 1019 AO_MCA_PP_BIT_OBS, /* pp_bits */ 1020 AO_MCA_II_BIT_MEM, /* ii_bits */ 1021 AO_MCA_R4_BIT_ERR, /* r4_bits */ 1022 0, /* addr valid hi */ 1023 0, /* addr valid lo */ 1024 AO_AED_PANIC_ALWAYS, /* panic_when */ 1025 0, /* flags */ 1026 0, /* errtype */ 1027 }, 1028 1029 { NULL } 1030 }; 1031 1032 const ao_error_disp_t *ao_error_disp[] = { 1033 ao_error_disp_dc, 1034 ao_error_disp_ic, 1035 ao_error_disp_bu, 1036 ao_error_disp_ls, 1037 ao_error_disp_nb, 1038 }; 1039