#include <sys/mca_x86.h>
#include "ao_mca_disp.h"

static const ao_error_disp_t ao_error_disp_dc[] = {
	/* Correctable D$ data infill from system memory */
	{
	FM_EREPORT_CPU_AMD_DC_INF_SYS_ECC1,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_INF_SYS_ECC1,
	( AMD_BANK_STAT_CECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask */
	AMD_BANK_STAT_CECC, /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	0, /* ext code 0000 */
	AO_MCA_PP_BIT_SRC, /* pp_bits */
	( AO_MCA_II_BIT_MEM | AO_MCA_II_BIT_IO ), /* ii_bits */
	AO_MCA_R4_BIT_DRD, /* r4_bits */
	39, /* addr valid hi */
	6, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Correctable D$ data infill from L2$ */
	{
	FM_EREPORT_CPU_AMD_DC_INF_L2_ECC1,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_INF_L2_ECC1,
	( AMD_BANK_STAT_CECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask */
	AMD_BANK_STAT_CECC, /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L2),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	AO_MCA_R4_BIT_DRD, /* r4_bits */
	39, /* addr valid hi */
	6, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Uncorrectable D$ data infill from system memory */
	{
	FM_EREPORT_CPU_AMD_DC_INF_SYS_ECCM,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_INF_SYS_ECCM,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC | AMD_BANK_STAT_CECC ), /* mask */
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	0, /* ext code 0000 */
	AO_MCA_PP_BIT_SRC, /* pp_bits */
	( AO_MCA_II_BIT_MEM | AO_MCA_II_BIT_IO ), /* ii_bits */
	AO_MCA_R4_BIT_DRD, /* r4_bits */
	39, /* addr valid hi */
	6, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Uncorrectable D$ data infill from L2$ */
	{
	FM_EREPORT_CPU_AMD_DC_INF_L2_ECCM,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_INF_L2_ECCM,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC | AMD_BANK_STAT_CECC ), /* mask */
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L2),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	AO_MCA_R4_BIT_DRD, /* r4_bits */
	39, /* addr valid hi */
	6, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Correctable single-bit error in Data Array from scrub */
	{
	FM_EREPORT_CPU_AMD_DC_DATA_ECC1,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_DATA_ECC1,
	( AMD_BANK_STAT_CECC | AMD_BANK_STAT_SCRUB | MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask */
	( AMD_BANK_STAT_CECC | AMD_BANK_STAT_SCRUB ), /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L1),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	AO_MCA_R4_BIT_ERR, /* r4_bits */
	11, /* addr valid hi */
	3, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Uncorrectable single-bit error in Data Array */
	{
	FM_EREPORT_CPU_AMD_DC_DATA_ECC1_UC,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_DATA_ECC1_UC,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_SCRUB ), /* mask */
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC ), /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L1),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	( AO_MCA_R4_BIT_DRD | AO_MCA_R4_BIT_DWR ), /* r4_bits */
	39, /* addr valid hi */
	3, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Uncorrectable single-bit error in Data Array */
	{
	FM_EREPORT_CPU_AMD_DC_DATA_ECC1_UC,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_DATA_ECC1_UC,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_SCRUB ), /* mask */
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC ), /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L1),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	( AO_MCA_R4_BIT_EVICT | AO_MCA_R4_BIT_SNOOP ), /* r4_bits */
	11, /* addr valid hi */
	6, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Uncorrectable multi-bit error in Data Array */
	{
	FM_EREPORT_CPU_AMD_DC_DATA_ECCM,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_DATA_ECCM,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_SCRUB ), /* mask */
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L1),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	( AO_MCA_R4_BIT_DRD | AO_MCA_R4_BIT_DWR ), /* r4_bits */
	39, /* addr valid hi */
	3, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Uncorrectable multi-bit error in Data Array */
	{
	FM_EREPORT_CPU_AMD_DC_DATA_ECCM,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_DATA_ECCM,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_SCRUB ), /* mask */
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L1),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	( AO_MCA_R4_BIT_EVICT | AO_MCA_R4_BIT_SNOOP ), /* r4_bits */
	11, /* addr valid hi */
	6, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Uncorrectable multi-bit error in Data Array from scrub */
	{
	FM_EREPORT_CPU_AMD_DC_DATA_ECCM,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_DATA_ECCM,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC | AMD_BANK_STAT_SCRUB | AMD_BANK_STAT_CECC ), /* mask */
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC | AMD_BANK_STAT_SCRUB ), /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L1),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	AO_MCA_R4_BIT_ERR, /* r4_bits */
	11, /* addr valid hi */
	3, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Main Tag Array Parity Error */
	{
	FM_EREPORT_CPU_AMD_DC_TAG_PAR,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_TAG_PAR,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L1),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	( AO_MCA_R4_BIT_DRD | AO_MCA_R4_BIT_DWR ), /* r4_bits */
	39, /* addr valid hi */
	3, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Snoop Tag Array Parity Error */
	{
	FM_EREPORT_CPU_AMD_DC_STAG_PAR,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_STAG_PAR,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L1),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	( AO_MCA_R4_BIT_SNOOP | AO_MCA_R4_BIT_EVICT ), /* r4_bits */
	11, /* addr valid hi */
	6, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* L1 DTLB Parity Error */
	{
	FM_EREPORT_CPU_AMD_DC_L1TLB_PAR,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_L1TLB_PAR,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKTLB(MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L1),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	0, /* r4_bits */
	47, /* addr valid hi */
	12, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_LINEAR, /* flags */
	0, /* errtype */
	},

	/* L1 DTLB Parity Error (multimatch) */
	{
	FM_EREPORT_CPU_AMD_DC_L1TLB_PAR,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_L1TLB_PAR,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKTLB(MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L1),
	1, /* ext code 0001 */
	0, /* pp_bits */
	0, /* ii_bits */
	0, /* r4_bits */
	47, /* addr valid hi */
	12, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_LINEAR, /* flags */
	0, /* errtype */
	},

	/* L2 DTLB Parity Error */
	{
	FM_EREPORT_CPU_AMD_DC_L2TLB_PAR,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_L2TLB_PAR,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKTLB(MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L2),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	0, /* r4_bits */
	47, /* addr valid hi */
	12, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_LINEAR, /* flags */
	0, /* errtype */
	},

	/* L2 DTLB Parity Error (multimatch) */
	{
	FM_EREPORT_CPU_AMD_DC_L2TLB_PAR,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_L2TLB_PAR,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKTLB(MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L2),
	1, /* ext code 0001 */
	0, /* pp_bits */
	0, /* ii_bits */
	0, /* r4_bits */
	47, /* addr valid hi */
	12, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_LINEAR, /* flags */
	0, /* errtype */
	},

	{ NULL }
};

static const ao_error_disp_t ao_error_disp_ic[] = {
	/* Correctable I$ data infill from system memory */
	{
	FM_EREPORT_CPU_AMD_IC_INF_SYS_ECC1,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_INF_SYS_ECC1,
	( AMD_BANK_STAT_CECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask */
	AMD_BANK_STAT_CECC, /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	0, /* ext code 0000 */
	AO_MCA_PP_BIT_SRC, /* pp_bits */
	AO_MCA_II_BIT_MEM, /* ii_bits */
	AO_MCA_R4_BIT_IRD, /* r4_bits */
	39, /* addr valid hi */
	6, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Correctable I$ data infill from L2$ */
	{
	FM_EREPORT_CPU_AMD_IC_INF_L2_ECC1,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_INF_L2_ECC1,
	( AMD_BANK_STAT_CECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask */
	AMD_BANK_STAT_CECC, /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L2),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	AO_MCA_R4_BIT_IRD, /* r4_bits */
	39, /* addr valid hi */
	6, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Uncorrectable I$ data infill from system memory */
	{
	FM_EREPORT_CPU_AMD_IC_INF_SYS_ECCM,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_INF_SYS_ECCM,
	( AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC ), /* mask */
	( AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	0, /* ext code 0000 */
	AO_MCA_PP_BIT_SRC, /* pp_bits */
	AO_MCA_II_BIT_MEM, /* ii_bits */
	AO_MCA_R4_BIT_IRD, /* r4_bits */
	39, /* addr valid hi */
	6, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Uncorrectable I$ data infill from L2$ */
	{
	FM_EREPORT_CPU_AMD_IC_INF_L2_ECCM,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_INF_L2_ECCM,
	( AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC ), /* mask */
	( AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L2),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	AO_MCA_R4_BIT_IRD, /* r4_bits */
	39, /* addr valid hi */
	6, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Data Array Parity Error */
	{
	FM_EREPORT_CPU_AMD_IC_DATA_PAR,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_DATA_PAR,
	( AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask */
	0, /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L1),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	AO_MCA_R4_BIT_IRD, /* r4_bits */
	47, /* addr valid hi */
	4, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	AO_AED_F_LINEAR, /* flags */
	0, /* errtype */
	},

	/* Main Tag Array Parity Error */
	{
	FM_EREPORT_CPU_AMD_IC_TAG_PAR,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_TAG_PAR,
	( AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask */
	0, /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L1),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	AO_MCA_R4_BIT_IRD, /* r4_bits */
	47, /* addr valid hi */
	6, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	AO_AED_F_LINEAR, /* flags */
	0, /* errtype */
	},

	/* Main Tag Array Parity Error */
	{
	FM_EREPORT_CPU_AMD_IC_TAG_PAR,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_TAG_PAR,
	( AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask */
	0, /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L1),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	AO_MCA_R4_BIT_EVICT, /* r4_bits */
	0, /* addr valid hi */
	0, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	AO_AED_F_LINEAR, /* flags */
	0, /* errtype */
	},

	/* Snoop Tag Array Parity Error */
	{
	FM_EREPORT_CPU_AMD_IC_STAG_PAR,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_STAG_PAR,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L1),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	AO_MCA_R4_BIT_SNOOP, /* r4_bits */
	39, /* addr valid hi */
	6, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Snoop Tag Array Parity Error */
	{
	FM_EREPORT_CPU_AMD_IC_STAG_PAR,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_STAG_PAR,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L1),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	AO_MCA_R4_BIT_EVICT, /* r4_bits */
	0, /* addr valid hi */
	0, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* L1 ITLB Parity Error */
	{
	FM_EREPORT_CPU_AMD_IC_L1TLB_PAR,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_L1TLB_PAR,
	( AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask */
	0, /* mask_res */
	AMD_ERRCODE_MKTLB(MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L1),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	0, /* r4_bits */
	47, /* addr valid hi */
	12, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	( AO_AED_F_LINEAR | AO_AED_F_PAGEALIGNED ), /* flags */
	0, /* errtype */
	},

	/* L1 ITLB Parity Error (multimatch) */
	{
	FM_EREPORT_CPU_AMD_IC_L1TLB_PAR,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_L1TLB_PAR,
	( AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask */
	0, /* mask_res */
	AMD_ERRCODE_MKTLB(MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L1),
	1, /* ext code 0001 */
	0, /* pp_bits */
	0, /* ii_bits */
	0, /* r4_bits */
	47, /* addr valid hi */
	12, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	( AO_AED_F_LINEAR | AO_AED_F_PAGEALIGNED ), /* flags */
	0, /* errtype */
	},

	/* L2 ITLB Parity Error */
	{
	FM_EREPORT_CPU_AMD_IC_L2TLB_PAR,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_L2TLB_PAR,
	( AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask */
	0, /* mask_res */
	AMD_ERRCODE_MKTLB(MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L2),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	0, /* r4_bits */
	47, /* addr valid hi */
	12, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	AO_AED_F_LINEAR, /* flags */
	0, /* errtype */
	},

	/* L2 ITLB Parity Error (multimatch) */
	{
	FM_EREPORT_CPU_AMD_IC_L2TLB_PAR,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_L2TLB_PAR,
	( AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask */
	0, /* mask_res */
	AMD_ERRCODE_MKTLB(MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L2),
	1, /* ext code 0001 */
	0, /* pp_bits */
	0, /* ii_bits */
	0, /* r4_bits */
	47, /* addr valid hi */
	12, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	AO_AED_F_LINEAR, /* flags */
	0, /* errtype */
	},

	/* System Data Read Error */
	{
	FM_EREPORT_CPU_AMD_IC_RDDE,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_RDDE,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	0, /* ext code 0000 */
	AO_MCA_PP_BIT_SRC, /* pp_bits */
	AO_MCA_II_BIT_MEM, /* ii_bits */
	AO_MCA_R4_BIT_IRD, /* r4_bits */
	0, /* addr valid hi */
	0, /* addr valid lo */
	AO_AED_PANIC_IFMCE, /* panic_when */
	0, /* flags */
	0, /* errtype */
	},

	{ NULL }
};

static const ao_error_disp_t ao_error_disp_bu[] = {
	/* L2 data array single-bit ECC during TLB reload, snoop, or copyback */
	{
	FM_EREPORT_CPU_AMD_BU_L2D_ECC1,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2D_ECC1,
	( AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask */
	AMD_BANK_STAT_CECC, /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_GEN, MCAX86_ERRCODE_LL_L2),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_SNOOP | AO_MCA_R4_BIT_EVICT ), /* r4_bits */
	39, /* addr valid hi */
	6, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* L2 data array multi-bit ECC during TLB reload, snoop, or copyback */
	{
	FM_EREPORT_CPU_AMD_BU_L2D_ECCM,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2D_ECCM,
	( AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC ), /* mask */
	( AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_GEN, MCAX86_ERRCODE_LL_L2),
	0, /* ext code 0000 */
	0, /* pp_bits */
	0, /* ii_bits */
	( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_SNOOP | AO_MCA_R4_BIT_EVICT ), /* r4_bits */
	39, /* addr valid hi */
	6, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* L2 main tag array single-bit ECC error on scrubber access */
	{
	FM_EREPORT_CPU_AMD_BU_L2T_ECC1,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2T_ECC1,
	( AMD_BANK_STAT_CECC | AMD_BANK_STAT_SCRUB | AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC ), /* mask */
	( AMD_BANK_STAT_CECC | AMD_BANK_STAT_SCRUB ), /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L2),
	2, /* ext code 0010 */
	0, /* pp_bits */
	0, /* ii_bits */
	AO_MCA_R4_BIT_ERR, /* r4_bits */
	15, /* addr valid hi */
	0, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	( AO_AED_F_PHYSICAL | AO_AED_F_L2SETWAY ), /* flags */
	0, /* errtype */
	},

	/* L2 main tag array multi-bit ECC error on scrubber access */
	{
	FM_EREPORT_CPU_AMD_BU_L2T_ECCM,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2T_ECCM,
	( AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_SCRUB | AMD_BANK_STAT_CECC ), /* mask */
	( AMD_BANK_STAT_UECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_SCRUB ), /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L2),
	2, /* ext code 0010 */
	0, /* pp_bits */
	0, /* ii_bits */
	AO_MCA_R4_BIT_ERR, /* r4_bits */
	15, /* addr valid hi */
	0, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	( AO_AED_F_PHYSICAL | AO_AED_F_L2SETWAY ), /* flags */
	0, /* errtype */
	},

	/* L2 main tag array parity error on I$ fetch */
	{
	FM_EREPORT_CPU_AMD_BU_L2T_PAR,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2T_PAR,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L2),
	2, /* ext code 0010 */
	0, /* pp_bits */
	0, /* ii_bits */
	AO_MCA_R4_BIT_IRD, /* r4_bits */
	15, /* addr valid hi */
	0, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	( AO_AED_F_PHYSICAL | AO_AED_F_L2SETWAY ), /* flags */
	0, /* errtype */
	},

	/* L2 main tag array parity error on D$ fetch */
	{
	FM_EREPORT_CPU_AMD_BU_L2T_PAR,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2T_PAR,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_DATA, MCAX86_ERRCODE_LL_L2),
	2, /* ext code 0010 */
	0, /* pp_bits */
	0, /* ii_bits */
	AO_MCA_R4_BIT_DRD, /* r4_bits */
	15, /* addr valid hi */
	0, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	( AO_AED_F_PHYSICAL | AO_AED_F_L2SETWAY ), /* flags */
	0, /* errtype */
	},

	/* L2 main tag array parity error on TLB reload, snoop, or copyback */
	{
	FM_EREPORT_CPU_AMD_BU_L2T_PAR,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2T_PAR,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_GEN, MCAX86_ERRCODE_LL_L2),
	2, /* ext code 0010 */
	0, /* pp_bits */
	0, /* ii_bits */
	( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_SNOOP | AO_MCA_R4_BIT_EVICT ), /* r4_bits */
	15, /* addr valid hi */
	0, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	( AO_AED_F_PHYSICAL | AO_AED_F_L2SETWAY ), /* flags */
	0, /* errtype */
	},

	/* L2 main tag array parity error on scrubber access */
	{
	FM_EREPORT_CPU_AMD_BU_L2T_PAR,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2T_PAR,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_SCRUB | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_SCRUB ), /* mask_res */
	AMD_ERRCODE_MKMEM(0, MCAX86_ERRCODE_TT_INSTR, MCAX86_ERRCODE_LL_L2),
	2, /* ext code 0010 */
	0, /* pp_bits */
	0, /* ii_bits */
	AO_MCA_R4_BIT_ERR, /* r4_bits */
	15, /* addr valid hi */
	0, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	( AO_AED_F_PHYSICAL | AO_AED_F_L2SETWAY ), /* flags */
	0, /* errtype */
	},

	/* System data single-bit ECC for hardware prefetch or TLB reload */
	{
	FM_EREPORT_CPU_AMD_BU_S_ECC1,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_S_ECC1,
	( AMD_BANK_STAT_CECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask */
	AMD_BANK_STAT_CECC, /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	0, /* ext code 0000 */
	AO_MCA_PP_BIT_SRC, /* pp_bits */
	( AO_MCA_II_BIT_MEM | AO_MCA_II_BIT_IO ), /* ii_bits */
	AO_MCA_R4_BIT_RD, /* r4_bits */
	39, /* addr valid hi */
	6, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* System data single-bit ECC for hardware prefetch or TLB reload */
	{
	FM_EREPORT_CPU_AMD_BU_S_ECC1,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_S_ECC1,
	( AMD_BANK_STAT_CECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask */
	AMD_BANK_STAT_CECC, /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	0, /* ext code 0000 */
	AO_MCA_PP_BIT_SRC, /* pp_bits */
	( AO_MCA_II_BIT_MEM | AO_MCA_II_BIT_IO ), /* ii_bits */
	AO_MCA_R4_BIT_PREFETCH, /* r4_bits */
	0, /* addr valid hi */
	0, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* System data multi-bit ECC for hardware prefetch or TLB reload */
	{
	FM_EREPORT_CPU_AMD_BU_S_ECCM,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_S_ECCM,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC | AMD_BANK_STAT_CECC ), /* mask */
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	0, /* ext code 0000 */
	AO_MCA_PP_BIT_SRC, /* pp_bits */
	( AO_MCA_II_BIT_MEM | AO_MCA_II_BIT_IO ), /* ii_bits */
	AO_MCA_R4_BIT_RD, /* r4_bits */
	39, /* addr valid hi */
	6, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* System data multi-bit ECC for hardware prefetch or TLB reload */
	{
	FM_EREPORT_CPU_AMD_BU_S_ECCM,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_S_ECCM,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC | AMD_BANK_STAT_CECC ), /* mask */
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	0, /* ext code 0000 */
	AO_MCA_PP_BIT_SRC, /* pp_bits */
	( AO_MCA_II_BIT_MEM | AO_MCA_II_BIT_IO ), /* ii_bits */
	AO_MCA_R4_BIT_PREFETCH, /* r4_bits */
	0, /* addr valid hi */
	0, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* System data read error for TLB reload or hardware prefetch */
	{
	FM_EREPORT_CPU_AMD_BU_S_RDE,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_S_RDE,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	0, /* ext code 0000 */
	AO_MCA_PP_BIT_SRC, /* pp_bits */
	( AO_MCA_II_BIT_MEM | AO_MCA_II_BIT_IO ), /* ii_bits */
	( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_PREFETCH ), /* r4_bits */
	39, /* addr valid hi */
	6, /* addr valid lo */
	AO_AED_PANIC_IFMCE, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	{ NULL }
};

static const ao_error_disp_t ao_error_disp_ls[] = {
	/* System data read error */
	{
	FM_EREPORT_CPU_AMD_LS_S_RDE,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_LS_S_RDE,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	0, /* ext code 0000 */
	AO_MCA_PP_BIT_SRC, /* pp_bits */
	( AO_MCA_II_BIT_MEM | AO_MCA_II_BIT_IO ), /* ii_bits */
	( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_WR ), /* r4_bits */
	39, /* addr valid hi */
	6, /* addr valid lo */
	AO_AED_PANIC_IFMCE, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	{ NULL }
};

static const ao_error_disp_t ao_error_disp_nb[] = {
	/* Correctable ECC error from Normal ECC */
	{
	FM_EREPORT_CPU_AMD_NB_MEM_CE,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_MEM_CE,
	( AMD_BANK_STAT_CECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask */
	AMD_BANK_STAT_CECC, /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	0, /* ext code 0000 */
	( AO_MCA_PP_BIT_SRC | AO_MCA_PP_BIT_RES ), /* pp_bits */
	AO_MCA_II_BIT_MEM, /* ii_bits */
	( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_WR ), /* r4_bits */
	39, /* addr valid hi */
	3, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Uncorrectable ECC error from Normal ECC */
	{
	FM_EREPORT_CPU_AMD_NB_MEM_UE,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_MEM_UE,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC | AMD_BANK_STAT_CECC ), /* mask */
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	0, /* ext code 0000 */
	( AO_MCA_PP_BIT_SRC | AO_MCA_PP_BIT_RES ), /* pp_bits */
	AO_MCA_II_BIT_MEM, /* ii_bits */
	( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_WR ), /* r4_bits */
	39, /* addr valid hi */
	3, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Correctable ECC error from ChipKill ECC */
	{
	FM_EREPORT_CPU_AMD_NB_MEM_CE,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_MEM_CE,
	( AMD_BANK_STAT_CECC | MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask */
	AMD_BANK_STAT_CECC, /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	8, /* ext code 1000 */
	( AO_MCA_PP_BIT_SRC | AO_MCA_PP_BIT_RES ), /* pp_bits */
	AO_MCA_II_BIT_MEM, /* ii_bits */
	( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_WR ), /* r4_bits */
	39, /* addr valid hi */
	3, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Uncorrectable ECC error from ChipKill ECC */
	{
	FM_EREPORT_CPU_AMD_NB_MEM_UE,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_MEM_UE,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC | AMD_BANK_STAT_CECC ), /* mask */
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_UECC ), /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	8, /* ext code 1000 */
	( AO_MCA_PP_BIT_SRC | AO_MCA_PP_BIT_RES ), /* pp_bits */
	AO_MCA_II_BIT_MEM, /* ii_bits */
	( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_WR ), /* r4_bits */
	39, /* addr valid hi */
	3, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Hypertransport CRC error */
	{
	FM_EREPORT_CPU_AMD_NB_HT_CRC,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_HT_CRC,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	1, /* ext code 0001 */
	AO_MCA_PP_BIT_OBS, /* pp_bits */
	AO_MCA_II_BIT_GEN, /* ii_bits */
	AO_MCA_R4_BIT_ERR, /* r4_bits */
	0, /* addr valid hi */
	0, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	0, /* flags */
	0, /* errtype */
	},

	/* Hypertransport Sync packet error */
	{
	FM_EREPORT_CPU_AMD_NB_HT_SYNC,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_HT_SYNC,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	2, /* ext code 0010 */
	AO_MCA_PP_BIT_OBS, /* pp_bits */
	AO_MCA_II_BIT_GEN, /* ii_bits */
	AO_MCA_R4_BIT_ERR, /* r4_bits */
	0, /* addr valid hi */
	0, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	0, /* flags */
	0, /* errtype */
	},

	/* Master Abort */
	{
	FM_EREPORT_CPU_AMD_NB_MA,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_MA,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	3, /* ext code 0011 */
	( AO_MCA_PP_BIT_SRC | AO_MCA_PP_BIT_OBS ), /* pp_bits */
	( AO_MCA_II_BIT_MEM | AO_MCA_II_BIT_IO ), /* ii_bits */
	( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_WR ), /* r4_bits */
	39, /* addr valid hi */
	3, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Target Abort */
	{
	FM_EREPORT_CPU_AMD_NB_TA,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_TA,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	4, /* ext code 0100 */
	( AO_MCA_PP_BIT_SRC | AO_MCA_PP_BIT_OBS ), /* pp_bits */
	( AO_MCA_II_BIT_MEM | AO_MCA_II_BIT_IO ), /* ii_bits */
	( AO_MCA_R4_BIT_RD | AO_MCA_R4_BIT_WR ), /* r4_bits */
	39, /* addr valid hi */
	3, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* GART Table Walk Error */
	{
	FM_EREPORT_CPU_AMD_NB_GART_WALK,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_GART_WALK,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKTLB(MCAX86_ERRCODE_TT_GEN, MCAX86_ERRCODE_LL_LG),
	5, /* ext code 0101 */
	0, /* pp_bits */
	0, /* ii_bits */
	0, /* r4_bits */
	39, /* addr valid hi */
	3, /* addr valid lo */
	AO_AED_PANIC_NEVER, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Atomic Read/Modify/Write error */
	{
	FM_EREPORT_CPU_AMD_NB_RMW,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_RMW,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	6, /* ext code 0110 */
	AO_MCA_PP_BIT_OBS, /* pp_bits */
	AO_MCA_II_BIT_IO, /* ii_bits */
	AO_MCA_R4_BIT_ERR, /* r4_bits */
	39, /* addr valid hi */
	3, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	AO_AED_F_PHYSICAL, /* flags */
	0, /* errtype */
	},

	/* Watchdog error (timeout) */
	{
	FM_EREPORT_CPU_AMD_NB_WDOG,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_WDOG,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_TIMEOUT, 0, 0, MCAX86_ERRCODE_LL_LG),
	7, /* ext code 0111 */
	AO_MCA_PP_BIT_GEN, /* pp_bits */
	AO_MCA_II_BIT_GEN, /* ii_bits */
	AO_MCA_R4_BIT_ERR, /* r4_bits */
	39, /* addr valid hi */
	3, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	0, /* flags */
	0, /* errtype */
	},

	/* DRAM Address Parity Error */
	{
	FM_EREPORT_CPU_AMD_NB_DRAMADDR_PAR,
	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_DRAMADDR_PAR,
	( MSR_MC_STATUS_UC | AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC ), /* mask */
	MSR_MC_STATUS_UC, /* mask_res */
	AMD_ERRCODE_MKBUS(0, MCAX86_ERRCODE_T_NONE, 0, 0, MCAX86_ERRCODE_LL_LG),
	13, /* ext code 1101 */
	AO_MCA_PP_BIT_OBS, /* pp_bits */
	AO_MCA_II_BIT_MEM, /* ii_bits */
	AO_MCA_R4_BIT_ERR, /* r4_bits */
	0, /* addr valid hi */
	0, /* addr valid lo */
	AO_AED_PANIC_ALWAYS, /* panic_when */
	0, /* flags */
	0, /* errtype */
	},

	{ NULL }
};

const ao_error_disp_t *ao_error_disp[] = {
	ao_error_disp_dc,
	ao_error_disp_ic,
	ao_error_disp_bu,
	ao_error_disp_ls,
	ao_error_disp_nb,
};