1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AArch64 code 4 * 5 * Copyright (C) 2018, Red Hat, Inc. 6 */ 7 8 #include <linux/compiler.h> 9 #include <assert.h> 10 11 #include "guest_modes.h" 12 #include "kvm_util.h" 13 #include "processor.h" 14 #include "ucall_common.h" 15 #include "vgic.h" 16 17 #include <linux/bitfield.h> 18 #include <linux/sizes.h> 19 20 #define DEFAULT_ARM64_GUEST_STACK_VADDR_MIN 0xac0000 21 22 static vm_vaddr_t exception_handlers; 23 24 static uint64_t page_align(struct kvm_vm *vm, uint64_t v) 25 { 26 return (v + vm->page_size) & ~(vm->page_size - 1); 27 } 28 29 static uint64_t pgd_index(struct kvm_vm *vm, vm_vaddr_t gva) 30 { 31 unsigned int shift = (vm->pgtable_levels - 1) * (vm->page_shift - 3) + vm->page_shift; 32 uint64_t mask = (1UL << (vm->va_bits - shift)) - 1; 33 34 return (gva >> shift) & mask; 35 } 36 37 static uint64_t pud_index(struct kvm_vm *vm, vm_vaddr_t gva) 38 { 39 unsigned int shift = 2 * (vm->page_shift - 3) + vm->page_shift; 40 uint64_t mask = (1UL << (vm->page_shift - 3)) - 1; 41 42 TEST_ASSERT(vm->pgtable_levels == 4, 43 "Mode %d does not have 4 page table levels", vm->mode); 44 45 return (gva >> shift) & mask; 46 } 47 48 static uint64_t pmd_index(struct kvm_vm *vm, vm_vaddr_t gva) 49 { 50 unsigned int shift = (vm->page_shift - 3) + vm->page_shift; 51 uint64_t mask = (1UL << (vm->page_shift - 3)) - 1; 52 53 TEST_ASSERT(vm->pgtable_levels >= 3, 54 "Mode %d does not have >= 3 page table levels", vm->mode); 55 56 return (gva >> shift) & mask; 57 } 58 59 static uint64_t pte_index(struct kvm_vm *vm, vm_vaddr_t gva) 60 { 61 uint64_t mask = (1UL << (vm->page_shift - 3)) - 1; 62 return (gva >> vm->page_shift) & mask; 63 } 64 65 static inline bool use_lpa2_pte_format(struct kvm_vm *vm) 66 { 67 return (vm->page_size == SZ_4K || vm->page_size == SZ_16K) && 68 (vm->pa_bits > 48 || vm->va_bits > 48); 69 } 70 71 static uint64_t addr_pte(struct kvm_vm *vm, uint64_t pa, uint64_t attrs) 72 { 73 uint64_t pte; 74 75 if (use_lpa2_pte_format(vm)) { 76 pte = pa & PTE_ADDR_MASK_LPA2(vm->page_shift); 77 pte |= FIELD_GET(GENMASK(51, 50), pa) << PTE_ADDR_51_50_LPA2_SHIFT; 78 attrs &= ~PTE_ADDR_51_50_LPA2; 79 } else { 80 pte = pa & PTE_ADDR_MASK(vm->page_shift); 81 if (vm->page_shift == 16) 82 pte |= FIELD_GET(GENMASK(51, 48), pa) << PTE_ADDR_51_48_SHIFT; 83 } 84 pte |= attrs; 85 86 return pte; 87 } 88 89 static uint64_t pte_addr(struct kvm_vm *vm, uint64_t pte) 90 { 91 uint64_t pa; 92 93 if (use_lpa2_pte_format(vm)) { 94 pa = pte & PTE_ADDR_MASK_LPA2(vm->page_shift); 95 pa |= FIELD_GET(PTE_ADDR_51_50_LPA2, pte) << 50; 96 } else { 97 pa = pte & PTE_ADDR_MASK(vm->page_shift); 98 if (vm->page_shift == 16) 99 pa |= FIELD_GET(PTE_ADDR_51_48, pte) << 48; 100 } 101 102 return pa; 103 } 104 105 static uint64_t ptrs_per_pgd(struct kvm_vm *vm) 106 { 107 unsigned int shift = (vm->pgtable_levels - 1) * (vm->page_shift - 3) + vm->page_shift; 108 return 1 << (vm->va_bits - shift); 109 } 110 111 static uint64_t __maybe_unused ptrs_per_pte(struct kvm_vm *vm) 112 { 113 return 1 << (vm->page_shift - 3); 114 } 115 116 void virt_arch_pgd_alloc(struct kvm_vm *vm) 117 { 118 size_t nr_pages = page_align(vm, ptrs_per_pgd(vm) * 8) / vm->page_size; 119 120 if (vm->pgd_created) 121 return; 122 123 vm->pgd = vm_phy_pages_alloc(vm, nr_pages, 124 KVM_GUEST_PAGE_TABLE_MIN_PADDR, 125 vm->memslots[MEM_REGION_PT]); 126 vm->pgd_created = true; 127 } 128 129 static void _virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, 130 uint64_t flags) 131 { 132 uint8_t attr_idx = flags & (PTE_ATTRINDX_MASK >> PTE_ATTRINDX_SHIFT); 133 uint64_t pg_attr; 134 uint64_t *ptep; 135 136 TEST_ASSERT((vaddr % vm->page_size) == 0, 137 "Virtual address not on page boundary,\n" 138 " vaddr: 0x%lx vm->page_size: 0x%x", vaddr, vm->page_size); 139 TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, 140 (vaddr >> vm->page_shift)), 141 "Invalid virtual address, vaddr: 0x%lx", vaddr); 142 TEST_ASSERT((paddr % vm->page_size) == 0, 143 "Physical address not on page boundary,\n" 144 " paddr: 0x%lx vm->page_size: 0x%x", paddr, vm->page_size); 145 TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn, 146 "Physical address beyond beyond maximum supported,\n" 147 " paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", 148 paddr, vm->max_gfn, vm->page_size); 149 150 ptep = addr_gpa2hva(vm, vm->pgd) + pgd_index(vm, vaddr) * 8; 151 if (!*ptep) 152 *ptep = addr_pte(vm, vm_alloc_page_table(vm), 153 PGD_TYPE_TABLE | PTE_VALID); 154 155 switch (vm->pgtable_levels) { 156 case 4: 157 ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, vaddr) * 8; 158 if (!*ptep) 159 *ptep = addr_pte(vm, vm_alloc_page_table(vm), 160 PUD_TYPE_TABLE | PTE_VALID); 161 /* fall through */ 162 case 3: 163 ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pmd_index(vm, vaddr) * 8; 164 if (!*ptep) 165 *ptep = addr_pte(vm, vm_alloc_page_table(vm), 166 PMD_TYPE_TABLE | PTE_VALID); 167 /* fall through */ 168 case 2: 169 ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pte_index(vm, vaddr) * 8; 170 break; 171 default: 172 TEST_FAIL("Page table levels must be 2, 3, or 4"); 173 } 174 175 pg_attr = PTE_AF | PTE_ATTRINDX(attr_idx) | PTE_TYPE_PAGE | PTE_VALID; 176 if (!use_lpa2_pte_format(vm)) 177 pg_attr |= PTE_SHARED; 178 179 *ptep = addr_pte(vm, paddr, pg_attr); 180 } 181 182 void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr) 183 { 184 uint64_t attr_idx = MT_NORMAL; 185 186 _virt_pg_map(vm, vaddr, paddr, attr_idx); 187 } 188 189 uint64_t *virt_get_pte_hva(struct kvm_vm *vm, vm_vaddr_t gva) 190 { 191 uint64_t *ptep; 192 193 if (!vm->pgd_created) 194 goto unmapped_gva; 195 196 ptep = addr_gpa2hva(vm, vm->pgd) + pgd_index(vm, gva) * 8; 197 if (!ptep) 198 goto unmapped_gva; 199 200 switch (vm->pgtable_levels) { 201 case 4: 202 ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, gva) * 8; 203 if (!ptep) 204 goto unmapped_gva; 205 /* fall through */ 206 case 3: 207 ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pmd_index(vm, gva) * 8; 208 if (!ptep) 209 goto unmapped_gva; 210 /* fall through */ 211 case 2: 212 ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pte_index(vm, gva) * 8; 213 if (!ptep) 214 goto unmapped_gva; 215 break; 216 default: 217 TEST_FAIL("Page table levels must be 2, 3, or 4"); 218 } 219 220 return ptep; 221 222 unmapped_gva: 223 TEST_FAIL("No mapping for vm virtual address, gva: 0x%lx", gva); 224 exit(EXIT_FAILURE); 225 } 226 227 vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva) 228 { 229 uint64_t *ptep = virt_get_pte_hva(vm, gva); 230 231 return pte_addr(vm, *ptep) + (gva & (vm->page_size - 1)); 232 } 233 234 static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent, uint64_t page, int level) 235 { 236 #ifdef DEBUG 237 static const char * const type[] = { "", "pud", "pmd", "pte" }; 238 uint64_t pte, *ptep; 239 240 if (level == 4) 241 return; 242 243 for (pte = page; pte < page + ptrs_per_pte(vm) * 8; pte += 8) { 244 ptep = addr_gpa2hva(vm, pte); 245 if (!*ptep) 246 continue; 247 fprintf(stream, "%*s%s: %lx: %lx at %p\n", indent, "", type[level], pte, *ptep, ptep); 248 pte_dump(stream, vm, indent + 1, pte_addr(vm, *ptep), level + 1); 249 } 250 #endif 251 } 252 253 void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent) 254 { 255 int level = 4 - (vm->pgtable_levels - 1); 256 uint64_t pgd, *ptep; 257 258 if (!vm->pgd_created) 259 return; 260 261 for (pgd = vm->pgd; pgd < vm->pgd + ptrs_per_pgd(vm) * 8; pgd += 8) { 262 ptep = addr_gpa2hva(vm, pgd); 263 if (!*ptep) 264 continue; 265 fprintf(stream, "%*spgd: %lx: %lx at %p\n", indent, "", pgd, *ptep, ptep); 266 pte_dump(stream, vm, indent + 1, pte_addr(vm, *ptep), level); 267 } 268 } 269 270 void kvm_get_default_vcpu_target(struct kvm_vm *vm, struct kvm_vcpu_init *init) 271 { 272 struct kvm_vcpu_init preferred = {}; 273 274 vm_ioctl(vm, KVM_ARM_PREFERRED_TARGET, &preferred); 275 276 *init = preferred; 277 } 278 279 void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct kvm_vcpu_init *init) 280 { 281 struct kvm_vcpu_init default_init = { .target = -1, }; 282 struct kvm_vm *vm = vcpu->vm; 283 uint64_t sctlr_el1, tcr_el1, ttbr0_el1; 284 285 if (!init) { 286 kvm_get_default_vcpu_target(vm, &default_init); 287 init = &default_init; 288 } 289 290 vcpu_ioctl(vcpu, KVM_ARM_VCPU_INIT, init); 291 vcpu->init = *init; 292 293 /* 294 * Enable FP/ASIMD to avoid trapping when accessing Q0-Q15 295 * registers, which the variable argument list macros do. 296 */ 297 vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_CPACR_EL1), 3 << 20); 298 299 sctlr_el1 = vcpu_get_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SCTLR_EL1)); 300 tcr_el1 = vcpu_get_reg(vcpu, ctxt_reg_alias(vcpu, SYS_TCR_EL1)); 301 302 /* Configure base granule size */ 303 switch (vm->mode) { 304 case VM_MODE_PXXV48_4K: 305 TEST_FAIL("AArch64 does not support 4K sized pages " 306 "with ANY-bit physical address ranges"); 307 case VM_MODE_P52V48_64K: 308 case VM_MODE_P48V48_64K: 309 case VM_MODE_P40V48_64K: 310 case VM_MODE_P36V48_64K: 311 tcr_el1 |= TCR_TG0_64K; 312 break; 313 case VM_MODE_P52V48_16K: 314 case VM_MODE_P48V48_16K: 315 case VM_MODE_P40V48_16K: 316 case VM_MODE_P36V48_16K: 317 case VM_MODE_P36V47_16K: 318 tcr_el1 |= TCR_TG0_16K; 319 break; 320 case VM_MODE_P52V48_4K: 321 case VM_MODE_P48V48_4K: 322 case VM_MODE_P40V48_4K: 323 case VM_MODE_P36V48_4K: 324 tcr_el1 |= TCR_TG0_4K; 325 break; 326 default: 327 TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode); 328 } 329 330 ttbr0_el1 = vm->pgd & GENMASK(47, vm->page_shift); 331 332 /* Configure output size */ 333 switch (vm->mode) { 334 case VM_MODE_P52V48_4K: 335 case VM_MODE_P52V48_16K: 336 case VM_MODE_P52V48_64K: 337 tcr_el1 |= TCR_IPS_52_BITS; 338 ttbr0_el1 |= FIELD_GET(GENMASK(51, 48), vm->pgd) << 2; 339 break; 340 case VM_MODE_P48V48_4K: 341 case VM_MODE_P48V48_16K: 342 case VM_MODE_P48V48_64K: 343 tcr_el1 |= TCR_IPS_48_BITS; 344 break; 345 case VM_MODE_P40V48_4K: 346 case VM_MODE_P40V48_16K: 347 case VM_MODE_P40V48_64K: 348 tcr_el1 |= TCR_IPS_40_BITS; 349 break; 350 case VM_MODE_P36V48_4K: 351 case VM_MODE_P36V48_16K: 352 case VM_MODE_P36V48_64K: 353 case VM_MODE_P36V47_16K: 354 tcr_el1 |= TCR_IPS_36_BITS; 355 break; 356 default: 357 TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode); 358 } 359 360 sctlr_el1 |= SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_I; 361 362 tcr_el1 |= TCR_IRGN0_WBWA | TCR_ORGN0_WBWA | TCR_SH0_INNER; 363 tcr_el1 |= TCR_T0SZ(vm->va_bits); 364 if (use_lpa2_pte_format(vm)) 365 tcr_el1 |= TCR_DS; 366 367 vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SCTLR_EL1), sctlr_el1); 368 vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_TCR_EL1), tcr_el1); 369 vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_MAIR_EL1), DEFAULT_MAIR_EL1); 370 vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_TTBR0_EL1), ttbr0_el1); 371 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_TPIDR_EL1), vcpu->id); 372 } 373 374 void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent) 375 { 376 uint64_t pstate, pc; 377 378 pstate = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pstate)); 379 pc = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc)); 380 381 fprintf(stream, "%*spstate: 0x%.16lx pc: 0x%.16lx\n", 382 indent, "", pstate, pc); 383 } 384 385 void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code) 386 { 387 vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.pc), (uint64_t)guest_code); 388 } 389 390 static struct kvm_vcpu *__aarch64_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id, 391 struct kvm_vcpu_init *init) 392 { 393 size_t stack_size; 394 uint64_t stack_vaddr; 395 struct kvm_vcpu *vcpu = __vm_vcpu_add(vm, vcpu_id); 396 397 stack_size = vm->page_size == 4096 ? DEFAULT_STACK_PGS * vm->page_size : 398 vm->page_size; 399 stack_vaddr = __vm_vaddr_alloc(vm, stack_size, 400 DEFAULT_ARM64_GUEST_STACK_VADDR_MIN, 401 MEM_REGION_DATA); 402 403 aarch64_vcpu_setup(vcpu, init); 404 405 vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SP_EL1), stack_vaddr + stack_size); 406 return vcpu; 407 } 408 409 struct kvm_vcpu *aarch64_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id, 410 struct kvm_vcpu_init *init, void *guest_code) 411 { 412 struct kvm_vcpu *vcpu = __aarch64_vcpu_add(vm, vcpu_id, init); 413 414 vcpu_arch_set_entry_point(vcpu, guest_code); 415 416 return vcpu; 417 } 418 419 struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id) 420 { 421 return __aarch64_vcpu_add(vm, vcpu_id, NULL); 422 } 423 424 void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...) 425 { 426 va_list ap; 427 int i; 428 429 TEST_ASSERT(num >= 1 && num <= 8, "Unsupported number of args,\n" 430 " num: %u", num); 431 432 va_start(ap, num); 433 434 for (i = 0; i < num; i++) { 435 vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.regs[i]), 436 va_arg(ap, uint64_t)); 437 } 438 439 va_end(ap); 440 } 441 442 void kvm_exit_unexpected_exception(int vector, uint64_t ec, bool valid_ec) 443 { 444 ucall(UCALL_UNHANDLED, 3, vector, ec, valid_ec); 445 while (1) 446 ; 447 } 448 449 void assert_on_unhandled_exception(struct kvm_vcpu *vcpu) 450 { 451 struct ucall uc; 452 453 if (get_ucall(vcpu, &uc) != UCALL_UNHANDLED) 454 return; 455 456 if (uc.args[2]) /* valid_ec */ { 457 assert(VECTOR_IS_SYNC(uc.args[0])); 458 TEST_FAIL("Unexpected exception (vector:0x%lx, ec:0x%lx)", 459 uc.args[0], uc.args[1]); 460 } else { 461 assert(!VECTOR_IS_SYNC(uc.args[0])); 462 TEST_FAIL("Unexpected exception (vector:0x%lx)", 463 uc.args[0]); 464 } 465 } 466 467 struct handlers { 468 handler_fn exception_handlers[VECTOR_NUM][ESR_ELx_EC_MAX + 1]; 469 }; 470 471 void vcpu_init_descriptor_tables(struct kvm_vcpu *vcpu) 472 { 473 extern char vectors; 474 475 vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_VBAR_EL1), (uint64_t)&vectors); 476 } 477 478 void route_exception(struct ex_regs *regs, int vector) 479 { 480 struct handlers *handlers = (struct handlers *)exception_handlers; 481 bool valid_ec; 482 int ec = 0; 483 484 switch (vector) { 485 case VECTOR_SYNC_CURRENT: 486 case VECTOR_SYNC_LOWER_64: 487 ec = ESR_ELx_EC(read_sysreg(esr_el1)); 488 valid_ec = true; 489 break; 490 case VECTOR_IRQ_CURRENT: 491 case VECTOR_IRQ_LOWER_64: 492 case VECTOR_FIQ_CURRENT: 493 case VECTOR_FIQ_LOWER_64: 494 case VECTOR_ERROR_CURRENT: 495 case VECTOR_ERROR_LOWER_64: 496 ec = 0; 497 valid_ec = false; 498 break; 499 default: 500 valid_ec = false; 501 goto unexpected_exception; 502 } 503 504 if (handlers && handlers->exception_handlers[vector][ec]) 505 return handlers->exception_handlers[vector][ec](regs); 506 507 unexpected_exception: 508 kvm_exit_unexpected_exception(vector, ec, valid_ec); 509 } 510 511 void vm_init_descriptor_tables(struct kvm_vm *vm) 512 { 513 vm->handlers = __vm_vaddr_alloc(vm, sizeof(struct handlers), 514 vm->page_size, MEM_REGION_DATA); 515 516 *(vm_vaddr_t *)addr_gva2hva(vm, (vm_vaddr_t)(&exception_handlers)) = vm->handlers; 517 } 518 519 void vm_install_sync_handler(struct kvm_vm *vm, int vector, int ec, 520 void (*handler)(struct ex_regs *)) 521 { 522 struct handlers *handlers = addr_gva2hva(vm, vm->handlers); 523 524 assert(VECTOR_IS_SYNC(vector)); 525 assert(vector < VECTOR_NUM); 526 assert(ec <= ESR_ELx_EC_MAX); 527 handlers->exception_handlers[vector][ec] = handler; 528 } 529 530 void vm_install_exception_handler(struct kvm_vm *vm, int vector, 531 void (*handler)(struct ex_regs *)) 532 { 533 struct handlers *handlers = addr_gva2hva(vm, vm->handlers); 534 535 assert(!VECTOR_IS_SYNC(vector)); 536 assert(vector < VECTOR_NUM); 537 handlers->exception_handlers[vector][0] = handler; 538 } 539 540 uint32_t guest_get_vcpuid(void) 541 { 542 return read_sysreg(tpidr_el1); 543 } 544 545 static uint32_t max_ipa_for_page_size(uint32_t vm_ipa, uint32_t gran, 546 uint32_t not_sup_val, uint32_t ipa52_min_val) 547 { 548 if (gran == not_sup_val) 549 return 0; 550 else if (gran >= ipa52_min_val && vm_ipa >= 52) 551 return 52; 552 else 553 return min(vm_ipa, 48U); 554 } 555 556 void aarch64_get_supported_page_sizes(uint32_t ipa, uint32_t *ipa4k, 557 uint32_t *ipa16k, uint32_t *ipa64k) 558 { 559 struct kvm_vcpu_init preferred_init; 560 int kvm_fd, vm_fd, vcpu_fd, err; 561 uint64_t val; 562 uint32_t gran; 563 struct kvm_one_reg reg = { 564 .id = KVM_ARM64_SYS_REG(SYS_ID_AA64MMFR0_EL1), 565 .addr = (uint64_t)&val, 566 }; 567 568 kvm_fd = open_kvm_dev_path_or_exit(); 569 vm_fd = __kvm_ioctl(kvm_fd, KVM_CREATE_VM, (void *)(unsigned long)ipa); 570 TEST_ASSERT(vm_fd >= 0, KVM_IOCTL_ERROR(KVM_CREATE_VM, vm_fd)); 571 572 vcpu_fd = ioctl(vm_fd, KVM_CREATE_VCPU, 0); 573 TEST_ASSERT(vcpu_fd >= 0, KVM_IOCTL_ERROR(KVM_CREATE_VCPU, vcpu_fd)); 574 575 err = ioctl(vm_fd, KVM_ARM_PREFERRED_TARGET, &preferred_init); 576 TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_ARM_PREFERRED_TARGET, err)); 577 err = ioctl(vcpu_fd, KVM_ARM_VCPU_INIT, &preferred_init); 578 TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_ARM_VCPU_INIT, err)); 579 580 err = ioctl(vcpu_fd, KVM_GET_ONE_REG, ®); 581 TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_GET_ONE_REG, vcpu_fd)); 582 583 gran = FIELD_GET(ID_AA64MMFR0_EL1_TGRAN4, val); 584 *ipa4k = max_ipa_for_page_size(ipa, gran, ID_AA64MMFR0_EL1_TGRAN4_NI, 585 ID_AA64MMFR0_EL1_TGRAN4_52_BIT); 586 587 gran = FIELD_GET(ID_AA64MMFR0_EL1_TGRAN64, val); 588 *ipa64k = max_ipa_for_page_size(ipa, gran, ID_AA64MMFR0_EL1_TGRAN64_NI, 589 ID_AA64MMFR0_EL1_TGRAN64_IMP); 590 591 gran = FIELD_GET(ID_AA64MMFR0_EL1_TGRAN16, val); 592 *ipa16k = max_ipa_for_page_size(ipa, gran, ID_AA64MMFR0_EL1_TGRAN16_NI, 593 ID_AA64MMFR0_EL1_TGRAN16_52_BIT); 594 595 close(vcpu_fd); 596 close(vm_fd); 597 close(kvm_fd); 598 } 599 600 #define __smccc_call(insn, function_id, arg0, arg1, arg2, arg3, arg4, arg5, \ 601 arg6, res) \ 602 asm volatile("mov w0, %w[function_id]\n" \ 603 "mov x1, %[arg0]\n" \ 604 "mov x2, %[arg1]\n" \ 605 "mov x3, %[arg2]\n" \ 606 "mov x4, %[arg3]\n" \ 607 "mov x5, %[arg4]\n" \ 608 "mov x6, %[arg5]\n" \ 609 "mov x7, %[arg6]\n" \ 610 #insn "#0\n" \ 611 "mov %[res0], x0\n" \ 612 "mov %[res1], x1\n" \ 613 "mov %[res2], x2\n" \ 614 "mov %[res3], x3\n" \ 615 : [res0] "=r"(res->a0), [res1] "=r"(res->a1), \ 616 [res2] "=r"(res->a2), [res3] "=r"(res->a3) \ 617 : [function_id] "r"(function_id), [arg0] "r"(arg0), \ 618 [arg1] "r"(arg1), [arg2] "r"(arg2), [arg3] "r"(arg3), \ 619 [arg4] "r"(arg4), [arg5] "r"(arg5), [arg6] "r"(arg6) \ 620 : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7") 621 622 623 void smccc_hvc(uint32_t function_id, uint64_t arg0, uint64_t arg1, 624 uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, 625 uint64_t arg6, struct arm_smccc_res *res) 626 { 627 __smccc_call(hvc, function_id, arg0, arg1, arg2, arg3, arg4, arg5, 628 arg6, res); 629 } 630 631 void smccc_smc(uint32_t function_id, uint64_t arg0, uint64_t arg1, 632 uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, 633 uint64_t arg6, struct arm_smccc_res *res) 634 { 635 __smccc_call(smc, function_id, arg0, arg1, arg2, arg3, arg4, arg5, 636 arg6, res); 637 } 638 639 void kvm_selftest_arch_init(void) 640 { 641 /* 642 * arm64 doesn't have a true default mode, so start by computing the 643 * available IPA space and page sizes early. 644 */ 645 guest_modes_append_default(); 646 } 647 648 void vm_vaddr_populate_bitmap(struct kvm_vm *vm) 649 { 650 /* 651 * arm64 selftests use only TTBR0_EL1, meaning that the valid VA space 652 * is [0, 2^(64 - TCR_EL1.T0SZ)). 653 */ 654 sparsebit_set_num(vm->vpages_valid, 0, 655 (1ULL << vm->va_bits) >> vm->page_shift); 656 } 657 658 /* Helper to call wfi instruction. */ 659 void wfi(void) 660 { 661 asm volatile("wfi"); 662 } 663 664 static bool request_mte; 665 static bool request_vgic = true; 666 667 void test_wants_mte(void) 668 { 669 request_mte = true; 670 } 671 672 void test_disable_default_vgic(void) 673 { 674 request_vgic = false; 675 } 676 677 void kvm_arch_vm_post_create(struct kvm_vm *vm, unsigned int nr_vcpus) 678 { 679 if (request_mte && vm_check_cap(vm, KVM_CAP_ARM_MTE)) 680 vm_enable_cap(vm, KVM_CAP_ARM_MTE, 0); 681 682 if (request_vgic && kvm_supports_vgic_v3()) { 683 vm->arch.gic_fd = __vgic_v3_setup(vm, nr_vcpus, 64); 684 vm->arch.has_gic = true; 685 } 686 } 687 688 void kvm_arch_vm_finalize_vcpus(struct kvm_vm *vm) 689 { 690 if (vm->arch.has_gic) 691 __vgic_v3_init(vm->arch.gic_fd); 692 } 693 694 void kvm_arch_vm_release(struct kvm_vm *vm) 695 { 696 if (vm->arch.has_gic) 697 close(vm->arch.gic_fd); 698 } 699