1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SELFTESTS_GIC_V5_H 4 #define __SELFTESTS_GIC_V5_H 5 6 #include <asm/barrier.h> 7 #include <asm/sysreg.h> 8 9 #include <linux/bitfield.h> 10 11 #include "processor.h" 12 13 /* 14 * Definitions for GICv5 instructions for the Current Domain 15 */ 16 #define GICV5_OP_GIC_CDAFF sys_insn(1, 0, 12, 1, 3) 17 #define GICV5_OP_GIC_CDDI sys_insn(1, 0, 12, 2, 0) 18 #define GICV5_OP_GIC_CDDIS sys_insn(1, 0, 12, 1, 0) 19 #define GICV5_OP_GIC_CDHM sys_insn(1, 0, 12, 2, 1) 20 #define GICV5_OP_GIC_CDEN sys_insn(1, 0, 12, 1, 1) 21 #define GICV5_OP_GIC_CDEOI sys_insn(1, 0, 12, 1, 7) 22 #define GICV5_OP_GIC_CDPEND sys_insn(1, 0, 12, 1, 4) 23 #define GICV5_OP_GIC_CDPRI sys_insn(1, 0, 12, 1, 2) 24 #define GICV5_OP_GIC_CDRCFG sys_insn(1, 0, 12, 1, 5) 25 #define GICV5_OP_GICR_CDIA sys_insn(1, 0, 12, 3, 0) 26 #define GICV5_OP_GICR_CDNMIA sys_insn(1, 0, 12, 3, 1) 27 28 /* Definitions for GIC CDAFF */ 29 #define GICV5_GIC_CDAFF_IAFFID_MASK GENMASK_ULL(47, 32) 30 #define GICV5_GIC_CDAFF_TYPE_MASK GENMASK_ULL(31, 29) 31 #define GICV5_GIC_CDAFF_IRM_MASK BIT_ULL(28) 32 #define GICV5_GIC_CDAFF_ID_MASK GENMASK_ULL(23, 0) 33 34 /* Definitions for GIC CDDI */ 35 #define GICV5_GIC_CDDI_TYPE_MASK GENMASK_ULL(31, 29) 36 #define GICV5_GIC_CDDI_ID_MASK GENMASK_ULL(23, 0) 37 38 /* Definitions for GIC CDDIS */ 39 #define GICV5_GIC_CDDIS_TYPE_MASK GENMASK_ULL(31, 29) 40 #define GICV5_GIC_CDDIS_TYPE(r) FIELD_GET(GICV5_GIC_CDDIS_TYPE_MASK, r) 41 #define GICV5_GIC_CDDIS_ID_MASK GENMASK_ULL(23, 0) 42 #define GICV5_GIC_CDDIS_ID(r) FIELD_GET(GICV5_GIC_CDDIS_ID_MASK, r) 43 44 /* Definitions for GIC CDEN */ 45 #define GICV5_GIC_CDEN_TYPE_MASK GENMASK_ULL(31, 29) 46 #define GICV5_GIC_CDEN_ID_MASK GENMASK_ULL(23, 0) 47 48 /* Definitions for GIC CDHM */ 49 #define GICV5_GIC_CDHM_HM_MASK BIT_ULL(32) 50 #define GICV5_GIC_CDHM_TYPE_MASK GENMASK_ULL(31, 29) 51 #define GICV5_GIC_CDHM_ID_MASK GENMASK_ULL(23, 0) 52 53 /* Definitions for GIC CDPEND */ 54 #define GICV5_GIC_CDPEND_PENDING_MASK BIT_ULL(32) 55 #define GICV5_GIC_CDPEND_TYPE_MASK GENMASK_ULL(31, 29) 56 #define GICV5_GIC_CDPEND_ID_MASK GENMASK_ULL(23, 0) 57 58 /* Definitions for GIC CDPRI */ 59 #define GICV5_GIC_CDPRI_PRIORITY_MASK GENMASK_ULL(39, 35) 60 #define GICV5_GIC_CDPRI_TYPE_MASK GENMASK_ULL(31, 29) 61 #define GICV5_GIC_CDPRI_ID_MASK GENMASK_ULL(23, 0) 62 63 /* Definitions for GIC CDRCFG */ 64 #define GICV5_GIC_CDRCFG_TYPE_MASK GENMASK_ULL(31, 29) 65 #define GICV5_GIC_CDRCFG_ID_MASK GENMASK_ULL(23, 0) 66 67 /* Definitions for GICR CDIA */ 68 #define GICV5_GICR_CDIA_VALID_MASK BIT_ULL(32) 69 #define GICV5_GICR_CDIA_VALID(r) FIELD_GET(GICV5_GICR_CDIA_VALID_MASK, r) 70 #define GICV5_GICR_CDIA_TYPE_MASK GENMASK_ULL(31, 29) 71 #define GICV5_GICR_CDIA_ID_MASK GENMASK_ULL(23, 0) 72 #define GICV5_GICR_CDIA_INTID GENMASK_ULL(31, 0) 73 74 /* Definitions for GICR CDNMIA */ 75 #define GICV5_GICR_CDNMIA_VALID_MASK BIT_ULL(32) 76 #define GICV5_GICR_CDNMIA_VALID(r) FIELD_GET(GICV5_GICR_CDNMIA_VALID_MASK, r) 77 #define GICV5_GICR_CDNMIA_TYPE_MASK GENMASK_ULL(31, 29) 78 #define GICV5_GICR_CDNMIA_ID_MASK GENMASK_ULL(23, 0) 79 80 #define gicr_insn(insn) read_sysreg_s(GICV5_OP_GICR_##insn) 81 #define gic_insn(v, insn) write_sysreg_s(v, GICV5_OP_GIC_##insn) 82 83 #define __GIC_BARRIER_INSN(op0, op1, CRn, CRm, op2, Rt) \ 84 __emit_inst(0xd5000000 | \ 85 sys_insn((op0), (op1), (CRn), (CRm), (op2)) | \ 86 ((Rt) & 0x1f)) 87 88 #define GSB_SYS_BARRIER_INSN __GIC_BARRIER_INSN(1, 0, 12, 0, 0, 31) 89 #define GSB_ACK_BARRIER_INSN __GIC_BARRIER_INSN(1, 0, 12, 0, 1, 31) 90 91 #define gsb_ack() asm volatile(GSB_ACK_BARRIER_INSN : : : "memory") 92 #define gsb_sys() asm volatile(GSB_SYS_BARRIER_INSN : : : "memory") 93 94 #define REPEAT_BYTE(x) ((~0ul / 0xff) * (x)) 95 96 #define GICV5_IRQ_DEFAULT_PRI 0b10000 97 98 #define GICV5_ARCH_PPI_SW_PPI 0x3 99 100 void gicv5_ppi_priority_init(void) 101 { 102 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR0_EL1); 103 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR1_EL1); 104 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR2_EL1); 105 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR3_EL1); 106 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR4_EL1); 107 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR5_EL1); 108 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR6_EL1); 109 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR7_EL1); 110 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR8_EL1); 111 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR9_EL1); 112 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR10_EL1); 113 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR11_EL1); 114 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR12_EL1); 115 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR13_EL1); 116 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR14_EL1); 117 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_DEFAULT_PRI), SYS_ICC_PPI_PRIORITYR15_EL1); 118 119 /* 120 * Context syncronization required to make sure system register writes 121 * effects are synchronised. 122 */ 123 isb(); 124 } 125 126 void gicv5_cpu_disable_interrupts(void) 127 { 128 u64 cr0; 129 130 cr0 = FIELD_PREP(ICC_CR0_EL1_EN, 0); 131 write_sysreg_s(cr0, SYS_ICC_CR0_EL1); 132 } 133 134 void gicv5_cpu_enable_interrupts(void) 135 { 136 u64 cr0, pcr; 137 138 write_sysreg_s(0, SYS_ICC_PPI_ENABLER0_EL1); 139 write_sysreg_s(0, SYS_ICC_PPI_ENABLER1_EL1); 140 141 gicv5_ppi_priority_init(); 142 143 pcr = FIELD_PREP(ICC_PCR_EL1_PRIORITY, GICV5_IRQ_DEFAULT_PRI); 144 write_sysreg_s(pcr, SYS_ICC_PCR_EL1); 145 146 cr0 = FIELD_PREP(ICC_CR0_EL1_EN, 1); 147 write_sysreg_s(cr0, SYS_ICC_CR0_EL1); 148 } 149 150 #endif 151