xref: /linux/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/cache.json (revision 06d07429858317ded2db7986113a9e0129cd599b) 
1[
2  {
3    "EventName": "L1_ICACHE_ACCESS",
4    "EventCode": "0x00000001",
5    "BriefDescription": "L1 instruction cache access"
6  },
7  {
8    "EventName": "L1_ICACHE_MISS",
9    "EventCode": "0x00000002",
10    "BriefDescription": "L1 instruction cache miss"
11  },
12  {
13    "EventName": "ITLB_MISS",
14    "EventCode": "0x00000003",
15    "BriefDescription": "I-UTLB miss"
16  },
17  {
18    "EventName": "DTLB_MISS",
19    "EventCode": "0x00000004",
20    "BriefDescription": "D-UTLB miss"
21  },
22  {
23    "EventName": "JTLB_MISS",
24    "EventCode": "0x00000005",
25    "BriefDescription": "JTLB miss"
26  },
27  {
28    "EventName": "L1_DCACHE_READ_ACCESS",
29    "EventCode": "0x0000000c",
30    "BriefDescription": "L1 data cache read access"
31  },
32  {
33    "EventName": "L1_DCACHE_READ_MISS",
34    "EventCode": "0x0000000d",
35    "BriefDescription": "L1 data cache read miss"
36  },
37  {
38    "EventName": "L1_DCACHE_WRITE_ACCESS",
39    "EventCode": "0x0000000e",
40    "BriefDescription": "L1 data cache write access"
41  },
42  {
43    "EventName": "L1_DCACHE_WRITE_MISS",
44    "EventCode": "0x0000000f",
45    "BriefDescription": "L1 data cache write miss"
46  },
47  {
48    "EventName": "LL_CACHE_READ_ACCESS",
49    "EventCode": "0x00000010",
50    "BriefDescription": "LL Cache read access"
51  },
52  {
53    "EventName": "LL_CACHE_READ_MISS",
54    "EventCode": "0x00000011",
55    "BriefDescription": "LL Cache read miss"
56  },
57  {
58    "EventName": "LL_CACHE_WRITE_ACCESS",
59    "EventCode": "0x00000012",
60    "BriefDescription": "LL Cache write access"
61  },
62  {
63    "EventName": "LL_CACHE_WRITE_MISS",
64    "EventCode": "0x00000013",
65    "BriefDescription": "LL Cache write miss"
66  }
67]
68