xref: /linux/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/memory.json (revision c7decec2f2d2ab0366567f9e30c0e1418cece43f) 
1[
2  {
3    "EventName": "L1_I_CACHE_MISSES",
4    "EventCode": "0x1",
5    "BriefDescription": "number of misses in L1 I-Cache"
6  },
7  {
8    "EventName": "L1_D_CACHE_MISSES",
9    "EventCode": "0x2",
10    "BriefDescription": "number of misses in L1 D-Cache"
11  },
12  {
13    "EventName": "ITLB_MISSES",
14    "EventCode": "0x3",
15    "BriefDescription": "number of misses in ITLB"
16  },
17  {
18    "EventName": "DTLB_MISSES",
19    "EventCode": "0x4",
20    "BriefDescription": "number of misses in DTLB"
21  },
22  {
23    "EventName": "L1_I_CACHE_ACCESSES",
24    "EventCode": "0x10",
25    "BriefDescription": "number of accesses to instruction cache"
26  },
27  {
28    "EventName": "L1_D_CACHE_ACCESSES",
29    "EventCode": "0x11",
30    "BriefDescription": "number of accesses to data cache"
31  },
32  {
33    "EventName": "L1_CACHE_LINE_EVICTION",
34    "EventCode": "0x12",
35    "BriefDescription": "number of data cache line eviction"
36  },
37  {
38    "EventName": "ITLB_FLUSH",
39    "EventCode": "0x13",
40    "BriefDescription": "number of ITLB flushes"
41  }
42]
43