xref: /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/instruction.json (revision 1ac731c529cd4d6adbce134754b51ff7d822b145) 
1[
2    {
3        "ArchStdEvent": "SW_INCR"
4    },
5    {
6        "PublicDescription": "This event counts all retired instructions, including those that fail their condition check.",
7        "ArchStdEvent": "INST_RETIRED"
8    },
9    {
10        "ArchStdEvent": "EXC_RETURN"
11    },
12    {
13        "PublicDescription": "This event only counts writes to CONTEXTIDR in AArch32 state, and via the CONTEXTIDR_EL1 mnemonic in AArch64 state.",
14        "ArchStdEvent": "CID_WRITE_RETIRED"
15    },
16    {
17        "ArchStdEvent": "INST_SPEC"
18    },
19    {
20        "PublicDescription": "This event only counts writes to TTBR0/TTBR1 in AArch32 state and TTBR0_EL1/TTBR1_EL1 in AArch64 state.",
21        "ArchStdEvent": "TTBR_WRITE_RETIRED"
22    },
23    {
24        "PublicDescription": "This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches.",
25        "ArchStdEvent": "BR_RETIRED"
26    },
27    {
28        "PublicDescription": "This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush.",
29        "ArchStdEvent": "BR_MIS_PRED_RETIRED"
30    },
31    {
32        "ArchStdEvent": "ASE_SPEC"
33    },
34    {
35        "ArchStdEvent": "BR_IMMED_SPEC"
36    },
37    {
38        "ArchStdEvent": "BR_INDIRECT_SPEC"
39    },
40    {
41        "ArchStdEvent": "BR_RETURN_SPEC"
42    },
43    {
44        "ArchStdEvent": "CRYPTO_SPEC"
45    },
46    {
47        "ArchStdEvent": "DMB_SPEC"
48    },
49    {
50        "ArchStdEvent": "DP_SPEC"
51    },
52    {
53        "ArchStdEvent": "DSB_SPEC"
54    },
55    {
56        "ArchStdEvent": "ISB_SPEC"
57    },
58    {
59        "ArchStdEvent": "LDREX_SPEC"
60    },
61    {
62        "ArchStdEvent": "LDST_SPEC"
63    },
64    {
65        "ArchStdEvent": "LD_SPEC"
66    },
67    {
68        "ArchStdEvent": "PC_WRITE_SPEC"
69    },
70    {
71        "ArchStdEvent": "RC_LD_SPEC"
72    },
73    {
74        "ArchStdEvent": "RC_ST_SPEC"
75    },
76    {
77        "ArchStdEvent": "STREX_FAIL_SPEC"
78    },
79    {
80        "ArchStdEvent": "STREX_PASS_SPEC"
81    },
82    {
83        "ArchStdEvent": "STREX_SPEC"
84    },
85    {
86        "ArchStdEvent": "ST_SPEC"
87    },
88    {
89        "ArchStdEvent": "VFP_SPEC"
90    }
91]
92