1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_AMD_IBS_H 3 #define _ASM_X86_AMD_IBS_H 4 5 /* 6 * From PPR Vol 1 for AMD Family 19h Model 01h B1 7 * 55898 Rev 0.35 - Feb 5, 2021 8 */ 9 10 #include "../msr-index.h" 11 12 /* IBS_OP_DATA2 DataSrc */ 13 #define IBS_DATA_SRC_LOC_CACHE 2 14 #define IBS_DATA_SRC_DRAM 3 15 #define IBS_DATA_SRC_REM_CACHE 4 16 #define IBS_DATA_SRC_IO 7 17 18 /* IBS_OP_DATA2 DataSrc Extension */ 19 #define IBS_DATA_SRC_EXT_LOC_CACHE 1 20 #define IBS_DATA_SRC_EXT_NEAR_CCX_CACHE 2 21 #define IBS_DATA_SRC_EXT_DRAM 3 22 #define IBS_DATA_SRC_EXT_FAR_CCX_CACHE 5 23 #define IBS_DATA_SRC_EXT_PMEM 6 24 #define IBS_DATA_SRC_EXT_IO 7 25 #define IBS_DATA_SRC_EXT_EXT_MEM 8 26 #define IBS_DATA_SRC_EXT_PEER_AGENT_MEM 12 27 28 /* 29 * IBS Hardware MSRs 30 */ 31 32 /* MSR 0xc0011030: IBS Fetch Control */ 33 union ibs_fetch_ctl { 34 __u64 val; 35 struct { 36 __u64 fetch_maxcnt:16,/* 0-15: instruction fetch max. count */ 37 fetch_cnt:16, /* 16-31: instruction fetch count */ 38 fetch_lat:16, /* 32-47: instruction fetch latency */ 39 fetch_en:1, /* 48: instruction fetch enable */ 40 fetch_val:1, /* 49: instruction fetch valid */ 41 fetch_comp:1, /* 50: instruction fetch complete */ 42 ic_miss:1, /* 51: i-cache miss */ 43 phy_addr_valid:1,/* 52: physical address valid */ 44 l1tlb_pgsz:2, /* 53-54: i-cache L1TLB page size 45 * (needs IbsPhyAddrValid) */ 46 l1tlb_miss:1, /* 55: i-cache fetch missed in L1TLB */ 47 l2tlb_miss:1, /* 56: i-cache fetch missed in L2TLB */ 48 rand_en:1, /* 57: random tagging enable */ 49 fetch_l2_miss:1,/* 58: L2 miss for sampled fetch 50 * (needs IbsFetchComp) */ 51 l3_miss_only:1, /* 59: Collect L3 miss samples only */ 52 fetch_oc_miss:1,/* 60: Op cache miss for the sampled fetch */ 53 fetch_l3_miss:1,/* 61: L3 cache miss for the sampled fetch */ 54 reserved:2; /* 62-63: reserved */ 55 }; 56 }; 57 58 /* MSR 0xc0011033: IBS Execution Control */ 59 union ibs_op_ctl { 60 __u64 val; 61 struct { 62 __u64 opmaxcnt:16, /* 0-15: periodic op max. count */ 63 l3_miss_only:1, /* 16: Collect L3 miss samples only */ 64 op_en:1, /* 17: op sampling enable */ 65 op_val:1, /* 18: op sample valid */ 66 cnt_ctl:1, /* 19: periodic op counter control */ 67 opmaxcnt_ext:7, /* 20-26: upper 7 bits of periodic op maximum count */ 68 reserved0:5, /* 27-31: reserved */ 69 opcurcnt:27, /* 32-58: periodic op counter current count */ 70 ldlat_thrsh:4, /* 59-62: Load Latency threshold */ 71 ldlat_en:1; /* 63: Load Latency enabled */ 72 }; 73 }; 74 75 /* MSR 0xc0011035: IBS Op Data 1 */ 76 union ibs_op_data { 77 __u64 val; 78 struct { 79 __u64 comp_to_ret_ctr:16, /* 0-15: op completion to retire count */ 80 tag_to_ret_ctr:16, /* 15-31: op tag to retire count */ 81 reserved1:2, /* 32-33: reserved */ 82 op_return:1, /* 34: return op */ 83 op_brn_taken:1, /* 35: taken branch op */ 84 op_brn_misp:1, /* 36: mispredicted branch op */ 85 op_brn_ret:1, /* 37: branch op retired */ 86 op_rip_invalid:1, /* 38: RIP is invalid */ 87 op_brn_fuse:1, /* 39: fused branch op */ 88 op_microcode:1, /* 40: microcode op */ 89 reserved2:23; /* 41-63: reserved */ 90 }; 91 }; 92 93 /* MSR 0xc0011036: IBS Op Data 2 */ 94 union ibs_op_data2 { 95 __u64 val; 96 struct { 97 __u64 data_src_lo:3, /* 0-2: data source low */ 98 reserved0:1, /* 3: reserved */ 99 rmt_node:1, /* 4: destination node */ 100 cache_hit_st:1, /* 5: cache hit state */ 101 data_src_hi:2, /* 6-7: data source high */ 102 reserved1:56; /* 8-63: reserved */ 103 }; 104 }; 105 106 /* MSR 0xc0011037: IBS Op Data 3 */ 107 union ibs_op_data3 { 108 __u64 val; 109 struct { 110 __u64 ld_op:1, /* 0: load op */ 111 st_op:1, /* 1: store op */ 112 dc_l1tlb_miss:1, /* 2: data cache L1TLB miss */ 113 dc_l2tlb_miss:1, /* 3: data cache L2TLB hit in 2M page */ 114 dc_l1tlb_hit_2m:1, /* 4: data cache L1TLB hit in 2M page */ 115 dc_l1tlb_hit_1g:1, /* 5: data cache L1TLB hit in 1G page */ 116 dc_l2tlb_hit_2m:1, /* 6: data cache L2TLB hit in 2M page */ 117 dc_miss:1, /* 7: data cache miss */ 118 dc_mis_acc:1, /* 8: misaligned access */ 119 reserved:4, /* 9-12: reserved */ 120 dc_wc_mem_acc:1, /* 13: write combining memory access */ 121 dc_uc_mem_acc:1, /* 14: uncacheable memory access */ 122 dc_locked_op:1, /* 15: locked operation */ 123 dc_miss_no_mab_alloc:1, /* 16: DC miss with no MAB allocated */ 124 dc_lin_addr_valid:1, /* 17: data cache linear address valid */ 125 dc_phy_addr_valid:1, /* 18: data cache physical address valid */ 126 dc_l2_tlb_hit_1g:1, /* 19: data cache L2 hit in 1GB page */ 127 l2_miss:1, /* 20: L2 cache miss */ 128 sw_pf:1, /* 21: software prefetch */ 129 op_mem_width:4, /* 22-25: load/store size in bytes */ 130 op_dc_miss_open_mem_reqs:6, /* 26-31: outstanding mem reqs on DC fill */ 131 dc_miss_lat:16, /* 32-47: data cache miss latency */ 132 tlb_refill_lat:16; /* 48-63: L1 TLB refill latency */ 133 }; 134 }; 135 136 /* MSR 0xc001103c: IBS Fetch Control Extended */ 137 union ic_ibs_extd_ctl { 138 __u64 val; 139 struct { 140 __u64 itlb_refill_lat:16, /* 0-15: ITLB Refill latency for sampled fetch */ 141 reserved:48; /* 16-63: reserved */ 142 }; 143 }; 144 145 /* 146 * IBS driver related 147 */ 148 149 struct perf_ibs_data { 150 u32 size; 151 union { 152 u32 data[0]; /* data buffer starts here */ 153 u32 caps; 154 }; 155 u64 regs[MSR_AMD64_IBS_REG_COUNT_MAX]; 156 }; 157 158 #endif /* _ASM_X86_AMD_IBS_H */ 159