1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * This driver supports the digital controls for the internal codec 4 * found in Allwinner's A33 SoCs. 5 * 6 * (C) Copyright 2010-2016 7 * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com> 8 * huangxin <huangxin@Reuuimllatech.com> 9 * Mylène Josserand <mylene.josserand@free-electrons.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/clk.h> 15 #include <linux/input.h> 16 #include <linux/io.h> 17 #include <linux/irq.h> 18 #include <linux/mutex.h> 19 #include <linux/of.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 #include <linux/log2.h> 23 24 #include <sound/jack.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/tlv.h> 29 30 #define SUN8I_SYSCLK_CTL 0x00c 31 #define SUN8I_SYSCLK_CTL_AIF1CLK_ENA 11 32 #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL (0x2 << 8) 33 #define SUN8I_SYSCLK_CTL_AIF2CLK_ENA 7 34 #define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_PLL (0x2 << 4) 35 #define SUN8I_SYSCLK_CTL_SYSCLK_ENA 3 36 #define SUN8I_SYSCLK_CTL_SYSCLK_SRC 0 37 #define SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF1CLK (0x0 << 0) 38 #define SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF2CLK (0x1 << 0) 39 #define SUN8I_MOD_CLK_ENA 0x010 40 #define SUN8I_MOD_CLK_ENA_AIF1 15 41 #define SUN8I_MOD_CLK_ENA_AIF2 14 42 #define SUN8I_MOD_CLK_ENA_AIF3 13 43 #define SUN8I_MOD_CLK_ENA_ADC 3 44 #define SUN8I_MOD_CLK_ENA_DAC 2 45 #define SUN8I_MOD_RST_CTL 0x014 46 #define SUN8I_MOD_RST_CTL_AIF1 15 47 #define SUN8I_MOD_RST_CTL_AIF2 14 48 #define SUN8I_MOD_RST_CTL_AIF3 13 49 #define SUN8I_MOD_RST_CTL_ADC 3 50 #define SUN8I_MOD_RST_CTL_DAC 2 51 #define SUN8I_SYS_SR_CTRL 0x018 52 #define SUN8I_SYS_SR_CTRL_AIF1_FS 12 53 #define SUN8I_SYS_SR_CTRL_AIF2_FS 8 54 #define SUN8I_AIF_CLK_CTRL(n) (0x040 * (1 + (n))) 55 #define SUN8I_AIF_CLK_CTRL_MSTR_MOD 15 56 #define SUN8I_AIF_CLK_CTRL_CLK_INV 13 57 #define SUN8I_AIF_CLK_CTRL_BCLK_DIV 9 58 #define SUN8I_AIF_CLK_CTRL_LRCK_DIV 6 59 #define SUN8I_AIF_CLK_CTRL_WORD_SIZ 4 60 #define SUN8I_AIF_CLK_CTRL_DATA_FMT 2 61 #define SUN8I_AIF1_ADCDAT_CTRL 0x044 62 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15 63 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14 64 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC 10 65 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC 8 66 #define SUN8I_AIF1_DACDAT_CTRL 0x048 67 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15 68 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14 69 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_SRC 10 70 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_SRC 8 71 #define SUN8I_AIF1_MXR_SRC 0x04c 72 #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L 15 73 #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL 14 74 #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL 13 75 #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR 12 76 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R 11 77 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR 10 78 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR 9 79 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL 8 80 #define SUN8I_AIF1_VOL_CTRL1 0x050 81 #define SUN8I_AIF1_VOL_CTRL1_AD0L_VOL 8 82 #define SUN8I_AIF1_VOL_CTRL1_AD0R_VOL 0 83 #define SUN8I_AIF1_VOL_CTRL3 0x058 84 #define SUN8I_AIF1_VOL_CTRL3_DA0L_VOL 8 85 #define SUN8I_AIF1_VOL_CTRL3_DA0R_VOL 0 86 #define SUN8I_AIF2_ADCDAT_CTRL 0x084 87 #define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_ENA 15 88 #define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_ENA 14 89 #define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_SRC 10 90 #define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_SRC 8 91 #define SUN8I_AIF2_DACDAT_CTRL 0x088 92 #define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_ENA 15 93 #define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_ENA 14 94 #define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_SRC 10 95 #define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_SRC 8 96 #define SUN8I_AIF2_MXR_SRC 0x08c 97 #define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA0L 15 98 #define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA1L 14 99 #define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF2DACR 13 100 #define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_ADCL 12 101 #define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA0R 11 102 #define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA1R 10 103 #define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF2DACL 9 104 #define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_ADCR 8 105 #define SUN8I_AIF2_VOL_CTRL1 0x090 106 #define SUN8I_AIF2_VOL_CTRL1_ADCL_VOL 8 107 #define SUN8I_AIF2_VOL_CTRL1_ADCR_VOL 0 108 #define SUN8I_AIF2_VOL_CTRL2 0x098 109 #define SUN8I_AIF2_VOL_CTRL2_DACL_VOL 8 110 #define SUN8I_AIF2_VOL_CTRL2_DACR_VOL 0 111 #define SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_AIF1 (0x0 << 0) 112 #define SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_AIF2 (0x1 << 0) 113 #define SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_AIF1CLK (0x2 << 0) 114 #define SUN8I_AIF3_PATH_CTRL 0x0cc 115 #define SUN8I_AIF3_PATH_CTRL_AIF3_ADC_SRC 10 116 #define SUN8I_AIF3_PATH_CTRL_AIF2_DAC_SRC 8 117 #define SUN8I_AIF3_PATH_CTRL_AIF3_PINS_TRI 7 118 #define SUN8I_ADC_DIG_CTRL 0x100 119 #define SUN8I_ADC_DIG_CTRL_ENAD 15 120 #define SUN8I_ADC_DIG_CTRL_ADOUT_DTS 2 121 #define SUN8I_ADC_DIG_CTRL_ADOUT_DLY 1 122 #define SUN8I_ADC_VOL_CTRL 0x104 123 #define SUN8I_ADC_VOL_CTRL_ADCL_VOL 8 124 #define SUN8I_ADC_VOL_CTRL_ADCR_VOL 0 125 #define SUN8I_HMIC_CTRL1 0x110 126 #define SUN8I_HMIC_CTRL1_HMIC_M 12 127 #define SUN8I_HMIC_CTRL1_HMIC_N 8 128 #define SUN8I_HMIC_CTRL1_MDATA_THRESHOLD_DB 5 129 #define SUN8I_HMIC_CTRL1_JACK_OUT_IRQ_EN 4 130 #define SUN8I_HMIC_CTRL1_JACK_IN_IRQ_EN 3 131 #define SUN8I_HMIC_CTRL1_HMIC_DATA_IRQ_EN 0 132 #define SUN8I_HMIC_CTRL2 0x114 133 #define SUN8I_HMIC_CTRL2_HMIC_SAMPLE 14 134 #define SUN8I_HMIC_CTRL2_HMIC_MDATA_THRESHOLD 8 135 #define SUN8I_HMIC_CTRL2_HMIC_SF 6 136 #define SUN8I_HMIC_STS 0x118 137 #define SUN8I_HMIC_STS_MDATA_DISCARD 13 138 #define SUN8I_HMIC_STS_HMIC_DATA 8 139 #define SUN8I_HMIC_STS_JACK_OUT_IRQ_ST 4 140 #define SUN8I_HMIC_STS_JACK_IN_IRQ_ST 3 141 #define SUN8I_HMIC_STS_HMIC_DATA_IRQ_ST 0 142 #define SUN8I_DAC_DIG_CTRL 0x120 143 #define SUN8I_DAC_DIG_CTRL_ENDA 15 144 #define SUN8I_DAC_VOL_CTRL 0x124 145 #define SUN8I_DAC_VOL_CTRL_DACL_VOL 8 146 #define SUN8I_DAC_VOL_CTRL_DACR_VOL 0 147 #define SUN8I_DAC_MXR_SRC 0x130 148 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L 15 149 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L 14 150 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL 13 151 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL 12 152 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R 11 153 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R 10 154 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9 155 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8 156 157 #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK GENMASK(9, 8) 158 #define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK GENMASK(5, 4) 159 #define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) 160 #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) 161 #define SUN8I_AIF_CLK_CTRL_CLK_INV_MASK GENMASK(14, 13) 162 #define SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK GENMASK(12, 9) 163 #define SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK GENMASK(8, 6) 164 #define SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK GENMASK(5, 4) 165 #define SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK GENMASK(3, 2) 166 #define SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_MASK GENMASK(1, 0) 167 #define SUN8I_HMIC_CTRL1_HMIC_M_MASK GENMASK(15, 12) 168 #define SUN8I_HMIC_CTRL1_HMIC_N_MASK GENMASK(11, 8) 169 #define SUN8I_HMIC_CTRL1_MDATA_THRESHOLD_DB_MASK GENMASK(6, 5) 170 #define SUN8I_HMIC_CTRL2_HMIC_SAMPLE_MASK GENMASK(15, 14) 171 #define SUN8I_HMIC_CTRL2_HMIC_SF_MASK GENMASK(7, 6) 172 #define SUN8I_HMIC_STS_HMIC_DATA_MASK GENMASK(12, 8) 173 174 #define SUN8I_CODEC_BUTTONS (SND_JACK_BTN_0|\ 175 SND_JACK_BTN_1|\ 176 SND_JACK_BTN_2|\ 177 SND_JACK_BTN_3) 178 179 #define SUN8I_CODEC_PASSTHROUGH_SAMPLE_RATE 48000 180 181 #define SUN8I_CODEC_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 |\ 182 SNDRV_PCM_FMTBIT_S16_LE |\ 183 SNDRV_PCM_FMTBIT_S20_LE |\ 184 SNDRV_PCM_FMTBIT_S24_LE |\ 185 SNDRV_PCM_FMTBIT_S20_3LE|\ 186 SNDRV_PCM_FMTBIT_S24_3LE) 187 188 #define SUN8I_CODEC_PCM_RATES (SNDRV_PCM_RATE_8000_48000|\ 189 SNDRV_PCM_RATE_88200 |\ 190 SNDRV_PCM_RATE_96000 |\ 191 SNDRV_PCM_RATE_176400 |\ 192 SNDRV_PCM_RATE_192000 |\ 193 SNDRV_PCM_RATE_KNOT) 194 195 enum { 196 SUN8I_CODEC_AIF1, 197 SUN8I_CODEC_AIF2, 198 SUN8I_CODEC_AIF3, 199 SUN8I_CODEC_NAIFS 200 }; 201 202 struct sun8i_codec_aif { 203 unsigned int lrck_div_order; 204 unsigned int sample_rate; 205 unsigned int slots; 206 unsigned int slot_width; 207 unsigned int active_streams : 2; 208 unsigned int open_streams : 2; 209 }; 210 211 struct sun8i_codec_quirks { 212 bool bus_clock : 1; 213 bool jack_detection : 1; 214 bool legacy_widgets : 1; 215 bool lrck_inversion : 1; 216 }; 217 218 enum { 219 SUN8I_JACK_STATUS_DISCONNECTED, 220 SUN8I_JACK_STATUS_WAITING_HBIAS, 221 SUN8I_JACK_STATUS_CONNECTED, 222 }; 223 224 struct sun8i_codec { 225 struct snd_soc_component *component; 226 struct regmap *regmap; 227 struct clk *clk_bus; 228 struct clk *clk_module; 229 const struct sun8i_codec_quirks *quirks; 230 struct sun8i_codec_aif aifs[SUN8I_CODEC_NAIFS]; 231 struct snd_soc_jack *jack; 232 struct delayed_work jack_work; 233 int jack_irq; 234 int jack_status; 235 int jack_last_sample; 236 ktime_t jack_hbias_ready; 237 struct mutex jack_mutex; 238 int last_hmic_irq; 239 unsigned int sysclk_rate; 240 int sysclk_refcnt; 241 }; 242 243 static struct snd_soc_dai_driver sun8i_codec_dais[]; 244 245 static int sun8i_codec_runtime_resume(struct device *dev) 246 { 247 struct sun8i_codec *scodec = dev_get_drvdata(dev); 248 int ret; 249 250 if (scodec->clk_bus) { 251 ret = clk_prepare_enable(scodec->clk_bus); 252 if (ret) { 253 dev_err(dev, "Failed to enable the bus clock\n"); 254 return ret; 255 } 256 } 257 258 regcache_cache_only(scodec->regmap, false); 259 260 ret = regcache_sync(scodec->regmap); 261 if (ret) { 262 dev_err(dev, "Failed to sync regmap cache\n"); 263 return ret; 264 } 265 266 return 0; 267 } 268 269 static int sun8i_codec_runtime_suspend(struct device *dev) 270 { 271 struct sun8i_codec *scodec = dev_get_drvdata(dev); 272 273 regcache_cache_only(scodec->regmap, true); 274 regcache_mark_dirty(scodec->regmap); 275 276 if (scodec->clk_bus) 277 clk_disable_unprepare(scodec->clk_bus); 278 279 return 0; 280 } 281 282 static int sun8i_codec_get_hw_rate(unsigned int sample_rate) 283 { 284 switch (sample_rate) { 285 case 7350: 286 case 8000: 287 return 0x0; 288 case 11025: 289 return 0x1; 290 case 12000: 291 return 0x2; 292 case 14700: 293 case 16000: 294 return 0x3; 295 case 22050: 296 return 0x4; 297 case 24000: 298 return 0x5; 299 case 29400: 300 case 32000: 301 return 0x6; 302 case 44100: 303 return 0x7; 304 case 48000: 305 return 0x8; 306 case 88200: 307 case 96000: 308 return 0x9; 309 case 176400: 310 case 192000: 311 return 0xa; 312 default: 313 return -EINVAL; 314 } 315 } 316 317 static int sun8i_codec_update_sample_rate(struct sun8i_codec *scodec) 318 { 319 unsigned int max_rate = 0; 320 int hw_rate, i; 321 322 for (i = SUN8I_CODEC_AIF1; i < SUN8I_CODEC_NAIFS; ++i) { 323 struct sun8i_codec_aif *aif = &scodec->aifs[i]; 324 325 if (aif->active_streams) 326 max_rate = max(max_rate, aif->sample_rate); 327 } 328 329 /* Set the sample rate for ADC->DAC passthrough when no AIF is active. */ 330 if (!max_rate) 331 max_rate = SUN8I_CODEC_PASSTHROUGH_SAMPLE_RATE; 332 333 hw_rate = sun8i_codec_get_hw_rate(max_rate); 334 if (hw_rate < 0) 335 return hw_rate; 336 337 regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, 338 SUN8I_SYS_SR_CTRL_AIF1_FS_MASK, 339 hw_rate << SUN8I_SYS_SR_CTRL_AIF1_FS); 340 341 return 0; 342 } 343 344 static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 345 { 346 struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); 347 u32 dsp_format, format, invert, value; 348 349 /* clock masters */ 350 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 351 case SND_SOC_DAIFMT_CBC_CFC: /* Codec slave, DAI master */ 352 value = 0x1; 353 break; 354 case SND_SOC_DAIFMT_CBP_CFP: /* Codec Master, DAI slave */ 355 value = 0x0; 356 break; 357 default: 358 return -EINVAL; 359 } 360 361 if (dai->id == SUN8I_CODEC_AIF3) { 362 /* AIF3 only supports master mode. */ 363 if (value) 364 return -EINVAL; 365 366 /* Use the AIF2 BCLK and LRCK for AIF3. */ 367 regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id), 368 SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_MASK, 369 SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_AIF2); 370 } else { 371 regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id), 372 BIT(SUN8I_AIF_CLK_CTRL_MSTR_MOD), 373 value << SUN8I_AIF_CLK_CTRL_MSTR_MOD); 374 } 375 376 /* DAI format */ 377 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 378 case SND_SOC_DAIFMT_I2S: 379 format = 0x0; 380 break; 381 case SND_SOC_DAIFMT_LEFT_J: 382 format = 0x1; 383 break; 384 case SND_SOC_DAIFMT_RIGHT_J: 385 format = 0x2; 386 break; 387 case SND_SOC_DAIFMT_DSP_A: 388 format = 0x3; 389 dsp_format = 0x0; /* Set LRCK_INV to 0 */ 390 break; 391 case SND_SOC_DAIFMT_DSP_B: 392 format = 0x3; 393 dsp_format = 0x1; /* Set LRCK_INV to 1 */ 394 break; 395 default: 396 return -EINVAL; 397 } 398 399 if (dai->id == SUN8I_CODEC_AIF3) { 400 /* AIF3 only supports DSP mode. */ 401 if (format != 3) 402 return -EINVAL; 403 } else { 404 regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id), 405 SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK, 406 format << SUN8I_AIF_CLK_CTRL_DATA_FMT); 407 } 408 409 /* clock inversion */ 410 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 411 case SND_SOC_DAIFMT_NB_NF: /* Normal */ 412 invert = 0x0; 413 break; 414 case SND_SOC_DAIFMT_NB_IF: /* Inverted LRCK */ 415 invert = 0x1; 416 break; 417 case SND_SOC_DAIFMT_IB_NF: /* Inverted BCLK */ 418 invert = 0x2; 419 break; 420 case SND_SOC_DAIFMT_IB_IF: /* Both inverted */ 421 invert = 0x3; 422 break; 423 default: 424 return -EINVAL; 425 } 426 427 if (format == 0x3) { 428 /* Inverted LRCK is not available in DSP mode. */ 429 if (invert & BIT(0)) 430 return -EINVAL; 431 432 /* Instead, the bit selects between DSP A/B formats. */ 433 invert |= dsp_format; 434 } else { 435 /* 436 * It appears that the DAI and the codec in the A33 SoC don't 437 * share the same polarity for the LRCK signal when they mean 438 * 'normal' and 'inverted' in the datasheet. 439 * 440 * Since the DAI here is our regular i2s driver that have been 441 * tested with way more codecs than just this one, it means 442 * that the codec probably gets it backward, and we have to 443 * invert the value here. 444 */ 445 invert ^= scodec->quirks->lrck_inversion; 446 } 447 448 regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id), 449 SUN8I_AIF_CLK_CTRL_CLK_INV_MASK, 450 invert << SUN8I_AIF_CLK_CTRL_CLK_INV); 451 452 return 0; 453 } 454 455 static int sun8i_codec_set_tdm_slot(struct snd_soc_dai *dai, 456 unsigned int tx_mask, unsigned int rx_mask, 457 int slots, int slot_width) 458 { 459 struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); 460 struct sun8i_codec_aif *aif = &scodec->aifs[dai->id]; 461 462 if (slot_width && !is_power_of_2(slot_width)) 463 return -EINVAL; 464 465 aif->slots = slots; 466 aif->slot_width = slot_width; 467 468 return 0; 469 } 470 471 static const unsigned int sun8i_codec_rates[] = { 472 7350, 8000, 11025, 12000, 14700, 16000, 22050, 24000, 473 29400, 32000, 44100, 48000, 88200, 96000, 176400, 192000, 474 }; 475 476 static const struct snd_pcm_hw_constraint_list sun8i_codec_all_rates = { 477 .list = sun8i_codec_rates, 478 .count = ARRAY_SIZE(sun8i_codec_rates), 479 }; 480 481 static const struct snd_pcm_hw_constraint_list sun8i_codec_22M_rates = { 482 .list = sun8i_codec_rates, 483 .count = ARRAY_SIZE(sun8i_codec_rates), 484 .mask = 0x5555, 485 }; 486 487 static const struct snd_pcm_hw_constraint_list sun8i_codec_24M_rates = { 488 .list = sun8i_codec_rates, 489 .count = ARRAY_SIZE(sun8i_codec_rates), 490 .mask = 0xaaaa, 491 }; 492 493 static int sun8i_codec_startup(struct snd_pcm_substream *substream, 494 struct snd_soc_dai *dai) 495 { 496 struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); 497 const struct snd_pcm_hw_constraint_list *list; 498 499 /* hw_constraints is not relevant for codec2codec DAIs. */ 500 if (dai->id != SUN8I_CODEC_AIF1) 501 return 0; 502 503 if (!scodec->sysclk_refcnt) 504 list = &sun8i_codec_all_rates; 505 else if (scodec->sysclk_rate == 22579200) 506 list = &sun8i_codec_22M_rates; 507 else if (scodec->sysclk_rate == 24576000) 508 list = &sun8i_codec_24M_rates; 509 else 510 return -EINVAL; 511 512 return snd_pcm_hw_constraint_list(substream->runtime, 0, 513 SNDRV_PCM_HW_PARAM_RATE, list); 514 } 515 516 struct sun8i_codec_clk_div { 517 u8 div; 518 u8 val; 519 }; 520 521 static const struct sun8i_codec_clk_div sun8i_codec_bclk_div[] = { 522 { .div = 1, .val = 0 }, 523 { .div = 2, .val = 1 }, 524 { .div = 4, .val = 2 }, 525 { .div = 6, .val = 3 }, 526 { .div = 8, .val = 4 }, 527 { .div = 12, .val = 5 }, 528 { .div = 16, .val = 6 }, 529 { .div = 24, .val = 7 }, 530 { .div = 32, .val = 8 }, 531 { .div = 48, .val = 9 }, 532 { .div = 64, .val = 10 }, 533 { .div = 96, .val = 11 }, 534 { .div = 128, .val = 12 }, 535 { .div = 192, .val = 13 }, 536 }; 537 538 static int sun8i_codec_get_bclk_div(unsigned int sysclk_rate, 539 unsigned int lrck_div_order, 540 unsigned int sample_rate) 541 { 542 unsigned int div = sysclk_rate / sample_rate >> lrck_div_order; 543 int i; 544 545 for (i = 0; i < ARRAY_SIZE(sun8i_codec_bclk_div); i++) { 546 const struct sun8i_codec_clk_div *bdiv = &sun8i_codec_bclk_div[i]; 547 548 if (bdiv->div == div) 549 return bdiv->val; 550 } 551 552 return -EINVAL; 553 } 554 555 static int sun8i_codec_get_lrck_div_order(unsigned int slots, 556 unsigned int slot_width) 557 { 558 unsigned int div = slots * slot_width; 559 560 if (div < 16 || div > 256) 561 return -EINVAL; 562 563 return order_base_2(div); 564 } 565 566 static unsigned int sun8i_codec_get_sysclk_rate(unsigned int sample_rate) 567 { 568 return (sample_rate % 4000) ? 22579200 : 24576000; 569 } 570 571 static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, 572 struct snd_pcm_hw_params *params, 573 struct snd_soc_dai *dai) 574 { 575 struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); 576 struct sun8i_codec_aif *aif = &scodec->aifs[dai->id]; 577 unsigned int sample_rate = params_rate(params); 578 unsigned int slots = aif->slots ?: params_channels(params); 579 unsigned int slot_width = aif->slot_width ?: params_width(params); 580 unsigned int sysclk_rate = sun8i_codec_get_sysclk_rate(sample_rate); 581 int bclk_div, lrck_div_order, ret, word_size; 582 u32 clk_reg; 583 584 /* word size */ 585 switch (params_width(params)) { 586 case 8: 587 word_size = 0x0; 588 break; 589 case 16: 590 word_size = 0x1; 591 break; 592 case 20: 593 word_size = 0x2; 594 break; 595 case 24: 596 word_size = 0x3; 597 break; 598 default: 599 return -EINVAL; 600 } 601 602 regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id), 603 SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK, 604 word_size << SUN8I_AIF_CLK_CTRL_WORD_SIZ); 605 606 /* LRCK divider (BCLK/LRCK ratio) */ 607 lrck_div_order = sun8i_codec_get_lrck_div_order(slots, slot_width); 608 if (lrck_div_order < 0) 609 return lrck_div_order; 610 611 if (dai->id == SUN8I_CODEC_AIF2 || dai->id == SUN8I_CODEC_AIF3) { 612 /* AIF2 and AIF3 share AIF2's BCLK and LRCK generation circuitry. */ 613 int partner = (SUN8I_CODEC_AIF2 + SUN8I_CODEC_AIF3) - dai->id; 614 const struct sun8i_codec_aif *partner_aif = &scodec->aifs[partner]; 615 const char *partner_name = sun8i_codec_dais[partner].name; 616 617 if (partner_aif->open_streams && 618 (lrck_div_order != partner_aif->lrck_div_order || 619 sample_rate != partner_aif->sample_rate)) { 620 dev_err(dai->dev, 621 "%s sample and bit rates must match %s when both are used\n", 622 dai->name, partner_name); 623 return -EBUSY; 624 } 625 626 clk_reg = SUN8I_AIF_CLK_CTRL(SUN8I_CODEC_AIF2); 627 } else { 628 clk_reg = SUN8I_AIF_CLK_CTRL(dai->id); 629 } 630 631 regmap_update_bits(scodec->regmap, clk_reg, 632 SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK, 633 (lrck_div_order - 4) << SUN8I_AIF_CLK_CTRL_LRCK_DIV); 634 635 /* BCLK divider (SYSCLK/BCLK ratio) */ 636 bclk_div = sun8i_codec_get_bclk_div(sysclk_rate, lrck_div_order, sample_rate); 637 if (bclk_div < 0) 638 return bclk_div; 639 640 regmap_update_bits(scodec->regmap, clk_reg, 641 SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK, 642 bclk_div << SUN8I_AIF_CLK_CTRL_BCLK_DIV); 643 644 /* 645 * SYSCLK rate 646 * 647 * Clock rate protection is reference counted; but hw_params may be 648 * called many times per substream, without matching calls to hw_free. 649 * Protect the clock rate once per AIF, on the first hw_params call 650 * for the first substream. clk_set_rate() will allow clock rate 651 * changes on subsequent calls if only one AIF has open streams. 652 */ 653 ret = (aif->open_streams ? clk_set_rate : clk_set_rate_exclusive)(scodec->clk_module, 654 sysclk_rate); 655 if (ret == -EBUSY) 656 dev_err(dai->dev, 657 "%s sample rate (%u Hz) conflicts with other audio streams\n", 658 dai->name, sample_rate); 659 if (ret < 0) 660 return ret; 661 662 if (!aif->open_streams) 663 scodec->sysclk_refcnt++; 664 scodec->sysclk_rate = sysclk_rate; 665 666 aif->lrck_div_order = lrck_div_order; 667 aif->sample_rate = sample_rate; 668 aif->open_streams |= BIT(substream->stream); 669 670 return sun8i_codec_update_sample_rate(scodec); 671 } 672 673 static int sun8i_codec_hw_free(struct snd_pcm_substream *substream, 674 struct snd_soc_dai *dai) 675 { 676 struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); 677 struct sun8i_codec_aif *aif = &scodec->aifs[dai->id]; 678 679 /* Drop references when the last substream for the AIF is freed. */ 680 if (aif->open_streams != BIT(substream->stream)) 681 goto done; 682 683 clk_rate_exclusive_put(scodec->clk_module); 684 scodec->sysclk_refcnt--; 685 aif->lrck_div_order = 0; 686 aif->sample_rate = 0; 687 688 done: 689 aif->open_streams &= ~BIT(substream->stream); 690 return 0; 691 } 692 693 static const struct snd_soc_dai_ops sun8i_codec_dai_ops = { 694 .set_fmt = sun8i_codec_set_fmt, 695 .set_tdm_slot = sun8i_codec_set_tdm_slot, 696 .startup = sun8i_codec_startup, 697 .hw_params = sun8i_codec_hw_params, 698 .hw_free = sun8i_codec_hw_free, 699 }; 700 701 static struct snd_soc_dai_driver sun8i_codec_dais[] = { 702 { 703 .name = "sun8i-codec-aif1", 704 .id = SUN8I_CODEC_AIF1, 705 .ops = &sun8i_codec_dai_ops, 706 /* capture capabilities */ 707 .capture = { 708 .stream_name = "AIF1 Capture", 709 .channels_min = 1, 710 .channels_max = 2, 711 .rates = SUN8I_CODEC_PCM_RATES, 712 .formats = SUN8I_CODEC_PCM_FORMATS, 713 .sig_bits = 24, 714 }, 715 /* playback capabilities */ 716 .playback = { 717 .stream_name = "AIF1 Playback", 718 .channels_min = 1, 719 .channels_max = 2, 720 .rates = SUN8I_CODEC_PCM_RATES, 721 .formats = SUN8I_CODEC_PCM_FORMATS, 722 }, 723 .symmetric_rate = true, 724 .symmetric_channels = true, 725 .symmetric_sample_bits = true, 726 }, 727 { 728 .name = "sun8i-codec-aif2", 729 .id = SUN8I_CODEC_AIF2, 730 .ops = &sun8i_codec_dai_ops, 731 /* capture capabilities */ 732 .capture = { 733 .stream_name = "AIF2 Capture", 734 .channels_min = 1, 735 .channels_max = 2, 736 .rates = SUN8I_CODEC_PCM_RATES, 737 .formats = SUN8I_CODEC_PCM_FORMATS, 738 .sig_bits = 24, 739 }, 740 /* playback capabilities */ 741 .playback = { 742 .stream_name = "AIF2 Playback", 743 .channels_min = 1, 744 .channels_max = 2, 745 .rates = SUN8I_CODEC_PCM_RATES, 746 .formats = SUN8I_CODEC_PCM_FORMATS, 747 }, 748 .symmetric_rate = true, 749 .symmetric_channels = true, 750 .symmetric_sample_bits = true, 751 }, 752 { 753 .name = "sun8i-codec-aif3", 754 .id = SUN8I_CODEC_AIF3, 755 .ops = &sun8i_codec_dai_ops, 756 /* capture capabilities */ 757 .capture = { 758 .stream_name = "AIF3 Capture", 759 .channels_min = 1, 760 .channels_max = 1, 761 .rates = SUN8I_CODEC_PCM_RATES, 762 .formats = SUN8I_CODEC_PCM_FORMATS, 763 .sig_bits = 24, 764 }, 765 /* playback capabilities */ 766 .playback = { 767 .stream_name = "AIF3 Playback", 768 .channels_min = 1, 769 .channels_max = 1, 770 .rates = SUN8I_CODEC_PCM_RATES, 771 .formats = SUN8I_CODEC_PCM_FORMATS, 772 }, 773 .symmetric_rate = true, 774 .symmetric_channels = true, 775 .symmetric_sample_bits = true, 776 }, 777 }; 778 779 static const DECLARE_TLV_DB_SCALE(sun8i_codec_vol_scale, -12000, 75, 1); 780 781 static const struct snd_kcontrol_new sun8i_codec_controls[] = { 782 SOC_DOUBLE_TLV("AIF1 AD0 Capture Volume", 783 SUN8I_AIF1_VOL_CTRL1, 784 SUN8I_AIF1_VOL_CTRL1_AD0L_VOL, 785 SUN8I_AIF1_VOL_CTRL1_AD0R_VOL, 786 0xc0, 0, sun8i_codec_vol_scale), 787 SOC_DOUBLE_TLV("AIF1 DA0 Playback Volume", 788 SUN8I_AIF1_VOL_CTRL3, 789 SUN8I_AIF1_VOL_CTRL3_DA0L_VOL, 790 SUN8I_AIF1_VOL_CTRL3_DA0R_VOL, 791 0xc0, 0, sun8i_codec_vol_scale), 792 SOC_DOUBLE_TLV("AIF2 ADC Capture Volume", 793 SUN8I_AIF2_VOL_CTRL1, 794 SUN8I_AIF2_VOL_CTRL1_ADCL_VOL, 795 SUN8I_AIF2_VOL_CTRL1_ADCR_VOL, 796 0xc0, 0, sun8i_codec_vol_scale), 797 SOC_DOUBLE_TLV("AIF2 DAC Playback Volume", 798 SUN8I_AIF2_VOL_CTRL2, 799 SUN8I_AIF2_VOL_CTRL2_DACL_VOL, 800 SUN8I_AIF2_VOL_CTRL2_DACR_VOL, 801 0xc0, 0, sun8i_codec_vol_scale), 802 SOC_DOUBLE_TLV("ADC Capture Volume", 803 SUN8I_ADC_VOL_CTRL, 804 SUN8I_ADC_VOL_CTRL_ADCL_VOL, 805 SUN8I_ADC_VOL_CTRL_ADCR_VOL, 806 0xc0, 0, sun8i_codec_vol_scale), 807 SOC_DOUBLE_TLV("DAC Playback Volume", 808 SUN8I_DAC_VOL_CTRL, 809 SUN8I_DAC_VOL_CTRL_DACL_VOL, 810 SUN8I_DAC_VOL_CTRL_DACR_VOL, 811 0xc0, 0, sun8i_codec_vol_scale), 812 }; 813 814 static int sun8i_codec_aif_event(struct snd_soc_dapm_widget *w, 815 struct snd_kcontrol *kcontrol, int event) 816 { 817 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 818 struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component); 819 struct sun8i_codec_aif *aif = &scodec->aifs[w->sname[3] - '1']; 820 int stream = w->id == snd_soc_dapm_aif_out; 821 822 if (SND_SOC_DAPM_EVENT_ON(event)) 823 aif->active_streams |= BIT(stream); 824 else 825 aif->active_streams &= ~BIT(stream); 826 827 return sun8i_codec_update_sample_rate(scodec); 828 } 829 830 static const char *const sun8i_aif_stereo_mux_enum_values[] = { 831 "Stereo", "Reverse Stereo", "Sum Mono", "Mix Mono" 832 }; 833 834 static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_ad0_stereo_mux_enum, 835 SUN8I_AIF1_ADCDAT_CTRL, 836 SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC, 837 SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC, 838 sun8i_aif_stereo_mux_enum_values); 839 840 static const struct snd_kcontrol_new sun8i_aif1_ad0_stereo_mux_control = 841 SOC_DAPM_ENUM("AIF1 AD0 Stereo Capture Route", 842 sun8i_aif1_ad0_stereo_mux_enum); 843 844 static SOC_ENUM_DOUBLE_DECL(sun8i_aif2_adc_stereo_mux_enum, 845 SUN8I_AIF2_ADCDAT_CTRL, 846 SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_SRC, 847 SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_SRC, 848 sun8i_aif_stereo_mux_enum_values); 849 850 static const struct snd_kcontrol_new sun8i_aif2_adc_stereo_mux_control = 851 SOC_DAPM_ENUM("AIF2 ADC Stereo Capture Route", 852 sun8i_aif2_adc_stereo_mux_enum); 853 854 static const char *const sun8i_aif3_adc_mux_enum_values[] = { 855 "None", "AIF2 ADCL", "AIF2 ADCR" 856 }; 857 858 static SOC_ENUM_SINGLE_DECL(sun8i_aif3_adc_mux_enum, 859 SUN8I_AIF3_PATH_CTRL, 860 SUN8I_AIF3_PATH_CTRL_AIF3_ADC_SRC, 861 sun8i_aif3_adc_mux_enum_values); 862 863 static const struct snd_kcontrol_new sun8i_aif3_adc_mux_control = 864 SOC_DAPM_ENUM("AIF3 ADC Source Capture Route", 865 sun8i_aif3_adc_mux_enum); 866 867 static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = { 868 SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital ADC Capture Switch", 869 SUN8I_AIF1_MXR_SRC, 870 SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L, 871 SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R, 1, 0), 872 SOC_DAPM_DOUBLE("AIF2 Digital ADC Capture Switch", 873 SUN8I_AIF1_MXR_SRC, 874 SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL, 875 SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR, 1, 0), 876 SOC_DAPM_DOUBLE("AIF1 Data Digital ADC Capture Switch", 877 SUN8I_AIF1_MXR_SRC, 878 SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL, 879 SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR, 1, 0), 880 SOC_DAPM_DOUBLE("AIF2 Inv Digital ADC Capture Switch", 881 SUN8I_AIF1_MXR_SRC, 882 SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR, 883 SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0), 884 }; 885 886 static const struct snd_kcontrol_new sun8i_aif2_adc_mixer_controls[] = { 887 SOC_DAPM_DOUBLE("AIF2 ADC Mixer AIF1 DA0 Capture Switch", 888 SUN8I_AIF2_MXR_SRC, 889 SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA0L, 890 SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA0R, 1, 0), 891 SOC_DAPM_DOUBLE("AIF2 ADC Mixer AIF1 DA1 Capture Switch", 892 SUN8I_AIF2_MXR_SRC, 893 SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA1L, 894 SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA1R, 1, 0), 895 SOC_DAPM_DOUBLE("AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", 896 SUN8I_AIF2_MXR_SRC, 897 SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF2DACR, 898 SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF2DACL, 1, 0), 899 SOC_DAPM_DOUBLE("AIF2 ADC Mixer ADC Capture Switch", 900 SUN8I_AIF2_MXR_SRC, 901 SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_ADCL, 902 SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_ADCR, 1, 0), 903 }; 904 905 static const char *const sun8i_aif2_dac_mux_enum_values[] = { 906 "AIF2", "AIF3+2", "AIF2+3" 907 }; 908 909 static SOC_ENUM_SINGLE_DECL(sun8i_aif2_dac_mux_enum, 910 SUN8I_AIF3_PATH_CTRL, 911 SUN8I_AIF3_PATH_CTRL_AIF2_DAC_SRC, 912 sun8i_aif2_dac_mux_enum_values); 913 914 static const struct snd_kcontrol_new sun8i_aif2_dac_mux_control = 915 SOC_DAPM_ENUM("AIF2 DAC Source Playback Route", 916 sun8i_aif2_dac_mux_enum); 917 918 static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_da0_stereo_mux_enum, 919 SUN8I_AIF1_DACDAT_CTRL, 920 SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_SRC, 921 SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_SRC, 922 sun8i_aif_stereo_mux_enum_values); 923 924 static const struct snd_kcontrol_new sun8i_aif1_da0_stereo_mux_control = 925 SOC_DAPM_ENUM("AIF1 DA0 Stereo Playback Route", 926 sun8i_aif1_da0_stereo_mux_enum); 927 928 static SOC_ENUM_DOUBLE_DECL(sun8i_aif2_dac_stereo_mux_enum, 929 SUN8I_AIF2_DACDAT_CTRL, 930 SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_SRC, 931 SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_SRC, 932 sun8i_aif_stereo_mux_enum_values); 933 934 static const struct snd_kcontrol_new sun8i_aif2_dac_stereo_mux_control = 935 SOC_DAPM_ENUM("AIF2 DAC Stereo Playback Route", 936 sun8i_aif2_dac_stereo_mux_enum); 937 938 static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { 939 SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch", 940 SUN8I_DAC_MXR_SRC, 941 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L, 942 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0), 943 SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch", 944 SUN8I_DAC_MXR_SRC, 945 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L, 946 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0), 947 SOC_DAPM_DOUBLE("AIF2 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, 948 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL, 949 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0), 950 SOC_DAPM_DOUBLE("ADC Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, 951 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL, 952 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0), 953 }; 954 955 static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { 956 /* System Clocks */ 957 SND_SOC_DAPM_CLOCK_SUPPLY("mod"), 958 959 SND_SOC_DAPM_SUPPLY("AIF1CLK", 960 SUN8I_SYSCLK_CTL, 961 SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0), 962 SND_SOC_DAPM_SUPPLY("AIF2CLK", 963 SUN8I_SYSCLK_CTL, 964 SUN8I_SYSCLK_CTL_AIF2CLK_ENA, 0, NULL, 0), 965 SND_SOC_DAPM_SUPPLY("SYSCLK", 966 SUN8I_SYSCLK_CTL, 967 SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0), 968 969 /* Module Clocks */ 970 SND_SOC_DAPM_SUPPLY("CLK AIF1", 971 SUN8I_MOD_CLK_ENA, 972 SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0), 973 SND_SOC_DAPM_SUPPLY("CLK AIF2", 974 SUN8I_MOD_CLK_ENA, 975 SUN8I_MOD_CLK_ENA_AIF2, 0, NULL, 0), 976 SND_SOC_DAPM_SUPPLY("CLK AIF3", 977 SUN8I_MOD_CLK_ENA, 978 SUN8I_MOD_CLK_ENA_AIF3, 0, NULL, 0), 979 SND_SOC_DAPM_SUPPLY("CLK ADC", 980 SUN8I_MOD_CLK_ENA, 981 SUN8I_MOD_CLK_ENA_ADC, 0, NULL, 0), 982 SND_SOC_DAPM_SUPPLY("CLK DAC", 983 SUN8I_MOD_CLK_ENA, 984 SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0), 985 986 /* Module Resets */ 987 SND_SOC_DAPM_SUPPLY("RST AIF1", 988 SUN8I_MOD_RST_CTL, 989 SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0), 990 SND_SOC_DAPM_SUPPLY("RST AIF2", 991 SUN8I_MOD_RST_CTL, 992 SUN8I_MOD_RST_CTL_AIF2, 0, NULL, 0), 993 SND_SOC_DAPM_SUPPLY("RST AIF3", 994 SUN8I_MOD_RST_CTL, 995 SUN8I_MOD_RST_CTL_AIF3, 0, NULL, 0), 996 SND_SOC_DAPM_SUPPLY("RST ADC", 997 SUN8I_MOD_RST_CTL, 998 SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0), 999 SND_SOC_DAPM_SUPPLY("RST DAC", 1000 SUN8I_MOD_RST_CTL, 1001 SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0), 1002 1003 /* Module Supplies */ 1004 SND_SOC_DAPM_SUPPLY("ADC", 1005 SUN8I_ADC_DIG_CTRL, 1006 SUN8I_ADC_DIG_CTRL_ENAD, 0, NULL, 0), 1007 SND_SOC_DAPM_SUPPLY("DAC", 1008 SUN8I_DAC_DIG_CTRL, 1009 SUN8I_DAC_DIG_CTRL_ENDA, 0, NULL, 0), 1010 1011 /* AIF "ADC" Outputs */ 1012 SND_SOC_DAPM_AIF_OUT_E("AIF1 AD0L", "AIF1 Capture", 0, 1013 SUN8I_AIF1_ADCDAT_CTRL, 1014 SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0, 1015 sun8i_codec_aif_event, 1016 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1017 SND_SOC_DAPM_AIF_OUT("AIF1 AD0R", "AIF1 Capture", 1, 1018 SUN8I_AIF1_ADCDAT_CTRL, 1019 SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0), 1020 1021 SND_SOC_DAPM_AIF_OUT_E("AIF2 ADCL", "AIF2 Capture", 0, 1022 SUN8I_AIF2_ADCDAT_CTRL, 1023 SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_ENA, 0, 1024 sun8i_codec_aif_event, 1025 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1026 SND_SOC_DAPM_AIF_OUT("AIF2 ADCR", "AIF2 Capture", 1, 1027 SUN8I_AIF2_ADCDAT_CTRL, 1028 SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_ENA, 0), 1029 1030 SND_SOC_DAPM_AIF_OUT_E("AIF3 ADC", "AIF3 Capture", 0, 1031 SND_SOC_NOPM, 0, 0, 1032 sun8i_codec_aif_event, 1033 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1034 1035 /* AIF "ADC" Mono/Stereo Muxes */ 1036 SND_SOC_DAPM_MUX("AIF1 AD0L Stereo Mux", SND_SOC_NOPM, 0, 0, 1037 &sun8i_aif1_ad0_stereo_mux_control), 1038 SND_SOC_DAPM_MUX("AIF1 AD0R Stereo Mux", SND_SOC_NOPM, 0, 0, 1039 &sun8i_aif1_ad0_stereo_mux_control), 1040 1041 SND_SOC_DAPM_MUX("AIF2 ADCL Stereo Mux", SND_SOC_NOPM, 0, 0, 1042 &sun8i_aif2_adc_stereo_mux_control), 1043 SND_SOC_DAPM_MUX("AIF2 ADCR Stereo Mux", SND_SOC_NOPM, 0, 0, 1044 &sun8i_aif2_adc_stereo_mux_control), 1045 1046 /* AIF "ADC" Output Muxes */ 1047 SND_SOC_DAPM_MUX("AIF3 ADC Source Capture Route", SND_SOC_NOPM, 0, 0, 1048 &sun8i_aif3_adc_mux_control), 1049 1050 /* AIF "ADC" Mixers */ 1051 SOC_MIXER_ARRAY("AIF1 AD0L Mixer", SND_SOC_NOPM, 0, 0, 1052 sun8i_aif1_ad0_mixer_controls), 1053 SOC_MIXER_ARRAY("AIF1 AD0R Mixer", SND_SOC_NOPM, 0, 0, 1054 sun8i_aif1_ad0_mixer_controls), 1055 1056 SOC_MIXER_ARRAY("AIF2 ADCL Mixer", SND_SOC_NOPM, 0, 0, 1057 sun8i_aif2_adc_mixer_controls), 1058 SOC_MIXER_ARRAY("AIF2 ADCR Mixer", SND_SOC_NOPM, 0, 0, 1059 sun8i_aif2_adc_mixer_controls), 1060 1061 /* AIF "DAC" Input Muxes */ 1062 SND_SOC_DAPM_MUX("AIF2 DACL Source", SND_SOC_NOPM, 0, 0, 1063 &sun8i_aif2_dac_mux_control), 1064 SND_SOC_DAPM_MUX("AIF2 DACR Source", SND_SOC_NOPM, 0, 0, 1065 &sun8i_aif2_dac_mux_control), 1066 1067 /* AIF "DAC" Mono/Stereo Muxes */ 1068 SND_SOC_DAPM_MUX("AIF1 DA0L Stereo Mux", SND_SOC_NOPM, 0, 0, 1069 &sun8i_aif1_da0_stereo_mux_control), 1070 SND_SOC_DAPM_MUX("AIF1 DA0R Stereo Mux", SND_SOC_NOPM, 0, 0, 1071 &sun8i_aif1_da0_stereo_mux_control), 1072 1073 SND_SOC_DAPM_MUX("AIF2 DACL Stereo Mux", SND_SOC_NOPM, 0, 0, 1074 &sun8i_aif2_dac_stereo_mux_control), 1075 SND_SOC_DAPM_MUX("AIF2 DACR Stereo Mux", SND_SOC_NOPM, 0, 0, 1076 &sun8i_aif2_dac_stereo_mux_control), 1077 1078 /* AIF "DAC" Inputs */ 1079 SND_SOC_DAPM_AIF_IN_E("AIF1 DA0L", "AIF1 Playback", 0, 1080 SUN8I_AIF1_DACDAT_CTRL, 1081 SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0, 1082 sun8i_codec_aif_event, 1083 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1084 SND_SOC_DAPM_AIF_IN("AIF1 DA0R", "AIF1 Playback", 1, 1085 SUN8I_AIF1_DACDAT_CTRL, 1086 SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0), 1087 1088 SND_SOC_DAPM_AIF_IN_E("AIF2 DACL", "AIF2 Playback", 0, 1089 SUN8I_AIF2_DACDAT_CTRL, 1090 SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_ENA, 0, 1091 sun8i_codec_aif_event, 1092 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1093 SND_SOC_DAPM_AIF_IN("AIF2 DACR", "AIF2 Playback", 1, 1094 SUN8I_AIF2_DACDAT_CTRL, 1095 SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_ENA, 0), 1096 1097 SND_SOC_DAPM_AIF_IN_E("AIF3 DAC", "AIF3 Playback", 0, 1098 SND_SOC_NOPM, 0, 0, 1099 sun8i_codec_aif_event, 1100 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1101 1102 /* ADC Inputs (connected to analog codec DAPM context) */ 1103 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 0, 0), 1104 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), 1105 1106 /* DAC Outputs (connected to analog codec DAPM context) */ 1107 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), 1108 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0), 1109 1110 /* DAC Mixers */ 1111 SOC_MIXER_ARRAY("DACL Mixer", SND_SOC_NOPM, 0, 0, 1112 sun8i_dac_mixer_controls), 1113 SOC_MIXER_ARRAY("DACR Mixer", SND_SOC_NOPM, 0, 0, 1114 sun8i_dac_mixer_controls), 1115 }; 1116 1117 static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { 1118 /* Clock Routes */ 1119 { "AIF1CLK", NULL, "mod" }, 1120 1121 { "SYSCLK", NULL, "AIF1CLK" }, 1122 1123 { "CLK AIF1", NULL, "AIF1CLK" }, 1124 { "CLK AIF1", NULL, "SYSCLK" }, 1125 { "RST AIF1", NULL, "CLK AIF1" }, 1126 { "AIF1 AD0L", NULL, "RST AIF1" }, 1127 { "AIF1 AD0R", NULL, "RST AIF1" }, 1128 { "AIF1 DA0L", NULL, "RST AIF1" }, 1129 { "AIF1 DA0R", NULL, "RST AIF1" }, 1130 1131 { "CLK AIF2", NULL, "AIF2CLK" }, 1132 { "CLK AIF2", NULL, "SYSCLK" }, 1133 { "RST AIF2", NULL, "CLK AIF2" }, 1134 { "AIF2 ADCL", NULL, "RST AIF2" }, 1135 { "AIF2 ADCR", NULL, "RST AIF2" }, 1136 { "AIF2 DACL", NULL, "RST AIF2" }, 1137 { "AIF2 DACR", NULL, "RST AIF2" }, 1138 1139 { "CLK AIF3", NULL, "AIF1CLK" }, 1140 { "CLK AIF3", NULL, "SYSCLK" }, 1141 { "RST AIF3", NULL, "CLK AIF3" }, 1142 { "AIF3 ADC", NULL, "RST AIF3" }, 1143 { "AIF3 DAC", NULL, "RST AIF3" }, 1144 1145 { "CLK ADC", NULL, "SYSCLK" }, 1146 { "RST ADC", NULL, "CLK ADC" }, 1147 { "ADC", NULL, "RST ADC" }, 1148 { "ADCL", NULL, "ADC" }, 1149 { "ADCR", NULL, "ADC" }, 1150 1151 { "CLK DAC", NULL, "SYSCLK" }, 1152 { "RST DAC", NULL, "CLK DAC" }, 1153 { "DAC", NULL, "RST DAC" }, 1154 { "DACL", NULL, "DAC" }, 1155 { "DACR", NULL, "DAC" }, 1156 1157 /* AIF "ADC" Output Routes */ 1158 { "AIF1 AD0L", NULL, "AIF1 AD0L Stereo Mux" }, 1159 { "AIF1 AD0R", NULL, "AIF1 AD0R Stereo Mux" }, 1160 1161 { "AIF2 ADCL", NULL, "AIF2 ADCL Stereo Mux" }, 1162 { "AIF2 ADCR", NULL, "AIF2 ADCR Stereo Mux" }, 1163 1164 { "AIF3 ADC", NULL, "AIF3 ADC Source Capture Route" }, 1165 1166 /* AIF "ADC" Mono/Stereo Mux Routes */ 1167 { "AIF1 AD0L Stereo Mux", "Stereo", "AIF1 AD0L Mixer" }, 1168 { "AIF1 AD0L Stereo Mux", "Reverse Stereo", "AIF1 AD0R Mixer" }, 1169 { "AIF1 AD0L Stereo Mux", "Sum Mono", "AIF1 AD0L Mixer" }, 1170 { "AIF1 AD0L Stereo Mux", "Sum Mono", "AIF1 AD0R Mixer" }, 1171 { "AIF1 AD0L Stereo Mux", "Mix Mono", "AIF1 AD0L Mixer" }, 1172 { "AIF1 AD0L Stereo Mux", "Mix Mono", "AIF1 AD0R Mixer" }, 1173 1174 { "AIF1 AD0R Stereo Mux", "Stereo", "AIF1 AD0R Mixer" }, 1175 { "AIF1 AD0R Stereo Mux", "Reverse Stereo", "AIF1 AD0L Mixer" }, 1176 { "AIF1 AD0R Stereo Mux", "Sum Mono", "AIF1 AD0L Mixer" }, 1177 { "AIF1 AD0R Stereo Mux", "Sum Mono", "AIF1 AD0R Mixer" }, 1178 { "AIF1 AD0R Stereo Mux", "Mix Mono", "AIF1 AD0L Mixer" }, 1179 { "AIF1 AD0R Stereo Mux", "Mix Mono", "AIF1 AD0R Mixer" }, 1180 1181 { "AIF2 ADCL Stereo Mux", "Stereo", "AIF2 ADCL Mixer" }, 1182 { "AIF2 ADCL Stereo Mux", "Reverse Stereo", "AIF2 ADCR Mixer" }, 1183 { "AIF2 ADCL Stereo Mux", "Sum Mono", "AIF2 ADCL Mixer" }, 1184 { "AIF2 ADCL Stereo Mux", "Sum Mono", "AIF2 ADCR Mixer" }, 1185 { "AIF2 ADCL Stereo Mux", "Mix Mono", "AIF2 ADCL Mixer" }, 1186 { "AIF2 ADCL Stereo Mux", "Mix Mono", "AIF2 ADCR Mixer" }, 1187 1188 { "AIF2 ADCR Stereo Mux", "Stereo", "AIF2 ADCR Mixer" }, 1189 { "AIF2 ADCR Stereo Mux", "Reverse Stereo", "AIF2 ADCL Mixer" }, 1190 { "AIF2 ADCR Stereo Mux", "Sum Mono", "AIF2 ADCL Mixer" }, 1191 { "AIF2 ADCR Stereo Mux", "Sum Mono", "AIF2 ADCR Mixer" }, 1192 { "AIF2 ADCR Stereo Mux", "Mix Mono", "AIF2 ADCL Mixer" }, 1193 { "AIF2 ADCR Stereo Mux", "Mix Mono", "AIF2 ADCR Mixer" }, 1194 1195 /* AIF "ADC" Output Mux Routes */ 1196 { "AIF3 ADC Source Capture Route", "AIF2 ADCL", "AIF2 ADCL Mixer" }, 1197 { "AIF3 ADC Source Capture Route", "AIF2 ADCR", "AIF2 ADCR Mixer" }, 1198 1199 /* AIF "ADC" Mixer Routes */ 1200 { "AIF1 AD0L Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0L Stereo Mux" }, 1201 { "AIF1 AD0L Mixer", "AIF2 Digital ADC Capture Switch", "AIF2 DACL Source" }, 1202 { "AIF1 AD0L Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCL" }, 1203 { "AIF1 AD0L Mixer", "AIF2 Inv Digital ADC Capture Switch", "AIF2 DACR Source" }, 1204 1205 { "AIF1 AD0R Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0R Stereo Mux" }, 1206 { "AIF1 AD0R Mixer", "AIF2 Digital ADC Capture Switch", "AIF2 DACR Source" }, 1207 { "AIF1 AD0R Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCR" }, 1208 { "AIF1 AD0R Mixer", "AIF2 Inv Digital ADC Capture Switch", "AIF2 DACL Source" }, 1209 1210 { "AIF2 ADCL Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0L Stereo Mux" }, 1211 { "AIF2 ADCL Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DACR Source" }, 1212 { "AIF2 ADCL Mixer", "AIF2 ADC Mixer ADC Capture Switch", "ADCL" }, 1213 1214 { "AIF2 ADCR Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0R Stereo Mux" }, 1215 { "AIF2 ADCR Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DACL Source" }, 1216 { "AIF2 ADCR Mixer", "AIF2 ADC Mixer ADC Capture Switch", "ADCR" }, 1217 1218 /* AIF "DAC" Input Mux Routes */ 1219 { "AIF2 DACL Source", "AIF2", "AIF2 DACL Stereo Mux" }, 1220 { "AIF2 DACL Source", "AIF3+2", "AIF3 DAC" }, 1221 { "AIF2 DACL Source", "AIF2+3", "AIF2 DACL Stereo Mux" }, 1222 1223 { "AIF2 DACR Source", "AIF2", "AIF2 DACR Stereo Mux" }, 1224 { "AIF2 DACR Source", "AIF3+2", "AIF2 DACR Stereo Mux" }, 1225 { "AIF2 DACR Source", "AIF2+3", "AIF3 DAC" }, 1226 1227 /* AIF "DAC" Mono/Stereo Mux Routes */ 1228 { "AIF1 DA0L Stereo Mux", "Stereo", "AIF1 DA0L" }, 1229 { "AIF1 DA0L Stereo Mux", "Reverse Stereo", "AIF1 DA0R" }, 1230 { "AIF1 DA0L Stereo Mux", "Sum Mono", "AIF1 DA0L" }, 1231 { "AIF1 DA0L Stereo Mux", "Sum Mono", "AIF1 DA0R" }, 1232 { "AIF1 DA0L Stereo Mux", "Mix Mono", "AIF1 DA0L" }, 1233 { "AIF1 DA0L Stereo Mux", "Mix Mono", "AIF1 DA0R" }, 1234 1235 { "AIF1 DA0R Stereo Mux", "Stereo", "AIF1 DA0R" }, 1236 { "AIF1 DA0R Stereo Mux", "Reverse Stereo", "AIF1 DA0L" }, 1237 { "AIF1 DA0R Stereo Mux", "Sum Mono", "AIF1 DA0L" }, 1238 { "AIF1 DA0R Stereo Mux", "Sum Mono", "AIF1 DA0R" }, 1239 { "AIF1 DA0R Stereo Mux", "Mix Mono", "AIF1 DA0L" }, 1240 { "AIF1 DA0R Stereo Mux", "Mix Mono", "AIF1 DA0R" }, 1241 1242 { "AIF2 DACL Stereo Mux", "Stereo", "AIF2 DACL" }, 1243 { "AIF2 DACL Stereo Mux", "Reverse Stereo", "AIF2 DACR" }, 1244 { "AIF2 DACL Stereo Mux", "Sum Mono", "AIF2 DACL" }, 1245 { "AIF2 DACL Stereo Mux", "Sum Mono", "AIF2 DACR" }, 1246 { "AIF2 DACL Stereo Mux", "Mix Mono", "AIF2 DACL" }, 1247 { "AIF2 DACL Stereo Mux", "Mix Mono", "AIF2 DACR" }, 1248 1249 { "AIF2 DACR Stereo Mux", "Stereo", "AIF2 DACR" }, 1250 { "AIF2 DACR Stereo Mux", "Reverse Stereo", "AIF2 DACL" }, 1251 { "AIF2 DACR Stereo Mux", "Sum Mono", "AIF2 DACL" }, 1252 { "AIF2 DACR Stereo Mux", "Sum Mono", "AIF2 DACR" }, 1253 { "AIF2 DACR Stereo Mux", "Mix Mono", "AIF2 DACL" }, 1254 { "AIF2 DACR Stereo Mux", "Mix Mono", "AIF2 DACR" }, 1255 1256 /* DAC Output Routes */ 1257 { "DACL", NULL, "DACL Mixer" }, 1258 { "DACR", NULL, "DACR Mixer" }, 1259 1260 /* DAC Mixer Routes */ 1261 { "DACL Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0L Stereo Mux" }, 1262 { "DACL Mixer", "AIF2 Digital DAC Playback Switch", "AIF2 DACL Source" }, 1263 { "DACL Mixer", "ADC Digital DAC Playback Switch", "ADCL" }, 1264 1265 { "DACR Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0R Stereo Mux" }, 1266 { "DACR Mixer", "AIF2 Digital DAC Playback Switch", "AIF2 DACR Source" }, 1267 { "DACR Mixer", "ADC Digital DAC Playback Switch", "ADCR" }, 1268 }; 1269 1270 static const struct snd_soc_dapm_widget sun8i_codec_legacy_widgets[] = { 1271 /* Legacy ADC Inputs (connected to analog codec DAPM context) */ 1272 SND_SOC_DAPM_ADC("AIF1 Slot 0 Left ADC", NULL, SND_SOC_NOPM, 0, 0), 1273 SND_SOC_DAPM_ADC("AIF1 Slot 0 Right ADC", NULL, SND_SOC_NOPM, 0, 0), 1274 1275 /* Legacy DAC Outputs (connected to analog codec DAPM context) */ 1276 SND_SOC_DAPM_DAC("AIF1 Slot 0 Left", NULL, SND_SOC_NOPM, 0, 0), 1277 SND_SOC_DAPM_DAC("AIF1 Slot 0 Right", NULL, SND_SOC_NOPM, 0, 0), 1278 }; 1279 1280 static const struct snd_soc_dapm_route sun8i_codec_legacy_routes[] = { 1281 /* Legacy ADC Routes */ 1282 { "ADCL", NULL, "AIF1 Slot 0 Left ADC" }, 1283 { "ADCR", NULL, "AIF1 Slot 0 Right ADC" }, 1284 1285 /* Legacy DAC Routes */ 1286 { "AIF1 Slot 0 Left", NULL, "DACL" }, 1287 { "AIF1 Slot 0 Right", NULL, "DACR" }, 1288 }; 1289 1290 static int sun8i_codec_component_probe(struct snd_soc_component *component) 1291 { 1292 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1293 struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component); 1294 int ret; 1295 1296 scodec->component = component; 1297 1298 /* Add widgets for backward compatibility with old device trees. */ 1299 if (scodec->quirks->legacy_widgets) { 1300 ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_legacy_widgets, 1301 ARRAY_SIZE(sun8i_codec_legacy_widgets)); 1302 if (ret) 1303 return ret; 1304 1305 ret = snd_soc_dapm_add_routes(dapm, sun8i_codec_legacy_routes, 1306 ARRAY_SIZE(sun8i_codec_legacy_routes)); 1307 if (ret) 1308 return ret; 1309 } 1310 1311 /* 1312 * AIF1CLK and AIF2CLK share a pair of clock parents: PLL_AUDIO ("mod") 1313 * and MCLK (from the CPU DAI connected to AIF1). MCLK's parent is also 1314 * PLL_AUDIO, so using it adds no additional flexibility. Use PLL_AUDIO 1315 * directly to simplify the clock tree. 1316 */ 1317 regmap_update_bits(scodec->regmap, SUN8I_SYSCLK_CTL, 1318 SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK | 1319 SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK, 1320 SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL | 1321 SUN8I_SYSCLK_CTL_AIF2CLK_SRC_PLL); 1322 1323 /* Use AIF1CLK as the SYSCLK parent since AIF1 is used most often. */ 1324 regmap_update_bits(scodec->regmap, SUN8I_SYSCLK_CTL, 1325 BIT(SUN8I_SYSCLK_CTL_SYSCLK_SRC), 1326 SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF1CLK); 1327 1328 /* Program the default sample rate. */ 1329 sun8i_codec_update_sample_rate(scodec); 1330 1331 return 0; 1332 } 1333 1334 static void sun8i_codec_set_hmic_bias(struct sun8i_codec *scodec, bool enable) 1335 { 1336 struct snd_soc_dapm_context *dapm = &scodec->component->card->dapm; 1337 int irq_mask = BIT(SUN8I_HMIC_CTRL1_HMIC_DATA_IRQ_EN); 1338 1339 if (enable) 1340 snd_soc_dapm_force_enable_pin(dapm, "HBIAS"); 1341 else 1342 snd_soc_dapm_disable_pin(dapm, "HBIAS"); 1343 1344 snd_soc_dapm_sync(dapm); 1345 1346 regmap_update_bits(scodec->regmap, SUN8I_HMIC_CTRL1, 1347 irq_mask, enable ? irq_mask : 0); 1348 } 1349 1350 static void sun8i_codec_jack_work(struct work_struct *work) 1351 { 1352 struct sun8i_codec *scodec = container_of(work, struct sun8i_codec, 1353 jack_work.work); 1354 unsigned int mdata; 1355 int type_mask = scodec->jack->jack->type; 1356 int type; 1357 1358 guard(mutex)(&scodec->jack_mutex); 1359 1360 if (scodec->jack_status == SUN8I_JACK_STATUS_DISCONNECTED) { 1361 if (scodec->last_hmic_irq != SUN8I_HMIC_STS_JACK_IN_IRQ_ST) 1362 return; 1363 1364 scodec->jack_last_sample = -1; 1365 1366 if (type_mask & SND_JACK_MICROPHONE) { 1367 /* 1368 * If we were in disconnected state, we enable HBIAS and 1369 * wait 600ms before reading initial HDATA value. 1370 */ 1371 scodec->jack_hbias_ready = ktime_add_ms(ktime_get(), 600); 1372 sun8i_codec_set_hmic_bias(scodec, true); 1373 queue_delayed_work(system_power_efficient_wq, 1374 &scodec->jack_work, 1375 msecs_to_jiffies(610)); 1376 scodec->jack_status = SUN8I_JACK_STATUS_WAITING_HBIAS; 1377 } else { 1378 snd_soc_jack_report(scodec->jack, SND_JACK_HEADPHONE, 1379 type_mask); 1380 scodec->jack_status = SUN8I_JACK_STATUS_CONNECTED; 1381 } 1382 } else if (scodec->jack_status == SUN8I_JACK_STATUS_WAITING_HBIAS) { 1383 /* 1384 * If we're waiting for HBIAS to stabilize, and we get plug-out 1385 * interrupt and nothing more for > 100ms, just cancel the 1386 * initialization. 1387 */ 1388 if (scodec->last_hmic_irq == SUN8I_HMIC_STS_JACK_OUT_IRQ_ST) { 1389 scodec->jack_status = SUN8I_JACK_STATUS_DISCONNECTED; 1390 sun8i_codec_set_hmic_bias(scodec, false); 1391 return; 1392 } 1393 1394 /* 1395 * If we're not done waiting for HBIAS to stabilize, wait more. 1396 */ 1397 if (!ktime_after(ktime_get(), scodec->jack_hbias_ready)) { 1398 s64 msecs = ktime_ms_delta(scodec->jack_hbias_ready, 1399 ktime_get()); 1400 1401 queue_delayed_work(system_power_efficient_wq, 1402 &scodec->jack_work, 1403 msecs_to_jiffies(msecs + 10)); 1404 return; 1405 } 1406 1407 /* 1408 * Everything is stabilized, determine jack type and report it. 1409 */ 1410 regmap_read(scodec->regmap, SUN8I_HMIC_STS, &mdata); 1411 mdata &= SUN8I_HMIC_STS_HMIC_DATA_MASK; 1412 mdata >>= SUN8I_HMIC_STS_HMIC_DATA; 1413 1414 regmap_write(scodec->regmap, SUN8I_HMIC_STS, 0); 1415 1416 type = mdata < 16 ? SND_JACK_HEADPHONE : SND_JACK_HEADSET; 1417 if (type == SND_JACK_HEADPHONE) 1418 sun8i_codec_set_hmic_bias(scodec, false); 1419 1420 snd_soc_jack_report(scodec->jack, type, type_mask); 1421 scodec->jack_status = SUN8I_JACK_STATUS_CONNECTED; 1422 } else if (scodec->jack_status == SUN8I_JACK_STATUS_CONNECTED) { 1423 if (scodec->last_hmic_irq != SUN8I_HMIC_STS_JACK_OUT_IRQ_ST) 1424 return; 1425 1426 scodec->jack_status = SUN8I_JACK_STATUS_DISCONNECTED; 1427 if (type_mask & SND_JACK_MICROPHONE) 1428 sun8i_codec_set_hmic_bias(scodec, false); 1429 1430 snd_soc_jack_report(scodec->jack, 0, type_mask); 1431 } 1432 } 1433 1434 static irqreturn_t sun8i_codec_jack_irq(int irq, void *dev_id) 1435 { 1436 struct sun8i_codec *scodec = dev_id; 1437 int type = SND_JACK_HEADSET; 1438 unsigned int status, value; 1439 1440 guard(mutex)(&scodec->jack_mutex); 1441 1442 regmap_read(scodec->regmap, SUN8I_HMIC_STS, &status); 1443 regmap_write(scodec->regmap, SUN8I_HMIC_STS, status); 1444 1445 /* 1446 * De-bounce in/out interrupts via a delayed work re-scheduling to 1447 * 100ms after each interrupt.. 1448 */ 1449 if (status & BIT(SUN8I_HMIC_STS_JACK_OUT_IRQ_ST)) { 1450 /* 1451 * Out interrupt has priority over in interrupt so that if 1452 * we get both, we assume the disconnected state, which is 1453 * safer. 1454 */ 1455 scodec->last_hmic_irq = SUN8I_HMIC_STS_JACK_OUT_IRQ_ST; 1456 mod_delayed_work(system_power_efficient_wq, &scodec->jack_work, 1457 msecs_to_jiffies(100)); 1458 } else if (status & BIT(SUN8I_HMIC_STS_JACK_IN_IRQ_ST)) { 1459 scodec->last_hmic_irq = SUN8I_HMIC_STS_JACK_IN_IRQ_ST; 1460 mod_delayed_work(system_power_efficient_wq, &scodec->jack_work, 1461 msecs_to_jiffies(100)); 1462 } else if (status & BIT(SUN8I_HMIC_STS_HMIC_DATA_IRQ_ST)) { 1463 /* 1464 * Ignore data interrupts until jack status turns to connected 1465 * state, which is after HMIC enable stabilization is completed. 1466 * Until then tha data are bogus. 1467 */ 1468 if (scodec->jack_status != SUN8I_JACK_STATUS_CONNECTED) 1469 return IRQ_HANDLED; 1470 1471 value = (status & SUN8I_HMIC_STS_HMIC_DATA_MASK) >> 1472 SUN8I_HMIC_STS_HMIC_DATA; 1473 1474 /* 1475 * Assumes 60 mV per ADC LSB increment, 2V bias voltage, 2.2kOhm 1476 * bias resistor. 1477 */ 1478 if (value == 0) 1479 type |= SND_JACK_BTN_0; 1480 else if (value == 1) 1481 type |= SND_JACK_BTN_3; 1482 else if (value <= 3) 1483 type |= SND_JACK_BTN_1; 1484 else if (value <= 8) 1485 type |= SND_JACK_BTN_2; 1486 1487 /* 1488 * De-bounce. Only report button after two consecutive A/D 1489 * samples are identical. 1490 */ 1491 if (scodec->jack_last_sample >= 0 && 1492 scodec->jack_last_sample == value) 1493 snd_soc_jack_report(scodec->jack, type, 1494 scodec->jack->jack->type); 1495 1496 scodec->jack_last_sample = value; 1497 } 1498 1499 return IRQ_HANDLED; 1500 } 1501 1502 static int sun8i_codec_enable_jack_detect(struct snd_soc_component *component, 1503 struct snd_soc_jack *jack, void *data) 1504 { 1505 struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component); 1506 struct platform_device *pdev = to_platform_device(component->dev); 1507 int ret; 1508 1509 if (!scodec->quirks->jack_detection) 1510 return 0; 1511 1512 scodec->jack = jack; 1513 1514 scodec->jack_irq = platform_get_irq(pdev, 0); 1515 if (scodec->jack_irq < 0) 1516 return scodec->jack_irq; 1517 1518 /* Reserved value required for jack IRQs to trigger. */ 1519 regmap_write(scodec->regmap, SUN8I_HMIC_CTRL1, 1520 0xf << SUN8I_HMIC_CTRL1_HMIC_N | 1521 0x0 << SUN8I_HMIC_CTRL1_MDATA_THRESHOLD_DB | 1522 0x4 << SUN8I_HMIC_CTRL1_HMIC_M); 1523 1524 /* Sample the ADC at 128 Hz; bypass smooth filter. */ 1525 regmap_write(scodec->regmap, SUN8I_HMIC_CTRL2, 1526 0x0 << SUN8I_HMIC_CTRL2_HMIC_SAMPLE | 1527 0x17 << SUN8I_HMIC_CTRL2_HMIC_MDATA_THRESHOLD | 1528 0x0 << SUN8I_HMIC_CTRL2_HMIC_SF); 1529 1530 /* Do not discard any MDATA, enable user written MDATA threshold. */ 1531 regmap_write(scodec->regmap, SUN8I_HMIC_STS, 0); 1532 1533 regmap_set_bits(scodec->regmap, SUN8I_HMIC_CTRL1, 1534 BIT(SUN8I_HMIC_CTRL1_JACK_OUT_IRQ_EN) | 1535 BIT(SUN8I_HMIC_CTRL1_JACK_IN_IRQ_EN)); 1536 1537 ret = devm_request_threaded_irq(&pdev->dev, scodec->jack_irq, 1538 NULL, sun8i_codec_jack_irq, 1539 IRQF_ONESHOT, 1540 dev_name(&pdev->dev), scodec); 1541 if (ret) 1542 return ret; 1543 1544 return 0; 1545 } 1546 1547 static void sun8i_codec_disable_jack_detect(struct snd_soc_component *component) 1548 { 1549 struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component); 1550 1551 if (!scodec->quirks->jack_detection) 1552 return; 1553 1554 devm_free_irq(component->dev, scodec->jack_irq, scodec); 1555 1556 cancel_delayed_work_sync(&scodec->jack_work); 1557 1558 regmap_clear_bits(scodec->regmap, SUN8I_HMIC_CTRL1, 1559 BIT(SUN8I_HMIC_CTRL1_JACK_OUT_IRQ_EN) | 1560 BIT(SUN8I_HMIC_CTRL1_JACK_IN_IRQ_EN) | 1561 BIT(SUN8I_HMIC_CTRL1_HMIC_DATA_IRQ_EN)); 1562 1563 scodec->jack = NULL; 1564 } 1565 1566 static int sun8i_codec_component_set_jack(struct snd_soc_component *component, 1567 struct snd_soc_jack *jack, void *data) 1568 { 1569 int ret = 0; 1570 1571 if (jack) 1572 ret = sun8i_codec_enable_jack_detect(component, jack, data); 1573 else 1574 sun8i_codec_disable_jack_detect(component); 1575 1576 return ret; 1577 } 1578 1579 static const struct snd_soc_component_driver sun8i_soc_component = { 1580 .controls = sun8i_codec_controls, 1581 .num_controls = ARRAY_SIZE(sun8i_codec_controls), 1582 .dapm_widgets = sun8i_codec_dapm_widgets, 1583 .num_dapm_widgets = ARRAY_SIZE(sun8i_codec_dapm_widgets), 1584 .dapm_routes = sun8i_codec_dapm_routes, 1585 .num_dapm_routes = ARRAY_SIZE(sun8i_codec_dapm_routes), 1586 .set_jack = sun8i_codec_component_set_jack, 1587 .probe = sun8i_codec_component_probe, 1588 .idle_bias_on = 1, 1589 .suspend_bias_off = 1, 1590 .endianness = 1, 1591 }; 1592 1593 static bool sun8i_codec_volatile_reg(struct device *dev, unsigned int reg) 1594 { 1595 return reg == SUN8I_HMIC_STS; 1596 } 1597 1598 static const struct regmap_config sun8i_codec_regmap_config = { 1599 .reg_bits = 32, 1600 .reg_stride = 4, 1601 .val_bits = 32, 1602 .volatile_reg = sun8i_codec_volatile_reg, 1603 .max_register = SUN8I_DAC_MXR_SRC, 1604 1605 .cache_type = REGCACHE_FLAT, 1606 }; 1607 1608 static int sun8i_codec_probe(struct platform_device *pdev) 1609 { 1610 struct sun8i_codec *scodec; 1611 void __iomem *base; 1612 int ret; 1613 1614 scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL); 1615 if (!scodec) 1616 return -ENOMEM; 1617 1618 scodec->quirks = of_device_get_match_data(&pdev->dev); 1619 INIT_DELAYED_WORK(&scodec->jack_work, sun8i_codec_jack_work); 1620 mutex_init(&scodec->jack_mutex); 1621 1622 platform_set_drvdata(pdev, scodec); 1623 1624 if (scodec->quirks->bus_clock) { 1625 scodec->clk_bus = devm_clk_get(&pdev->dev, "bus"); 1626 if (IS_ERR(scodec->clk_bus)) { 1627 dev_err(&pdev->dev, "Failed to get the bus clock\n"); 1628 return PTR_ERR(scodec->clk_bus); 1629 } 1630 } 1631 1632 scodec->clk_module = devm_clk_get(&pdev->dev, "mod"); 1633 if (IS_ERR(scodec->clk_module)) { 1634 dev_err(&pdev->dev, "Failed to get the module clock\n"); 1635 return PTR_ERR(scodec->clk_module); 1636 } 1637 1638 base = devm_platform_ioremap_resource(pdev, 0); 1639 if (IS_ERR(base)) { 1640 dev_err(&pdev->dev, "Failed to map the registers\n"); 1641 return PTR_ERR(base); 1642 } 1643 1644 scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base, 1645 &sun8i_codec_regmap_config); 1646 if (IS_ERR(scodec->regmap)) { 1647 dev_err(&pdev->dev, "Failed to create our regmap\n"); 1648 return PTR_ERR(scodec->regmap); 1649 } 1650 1651 regcache_cache_only(scodec->regmap, true); 1652 pm_runtime_enable(&pdev->dev); 1653 if (!pm_runtime_enabled(&pdev->dev)) { 1654 ret = sun8i_codec_runtime_resume(&pdev->dev); 1655 if (ret) 1656 goto err_pm_disable; 1657 } 1658 1659 ret = devm_snd_soc_register_component(&pdev->dev, &sun8i_soc_component, 1660 sun8i_codec_dais, 1661 ARRAY_SIZE(sun8i_codec_dais)); 1662 if (ret) { 1663 dev_err(&pdev->dev, "Failed to register codec\n"); 1664 goto err_suspend; 1665 } 1666 1667 return ret; 1668 1669 err_suspend: 1670 if (!pm_runtime_status_suspended(&pdev->dev)) 1671 sun8i_codec_runtime_suspend(&pdev->dev); 1672 1673 err_pm_disable: 1674 pm_runtime_disable(&pdev->dev); 1675 1676 return ret; 1677 } 1678 1679 static void sun8i_codec_remove(struct platform_device *pdev) 1680 { 1681 pm_runtime_disable(&pdev->dev); 1682 if (!pm_runtime_status_suspended(&pdev->dev)) 1683 sun8i_codec_runtime_suspend(&pdev->dev); 1684 } 1685 1686 static const struct sun8i_codec_quirks sun8i_a33_quirks = { 1687 .bus_clock = true, 1688 .legacy_widgets = true, 1689 .lrck_inversion = true, 1690 }; 1691 1692 static const struct sun8i_codec_quirks sun50i_a64_quirks = { 1693 .bus_clock = true, 1694 .jack_detection = true, 1695 }; 1696 1697 static const struct of_device_id sun8i_codec_of_match[] = { 1698 { .compatible = "allwinner,sun8i-a33-codec", .data = &sun8i_a33_quirks }, 1699 { .compatible = "allwinner,sun50i-a64-codec", .data = &sun50i_a64_quirks }, 1700 {} 1701 }; 1702 MODULE_DEVICE_TABLE(of, sun8i_codec_of_match); 1703 1704 static const struct dev_pm_ops sun8i_codec_pm_ops = { 1705 SET_RUNTIME_PM_OPS(sun8i_codec_runtime_suspend, 1706 sun8i_codec_runtime_resume, NULL) 1707 }; 1708 1709 static struct platform_driver sun8i_codec_driver = { 1710 .driver = { 1711 .name = "sun8i-codec", 1712 .of_match_table = sun8i_codec_of_match, 1713 .pm = &sun8i_codec_pm_ops, 1714 }, 1715 .probe = sun8i_codec_probe, 1716 .remove_new = sun8i_codec_remove, 1717 }; 1718 module_platform_driver(sun8i_codec_driver); 1719 1720 MODULE_DESCRIPTION("Allwinner A33 (sun8i) codec driver"); 1721 MODULE_AUTHOR("Mylène Josserand <mylene.josserand@free-electrons.com>"); 1722 MODULE_LICENSE("GPL"); 1723 MODULE_ALIAS("platform:sun8i-codec"); 1724