1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek ALSA SoC Audio DAI TDM Control 4 * 5 * Copyright (c) 2025 MediaTek Inc. 6 * Author: Darren Ye <darren.ye@mediatek.com> 7 */ 8 9 #include <linux/regmap.h> 10 #include <sound/pcm_params.h> 11 12 #include "mt8196-afe-clk.h" 13 #include "mt8196-afe-common.h" 14 #include "mt8196-interconnection.h" 15 16 struct mtk_afe_tdm_priv { 17 int bck_id; 18 int bck_rate; 19 20 int mclk_id; 21 int mclk_multiple; /* according to sample rate */ 22 int mclk_rate; 23 int mclk_apll; 24 }; 25 26 enum { 27 TDM_WLEN_8_BIT, 28 TDM_WLEN_16_BIT, 29 TDM_WLEN_24_BIT, 30 TDM_WLEN_32_BIT, 31 }; 32 33 enum { 34 TDM_CHANNEL_BCK_16, 35 TDM_CHANNEL_BCK_24, 36 TDM_CHANNEL_BCK_32, 37 }; 38 39 enum { 40 TDM_CHANNEL_NUM_2, 41 TDM_CHANNEL_NUM_4, 42 TDM_CHANNEL_NUM_8, 43 }; 44 45 enum { 46 TDM_CH_START_O30_O31, 47 TDM_CH_START_O32_O33, 48 TDM_CH_START_O34_O35, 49 TDM_CH_START_O36_O37, 50 TDM_CH_ZERO, 51 }; 52 53 enum { 54 DPTX_CHANNEL_2, 55 DPTX_CHANNEL_8, 56 }; 57 58 enum { 59 DPTX_WLEN_24_BIT, 60 DPTX_WLEN_16_BIT, 61 }; 62 63 #define DPTX_CH_EN_MASK_2CH (0x3) 64 #define DPTX_CH_EN_MASK_4CH (0xf) 65 #define DPTX_CH_EN_MASK_6CH (0x3f) 66 #define DPTX_CH_EN_MASK_8CH (0xff) 67 68 static unsigned int get_tdm_wlen(snd_pcm_format_t format) 69 { 70 return (snd_pcm_format_physical_width(format) / 8) - 1; 71 } 72 73 static unsigned int get_tdm_channel_bck(snd_pcm_format_t format) 74 { 75 return snd_pcm_format_physical_width(format) <= 16 ? 76 TDM_CHANNEL_BCK_16 : TDM_CHANNEL_BCK_32; 77 } 78 79 static unsigned int get_tdm_lrck_width(snd_pcm_format_t format) 80 { 81 return snd_pcm_format_physical_width(format) - 1; 82 } 83 84 static unsigned int get_tdm_ch(unsigned int ch) 85 { 86 switch (ch) { 87 case 1: 88 case 2: 89 return TDM_CHANNEL_NUM_2; 90 case 3: 91 case 4: 92 return TDM_CHANNEL_NUM_4; 93 case 5: 94 case 6: 95 case 7: 96 case 8: 97 default: 98 return TDM_CHANNEL_NUM_8; 99 } 100 } 101 102 static unsigned int get_dptx_ch_enable_mask(struct device *dev, unsigned int ch) 103 { 104 switch (ch) { 105 case 1: 106 case 2: 107 return DPTX_CH_EN_MASK_2CH; 108 case 3: 109 case 4: 110 return DPTX_CH_EN_MASK_4CH; 111 case 5: 112 case 6: 113 return DPTX_CH_EN_MASK_6CH; 114 case 7: 115 case 8: 116 return DPTX_CH_EN_MASK_8CH; 117 default: 118 dev_warn(dev, "invalid channel num, default use 2ch\n"); 119 return DPTX_CH_EN_MASK_2CH; 120 } 121 } 122 123 static unsigned int get_dptx_ch(unsigned int ch) 124 { 125 if (ch == 2) 126 return DPTX_CHANNEL_2; 127 else 128 return DPTX_CHANNEL_8; 129 } 130 131 static unsigned int get_dptx_wlen(snd_pcm_format_t format) 132 { 133 return snd_pcm_format_physical_width(format) <= 16 ? 134 DPTX_WLEN_16_BIT : DPTX_WLEN_24_BIT; 135 } 136 137 /* interconnection */ 138 enum { 139 HDMI_CONN_CH0, 140 HDMI_CONN_CH1, 141 HDMI_CONN_CH2, 142 HDMI_CONN_CH3, 143 HDMI_CONN_CH4, 144 HDMI_CONN_CH5, 145 HDMI_CONN_CH6, 146 HDMI_CONN_CH7, 147 }; 148 149 static const char *const hdmi_conn_mux_map[] = { 150 "CH0", "CH1", "CH2", "CH3", "CH4", "CH5", "CH6", "CH7", 151 }; 152 153 static int hdmi_conn_mux_map_value[] = { 154 HDMI_CONN_CH0, HDMI_CONN_CH1, HDMI_CONN_CH2, HDMI_CONN_CH3, 155 HDMI_CONN_CH4, HDMI_CONN_CH5, HDMI_CONN_CH6, HDMI_CONN_CH7, 156 }; 157 158 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum, 159 AFE_HDMI_CONN0, HDMI_O_0_SFT, HDMI_O_0_MASK, 160 hdmi_conn_mux_map, hdmi_conn_mux_map_value); 161 162 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum, 163 AFE_HDMI_CONN0, 164 HDMI_O_1_SFT, 165 HDMI_O_1_MASK, 166 hdmi_conn_mux_map, 167 hdmi_conn_mux_map_value); 168 169 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum, 170 AFE_HDMI_CONN0, 171 HDMI_O_2_SFT, 172 HDMI_O_2_MASK, 173 hdmi_conn_mux_map, 174 hdmi_conn_mux_map_value); 175 176 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum, 177 AFE_HDMI_CONN0, 178 HDMI_O_3_SFT, 179 HDMI_O_3_MASK, 180 hdmi_conn_mux_map, 181 hdmi_conn_mux_map_value); 182 183 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum, 184 AFE_HDMI_CONN0, 185 HDMI_O_4_SFT, 186 HDMI_O_4_MASK, 187 hdmi_conn_mux_map, 188 hdmi_conn_mux_map_value); 189 190 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum, 191 AFE_HDMI_CONN0, 192 HDMI_O_5_SFT, 193 HDMI_O_5_MASK, 194 hdmi_conn_mux_map, 195 hdmi_conn_mux_map_value); 196 197 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum, 198 AFE_HDMI_CONN0, 199 HDMI_O_6_SFT, 200 HDMI_O_6_MASK, 201 hdmi_conn_mux_map, 202 hdmi_conn_mux_map_value); 203 204 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum, 205 AFE_HDMI_CONN0, 206 HDMI_O_7_SFT, 207 HDMI_O_7_MASK, 208 hdmi_conn_mux_map, 209 hdmi_conn_mux_map_value); 210 211 static const struct snd_kcontrol_new mtk_dai_tdm_controls[] = { 212 SOC_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum), 213 SOC_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum), 214 SOC_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum), 215 SOC_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum), 216 SOC_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum), 217 SOC_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum), 218 SOC_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum), 219 SOC_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum), 220 }; 221 222 static const char *const tdm_out_demux_texts[] = { 223 "NONE", "TDMOUT", "DPTXOUT", 224 }; 225 226 static SOC_ENUM_SINGLE_DECL(tdm_out_demux_enum, 227 SND_SOC_NOPM, 228 0, 229 tdm_out_demux_texts); 230 static const struct snd_kcontrol_new tdm_out_demux_control = 231 SOC_DAPM_ENUM("TDM DEMUX ROUTE", tdm_out_demux_enum); 232 233 enum { 234 SUPPLY_SEQ_APLL, 235 SUPPLY_SEQ_TDM_MCK_EN, 236 SUPPLY_SEQ_TDM_BCK_EN, 237 SUPPLY_SEQ_TDM_DPTX_MCK_EN, 238 SUPPLY_SEQ_TDM_DPTX_BCK_EN, 239 SUPPLY_SEQ_TDM_CG_EN, 240 }; 241 242 static int get_tdm_id_by_name(const char *name) 243 { 244 if (strstr(name, "DPTX")) 245 return MT8196_DAI_TDM_DPTX; 246 else 247 return MT8196_DAI_TDM; 248 } 249 250 static int mtk_tdm_bck_en_event(struct snd_soc_dapm_widget *w, 251 struct snd_kcontrol *kcontrol, 252 int event) 253 { 254 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 255 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 256 struct mt8196_afe_private *afe_priv = afe->platform_priv; 257 int dai_id = get_tdm_id_by_name(w->name); 258 struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id]; 259 260 dev_dbg(cmpnt->dev, "name %s, event 0x%x, dai_id %d\n", 261 w->name, event, dai_id); 262 263 switch (event) { 264 case SND_SOC_DAPM_PRE_PMU: 265 mt8196_mck_enable(afe, tdm_priv->bck_id, tdm_priv->bck_rate); 266 break; 267 case SND_SOC_DAPM_POST_PMD: 268 mt8196_mck_disable(afe, tdm_priv->bck_id); 269 break; 270 default: 271 break; 272 } 273 274 return 0; 275 } 276 277 static int mtk_tdm_mck_en_event(struct snd_soc_dapm_widget *w, 278 struct snd_kcontrol *kcontrol, 279 int event) 280 { 281 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 282 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 283 struct mt8196_afe_private *afe_priv = afe->platform_priv; 284 int dai_id = get_tdm_id_by_name(w->name); 285 struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id]; 286 287 dev_dbg(cmpnt->dev, "name %s, event 0x%x, dai_id %d\n", 288 w->name, event, dai_id); 289 290 switch (event) { 291 case SND_SOC_DAPM_PRE_PMU: 292 mt8196_mck_enable(afe, tdm_priv->mclk_id, tdm_priv->mclk_rate); 293 break; 294 case SND_SOC_DAPM_POST_PMD: 295 tdm_priv->mclk_rate = 0; 296 mt8196_mck_disable(afe, tdm_priv->mclk_id); 297 break; 298 default: 299 break; 300 } 301 302 return 0; 303 } 304 305 static const struct snd_soc_dapm_widget mtk_dai_tdm_widgets[] = { 306 SND_SOC_DAPM_DEMUX("TDM_DEMUX", SND_SOC_NOPM, 0, 0, 307 &tdm_out_demux_control), 308 309 SND_SOC_DAPM_SUPPLY_S("TDM_BCK", SUPPLY_SEQ_TDM_BCK_EN, 310 SND_SOC_NOPM, 0, 0, 311 mtk_tdm_bck_en_event, 312 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 313 314 SND_SOC_DAPM_SUPPLY_S("TDM_MCK", SUPPLY_SEQ_TDM_MCK_EN, 315 SND_SOC_NOPM, 0, 0, 316 mtk_tdm_mck_en_event, 317 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 318 319 SND_SOC_DAPM_SUPPLY_S("TDM_DPTX_BCK", SUPPLY_SEQ_TDM_DPTX_BCK_EN, 320 SND_SOC_NOPM, 0, 0, 321 mtk_tdm_bck_en_event, 322 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 323 324 SND_SOC_DAPM_SUPPLY_S("TDM_DPTX_MCK", SUPPLY_SEQ_TDM_DPTX_MCK_EN, 325 SND_SOC_NOPM, 0, 0, 326 mtk_tdm_mck_en_event, 327 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 328 329 /* cg */ 330 SND_SOC_DAPM_SUPPLY_S("TDM_CG", SUPPLY_SEQ_TDM_CG_EN, 331 AUDIO_TOP_CON2, PDN_TDM_OUT_SFT, 1, 332 NULL, 0), 333 }; 334 335 static int mtk_afe_tdm_apll_connect(struct snd_soc_dapm_widget *source, 336 struct snd_soc_dapm_widget *sink) 337 { 338 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(sink->dapm); 339 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 340 struct mt8196_afe_private *afe_priv = afe->platform_priv; 341 int dai_id = get_tdm_id_by_name(sink->name); 342 struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id]; 343 int cur_apll; 344 345 /* which apll */ 346 cur_apll = mt8196_get_apll_by_name(afe, source->name); 347 348 return (tdm_priv->mclk_apll == cur_apll) ? 1 : 0; 349 } 350 351 static const struct snd_soc_dapm_route mtk_dai_tdm_routes[] = { 352 {"TDM_DEMUX", NULL, "HDMI"}, 353 354 {"TDM", "TDMOUT", "TDM_DEMUX"}, 355 {"TDM", NULL, "TDM_BCK"}, 356 {"TDM", NULL, "TDM_CG"}, 357 358 {"TDM_DPTX", "DPTXOUT", "TDM_DEMUX"}, 359 {"TDM_DPTX", NULL, "TDM_DPTX_BCK"}, 360 {"TDM_DPTX", NULL, "TDM_CG"}, 361 362 {"TDM_BCK", NULL, "TDM_MCK"}, 363 {"TDM_DPTX_BCK", NULL, "TDM_DPTX_MCK"}, 364 {"TDM_MCK", NULL, APLL1_W_NAME, mtk_afe_tdm_apll_connect}, 365 {"TDM_MCK", NULL, APLL2_W_NAME, mtk_afe_tdm_apll_connect}, 366 {"TDM_DPTX_MCK", NULL, APLL1_W_NAME, mtk_afe_tdm_apll_connect}, 367 {"TDM_DPTX_MCK", NULL, APLL2_W_NAME, mtk_afe_tdm_apll_connect}, 368 }; 369 370 /* dai ops */ 371 static int mtk_dai_tdm_cal_mclk(struct mtk_base_afe *afe, 372 struct mtk_afe_tdm_priv *tdm_priv, 373 int freq) 374 { 375 int apll; 376 int apll_rate; 377 378 apll = mt8196_get_apll_by_rate(afe, freq); 379 apll_rate = mt8196_get_apll_rate(afe, apll); 380 381 if (freq > apll_rate) 382 return -EINVAL; 383 384 if (apll_rate % freq != 0) 385 return -EINVAL; 386 387 tdm_priv->mclk_rate = freq; 388 tdm_priv->mclk_apll = apll; 389 390 return 0; 391 } 392 393 static int mtk_dai_tdm_hw_params(struct snd_pcm_substream *substream, 394 struct snd_pcm_hw_params *params, 395 struct snd_soc_dai *dai) 396 { 397 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 398 struct mt8196_afe_private *afe_priv = afe->platform_priv; 399 int tdm_id = dai->id; 400 struct mtk_afe_tdm_priv *tdm_priv; 401 unsigned int rate = params_rate(params); 402 unsigned int channels = params_channels(params); 403 snd_pcm_format_t format = params_format(params); 404 unsigned int tdm_con = 0; 405 406 if (tdm_id >= MT8196_DAI_NUM || tdm_id < 0) 407 return -EINVAL; 408 409 tdm_priv = afe_priv->dai_priv[tdm_id]; 410 411 if (!tdm_priv) 412 return -EINVAL; 413 414 /* calculate mclk_rate, if not set explicitly */ 415 if (!tdm_priv->mclk_rate) { 416 tdm_priv->mclk_rate = rate * tdm_priv->mclk_multiple; 417 mtk_dai_tdm_cal_mclk(afe, 418 tdm_priv, 419 tdm_priv->mclk_rate); 420 } 421 422 /* calculate bck */ 423 tdm_priv->bck_rate = rate * 424 channels * 425 snd_pcm_format_physical_width(format); 426 427 if (tdm_priv->bck_rate > tdm_priv->mclk_rate) 428 return -EINVAL; 429 430 if (tdm_priv->mclk_rate % tdm_priv->bck_rate != 0) 431 return -EINVAL; 432 433 dev_dbg(afe->dev, "id %d, rate %d, ch %d, fmt %d, mclk %d, bck %d\n", 434 tdm_id, rate, channels, format, tdm_priv->mclk_rate, tdm_priv->bck_rate); 435 436 /* set tdm */ 437 tdm_con = 0 << BCK_INVERSE_SFT; 438 tdm_con |= 0 << LRCK_INVERSE_SFT; 439 tdm_con |= 0 << DELAY_DATA_SFT; 440 tdm_con |= 1 << LEFT_ALIGN_SFT; 441 tdm_con |= get_tdm_wlen(format) << WLEN_SFT; 442 tdm_con |= get_tdm_ch(channels) << CHANNEL_NUM_SFT; 443 tdm_con |= get_tdm_channel_bck(format) << CHANNEL_BCK_CYCLES_SFT; 444 tdm_con |= get_tdm_lrck_width(format) << LRCK_TDM_WIDTH_SFT; 445 regmap_write(afe->regmap, AFE_TDM_CON1, tdm_con); 446 447 /* set dptx */ 448 if (tdm_id == MT8196_DAI_TDM_DPTX) { 449 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 450 DPTX_CHANNEL_ENABLE_MASK_SFT, 451 get_dptx_ch_enable_mask(afe->dev, channels) << 452 DPTX_CHANNEL_ENABLE_SFT); 453 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 454 DPTX_CHANNEL_NUMBER_MASK_SFT, 455 get_dptx_ch(channels) << 456 DPTX_CHANNEL_NUMBER_SFT); 457 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 458 DPTX_16BIT_MASK_SFT, 459 get_dptx_wlen(format) << DPTX_16BIT_SFT); 460 } 461 switch (channels) { 462 case 1: 463 case 2: 464 tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT; 465 tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT1_SFT; 466 tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT; 467 tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT; 468 break; 469 case 3: 470 case 4: 471 tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT; 472 tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT; 473 tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT; 474 tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT; 475 break; 476 case 5: 477 case 6: 478 tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT; 479 tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT; 480 tdm_con |= TDM_CH_START_O34_O35 << ST_CH_PAIR_SOUT2_SFT; 481 tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT; 482 break; 483 case 7: 484 case 8: 485 tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT; 486 tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT; 487 tdm_con |= TDM_CH_START_O34_O35 << ST_CH_PAIR_SOUT2_SFT; 488 tdm_con |= TDM_CH_START_O36_O37 << ST_CH_PAIR_SOUT3_SFT; 489 break; 490 default: 491 tdm_con = 0; 492 } 493 494 regmap_write(afe->regmap, AFE_TDM_CON2, tdm_con); 495 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 496 HDMI_CH_NUM_MASK_SFT, 497 channels << HDMI_CH_NUM_SFT); 498 499 return 0; 500 } 501 502 static int mtk_dai_tdm_trigger(struct snd_pcm_substream *substream, 503 int cmd, 504 struct snd_soc_dai *dai) 505 { 506 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 507 int tdm_id = dai->id; 508 509 dev_dbg(afe->dev, "cmd %d, tdm_id %d\n", cmd, tdm_id); 510 511 switch (cmd) { 512 case SNDRV_PCM_TRIGGER_START: 513 case SNDRV_PCM_TRIGGER_RESUME: 514 /* enable Out control */ 515 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 516 HDMI_OUT_ON_MASK_SFT, 517 0x1 << HDMI_OUT_ON_SFT); 518 519 /* enable dptx */ 520 if (tdm_id == MT8196_DAI_TDM_DPTX) { 521 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 522 DPTX_ON_MASK_SFT, 0x1 << 523 DPTX_ON_SFT); 524 } 525 526 /* enable tdm */ 527 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 528 TDM_EN_MASK_SFT, 0x1 << TDM_EN_SFT); 529 break; 530 case SNDRV_PCM_TRIGGER_STOP: 531 case SNDRV_PCM_TRIGGER_SUSPEND: 532 /* disable tdm */ 533 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 534 TDM_EN_MASK_SFT, 0); 535 536 /* disable dptx */ 537 if (tdm_id == MT8196_DAI_TDM_DPTX) { 538 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 539 DPTX_ON_MASK_SFT, 0); 540 } 541 542 /* disable Out control */ 543 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 544 HDMI_OUT_ON_MASK_SFT, 0); 545 break; 546 default: 547 return -EINVAL; 548 } 549 550 return 0; 551 } 552 553 static int mtk_dai_tdm_set_sysclk(struct snd_soc_dai *dai, 554 int clk_id, unsigned int freq, int dir) 555 { 556 struct mtk_base_afe *afe = dev_get_drvdata(dai->dev); 557 struct mt8196_afe_private *afe_priv = afe->platform_priv; 558 struct mtk_afe_tdm_priv *tdm_priv; 559 560 if (dai->id >= MT8196_DAI_NUM || dai->id < 0) 561 return -EINVAL; 562 563 tdm_priv = afe_priv->dai_priv[dai->id]; 564 565 if (!tdm_priv) 566 return -EINVAL; 567 568 if (dir != SND_SOC_CLOCK_OUT) 569 return -EINVAL; 570 571 dev_dbg(afe->dev, "freq %d\n", freq); 572 573 return mtk_dai_tdm_cal_mclk(afe, tdm_priv, freq); 574 } 575 576 static const struct snd_soc_dai_ops mtk_dai_tdm_ops = { 577 .hw_params = mtk_dai_tdm_hw_params, 578 .trigger = mtk_dai_tdm_trigger, 579 .set_sysclk = mtk_dai_tdm_set_sysclk, 580 }; 581 582 /* dai driver */ 583 #define MTK_TDM_RATES (SNDRV_PCM_RATE_8000_48000 |\ 584 SNDRV_PCM_RATE_88200 |\ 585 SNDRV_PCM_RATE_96000 |\ 586 SNDRV_PCM_RATE_176400 |\ 587 SNDRV_PCM_RATE_192000) 588 589 #define MTK_TDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 590 SNDRV_PCM_FMTBIT_S24_LE |\ 591 SNDRV_PCM_FMTBIT_S32_LE) 592 593 static struct snd_soc_dai_driver mtk_dai_tdm_driver[] = { 594 { 595 .name = "TDM", 596 .id = MT8196_DAI_TDM, 597 .playback = { 598 .stream_name = "TDM", 599 .channels_min = 2, 600 .channels_max = 8, 601 .rates = MTK_TDM_RATES, 602 .formats = MTK_TDM_FORMATS, 603 }, 604 .ops = &mtk_dai_tdm_ops, 605 }, 606 { 607 .name = "TDM_DPTX", 608 .id = MT8196_DAI_TDM_DPTX, 609 .playback = { 610 .stream_name = "TDM_DPTX", 611 .channels_min = 2, 612 .channels_max = 8, 613 .rates = MTK_TDM_RATES, 614 .formats = MTK_TDM_FORMATS, 615 }, 616 .ops = &mtk_dai_tdm_ops, 617 }, 618 }; 619 620 static struct mtk_afe_tdm_priv *init_tdm_priv_data(struct mtk_base_afe *afe, 621 int id) 622 { 623 struct mtk_afe_tdm_priv *tdm_priv; 624 625 tdm_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_afe_tdm_priv), 626 GFP_KERNEL); 627 if (!tdm_priv) 628 return NULL; 629 630 if (id == MT8196_DAI_TDM_DPTX) 631 tdm_priv->mclk_multiple = 256; 632 else 633 tdm_priv->mclk_multiple = 128; 634 635 tdm_priv->bck_id = MT8196_TDMOUT_BCK; 636 tdm_priv->mclk_id = MT8196_TDMOUT_MCK; 637 638 return tdm_priv; 639 } 640 641 int mt8196_dai_tdm_register(struct mtk_base_afe *afe) 642 { 643 struct mt8196_afe_private *afe_priv = afe->platform_priv; 644 struct mtk_afe_tdm_priv *tdm_priv, *tdm_dptx_priv; 645 struct mtk_base_afe_dai *dai; 646 647 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 648 if (!dai) 649 return -ENOMEM; 650 651 dai->dai_drivers = mtk_dai_tdm_driver; 652 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_tdm_driver); 653 dai->controls = mtk_dai_tdm_controls; 654 dai->num_controls = ARRAY_SIZE(mtk_dai_tdm_controls); 655 dai->dapm_widgets = mtk_dai_tdm_widgets; 656 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_tdm_widgets); 657 dai->dapm_routes = mtk_dai_tdm_routes; 658 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_tdm_routes); 659 660 tdm_priv = init_tdm_priv_data(afe, MT8196_DAI_TDM); 661 if (!tdm_priv) 662 return -ENOMEM; 663 664 tdm_dptx_priv = init_tdm_priv_data(afe, MT8196_DAI_TDM_DPTX); 665 if (!tdm_dptx_priv) 666 return -ENOMEM; 667 668 list_add(&dai->list, &afe->sub_dais); 669 670 afe_priv->dai_priv[MT8196_DAI_TDM] = tdm_priv; 671 afe_priv->dai_priv[MT8196_DAI_TDM_DPTX] = tdm_dptx_priv; 672 673 return 0; 674 } 675 676