1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek ALSA SoC Audio DAI I2S Control 4 * 5 * Copyright (c) 2025 MediaTek Inc. 6 * Author: Darren Ye <darren.ye@mediatek.com> 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/regmap.h> 11 12 #include <sound/pcm_params.h> 13 14 #include "mt8196-afe-clk.h" 15 #include "mt8196-afe-common.h" 16 #include "mt8196-interconnection.h" 17 18 #include "../common/mtk-afe-fe-dai.h" 19 20 #define ETDM_22M_CLOCK_THRES 11289600 21 22 enum { 23 ETDM_CLK_SOURCE_H26M, 24 ETDM_CLK_SOURCE_APLL, 25 ETDM_CLK_SOURCE_SPDIF, 26 ETDM_CLK_SOURCE_HDMI, 27 ETDM_CLK_SOURCE_EARC, 28 ETDM_CLK_SOURCE_LINEIN, 29 }; 30 31 enum { 32 ETDM_RELATCH_SEL_H26M, 33 ETDM_RELATCH_SEL_APLL, 34 }; 35 36 enum { 37 ETDM_RATE_8K, 38 ETDM_RATE_12K, 39 ETDM_RATE_16K, 40 ETDM_RATE_24K, 41 ETDM_RATE_32K, 42 ETDM_RATE_48K, 43 ETDM_RATE_64K, 44 ETDM_RATE_96K, 45 ETDM_RATE_128K, 46 ETDM_RATE_192K, 47 ETDM_RATE_256K, 48 ETDM_RATE_384K, 49 ETDM_RATE_11025 = 16, 50 ETDM_RATE_22050, 51 ETDM_RATE_44100, 52 ETDM_RATE_88200, 53 ETDM_RATE_176400, 54 ETDM_RATE_352800, 55 }; 56 57 enum { 58 ETDM_CONN_8K, 59 ETDM_CONN_11K, 60 ETDM_CONN_12K, 61 ETDM_CONN_16K = 4, 62 ETDM_CONN_22K, 63 ETDM_CONN_24K, 64 ETDM_CONN_32K = 8, 65 ETDM_CONN_44K, 66 ETDM_CONN_48K, 67 ETDM_CONN_88K = 13, 68 ETDM_CONN_96K, 69 ETDM_CONN_176K = 17, 70 ETDM_CONN_192K, 71 ETDM_CONN_352K = 21, 72 ETDM_CONN_384K, 73 }; 74 75 enum { 76 ETDM_WLEN_8_BIT = 0x7, 77 ETDM_WLEN_16_BIT = 0xf, 78 ETDM_WLEN_32_BIT = 0x1f, 79 }; 80 81 enum { 82 ETDM_SLAVE_SEL_ETDMIN0_MASTER, 83 ETDM_SLAVE_SEL_ETDMIN0_SLAVE, 84 ETDM_SLAVE_SEL_ETDMIN1_MASTER, 85 ETDM_SLAVE_SEL_ETDMIN1_SLAVE, 86 ETDM_SLAVE_SEL_ETDMIN2_MASTER, 87 ETDM_SLAVE_SEL_ETDMIN2_SLAVE, 88 ETDM_SLAVE_SEL_ETDMIN3_MASTER, 89 ETDM_SLAVE_SEL_ETDMIN3_SLAVE, 90 ETDM_SLAVE_SEL_ETDMOUT0_MASTER, 91 ETDM_SLAVE_SEL_ETDMOUT0_SLAVE, 92 ETDM_SLAVE_SEL_ETDMOUT1_MASTER, 93 ETDM_SLAVE_SEL_ETDMOUT1_SLAVE, 94 ETDM_SLAVE_SEL_ETDMOUT2_MASTER, 95 ETDM_SLAVE_SEL_ETDMOUT2_SLAVE, 96 ETDM_SLAVE_SEL_ETDMOUT3_MASTER, 97 ETDM_SLAVE_SEL_ETDMOUT3_SLAVE, 98 }; 99 100 enum { 101 ETDM_SLAVE_SEL_ETDMIN4_MASTER, 102 ETDM_SLAVE_SEL_ETDMIN4_SLAVE, 103 ETDM_SLAVE_SEL_ETDMIN5_MASTER, 104 ETDM_SLAVE_SEL_ETDMIN5_SLAVE, 105 ETDM_SLAVE_SEL_ETDMIN6_MASTER, 106 ETDM_SLAVE_SEL_ETDMIN6_SLAVE, 107 ETDM_SLAVE_SEL_ETDMIN7_MASTER, 108 ETDM_SLAVE_SEL_ETDMIN7_SLAVE, 109 ETDM_SLAVE_SEL_ETDMOUT4_MASTER, 110 ETDM_SLAVE_SEL_ETDMOUT4_SLAVE, 111 ETDM_SLAVE_SEL_ETDMOUT5_MASTER, 112 ETDM_SLAVE_SEL_ETDMOUT5_SLAVE, 113 ETDM_SLAVE_SEL_ETDMOUT6_MASTER, 114 ETDM_SLAVE_SEL_ETDMOUT6_SLAVE, 115 ETDM_SLAVE_SEL_ETDMOUT7_MASTER, 116 ETDM_SLAVE_SEL_ETDMOUT7_SLAVE, 117 }; 118 119 enum { 120 MTK_DAI_ETDM_FORMAT_I2S, 121 MTK_DAI_ETDM_FORMAT_LJ, 122 MTK_DAI_ETDM_FORMAT_RJ, 123 MTK_DAI_ETDM_FORMAT_EIAJ, 124 MTK_DAI_ETDM_FORMAT_DSPA, 125 MTK_DAI_ETDM_FORMAT_DSPB, 126 }; 127 128 static unsigned int get_etdm_wlen(snd_pcm_format_t format) 129 { 130 return snd_pcm_format_physical_width(format) < 16 ? 131 ETDM_WLEN_16_BIT : ETDM_WLEN_32_BIT; 132 } 133 134 static unsigned int get_etdm_lrck_width(snd_pcm_format_t format) 135 { 136 /* The valid data bit number should be large than 7 due to hardware limitation. */ 137 return snd_pcm_format_physical_width(format) - 1; 138 } 139 140 static unsigned int get_etdm_rate(unsigned int rate) 141 { 142 switch (rate) { 143 case 8000: 144 return ETDM_RATE_8K; 145 case 12000: 146 return ETDM_RATE_12K; 147 case 16000: 148 return ETDM_RATE_16K; 149 case 24000: 150 return ETDM_RATE_24K; 151 case 32000: 152 return ETDM_RATE_32K; 153 case 48000: 154 return ETDM_RATE_48K; 155 case 64000: 156 return ETDM_RATE_64K; 157 case 96000: 158 return ETDM_RATE_96K; 159 case 128000: 160 return ETDM_RATE_128K; 161 case 192000: 162 return ETDM_RATE_192K; 163 case 256000: 164 return ETDM_RATE_256K; 165 case 384000: 166 return ETDM_RATE_384K; 167 case 11025: 168 return ETDM_RATE_11025; 169 case 22050: 170 return ETDM_RATE_22050; 171 case 44100: 172 return ETDM_RATE_44100; 173 case 88200: 174 return ETDM_RATE_88200; 175 case 176400: 176 return ETDM_RATE_176400; 177 case 352800: 178 return ETDM_RATE_352800; 179 default: 180 return 0; 181 } 182 } 183 184 static unsigned int get_etdm_inconn_rate(unsigned int rate) 185 { 186 switch (rate) { 187 case 8000: 188 return ETDM_CONN_8K; 189 case 12000: 190 return ETDM_CONN_12K; 191 case 16000: 192 return ETDM_CONN_16K; 193 case 24000: 194 return ETDM_CONN_24K; 195 case 32000: 196 return ETDM_CONN_32K; 197 case 48000: 198 return ETDM_CONN_48K; 199 case 96000: 200 return ETDM_CONN_96K; 201 case 192000: 202 return ETDM_CONN_192K; 203 case 384000: 204 return ETDM_CONN_384K; 205 case 11025: 206 return ETDM_CONN_11K; 207 case 22050: 208 return ETDM_CONN_22K; 209 case 44100: 210 return ETDM_CONN_44K; 211 case 88200: 212 return ETDM_CONN_88K; 213 case 176400: 214 return ETDM_CONN_176K; 215 case 352800: 216 return ETDM_CONN_352K; 217 default: 218 return 0; 219 } 220 } 221 222 struct mtk_afe_i2s_priv { 223 u8 id; 224 u32 rate; /* for determine which apll to use */ 225 int low_jitter_en; 226 const char *share_property_name; 227 int share_i2s_id; 228 u32 mclk_rate; 229 u8 mclk_id; 230 u8 mclk_apll; 231 u8 ch_num; 232 u8 sync; 233 u8 ip_mode; 234 u8 format; 235 }; 236 237 /* this enum is merely for mtk_afe_i2s_priv & mtk_base_etdm_data declare */ 238 enum { 239 DAI_I2SIN0, 240 DAI_I2SIN1, 241 DAI_I2SIN2, 242 DAI_I2SIN3, 243 DAI_I2SIN4, 244 DAI_I2SIN6, 245 DAI_I2SOUT0, 246 DAI_I2SOUT1, 247 DAI_I2SOUT2, 248 DAI_I2SOUT3, 249 DAI_I2SOUT4, 250 DAI_I2SOUT6, 251 DAI_FMI2S_MASTER, 252 DAI_I2S_NUM, 253 }; 254 255 static bool is_etdm_in_pad_top(unsigned int dai_num) 256 { 257 switch (dai_num) { 258 case DAI_I2SOUT4: 259 case DAI_I2SIN4: 260 return true; 261 default: 262 return false; 263 } 264 } 265 266 struct mtk_base_etdm_data { 267 u16 enable_reg; 268 u16 enable_mask; 269 u8 enable_shift; 270 u16 sync_reg; 271 u16 sync_mask; 272 u8 sync_shift; 273 u16 ch_reg; 274 u16 ch_mask; 275 u8 ch_shift; 276 u16 ip_mode_reg; 277 u16 ip_mode_mask; 278 u8 ip_mode_shift; 279 u16 init_count_reg; 280 u16 init_count_mask; 281 u8 init_count_shift; 282 u16 init_point_reg; 283 u16 init_point_mask; 284 u8 init_point_shift; 285 u16 lrck_reset_reg; 286 u16 lrck_reset_mask; 287 u8 lrck_reset_shift; 288 u16 clk_source_reg; 289 u16 clk_source_mask; 290 u8 clk_source_shift; 291 u16 ck_en_sel_reg; 292 u16 ck_en_sel_mask; 293 u8 ck_en_sel_shift; 294 u16 fs_timing_reg; 295 u16 fs_timing_mask; 296 u8 fs_timing_shift; 297 u16 relatch_en_sel_reg; 298 u16 relatch_en_sel_mask; 299 u8 relatch_en_sel_shift; 300 u16 use_afifo_reg; 301 u16 use_afifo_mask; 302 u8 use_afifo_shift; 303 u16 afifo_mode_reg; 304 u16 afifo_mode_mask; 305 u8 afifo_mode_shift; 306 u16 almost_end_ch_reg; 307 u16 almost_end_ch_mask; 308 u8 almost_end_ch_shift; 309 u16 almost_end_bit_reg; 310 u16 almost_end_bit_mask; 311 u8 almost_end_bit_shift; 312 u16 out2latch_time_reg; 313 u16 out2latch_time_mask; 314 u8 out2latch_time_shift; 315 u16 tdm_mode_reg; 316 u16 tdm_mode_mask; 317 u8 tdm_mode_shift; 318 u16 relatch_domain_sel_reg; 319 u16 relatch_domain_sel_mask; 320 u8 relatch_domain_sel_shift; 321 u16 bit_length_reg; 322 u16 bit_length_mask; 323 u8 bit_length_shift; 324 u16 word_length_reg; 325 u16 word_length_mask; 326 u8 word_length_shift; 327 u16 cowork_reg; 328 u16 cowork_mask; 329 u8 cowork_shift; 330 u32 cowork_val; 331 u16 in2latch_time_reg; 332 u16 in2latch_time_mask; 333 u8 in2latch_time_shift; 334 u16 pad_top_ck_en_reg; 335 u16 pad_top_ck_en_mask; 336 u8 pad_top_ck_en_shift; 337 u16 master_latch_reg; 338 u16 master_latch_mask; 339 u8 master_latch_shift; 340 }; 341 342 /* 343 * _cfg_vlp_reg should be a variable or constant, not an expression 344 * with side effects. 345 */ 346 #define MTK_ETDM_IN_DATA(_id, _cowork, _cfg_vlp_reg) \ 347 [DAI_I2SIN##_id] = { \ 348 .enable_reg = ETDM_IN##_id##_CON0, \ 349 .enable_mask = REG_ETDM_IN_EN_MASK, \ 350 .enable_shift = REG_ETDM_IN_EN_SFT, \ 351 .sync_reg = ETDM_IN##_id##_CON0, \ 352 .sync_mask = REG_SYNC_MODE_MASK, \ 353 .sync_shift = REG_SYNC_MODE_SFT, \ 354 .ch_reg = ETDM_IN##_id##_CON0, \ 355 .ch_mask = REG_CH_NUM_MASK, \ 356 .ch_shift = REG_CH_NUM_SFT, \ 357 .ip_mode_reg = ETDM_IN##_id##_CON2, \ 358 .ip_mode_mask = REG_MULTI_IP_MODE_MASK, \ 359 .ip_mode_shift = REG_MULTI_IP_MODE_SFT, \ 360 .init_count_reg = ETDM_IN##_id##_CON1, \ 361 .init_count_mask = REG_INITIAL_COUNT_MASK, \ 362 .init_count_shift = REG_INITIAL_COUNT_SFT, \ 363 .init_point_reg = ETDM_IN##_id##_CON1, \ 364 .init_point_mask = REG_INITIAL_POINT_MASK, \ 365 .init_point_shift = REG_INITIAL_POINT_SFT, \ 366 .lrck_reset_reg = ETDM_IN##_id##_CON1, \ 367 .lrck_reset_mask = REG_LRCK_RESET_MASK, \ 368 .lrck_reset_shift = REG_LRCK_RESET_SFT, \ 369 .clk_source_reg = ETDM_IN##_id##_CON2, \ 370 .clk_source_mask = REG_CLOCK_SOURCE_SEL_MASK, \ 371 .clk_source_shift = REG_CLOCK_SOURCE_SEL_SFT, \ 372 .ck_en_sel_reg = ETDM_IN##_id##_CON2, \ 373 .ck_en_sel_mask = REG_CK_EN_SEL_AUTO_MASK, \ 374 .ck_en_sel_shift = REG_CK_EN_SEL_AUTO_SFT, \ 375 .fs_timing_reg = ETDM_IN##_id##_CON3, \ 376 .fs_timing_mask = REG_FS_TIMING_SEL_MASK, \ 377 .fs_timing_shift = REG_FS_TIMING_SEL_SFT, \ 378 .relatch_en_sel_reg = ETDM_IN##_id##_CON4, \ 379 .relatch_en_sel_mask = REG_RELATCH_1X_EN_SEL_MASK, \ 380 .relatch_en_sel_shift = REG_RELATCH_1X_EN_SEL_SFT, \ 381 .use_afifo_reg = ETDM_IN##_id##_CON8, \ 382 .use_afifo_mask = REG_ETDM_USE_AFIFO_MASK, \ 383 .use_afifo_shift = REG_ETDM_USE_AFIFO_SFT, \ 384 .afifo_mode_reg = ETDM_IN##_id##_CON8, \ 385 .afifo_mode_mask = REG_AFIFO_MODE_MASK, \ 386 .afifo_mode_shift = REG_AFIFO_MODE_SFT, \ 387 .almost_end_ch_reg = ETDM_IN##_id##_CON9, \ 388 .almost_end_ch_mask = REG_ALMOST_END_CH_COUNT_MASK, \ 389 .almost_end_ch_shift = REG_ALMOST_END_CH_COUNT_SFT, \ 390 .almost_end_bit_reg = ETDM_IN##_id##_CON9, \ 391 .almost_end_bit_mask = REG_ALMOST_END_BIT_COUNT_MASK, \ 392 .almost_end_bit_shift = REG_ALMOST_END_BIT_COUNT_SFT, \ 393 .out2latch_time_reg = ETDM_IN##_id##_CON9, \ 394 .out2latch_time_mask = REG_OUT2LATCH_TIME_MASK, \ 395 .out2latch_time_shift = REG_OUT2LATCH_TIME_SFT, \ 396 .tdm_mode_reg = ETDM_IN##_id##_CON0, \ 397 .tdm_mode_mask = REG_FMT_MASK, \ 398 .tdm_mode_shift = REG_FMT_SFT, \ 399 .relatch_domain_sel_reg = ETDM_IN##_id##_CON0, \ 400 .relatch_domain_sel_mask = REG_RELATCH_1X_EN_DOMAIN_SEL_MASK, \ 401 .relatch_domain_sel_shift = REG_RELATCH_1X_EN_DOMAIN_SEL_SFT, \ 402 .bit_length_reg = ETDM_IN##_id##_CON0, \ 403 .bit_length_mask = REG_BIT_LENGTH_MASK, \ 404 .bit_length_shift = REG_BIT_LENGTH_SFT, \ 405 .word_length_reg = ETDM_IN##_id##_CON0, \ 406 .word_length_mask = REG_WORD_LENGTH_MASK, \ 407 .word_length_shift = REG_WORD_LENGTH_SFT, \ 408 .cowork_reg = _cowork, \ 409 .cowork_mask = ETDM_IN##_id##_SLAVE_SEL_MASK, \ 410 .cowork_shift = ETDM_IN##_id##_SLAVE_SEL_SFT, \ 411 .cowork_val = ETDM_SLAVE_SEL_ETDMOUT##_id##_MASTER, \ 412 .pad_top_ck_en_reg = _cfg_vlp_reg, \ 413 .pad_top_ck_en_mask = RG_I2S4_PAD_TOP_CK_EN_MASK, \ 414 .pad_top_ck_en_shift = RG_I2S4_PAD_TOP_CK_EN_SFT, \ 415 .master_latch_reg = _cfg_vlp_reg, \ 416 .master_latch_mask = RG_I2S4_IN_BCK_NEG_EG_LATCH_MASK, \ 417 .master_latch_shift = RG_I2S4_IN_BCK_NEG_EG_LATCH_SFT, \ 418 } 419 420 /* 421 * _cfg_vlp_reg should be a variable or constant, not an expression 422 * with side effects. 423 */ 424 #define MTK_ETDM_OUT_DATA(_id, _cowork, _cfg_vlp_reg) \ 425 [DAI_I2SOUT##_id] = { \ 426 .enable_reg = ETDM_OUT##_id##_CON0, \ 427 .enable_mask = OUT_REG_ETDM_OUT_EN_MASK, \ 428 .enable_shift = OUT_REG_ETDM_OUT_EN_SFT, \ 429 .sync_reg = ETDM_OUT##_id##_CON0, \ 430 .sync_mask = REG_SYNC_MODE_MASK, \ 431 .sync_shift = REG_SYNC_MODE_SFT, \ 432 .ch_reg = ETDM_OUT##_id##_CON0, \ 433 .ch_mask = REG_CH_NUM_MASK, \ 434 .ch_shift = REG_CH_NUM_SFT, \ 435 .init_count_reg = ETDM_OUT##_id##_CON1, \ 436 .init_count_mask = OUT_REG_INITIAL_COUNT_MASK, \ 437 .init_count_shift = OUT_REG_INITIAL_COUNT_SFT, \ 438 .init_point_reg = ETDM_OUT##_id##_CON1, \ 439 .init_point_mask = OUT_REG_INITIAL_POINT_MASK, \ 440 .init_point_shift = OUT_REG_INITIAL_POINT_SFT, \ 441 .lrck_reset_reg = ETDM_OUT##_id##_CON1, \ 442 .lrck_reset_mask = OUT_REG_LRCK_RESET_MASK, \ 443 .lrck_reset_shift = OUT_REG_LRCK_RESET_SFT, \ 444 .clk_source_reg = ETDM_OUT##_id##_CON4, \ 445 .clk_source_mask = OUT_REG_CLOCK_SOURCE_SEL_MASK, \ 446 .clk_source_shift = OUT_REG_CLOCK_SOURCE_SEL_SFT, \ 447 .fs_timing_reg = ETDM_OUT##_id##_CON4, \ 448 .fs_timing_mask = OUT_REG_FS_TIMING_SEL_MASK, \ 449 .fs_timing_shift = OUT_REG_FS_TIMING_SEL_SFT, \ 450 .relatch_en_sel_reg = ETDM_OUT##_id##_CON4, \ 451 .relatch_en_sel_mask = OUT_REG_RELATCH_EN_SEL_MASK, \ 452 .relatch_en_sel_shift = OUT_REG_RELATCH_EN_SEL_SFT, \ 453 .tdm_mode_reg = ETDM_OUT##_id##_CON0, \ 454 .tdm_mode_mask = OUT_REG_FMT_MASK, \ 455 .tdm_mode_shift = OUT_REG_FMT_SFT, \ 456 .relatch_domain_sel_reg = ETDM_OUT##_id##_CON0, \ 457 .relatch_domain_sel_mask = OUT_REG_RELATCH_DOMAIN_SEL_MASK, \ 458 .relatch_domain_sel_shift = OUT_REG_RELATCH_DOMAIN_SEL_SFT, \ 459 .bit_length_reg = ETDM_OUT##_id##_CON0, \ 460 .bit_length_mask = OUT_REG_BIT_LENGTH_MASK, \ 461 .bit_length_shift = OUT_REG_BIT_LENGTH_SFT, \ 462 .word_length_reg = ETDM_OUT##_id##_CON0, \ 463 .word_length_mask = OUT_REG_WORD_LENGTH_MASK, \ 464 .word_length_shift = OUT_REG_WORD_LENGTH_SFT, \ 465 .cowork_reg = _cowork, \ 466 .cowork_mask = ETDM_OUT##_id##_SLAVE_SEL_MASK, \ 467 .cowork_shift = ETDM_OUT##_id##_SLAVE_SEL_SFT, \ 468 .cowork_val = ETDM_SLAVE_SEL_ETDMIN##_id##_MASTER, \ 469 .in2latch_time_reg = ETDM_OUT##_id##_CON2, \ 470 .in2latch_time_mask = OUT_REG_IN2LATCH_TIME_MASK, \ 471 .in2latch_time_shift = OUT_REG_IN2LATCH_TIME_SFT, \ 472 .pad_top_ck_en_reg = _cfg_vlp_reg, \ 473 .pad_top_ck_en_mask = RG_I2S4_PAD_TOP_CK_EN_MASK, \ 474 .pad_top_ck_en_shift = RG_I2S4_PAD_TOP_CK_EN_SFT, \ 475 .master_latch_reg = _cfg_vlp_reg, \ 476 .master_latch_mask = RG_I2S4_OUT_BCK_NEG_EG_LATCH_MASK, \ 477 .master_latch_shift = RG_I2S4_OUT_BCK_NEG_EG_LATCH_SFT, \ 478 } 479 480 static const struct mtk_base_etdm_data mtk_etdm_data[DAI_I2S_NUM] = { 481 MTK_ETDM_IN_DATA(0, ETDM_0_3_COWORK_CON0, 0), 482 MTK_ETDM_IN_DATA(1, ETDM_0_3_COWORK_CON1, 0), 483 MTK_ETDM_IN_DATA(2, ETDM_0_3_COWORK_CON2, 0), 484 MTK_ETDM_IN_DATA(3, ETDM_0_3_COWORK_CON3, 0), 485 MTK_ETDM_IN_DATA(4, ETDM_4_7_COWORK_CON0, AUD_TOP_CFG_VLP_RG), 486 MTK_ETDM_IN_DATA(6, ETDM_4_7_COWORK_CON2, 0), 487 488 MTK_ETDM_OUT_DATA(0, ETDM_0_3_COWORK_CON0, 0), 489 MTK_ETDM_OUT_DATA(1, ETDM_0_3_COWORK_CON0, 0), 490 MTK_ETDM_OUT_DATA(2, ETDM_0_3_COWORK_CON2, 0), 491 MTK_ETDM_OUT_DATA(3, ETDM_0_3_COWORK_CON2, 0), 492 MTK_ETDM_OUT_DATA(4, ETDM_4_7_COWORK_CON0, AUD_TOP_CFG_VLP_RG), 493 MTK_ETDM_OUT_DATA(6, ETDM_4_7_COWORK_CON2, 0), 494 }; 495 496 enum { 497 I2S_FMT_EIAJ, 498 I2S_FMT_I2S, 499 }; 500 501 enum { 502 I2S_WLEN_16_BIT, 503 I2S_WLEN_32_BIT, 504 }; 505 506 enum { 507 I2S_IN_PAD_CONNSYS, 508 I2S_IN_PAD_IO_MUX, 509 }; 510 511 static unsigned int get_i2s_wlen(snd_pcm_format_t format) 512 { 513 return snd_pcm_format_physical_width(format) <= 16 ? 514 I2S_WLEN_16_BIT : I2S_WLEN_32_BIT; 515 } 516 517 #define I2SIN0_MCLK_EN_W_NAME "I2SIN0_MCLK_EN" 518 #define I2SIN1_MCLK_EN_W_NAME "I2SIN1_MCLK_EN" 519 #define I2SIN2_MCLK_EN_W_NAME "I2SIN2_MCLK_EN" 520 #define I2SIN3_MCLK_EN_W_NAME "I2SIN3_MCLK_EN" 521 #define I2SIN4_MCLK_EN_W_NAME "I2SIN4_MCLK_EN" 522 #define I2SIN6_MCLK_EN_W_NAME "I2SIN6_MCLK_EN" 523 #define I2SOUT0_MCLK_EN_W_NAME "I2SOUT0_MCLK_EN" 524 #define I2SOUT1_MCLK_EN_W_NAME "I2SOUT1_MCLK_EN" 525 #define I2SOUT2_MCLK_EN_W_NAME "I2SOUT2_MCLK_EN" 526 #define I2SOUT3_MCLK_EN_W_NAME "I2SOUT3_MCLK_EN" 527 #define I2SOUT4_MCLK_EN_W_NAME "I2SOUT4_MCLK_EN" 528 #define I2SOUT6_MCLK_EN_W_NAME "I2SOUT6_MCLK_EN" 529 #define FMI2S_MASTER_MCLK_EN_W_NAME "FMI2S_MASTER_MCLK_EN" 530 531 static int get_i2s_id_by_name(struct mtk_base_afe *afe, 532 const char *name) 533 { 534 if (strncmp(name, "I2SIN0", 6) == 0) 535 return MT8196_DAI_I2S_IN0; 536 else if (strncmp(name, "I2SIN1", 6) == 0) 537 return MT8196_DAI_I2S_IN1; 538 else if (strncmp(name, "I2SIN2", 6) == 0) 539 return MT8196_DAI_I2S_IN2; 540 else if (strncmp(name, "I2SIN3", 6) == 0) 541 return MT8196_DAI_I2S_IN3; 542 else if (strncmp(name, "I2SIN4", 6) == 0) 543 return MT8196_DAI_I2S_IN4; 544 else if (strncmp(name, "I2SIN6", 6) == 0) 545 return MT8196_DAI_I2S_IN6; 546 else if (strncmp(name, "I2SOUT0", 7) == 0) 547 return MT8196_DAI_I2S_OUT0; 548 else if (strncmp(name, "I2SOUT1", 7) == 0) 549 return MT8196_DAI_I2S_OUT1; 550 else if (strncmp(name, "I2SOUT2", 7) == 0) 551 return MT8196_DAI_I2S_OUT2; 552 else if (strncmp(name, "I2SOUT3", 7) == 0) 553 return MT8196_DAI_I2S_OUT3; 554 else if (strncmp(name, "I2SOUT4", 7) == 0) 555 return MT8196_DAI_I2S_OUT4; 556 else if (strncmp(name, "I2SOUT6", 7) == 0) 557 return MT8196_DAI_I2S_OUT6; 558 else if (strncmp(name, "FMI2S_MASTER", 12) == 0) 559 return MT8196_DAI_FM_I2S_MASTER; 560 else 561 return -EINVAL; 562 } 563 564 static struct mtk_afe_i2s_priv *get_i2s_priv_by_name(struct mtk_base_afe *afe, 565 const char *name) 566 { 567 struct mt8196_afe_private *afe_priv = afe->platform_priv; 568 int dai_id = get_i2s_id_by_name(afe, name); 569 570 if (dai_id < 0) 571 return NULL; 572 573 return afe_priv->dai_priv[dai_id]; 574 } 575 576 static const char * const etdm_0_3_loopback_text[] = { 577 "etdmin0", "etdmin1", 578 "etdmin2", "etdmin3", 579 "etdmout0", "etdmout1", 580 "etdmout2", "etdmout3" 581 }; 582 583 static const char * const etdm_4_7_loopback_text[] = { 584 "etdmin4", "etdmin5", 585 "etdmin6", "etdmin7", 586 "etdmout4", "etdmout5", 587 "etdmout6", "etdmout7" 588 }; 589 590 static const u32 etdm_loopback_values[] = { 591 0, 2, 4, 6, 8, 10, 12, 14 592 }; 593 594 static const struct soc_enum i2sin0_loopback_enum = 595 SOC_VALUE_ENUM_SINGLE(ETDM_0_3_COWORK_CON1, ETDM_IN0_SDATA0_SEL_SFT, 596 ETDM_IN0_SDATA0_SEL_MASK, ARRAY_SIZE(etdm_0_3_loopback_text), 597 etdm_0_3_loopback_text, etdm_loopback_values); 598 599 static const struct soc_enum i2sin1_loopback_enum = 600 SOC_VALUE_ENUM_SINGLE(ETDM_0_3_COWORK_CON1, ETDM_IN1_SDATA0_SEL_SFT, 601 ETDM_IN1_SDATA0_SEL_MASK, ARRAY_SIZE(etdm_0_3_loopback_text), 602 etdm_0_3_loopback_text, etdm_loopback_values); 603 604 static const struct soc_enum i2sin2_loopback_enum = 605 SOC_VALUE_ENUM_SINGLE(ETDM_0_3_COWORK_CON3, ETDM_IN2_SDATA0_SEL_SFT, 606 ETDM_IN2_SDATA0_SEL_MASK, ARRAY_SIZE(etdm_0_3_loopback_text), 607 etdm_0_3_loopback_text, etdm_loopback_values); 608 609 static const struct soc_enum i2sin3_loopback_enum = 610 SOC_VALUE_ENUM_SINGLE(ETDM_0_3_COWORK_CON3, ETDM_IN3_SDATA0_SEL_SFT, 611 ETDM_IN3_SDATA0_SEL_MASK, ARRAY_SIZE(etdm_0_3_loopback_text), 612 etdm_0_3_loopback_text, etdm_loopback_values); 613 614 static const struct soc_enum i2sin4_loopback_enum = 615 SOC_VALUE_ENUM_SINGLE(ETDM_4_7_COWORK_CON1, ETDM_IN4_SDATA0_SEL_SFT, 616 ETDM_IN4_SDATA0_SEL_MASK, ARRAY_SIZE(etdm_4_7_loopback_text), 617 etdm_4_7_loopback_text, etdm_loopback_values); 618 619 static const struct soc_enum i2sin6_loopback_enum = 620 SOC_VALUE_ENUM_SINGLE(ETDM_4_7_COWORK_CON3, ETDM_IN6_SDATA0_SEL_SFT, 621 ETDM_IN6_SDATA0_SEL_MASK, ARRAY_SIZE(etdm_4_7_loopback_text), 622 etdm_4_7_loopback_text, etdm_loopback_values); 623 624 static const struct snd_kcontrol_new mtk_dai_i2s_controls[] = { 625 SOC_ENUM("I2SIN0 LOOPBACK", i2sin0_loopback_enum), 626 SOC_ENUM("I2SIN1 LOOPBACK", i2sin1_loopback_enum), 627 SOC_ENUM("I2SIN2 LOOPBACK", i2sin2_loopback_enum), 628 SOC_ENUM("I2SIN3 LOOPBACK", i2sin3_loopback_enum), 629 /* The following I2S does not support multi-ip mode */ 630 SOC_ENUM("I2SIN4 LOOPBACK", i2sin4_loopback_enum), 631 SOC_ENUM("I2SIN6 LOOPBACK", i2sin6_loopback_enum), 632 }; 633 634 /* interconnection */ 635 static const struct snd_kcontrol_new mtk_i2sout0_ch1_mix[] = { 636 SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN108_1, I_DL0_CH1, 1, 0), 637 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN108_1, I_DL1_CH1, 1, 0), 638 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN108_1, I_DL2_CH1, 1, 0), 639 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN108_1, I_DL3_CH1, 1, 0), 640 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN108_1, I_DL4_CH1, 1, 0), 641 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN108_1, I_DL5_CH1, 1, 0), 642 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN108_1, I_DL6_CH1, 1, 0), 643 SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN108_1, I_DL7_CH1, 1, 0), 644 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN108_1, I_DL8_CH1, 1, 0), 645 SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN108_1, I_DL_24CH_CH1, 1, 0), 646 SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH1", AFE_CONN108_2, I_DL23_CH1, 1, 0), 647 SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH1", AFE_CONN108_2, I_DL24_CH1, 1, 0), 648 SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN108_0, 649 I_GAIN0_OUT_CH1, 1, 0), 650 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN108_0, 651 I_ADDA_UL_CH1, 1, 0), 652 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN108_0, 653 I_ADDA_UL_CH2, 1, 0), 654 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN108_0, 655 I_ADDA_UL_CH3, 1, 0), 656 SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN108_4, 657 I_PCM_0_CAP_CH1, 1, 0), 658 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN108_4, 659 I_PCM_1_CAP_CH1, 1, 0), 660 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH1", AFE_CONN108_6, 661 I_SRC_2_OUT_CH1, 1, 0), 662 }; 663 664 static const struct snd_kcontrol_new mtk_i2sout0_ch2_mix[] = { 665 SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN109_1, I_DL0_CH2, 1, 0), 666 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN109_1, I_DL1_CH2, 1, 0), 667 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN109_1, I_DL2_CH2, 1, 0), 668 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN109_1, I_DL3_CH2, 1, 0), 669 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN109_1, I_DL4_CH2, 1, 0), 670 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN109_1, I_DL5_CH2, 1, 0), 671 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN109_1, I_DL6_CH2, 1, 0), 672 SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN109_1, I_DL7_CH2, 1, 0), 673 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN109_1, I_DL8_CH2, 1, 0), 674 SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN109_1, I_DL_24CH_CH2, 1, 0), 675 SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH2", AFE_CONN109_2, I_DL23_CH2, 1, 0), 676 SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH2", AFE_CONN109_2, I_DL24_CH2, 1, 0), 677 SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN109_0, 678 I_GAIN0_OUT_CH2, 1, 0), 679 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN109_0, 680 I_ADDA_UL_CH1, 1, 0), 681 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN109_0, 682 I_ADDA_UL_CH2, 1, 0), 683 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN109_0, 684 I_ADDA_UL_CH3, 1, 0), 685 SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN109_4, 686 I_PCM_0_CAP_CH1, 1, 0), 687 SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN109_4, 688 I_PCM_0_CAP_CH2, 1, 0), 689 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN109_4, 690 I_PCM_1_CAP_CH1, 1, 0), 691 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN109_4, 692 I_PCM_1_CAP_CH2, 1, 0), 693 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH2", AFE_CONN109_6, 694 I_SRC_2_OUT_CH2, 1, 0), 695 }; 696 697 static const struct snd_kcontrol_new mtk_i2sout1_ch1_mix[] = { 698 SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN110_1, I_DL0_CH1, 1, 0), 699 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN110_1, I_DL1_CH1, 1, 0), 700 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN110_1, I_DL2_CH1, 1, 0), 701 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN110_1, I_DL3_CH1, 1, 0), 702 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN110_1, I_DL4_CH1, 1, 0), 703 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN110_1, I_DL5_CH1, 1, 0), 704 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN110_1, I_DL6_CH1, 1, 0), 705 SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN110_1, I_DL7_CH1, 1, 0), 706 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN110_1, I_DL8_CH1, 1, 0), 707 SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN110_1, I_DL_24CH_CH1, 1, 0), 708 SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN110_0, 709 I_GAIN0_OUT_CH1, 1, 0), 710 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN110_0, 711 I_ADDA_UL_CH1, 1, 0), 712 SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN110_4, 713 I_PCM_0_CAP_CH1, 1, 0), 714 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN110_4, 715 I_PCM_1_CAP_CH1, 1, 0), 716 }; 717 718 static const struct snd_kcontrol_new mtk_i2sout1_ch2_mix[] = { 719 SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN111_1, I_DL0_CH2, 1, 0), 720 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN111_1, I_DL1_CH2, 1, 0), 721 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN111_1, I_DL2_CH2, 1, 0), 722 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN111_1, I_DL3_CH2, 1, 0), 723 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN111_1, I_DL4_CH2, 1, 0), 724 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN111_1, I_DL5_CH2, 1, 0), 725 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN111_1, I_DL6_CH2, 1, 0), 726 SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN111_1, I_DL7_CH2, 1, 0), 727 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN111_1, I_DL8_CH2, 1, 0), 728 SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN111_1, I_DL_24CH_CH2, 1, 0), 729 SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN111_0, 730 I_GAIN0_OUT_CH2, 1, 0), 731 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN111_0, 732 I_ADDA_UL_CH2, 1, 0), 733 SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN111_4, 734 I_PCM_0_CAP_CH1, 1, 0), 735 SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN111_4, 736 I_PCM_0_CAP_CH2, 1, 0), 737 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN111_4, 738 I_PCM_1_CAP_CH1, 1, 0), 739 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN111_4, 740 I_PCM_1_CAP_CH2, 1, 0), 741 }; 742 743 static const struct snd_kcontrol_new mtk_i2sout2_ch1_mix[] = { 744 SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN112_1, I_DL0_CH1, 1, 0), 745 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN112_1, I_DL1_CH1, 1, 0), 746 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN112_1, I_DL2_CH1, 1, 0), 747 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN112_1, I_DL3_CH1, 1, 0), 748 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN112_1, I_DL4_CH1, 1, 0), 749 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN112_1, I_DL5_CH1, 1, 0), 750 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN112_1, I_DL6_CH1, 1, 0), 751 SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN112_1, I_DL7_CH1, 1, 0), 752 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN112_1, I_DL8_CH1, 1, 0), 753 SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN112_1, I_DL_24CH_CH1, 1, 0), 754 SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN112_0, 755 I_GAIN0_OUT_CH1, 1, 0), 756 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN112_0, 757 I_ADDA_UL_CH1, 1, 0), 758 SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN112_4, 759 I_PCM_0_CAP_CH1, 1, 0), 760 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN112_4, 761 I_PCM_1_CAP_CH1, 1, 0), 762 }; 763 764 static const struct snd_kcontrol_new mtk_i2sout2_ch2_mix[] = { 765 SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN113_1, I_DL0_CH2, 1, 0), 766 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN113_1, I_DL1_CH2, 1, 0), 767 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN113_1, I_DL2_CH2, 1, 0), 768 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN113_1, I_DL3_CH2, 1, 0), 769 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN113_1, I_DL4_CH2, 1, 0), 770 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN113_1, I_DL5_CH2, 1, 0), 771 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN113_1, I_DL6_CH2, 1, 0), 772 SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN113_1, I_DL7_CH2, 1, 0), 773 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN113_1, I_DL8_CH2, 1, 0), 774 SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN113_1, I_DL_24CH_CH2, 1, 0), 775 SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN113_0, 776 I_GAIN0_OUT_CH2, 1, 0), 777 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN113_0, 778 I_ADDA_UL_CH2, 1, 0), 779 SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN113_4, 780 I_PCM_0_CAP_CH1, 1, 0), 781 SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN113_4, 782 I_PCM_0_CAP_CH2, 1, 0), 783 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN113_4, 784 I_PCM_1_CAP_CH1, 1, 0), 785 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN113_4, 786 I_PCM_1_CAP_CH2, 1, 0), 787 }; 788 789 static const struct snd_kcontrol_new mtk_i2sout3_ch1_mix[] = { 790 SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN114_1, I_DL0_CH1, 1, 0), 791 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN114_1, I_DL1_CH1, 1, 0), 792 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN114_1, I_DL2_CH1, 1, 0), 793 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN114_1, I_DL3_CH1, 1, 0), 794 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN114_1, I_DL4_CH1, 1, 0), 795 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN114_1, I_DL5_CH1, 1, 0), 796 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN114_1, I_DL6_CH1, 1, 0), 797 SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN114_1, I_DL7_CH1, 1, 0), 798 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN114_1, I_DL8_CH1, 1, 0), 799 SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN114_1, I_DL_24CH_CH1, 1, 0), 800 SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN114_0, 801 I_GAIN0_OUT_CH1, 1, 0), 802 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN114_0, 803 I_ADDA_UL_CH1, 1, 0), 804 SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN114_4, 805 I_PCM_0_CAP_CH1, 1, 0), 806 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN114_4, 807 I_PCM_1_CAP_CH1, 1, 0), 808 }; 809 810 static const struct snd_kcontrol_new mtk_i2sout3_ch2_mix[] = { 811 SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN115_1, I_DL0_CH2, 1, 0), 812 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN115_1, I_DL1_CH2, 1, 0), 813 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN115_1, I_DL2_CH2, 1, 0), 814 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN115_1, I_DL3_CH2, 1, 0), 815 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN115_1, I_DL4_CH2, 1, 0), 816 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN115_1, I_DL5_CH2, 1, 0), 817 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN115_1, I_DL6_CH2, 1, 0), 818 SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN115_1, I_DL7_CH2, 1, 0), 819 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN115_1, I_DL8_CH2, 1, 0), 820 SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN115_1, I_DL_24CH_CH2, 1, 0), 821 SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN115_0, 822 I_GAIN0_OUT_CH2, 1, 0), 823 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN115_0, 824 I_ADDA_UL_CH2, 1, 0), 825 SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN115_4, 826 I_PCM_0_CAP_CH2, 1, 0), 827 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN115_4, 828 I_PCM_1_CAP_CH2, 1, 0), 829 }; 830 831 static const struct snd_kcontrol_new mtk_i2sout4_ch1_mix[] = { 832 SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN116_1, I_DL0_CH1, 1, 0), 833 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN116_1, I_DL1_CH1, 1, 0), 834 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN116_1, I_DL2_CH1, 1, 0), 835 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN116_1, I_DL3_CH1, 1, 0), 836 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN116_1, I_DL4_CH1, 1, 0), 837 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN116_1, I_DL5_CH1, 1, 0), 838 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN116_1, I_DL6_CH1, 1, 0), 839 SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN116_1, I_DL7_CH1, 1, 0), 840 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN116_1, I_DL8_CH1, 1, 0), 841 SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN116_1, I_DL_24CH_CH1, 1, 0), 842 SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH1", AFE_CONN116_2, I_DL24_CH1, 1, 0), 843 SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN116_0, 844 I_GAIN0_OUT_CH1, 1, 0), 845 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN116_0, 846 I_ADDA_UL_CH1, 1, 0), 847 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN116_0, 848 I_ADDA_UL_CH2, 1, 0), 849 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN116_0, 850 I_ADDA_UL_CH3, 1, 0), 851 SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN116_4, 852 I_PCM_0_CAP_CH1, 1, 0), 853 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN116_4, 854 I_PCM_1_CAP_CH1, 1, 0), 855 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH1", AFE_CONN116_6, 856 I_SRC_2_OUT_CH1, 1, 0), 857 }; 858 859 static const struct snd_kcontrol_new mtk_i2sout4_ch2_mix[] = { 860 SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN117_1, I_DL0_CH2, 1, 0), 861 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN117_1, I_DL1_CH2, 1, 0), 862 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN117_1, I_DL2_CH2, 1, 0), 863 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN117_1, I_DL3_CH2, 1, 0), 864 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN117_1, I_DL4_CH2, 1, 0), 865 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN117_1, I_DL5_CH2, 1, 0), 866 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN117_1, I_DL6_CH2, 1, 0), 867 SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN117_1, I_DL7_CH2, 1, 0), 868 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN117_1, I_DL8_CH2, 1, 0), 869 SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN117_1, I_DL_24CH_CH2, 1, 0), 870 SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH2", AFE_CONN117_2, I_DL24_CH2, 1, 0), 871 SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN117_0, 872 I_GAIN0_OUT_CH2, 1, 0), 873 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN117_0, 874 I_ADDA_UL_CH1, 1, 0), 875 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN117_0, 876 I_ADDA_UL_CH2, 1, 0), 877 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN117_0, 878 I_ADDA_UL_CH3, 1, 0), 879 SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN117_4, 880 I_PCM_0_CAP_CH1, 1, 0), 881 SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN117_4, 882 I_PCM_0_CAP_CH2, 1, 0), 883 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN117_4, 884 I_PCM_1_CAP_CH1, 1, 0), 885 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN117_4, 886 I_PCM_1_CAP_CH2, 1, 0), 887 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH2", AFE_CONN117_6, 888 I_SRC_2_OUT_CH2, 1, 0), 889 }; 890 891 static const struct snd_kcontrol_new mtk_i2sout4_ch3_mix[] = { 892 SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH3", AFE_CONN118_1, I_DL_24CH_CH3, 1, 0), 893 SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN118_4, 894 I_PCM_0_CAP_CH1, 1, 0), 895 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN118_4, 896 I_PCM_1_CAP_CH1, 1, 0), 897 }; 898 899 static const struct snd_kcontrol_new mtk_i2sout4_ch4_mix[] = { 900 SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH4", AFE_CONN119_1, I_DL_24CH_CH4, 1, 0), 901 SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN118_4, 902 I_PCM_0_CAP_CH1, 1, 0), 903 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN118_4, 904 I_PCM_1_CAP_CH1, 1, 0), 905 }; 906 907 static const struct snd_kcontrol_new mtk_i2sout4_ch5_mix[] = { 908 SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH5", AFE_CONN120_1, I_DL_24CH_CH5, 1, 0), 909 }; 910 911 static const struct snd_kcontrol_new mtk_i2sout4_ch6_mix[] = { 912 SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH6", AFE_CONN121_1, I_DL_24CH_CH6, 1, 0), 913 }; 914 915 static const struct snd_kcontrol_new mtk_i2sout4_ch7_mix[] = { 916 SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH7", AFE_CONN122_1, I_DL_24CH_CH7, 1, 0), 917 }; 918 919 static const struct snd_kcontrol_new mtk_i2sout4_ch8_mix[] = { 920 SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH8", AFE_CONN123_1, I_DL_24CH_CH8, 1, 0), 921 }; 922 923 static const struct snd_kcontrol_new mtk_i2sout6_ch1_mix[] = { 924 SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN148_1, I_DL0_CH1, 1, 0), 925 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN148_1, I_DL1_CH1, 1, 0), 926 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN148_1, I_DL2_CH1, 1, 0), 927 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN148_1, I_DL3_CH1, 1, 0), 928 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN148_1, I_DL4_CH1, 1, 0), 929 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN148_1, I_DL5_CH1, 1, 0), 930 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN148_1, I_DL6_CH1, 1, 0), 931 SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN148_1, I_DL7_CH1, 1, 0), 932 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN148_1, I_DL8_CH1, 1, 0), 933 SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH1", AFE_CONN148_2, I_DL23_CH1, 1, 0), 934 SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN148_1, I_DL_24CH_CH1, 1, 0), 935 SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN148_0, 936 I_GAIN0_OUT_CH1, 1, 0), 937 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN148_0, 938 I_ADDA_UL_CH1, 1, 0), 939 SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN148_4, 940 I_PCM_0_CAP_CH1, 1, 0), 941 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN148_4, 942 I_PCM_1_CAP_CH1, 1, 0), 943 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH1", AFE_CONN148_6, 944 I_SRC_1_OUT_CH1, 1, 0), 945 }; 946 947 static const struct snd_kcontrol_new mtk_i2sout6_ch2_mix[] = { 948 SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN149_1, I_DL0_CH2, 1, 0), 949 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN149_1, I_DL1_CH2, 1, 0), 950 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN149_1, I_DL2_CH2, 1, 0), 951 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN149_1, I_DL3_CH2, 1, 0), 952 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN149_1, I_DL4_CH2, 1, 0), 953 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN149_1, I_DL5_CH2, 1, 0), 954 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN149_1, I_DL6_CH2, 1, 0), 955 SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN149_1, I_DL7_CH2, 1, 0), 956 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN149_1, I_DL8_CH2, 1, 0), 957 SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH2", AFE_CONN149_2, I_DL23_CH2, 1, 0), 958 SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN149_1, I_DL_24CH_CH2, 1, 0), 959 SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN149_0, 960 I_GAIN0_OUT_CH2, 1, 0), 961 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN149_0, 962 I_ADDA_UL_CH2, 1, 0), 963 SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN149_4, 964 I_PCM_0_CAP_CH1, 1, 0), 965 SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN149_4, 966 I_PCM_0_CAP_CH2, 1, 0), 967 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN149_4, 968 I_PCM_1_CAP_CH1, 1, 0), 969 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN149_4, 970 I_PCM_1_CAP_CH2, 1, 0), 971 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH2", AFE_CONN148_6, 972 I_SRC_1_OUT_CH2, 1, 0), 973 }; 974 975 enum { 976 SUPPLY_SEQ_APLL, 977 SUPPLY_SEQ_I2S_MCLK_EN, 978 SUPPLY_SEQ_I2S_CG_EN, 979 SUPPLY_SEQ_I2S_EN, 980 }; 981 982 static int mtk_apll_event(struct snd_soc_dapm_widget *w, 983 struct snd_kcontrol *kcontrol, 984 int event) 985 { 986 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 987 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 988 989 dev_dbg(cmpnt->dev, "name %s, event 0x%x\n", w->name, event); 990 991 switch (event) { 992 case SND_SOC_DAPM_PRE_PMU: 993 if (strcmp(w->name, APLL1_W_NAME) == 0) 994 mt8196_apll1_enable(afe); 995 else 996 mt8196_apll2_enable(afe); 997 break; 998 case SND_SOC_DAPM_POST_PMD: 999 if (strcmp(w->name, APLL1_W_NAME) == 0) 1000 mt8196_apll1_disable(afe); 1001 else 1002 mt8196_apll2_disable(afe); 1003 break; 1004 default: 1005 break; 1006 } 1007 1008 return 0; 1009 } 1010 1011 static int mtk_mclk_en_event(struct snd_soc_dapm_widget *w, 1012 struct snd_kcontrol *kcontrol, 1013 int event) 1014 { 1015 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1016 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 1017 struct mtk_afe_i2s_priv *i2s_priv; 1018 1019 dev_dbg(cmpnt->dev, "name %s, event 0x%x\n", w->name, event); 1020 1021 i2s_priv = get_i2s_priv_by_name(afe, w->name); 1022 1023 if (!i2s_priv) 1024 return -EINVAL; 1025 1026 switch (event) { 1027 case SND_SOC_DAPM_PRE_PMU: 1028 mt8196_mck_enable(afe, i2s_priv->mclk_id, i2s_priv->mclk_rate); 1029 break; 1030 case SND_SOC_DAPM_POST_PMD: 1031 i2s_priv->mclk_rate = 0; 1032 mt8196_mck_disable(afe, i2s_priv->mclk_id); 1033 break; 1034 default: 1035 break; 1036 } 1037 1038 return 0; 1039 } 1040 1041 static const struct snd_soc_dapm_widget mtk_dai_i2s_widgets[] = { 1042 SND_SOC_DAPM_MIXER("I2SOUT0_CH1", SND_SOC_NOPM, 0, 0, 1043 mtk_i2sout0_ch1_mix, 1044 ARRAY_SIZE(mtk_i2sout0_ch1_mix)), 1045 SND_SOC_DAPM_MIXER("I2SOUT0_CH2", SND_SOC_NOPM, 0, 0, 1046 mtk_i2sout0_ch2_mix, 1047 ARRAY_SIZE(mtk_i2sout0_ch2_mix)), 1048 1049 SND_SOC_DAPM_MIXER("I2SOUT1_CH1", SND_SOC_NOPM, 0, 0, 1050 mtk_i2sout1_ch1_mix, 1051 ARRAY_SIZE(mtk_i2sout1_ch1_mix)), 1052 SND_SOC_DAPM_MIXER("I2SOUT1_CH2", SND_SOC_NOPM, 0, 0, 1053 mtk_i2sout1_ch2_mix, 1054 ARRAY_SIZE(mtk_i2sout1_ch2_mix)), 1055 1056 SND_SOC_DAPM_MIXER("I2SOUT2_CH1", SND_SOC_NOPM, 0, 0, 1057 mtk_i2sout2_ch1_mix, 1058 ARRAY_SIZE(mtk_i2sout2_ch1_mix)), 1059 SND_SOC_DAPM_MIXER("I2SOUT2_CH2", SND_SOC_NOPM, 0, 0, 1060 mtk_i2sout2_ch2_mix, 1061 ARRAY_SIZE(mtk_i2sout2_ch2_mix)), 1062 1063 SND_SOC_DAPM_MIXER("I2SOUT3_CH1", SND_SOC_NOPM, 0, 0, 1064 mtk_i2sout3_ch1_mix, 1065 ARRAY_SIZE(mtk_i2sout3_ch1_mix)), 1066 SND_SOC_DAPM_MIXER("I2SOUT3_CH2", SND_SOC_NOPM, 0, 0, 1067 mtk_i2sout3_ch2_mix, 1068 ARRAY_SIZE(mtk_i2sout3_ch2_mix)), 1069 1070 SND_SOC_DAPM_MIXER("I2SOUT4_CH1", SND_SOC_NOPM, 0, 0, 1071 mtk_i2sout4_ch1_mix, 1072 ARRAY_SIZE(mtk_i2sout4_ch1_mix)), 1073 SND_SOC_DAPM_MIXER("I2SOUT4_CH2", SND_SOC_NOPM, 0, 0, 1074 mtk_i2sout4_ch2_mix, 1075 ARRAY_SIZE(mtk_i2sout4_ch2_mix)), 1076 SND_SOC_DAPM_MIXER("I2SOUT4_CH3", SND_SOC_NOPM, 0, 0, 1077 mtk_i2sout4_ch3_mix, 1078 ARRAY_SIZE(mtk_i2sout4_ch3_mix)), 1079 SND_SOC_DAPM_MIXER("I2SOUT4_CH4", SND_SOC_NOPM, 0, 0, 1080 mtk_i2sout4_ch4_mix, 1081 ARRAY_SIZE(mtk_i2sout4_ch4_mix)), 1082 SND_SOC_DAPM_MIXER("I2SOUT4_CH5", SND_SOC_NOPM, 0, 0, 1083 mtk_i2sout4_ch5_mix, 1084 ARRAY_SIZE(mtk_i2sout4_ch5_mix)), 1085 SND_SOC_DAPM_MIXER("I2SOUT4_CH6", SND_SOC_NOPM, 0, 0, 1086 mtk_i2sout4_ch6_mix, 1087 ARRAY_SIZE(mtk_i2sout4_ch6_mix)), 1088 SND_SOC_DAPM_MIXER("I2SOUT4_CH7", SND_SOC_NOPM, 0, 0, 1089 mtk_i2sout4_ch7_mix, 1090 ARRAY_SIZE(mtk_i2sout4_ch7_mix)), 1091 SND_SOC_DAPM_MIXER("I2SOUT4_CH8", SND_SOC_NOPM, 0, 0, 1092 mtk_i2sout4_ch8_mix, 1093 ARRAY_SIZE(mtk_i2sout4_ch8_mix)), 1094 1095 SND_SOC_DAPM_MIXER("I2SOUT6_CH1", SND_SOC_NOPM, 0, 0, 1096 mtk_i2sout6_ch1_mix, 1097 ARRAY_SIZE(mtk_i2sout6_ch1_mix)), 1098 SND_SOC_DAPM_MIXER("I2SOUT6_CH2", SND_SOC_NOPM, 0, 0, 1099 mtk_i2sout6_ch2_mix, 1100 ARRAY_SIZE(mtk_i2sout6_ch2_mix)), 1101 1102 /* i2s en*/ 1103 SND_SOC_DAPM_SUPPLY_S("I2SIN0_EN", SUPPLY_SEQ_I2S_EN, 1104 ETDM_IN0_CON0, REG_ETDM_IN_EN_SFT, 0, 1105 NULL, 0), 1106 SND_SOC_DAPM_SUPPLY_S("I2SIN1_EN", SUPPLY_SEQ_I2S_EN, 1107 ETDM_IN1_CON0, REG_ETDM_IN_EN_SFT, 0, 1108 NULL, 0), 1109 SND_SOC_DAPM_SUPPLY_S("I2SIN2_EN", SUPPLY_SEQ_I2S_EN, 1110 ETDM_IN2_CON0, REG_ETDM_IN_EN_SFT, 0, 1111 NULL, 0), 1112 SND_SOC_DAPM_SUPPLY_S("I2SIN3_EN", SUPPLY_SEQ_I2S_EN, 1113 ETDM_IN3_CON0, REG_ETDM_IN_EN_SFT, 0, 1114 NULL, 0), 1115 SND_SOC_DAPM_SUPPLY_S("I2SIN4_EN", SUPPLY_SEQ_I2S_EN, 1116 ETDM_IN4_CON0, REG_ETDM_IN_EN_SFT, 0, 1117 NULL, 0), 1118 SND_SOC_DAPM_SUPPLY_S("I2SIN6_EN", SUPPLY_SEQ_I2S_EN, 1119 ETDM_IN6_CON0, REG_ETDM_IN_EN_SFT, 0, 1120 NULL, 0), 1121 SND_SOC_DAPM_SUPPLY_S("I2SOUT0_EN", SUPPLY_SEQ_I2S_EN, 1122 ETDM_OUT0_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0, 1123 NULL, 0), 1124 SND_SOC_DAPM_SUPPLY_S("I2SOUT1_EN", SUPPLY_SEQ_I2S_EN, 1125 ETDM_OUT1_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0, 1126 NULL, 0), 1127 SND_SOC_DAPM_SUPPLY_S("I2SOUT2_EN", SUPPLY_SEQ_I2S_EN, 1128 ETDM_OUT2_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0, 1129 NULL, 0), 1130 SND_SOC_DAPM_SUPPLY_S("I2SOUT3_EN", SUPPLY_SEQ_I2S_EN, 1131 ETDM_OUT3_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0, 1132 NULL, 0), 1133 SND_SOC_DAPM_SUPPLY_S("I2SOUT4_EN", SUPPLY_SEQ_I2S_EN, 1134 ETDM_OUT4_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0, 1135 NULL, 0), 1136 SND_SOC_DAPM_SUPPLY_S("I2SOUT6_EN", SUPPLY_SEQ_I2S_EN, 1137 ETDM_OUT6_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0, 1138 NULL, 0), 1139 SND_SOC_DAPM_SUPPLY_S("FMI2S_MASTER_EN", SUPPLY_SEQ_I2S_EN, 1140 AFE_CONNSYS_I2S_CON, I2S_EN_SFT, 0, 1141 NULL, 0), 1142 1143 /* i2s mclk en */ 1144 SND_SOC_DAPM_SUPPLY_S(I2SIN0_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 1145 SND_SOC_NOPM, 0, 0, 1146 mtk_mclk_en_event, 1147 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1148 SND_SOC_DAPM_SUPPLY_S(I2SIN1_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 1149 SND_SOC_NOPM, 0, 0, 1150 mtk_mclk_en_event, 1151 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1152 SND_SOC_DAPM_SUPPLY_S(I2SIN2_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 1153 SND_SOC_NOPM, 0, 0, 1154 mtk_mclk_en_event, 1155 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1156 SND_SOC_DAPM_SUPPLY_S(I2SIN3_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 1157 SND_SOC_NOPM, 0, 0, 1158 mtk_mclk_en_event, 1159 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1160 SND_SOC_DAPM_SUPPLY_S(I2SIN4_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 1161 SND_SOC_NOPM, 0, 0, 1162 mtk_mclk_en_event, 1163 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1164 SND_SOC_DAPM_SUPPLY_S(I2SIN6_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 1165 SND_SOC_NOPM, 0, 0, 1166 mtk_mclk_en_event, 1167 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1168 SND_SOC_DAPM_SUPPLY_S(I2SOUT0_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 1169 SND_SOC_NOPM, 0, 0, 1170 mtk_mclk_en_event, 1171 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1172 SND_SOC_DAPM_SUPPLY_S(I2SOUT1_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 1173 SND_SOC_NOPM, 0, 0, 1174 mtk_mclk_en_event, 1175 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1176 SND_SOC_DAPM_SUPPLY_S(I2SOUT2_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 1177 SND_SOC_NOPM, 0, 0, 1178 mtk_mclk_en_event, 1179 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1180 SND_SOC_DAPM_SUPPLY_S(I2SOUT3_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 1181 SND_SOC_NOPM, 0, 0, 1182 mtk_mclk_en_event, 1183 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1184 SND_SOC_DAPM_SUPPLY_S(I2SOUT4_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 1185 SND_SOC_NOPM, 0, 0, 1186 mtk_mclk_en_event, 1187 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1188 SND_SOC_DAPM_SUPPLY_S(I2SOUT6_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 1189 SND_SOC_NOPM, 0, 0, 1190 mtk_mclk_en_event, 1191 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1192 SND_SOC_DAPM_SUPPLY_S(FMI2S_MASTER_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 1193 SND_SOC_NOPM, 0, 0, 1194 mtk_mclk_en_event, 1195 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1196 1197 /* cg */ 1198 SND_SOC_DAPM_SUPPLY_S("I2SOUT0_CG", SUPPLY_SEQ_I2S_CG_EN, 1199 AUDIO_TOP_CON2, PDN_ETDM_OUT0_SFT, 1, 1200 NULL, 0), 1201 SND_SOC_DAPM_SUPPLY_S("I2SOUT1_CG", SUPPLY_SEQ_I2S_CG_EN, 1202 AUDIO_TOP_CON2, PDN_ETDM_OUT1_SFT, 1, 1203 NULL, 0), 1204 SND_SOC_DAPM_SUPPLY_S("I2SOUT2_CG", SUPPLY_SEQ_I2S_CG_EN, 1205 AUDIO_TOP_CON2, PDN_ETDM_OUT2_SFT, 1, 1206 NULL, 0), 1207 SND_SOC_DAPM_SUPPLY_S("I2SOUT3_CG", SUPPLY_SEQ_I2S_CG_EN, 1208 AUDIO_TOP_CON2, PDN_ETDM_OUT3_SFT, 1, 1209 NULL, 0), 1210 SND_SOC_DAPM_SUPPLY_S("I2SOUT4_CG", SUPPLY_SEQ_I2S_CG_EN, 1211 AUDIO_TOP_CON2, PDN_ETDM_OUT4_SFT, 1, 1212 NULL, 0), 1213 SND_SOC_DAPM_SUPPLY_S("I2SOUT6_CG", SUPPLY_SEQ_I2S_CG_EN, 1214 AUDIO_TOP_CON2, PDN_ETDM_OUT6_SFT, 1, 1215 NULL, 0), 1216 SND_SOC_DAPM_SUPPLY_S("I2SIN0_CG", SUPPLY_SEQ_I2S_CG_EN, 1217 AUDIO_TOP_CON2, PDN_ETDM_IN0_SFT, 1, 1218 NULL, 0), 1219 SND_SOC_DAPM_SUPPLY_S("I2SIN1_CG", SUPPLY_SEQ_I2S_CG_EN, 1220 AUDIO_TOP_CON2, PDN_ETDM_IN1_SFT, 1, 1221 NULL, 0), 1222 SND_SOC_DAPM_SUPPLY_S("I2SIN2_CG", SUPPLY_SEQ_I2S_CG_EN, 1223 AUDIO_TOP_CON2, PDN_ETDM_IN2_SFT, 1, 1224 NULL, 0), 1225 SND_SOC_DAPM_SUPPLY_S("I2SIN3_CG", SUPPLY_SEQ_I2S_CG_EN, 1226 AUDIO_TOP_CON2, PDN_ETDM_IN3_SFT, 1, 1227 NULL, 0), 1228 SND_SOC_DAPM_SUPPLY_S("I2SIN4_CG", SUPPLY_SEQ_I2S_CG_EN, 1229 AUDIO_TOP_CON2, PDN_ETDM_IN4_SFT, 1, 1230 NULL, 0), 1231 SND_SOC_DAPM_SUPPLY_S("I2SIN6_CG", SUPPLY_SEQ_I2S_CG_EN, 1232 AUDIO_TOP_CON2, PDN_ETDM_IN6_SFT, 1, 1233 NULL, 0), 1234 SND_SOC_DAPM_SUPPLY_S("FMI2S_MASTER_CG", SUPPLY_SEQ_I2S_CG_EN, 1235 AUDIO_TOP_CON0, PDN_FM_I2S_SFT, 1, 1236 NULL, 0), 1237 1238 /* apll */ 1239 SND_SOC_DAPM_SUPPLY_S(APLL1_W_NAME, SUPPLY_SEQ_APLL, 1240 SND_SOC_NOPM, 0, 0, 1241 mtk_apll_event, 1242 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1243 SND_SOC_DAPM_SUPPLY_S(APLL2_W_NAME, SUPPLY_SEQ_APLL, 1244 SND_SOC_NOPM, 0, 0, 1245 mtk_apll_event, 1246 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1247 1248 SND_SOC_DAPM_MIXER("SOF_DMA_DL_24CH", SND_SOC_NOPM, 0, 0, NULL, 0), 1249 SND_SOC_DAPM_MIXER("SOF_DMA_DL1", SND_SOC_NOPM, 0, 0, NULL, 0), 1250 }; 1251 1252 static int mtk_afe_i2s_share_connect(struct snd_soc_dapm_widget *source, 1253 struct snd_soc_dapm_widget *sink) 1254 { 1255 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(sink->dapm); 1256 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 1257 struct mtk_afe_i2s_priv *i2s_priv; 1258 1259 i2s_priv = get_i2s_priv_by_name(afe, sink->name); 1260 if (!i2s_priv) 1261 return 0; 1262 1263 if (i2s_priv->share_i2s_id < 0) 1264 return 0; 1265 1266 return i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name); 1267 } 1268 1269 static int mtk_afe_i2s_apll_connect(struct snd_soc_dapm_widget *source, 1270 struct snd_soc_dapm_widget *sink) 1271 { 1272 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(sink->dapm); 1273 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 1274 struct mtk_afe_i2s_priv *i2s_priv; 1275 int cur_apll; 1276 int needed_apll; 1277 1278 i2s_priv = get_i2s_priv_by_name(afe, sink->name); 1279 if (!i2s_priv) 1280 return 0; 1281 1282 /* which apll */ 1283 cur_apll = mt8196_get_apll_by_name(afe, source->name); 1284 1285 /* choose APLL from i2s rate */ 1286 needed_apll = mt8196_get_apll_by_rate(afe, i2s_priv->rate); 1287 1288 return needed_apll == cur_apll; 1289 } 1290 1291 static int mtk_afe_i2s_mclk_connect(struct snd_soc_dapm_widget *source, 1292 struct snd_soc_dapm_widget *sink) 1293 { 1294 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(sink->dapm); 1295 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 1296 struct mtk_afe_i2s_priv *i2s_priv; 1297 int i2s_num; 1298 1299 i2s_priv = get_i2s_priv_by_name(afe, sink->name); 1300 if (!i2s_priv) 1301 return 0; 1302 1303 i2s_num = get_i2s_id_by_name(afe, source->name); 1304 if (get_i2s_id_by_name(afe, sink->name) == i2s_num) 1305 return i2s_priv->mclk_rate > 0; 1306 1307 /* check if share i2s need mclk */ 1308 if (i2s_priv->share_i2s_id < 0) 1309 return 0; 1310 1311 if (i2s_priv->share_i2s_id == i2s_num) 1312 return i2s_priv->mclk_rate > 0; 1313 1314 return 0; 1315 } 1316 1317 static int mtk_afe_mclk_apll_connect(struct snd_soc_dapm_widget *source, 1318 struct snd_soc_dapm_widget *sink) 1319 { 1320 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(sink->dapm); 1321 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 1322 struct mtk_afe_i2s_priv *i2s_priv; 1323 int cur_apll; 1324 1325 i2s_priv = get_i2s_priv_by_name(afe, sink->name); 1326 if (!i2s_priv) 1327 return 0; 1328 1329 /* which apll */ 1330 cur_apll = mt8196_get_apll_by_name(afe, source->name); 1331 1332 return i2s_priv->mclk_apll == cur_apll; 1333 } 1334 1335 static const struct snd_soc_dapm_route mtk_dai_i2s_routes[] = { 1336 /* i2sin0 */ 1337 {"I2SIN0", NULL, "I2SIN0_EN"}, 1338 {"I2SIN0", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, 1339 {"I2SIN0", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, 1340 {"I2SIN0", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, 1341 {"I2SIN0", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, 1342 {"I2SIN0", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, 1343 {"I2SIN0", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, 1344 {"I2SIN0", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, 1345 {"I2SIN0", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, 1346 {"I2SIN0", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, 1347 {"I2SIN0", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, 1348 {"I2SIN0", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, 1349 {"I2SIN0", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, 1350 1351 {"I2SIN0", NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1352 {"I2SIN0", NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1353 1354 {"I2SIN0", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1355 {"I2SIN0", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1356 {"I2SIN0", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1357 {"I2SIN0", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1358 {"I2SIN0", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1359 {"I2SIN0", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1360 {"I2SIN0", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1361 {"I2SIN0", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1362 {"I2SIN0", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1363 {"I2SIN0", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1364 {"I2SIN0", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1365 {"I2SIN0", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1366 {"I2SIN0", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1367 1368 {I2SIN0_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1369 {I2SIN0_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1370 {"I2SIN0", NULL, "I2SIN0_CG"}, 1371 1372 /* i2sin1 */ 1373 {"I2SIN1", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, 1374 {"I2SIN1", NULL, "I2SIN1_EN"}, 1375 {"I2SIN1", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, 1376 {"I2SIN1", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, 1377 {"I2SIN1", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, 1378 {"I2SIN1", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, 1379 {"I2SIN1", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, 1380 {"I2SIN1", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, 1381 {"I2SIN1", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, 1382 {"I2SIN1", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, 1383 {"I2SIN1", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, 1384 {"I2SIN1", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, 1385 {"I2SIN1", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, 1386 1387 {"I2SIN1", NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1388 {"I2SIN1", NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1389 1390 {"I2SIN1", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1391 {"I2SIN1", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1392 {"I2SIN1", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1393 {"I2SIN1", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1394 {"I2SIN1", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1395 {"I2SIN1", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1396 {"I2SIN1", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1397 {"I2SIN1", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1398 {"I2SIN1", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1399 {"I2SIN1", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1400 {"I2SIN1", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1401 {"I2SIN1", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1402 {"I2SIN1", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1403 {I2SIN1_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1404 {I2SIN1_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1405 {"I2SIN1", NULL, "I2SIN1_CG"}, 1406 1407 /* i2sin2 */ 1408 {"I2SIN2", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, 1409 {"I2SIN2", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, 1410 {"I2SIN2", NULL, "I2SIN2_EN"}, 1411 {"I2SIN2", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, 1412 {"I2SIN2", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, 1413 {"I2SIN2", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, 1414 {"I2SIN2", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, 1415 {"I2SIN2", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, 1416 {"I2SIN2", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, 1417 {"I2SIN2", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, 1418 {"I2SIN2", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, 1419 {"I2SIN2", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, 1420 {"I2SIN2", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, 1421 1422 {"I2SIN2", NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1423 {"I2SIN2", NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1424 1425 {"I2SIN2", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1426 {"I2SIN2", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1427 {"I2SIN2", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1428 {"I2SIN2", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1429 {"I2SIN2", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1430 {"I2SIN2", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1431 {"I2SIN2", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1432 {"I2SIN2", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1433 {"I2SIN2", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1434 {"I2SIN2", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1435 {"I2SIN2", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1436 {"I2SIN2", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1437 {"I2SIN2", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1438 {I2SIN2_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1439 {I2SIN2_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1440 {"I2SIN2", NULL, "I2SIN2_CG"}, 1441 1442 /* i2sin3 */ 1443 {"I2SIN3", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, 1444 {"I2SIN3", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, 1445 {"I2SIN3", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, 1446 {"I2SIN3", NULL, "I2SIN3_EN"}, 1447 {"I2SIN3", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, 1448 {"I2SIN3", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, 1449 {"I2SIN3", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, 1450 {"I2SIN3", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, 1451 {"I2SIN3", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, 1452 {"I2SIN3", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, 1453 {"I2SIN3", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, 1454 {"I2SIN3", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, 1455 {"I2SIN3", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, 1456 1457 {"I2SIN3", NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1458 {"I2SIN3", NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1459 1460 {"I2SIN3", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1461 {"I2SIN3", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1462 {"I2SIN3", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1463 {"I2SIN3", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1464 {"I2SIN3", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1465 {"I2SIN3", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1466 {"I2SIN3", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1467 {"I2SIN3", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1468 {"I2SIN3", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1469 {"I2SIN3", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1470 {"I2SIN3", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1471 {"I2SIN3", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1472 {"I2SIN3", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1473 {I2SIN3_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1474 {I2SIN3_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1475 {"I2SIN3", NULL, "I2SIN3_CG"}, 1476 1477 /* i2sin4 */ 1478 {"I2SIN4", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, 1479 {"I2SIN4", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, 1480 {"I2SIN4", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, 1481 {"I2SIN4", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, 1482 {"I2SIN4", NULL, "I2SIN4_EN"}, 1483 {"I2SIN4", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, 1484 {"I2SIN4", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, 1485 {"I2SIN4", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, 1486 {"I2SIN4", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, 1487 {"I2SIN4", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, 1488 {"I2SIN4", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, 1489 {"I2SIN4", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, 1490 {"I2SIN4", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, 1491 1492 {"I2SIN4", NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1493 {"I2SIN4", NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1494 1495 {"I2SIN4", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1496 {"I2SIN4", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1497 {"I2SIN4", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1498 {"I2SIN4", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1499 {"I2SIN4", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1500 {"I2SIN4", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1501 {"I2SIN4", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1502 {"I2SIN4", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1503 {"I2SIN4", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1504 {"I2SIN4", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1505 {"I2SIN4", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1506 {"I2SIN4", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1507 {"I2SIN4", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1508 {I2SIN4_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1509 {I2SIN4_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1510 {"I2SIN4", NULL, "I2SIN4_CG"}, 1511 1512 /* i2sin6 */ 1513 {"I2SIN6", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, 1514 {"I2SIN6", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, 1515 {"I2SIN6", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, 1516 {"I2SIN6", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, 1517 {"I2SIN6", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, 1518 {"I2SIN6", NULL, "I2SIN6_EN"}, 1519 {"I2SIN6", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, 1520 {"I2SIN6", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, 1521 {"I2SIN6", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, 1522 {"I2SIN6", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, 1523 {"I2SIN6", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, 1524 {"I2SIN6", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, 1525 {"I2SIN6", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, 1526 1527 {"I2SIN6", NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1528 {"I2SIN6", NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1529 1530 {"I2SIN6", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1531 {"I2SIN6", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1532 {"I2SIN6", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1533 {"I2SIN6", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1534 {"I2SIN6", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1535 {"I2SIN6", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1536 {"I2SIN6", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1537 {"I2SIN6", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1538 {"I2SIN6", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1539 {"I2SIN6", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1540 {"I2SIN6", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1541 {"I2SIN6", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1542 {"I2SIN6", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1543 {I2SIN6_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1544 {I2SIN6_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1545 {"I2SIN6", NULL, "I2SIN6_CG"}, 1546 {"I2SIN6", NULL, "I2SOUT6_CG"}, 1547 1548 /* i2sout0 */ 1549 {"I2SOUT0_CH1", "DL0_CH1", "DL0"}, 1550 {"I2SOUT0_CH2", "DL0_CH2", "DL0"}, 1551 {"I2SOUT0_CH1", "DL1_CH1", "DL1"}, 1552 {"I2SOUT0_CH2", "DL1_CH2", "DL1"}, 1553 {"I2SOUT0_CH1", "DL2_CH1", "DL2"}, 1554 {"I2SOUT0_CH2", "DL2_CH2", "DL2"}, 1555 {"I2SOUT0_CH1", "DL3_CH1", "DL3"}, 1556 {"I2SOUT0_CH2", "DL3_CH2", "DL3"}, 1557 {"I2SOUT0_CH1", "DL4_CH1", "DL4"}, 1558 {"I2SOUT0_CH2", "DL4_CH2", "DL4"}, 1559 {"I2SOUT0_CH1", "DL5_CH1", "DL5"}, 1560 {"I2SOUT0_CH2", "DL5_CH2", "DL5"}, 1561 {"I2SOUT0_CH1", "DL6_CH1", "DL6"}, 1562 {"I2SOUT0_CH2", "DL6_CH2", "DL6"}, 1563 {"I2SOUT0_CH1", "DL7_CH1", "DL7"}, 1564 {"I2SOUT0_CH2", "DL7_CH2", "DL7"}, 1565 {"I2SOUT0_CH1", "DL8_CH1", "DL8"}, 1566 {"I2SOUT0_CH2", "DL8_CH2", "DL8"}, 1567 {"I2SOUT0_CH1", "DL23_CH1", "DL23"}, 1568 {"I2SOUT0_CH2", "DL23_CH2", "DL23"}, 1569 {"I2SOUT0_CH1", "DL_24CH_CH1", "DL_24CH"}, 1570 {"I2SOUT0_CH2", "DL_24CH_CH2", "DL_24CH"}, 1571 1572 {"I2SOUT0_CH1", "DL24_CH1", "DL24"}, 1573 {"I2SOUT0_CH2", "DL24_CH2", "DL24"}, 1574 1575 {"I2SOUT0", NULL, "I2SOUT0_CH1"}, 1576 {"I2SOUT0", NULL, "I2SOUT0_CH2"}, 1577 1578 {"I2SOUT0", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, 1579 {"I2SOUT0", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, 1580 {"I2SOUT0", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, 1581 {"I2SOUT0", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, 1582 {"I2SOUT0", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, 1583 {"I2SOUT0", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, 1584 {"I2SOUT0", NULL, "I2SOUT0_EN"}, 1585 {"I2SOUT0", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, 1586 {"I2SOUT0", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, 1587 {"I2SOUT0", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, 1588 {"I2SOUT0", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, 1589 {"I2SOUT0", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, 1590 {"I2SOUT0", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, 1591 1592 {"I2SOUT0", NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1593 {"I2SOUT0", NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1594 1595 {"I2SOUT0", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1596 {"I2SOUT0", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1597 {"I2SOUT0", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1598 {"I2SOUT0", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1599 {"I2SOUT0", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1600 {"I2SOUT0", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1601 {"I2SOUT0", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1602 {"I2SOUT0", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1603 {"I2SOUT0", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1604 {"I2SOUT0", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1605 {"I2SOUT0", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1606 {"I2SOUT0", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1607 {"I2SOUT0", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1608 {I2SOUT0_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1609 {I2SOUT0_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1610 {"I2SOUT0", NULL, "I2SOUT0_CG"}, 1611 {"I2SOUT0", NULL, "I2SIN0_CG"}, 1612 1613 /* i2sout1 */ 1614 {"I2SOUT1_CH1", "DL0_CH1", "DL0"}, 1615 {"I2SOUT1_CH2", "DL0_CH2", "DL0"}, 1616 {"I2SOUT1_CH1", "DL1_CH1", "DL1"}, 1617 {"I2SOUT1_CH2", "DL1_CH2", "DL1"}, 1618 {"I2SOUT1_CH1", "DL2_CH1", "DL2"}, 1619 {"I2SOUT1_CH2", "DL2_CH2", "DL2"}, 1620 {"I2SOUT1_CH1", "DL3_CH1", "DL3"}, 1621 {"I2SOUT1_CH2", "DL3_CH2", "DL3"}, 1622 {"I2SOUT1_CH1", "DL4_CH1", "DL4"}, 1623 {"I2SOUT1_CH2", "DL4_CH2", "DL4"}, 1624 {"I2SOUT1_CH1", "DL5_CH1", "DL5"}, 1625 {"I2SOUT1_CH2", "DL5_CH2", "DL5"}, 1626 {"I2SOUT1_CH1", "DL6_CH1", "DL6"}, 1627 {"I2SOUT1_CH2", "DL6_CH2", "DL6"}, 1628 {"I2SOUT1_CH1", "DL7_CH1", "DL7"}, 1629 {"I2SOUT1_CH2", "DL7_CH2", "DL7"}, 1630 {"I2SOUT1_CH1", "DL8_CH1", "DL8"}, 1631 {"I2SOUT1_CH2", "DL8_CH2", "DL8"}, 1632 {"I2SOUT1_CH1", "DL_24CH_CH1", "DL_24CH"}, 1633 {"I2SOUT1_CH2", "DL_24CH_CH2", "DL_24CH"}, 1634 1635 {"I2SOUT1", NULL, "I2SOUT1_CH1"}, 1636 {"I2SOUT1", NULL, "I2SOUT1_CH2"}, 1637 1638 {"I2SOUT1", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, 1639 {"I2SOUT1", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, 1640 {"I2SOUT1", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, 1641 {"I2SOUT1", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, 1642 {"I2SOUT1", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, 1643 {"I2SOUT1", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, 1644 {"I2SOUT1", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, 1645 {"I2SOUT1", NULL, "I2SOUT1_EN"}, 1646 {"I2SOUT1", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, 1647 {"I2SOUT1", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, 1648 {"I2SOUT1", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, 1649 {"I2SOUT1", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, 1650 {"I2SOUT1", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, 1651 1652 {"I2SOUT1", NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1653 {"I2SOUT1", NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1654 1655 {"I2SOUT1", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1656 {"I2SOUT1", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1657 {"I2SOUT1", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1658 {"I2SOUT1", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1659 {"I2SOUT1", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1660 {"I2SOUT1", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1661 {"I2SOUT1", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1662 {"I2SOUT1", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1663 {"I2SOUT1", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1664 {"I2SOUT1", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1665 {"I2SOUT1", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1666 {"I2SOUT1", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1667 {"I2SOUT1", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1668 {I2SOUT1_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1669 {I2SOUT1_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1670 {"I2SOUT1", NULL, "I2SOUT1_CG"}, 1671 {"I2SOUT1", NULL, "I2SIN1_CG"}, 1672 1673 /* i2sout2 */ 1674 {"I2SOUT2_CH1", "DL0_CH1", "DL0"}, 1675 {"I2SOUT2_CH2", "DL0_CH2", "DL0"}, 1676 {"I2SOUT2_CH1", "DL1_CH1", "DL1"}, 1677 {"I2SOUT2_CH2", "DL1_CH2", "DL1"}, 1678 {"I2SOUT2_CH1", "DL2_CH1", "DL2"}, 1679 {"I2SOUT2_CH2", "DL2_CH2", "DL2"}, 1680 {"I2SOUT2_CH1", "DL3_CH1", "DL3"}, 1681 {"I2SOUT2_CH2", "DL3_CH2", "DL3"}, 1682 {"I2SOUT2_CH1", "DL4_CH1", "DL4"}, 1683 {"I2SOUT2_CH2", "DL4_CH2", "DL4"}, 1684 {"I2SOUT2_CH1", "DL5_CH1", "DL5"}, 1685 {"I2SOUT2_CH2", "DL5_CH2", "DL5"}, 1686 {"I2SOUT2_CH1", "DL6_CH1", "DL6"}, 1687 {"I2SOUT2_CH2", "DL6_CH2", "DL6"}, 1688 {"I2SOUT2_CH1", "DL7_CH1", "DL7"}, 1689 {"I2SOUT2_CH2", "DL7_CH2", "DL7"}, 1690 {"I2SOUT2_CH1", "DL8_CH1", "DL8"}, 1691 {"I2SOUT2_CH2", "DL8_CH2", "DL8"}, 1692 {"I2SOUT2_CH1", "DL_24CH_CH1", "DL_24CH"}, 1693 {"I2SOUT2_CH2", "DL_24CH_CH2", "DL_24CH"}, 1694 1695 {"I2SOUT2", NULL, "I2SOUT2_CH1"}, 1696 {"I2SOUT2", NULL, "I2SOUT2_CH2"}, 1697 1698 {"I2SOUT2", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, 1699 {"I2SOUT2", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, 1700 {"I2SOUT2", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, 1701 {"I2SOUT2", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, 1702 {"I2SOUT2", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, 1703 {"I2SOUT2", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, 1704 {"I2SOUT2", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, 1705 {"I2SOUT2", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, 1706 {"I2SOUT2", NULL, "I2SOUT2_EN"}, 1707 {"I2SOUT2", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, 1708 {"I2SOUT2", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, 1709 {"I2SOUT2", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, 1710 {"I2SOUT2", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, 1711 1712 {"I2SOUT2", NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1713 {"I2SOUT2", NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1714 1715 {"I2SOUT2", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1716 {"I2SOUT2", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1717 {"I2SOUT2", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1718 {"I2SOUT2", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1719 {"I2SOUT2", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1720 {"I2SOUT2", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1721 {"I2SOUT2", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1722 {"I2SOUT2", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1723 {"I2SOUT2", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1724 {"I2SOUT2", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1725 {"I2SOUT2", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1726 {"I2SOUT2", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1727 {"I2SOUT2", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1728 {I2SOUT2_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1729 {I2SOUT2_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1730 {"I2SOUT2", NULL, "I2SOUT2_CG"}, 1731 {"I2SOUT2", NULL, "I2SIN2_CG"}, 1732 1733 /* i2sout3 */ 1734 {"I2SOUT3_CH1", "DL0_CH1", "DL0"}, 1735 {"I2SOUT3_CH2", "DL0_CH2", "DL0"}, 1736 {"I2SOUT3_CH1", "DL1_CH1", "DL1"}, 1737 {"I2SOUT3_CH2", "DL1_CH2", "DL1"}, 1738 {"I2SOUT3_CH1", "DL2_CH1", "DL2"}, 1739 {"I2SOUT3_CH2", "DL2_CH2", "DL2"}, 1740 {"I2SOUT3_CH1", "DL3_CH1", "DL3"}, 1741 {"I2SOUT3_CH2", "DL3_CH2", "DL3"}, 1742 {"I2SOUT3_CH1", "DL4_CH1", "DL4"}, 1743 {"I2SOUT3_CH2", "DL4_CH2", "DL4"}, 1744 {"I2SOUT3_CH1", "DL5_CH1", "DL5"}, 1745 {"I2SOUT3_CH2", "DL5_CH2", "DL5"}, 1746 {"I2SOUT3_CH1", "DL6_CH1", "DL6"}, 1747 {"I2SOUT3_CH2", "DL6_CH2", "DL6"}, 1748 {"I2SOUT3_CH1", "DL7_CH1", "DL7"}, 1749 {"I2SOUT3_CH2", "DL7_CH2", "DL7"}, 1750 {"I2SOUT3_CH1", "DL8_CH1", "DL8"}, 1751 {"I2SOUT3_CH2", "DL8_CH2", "DL8"}, 1752 {"I2SOUT3_CH1", "DL_24CH_CH1", "DL_24CH"}, 1753 {"I2SOUT3_CH2", "DL_24CH_CH2", "DL_24CH"}, 1754 1755 {"I2SOUT3", NULL, "I2SOUT3_CH1"}, 1756 {"I2SOUT3", NULL, "I2SOUT3_CH2"}, 1757 1758 {"I2SOUT3", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, 1759 {"I2SOUT3", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, 1760 {"I2SOUT3", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, 1761 {"I2SOUT3", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, 1762 {"I2SOUT3", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, 1763 {"I2SOUT3", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, 1764 {"I2SOUT3", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, 1765 {"I2SOUT3", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, 1766 {"I2SOUT3", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, 1767 {"I2SOUT3", NULL, "I2SOUT3_EN"}, 1768 {"I2SOUT3", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, 1769 {"I2SOUT3", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, 1770 {"I2SOUT3", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, 1771 1772 {"I2SOUT3", NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1773 {"I2SOUT3", NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1774 1775 {"I2SOUT3", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1776 {"I2SOUT3", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1777 {"I2SOUT3", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1778 {"I2SOUT3", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1779 {"I2SOUT3", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1780 {"I2SOUT3", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1781 {"I2SOUT3", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1782 {"I2SOUT3", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1783 {"I2SOUT3", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1784 {"I2SOUT3", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1785 {"I2SOUT3", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1786 {"I2SOUT3", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1787 {"I2SOUT3", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1788 {I2SOUT3_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1789 {I2SOUT3_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1790 {"I2SOUT3", NULL, "I2SOUT3_CG"}, 1791 {"I2SOUT3", NULL, "I2SIN3_CG"}, 1792 1793 /* i2sout4 */ 1794 {"I2SOUT4_CH1", "DL0_CH1", "DL0"}, 1795 {"I2SOUT4_CH2", "DL0_CH2", "DL0"}, 1796 {"I2SOUT4_CH1", "DL1_CH1", "DL1"}, 1797 {"I2SOUT4_CH2", "DL1_CH2", "DL1"}, 1798 {"I2SOUT4_CH1", "DL2_CH1", "DL2"}, 1799 {"I2SOUT4_CH2", "DL2_CH2", "DL2"}, 1800 {"I2SOUT4_CH1", "DL3_CH1", "DL3"}, 1801 {"I2SOUT4_CH2", "DL3_CH2", "DL3"}, 1802 {"I2SOUT4_CH1", "DL4_CH1", "DL4"}, 1803 {"I2SOUT4_CH2", "DL4_CH2", "DL4"}, 1804 {"I2SOUT4_CH1", "DL5_CH1", "DL5"}, 1805 {"I2SOUT4_CH2", "DL5_CH2", "DL5"}, 1806 {"I2SOUT4_CH1", "DL6_CH1", "DL6"}, 1807 {"I2SOUT4_CH2", "DL6_CH2", "DL6"}, 1808 {"I2SOUT4_CH1", "DL7_CH1", "DL7"}, 1809 {"I2SOUT4_CH2", "DL7_CH2", "DL7"}, 1810 {"I2SOUT4_CH1", "DL8_CH1", "DL8"}, 1811 {"I2SOUT4_CH2", "DL8_CH2", "DL8"}, 1812 {"I2SOUT4_CH1", "DL_24CH_CH1", "DL_24CH"}, 1813 {"I2SOUT4_CH2", "DL_24CH_CH2", "DL_24CH"}, 1814 {"I2SOUT4_CH3", "DL_24CH_CH3", "DL_24CH"}, 1815 {"I2SOUT4_CH4", "DL_24CH_CH4", "DL_24CH"}, 1816 {"I2SOUT4_CH5", "DL_24CH_CH5", "DL_24CH"}, 1817 {"I2SOUT4_CH6", "DL_24CH_CH6", "DL_24CH"}, 1818 {"I2SOUT4_CH7", "DL_24CH_CH7", "DL_24CH"}, 1819 {"I2SOUT4_CH8", "DL_24CH_CH8", "DL_24CH"}, 1820 {"I2SOUT4_CH1", "DL24_CH1", "DL24"}, 1821 {"I2SOUT4_CH2", "DL24_CH2", "DL24"}, 1822 1823 /* SOF Downlink */ 1824 {"I2SOUT4_CH1", "DL_24CH_CH1", "SOF_DMA_DL_24CH"}, 1825 {"I2SOUT4_CH2", "DL_24CH_CH2", "SOF_DMA_DL_24CH"}, 1826 {"I2SOUT4_CH3", "DL_24CH_CH3", "SOF_DMA_DL_24CH"}, 1827 {"I2SOUT4_CH4", "DL_24CH_CH4", "SOF_DMA_DL_24CH"}, 1828 1829 {"I2SOUT4", NULL, "I2SOUT4_CH1"}, 1830 {"I2SOUT4", NULL, "I2SOUT4_CH2"}, 1831 {"I2SOUT4", NULL, "I2SOUT4_CH3"}, 1832 {"I2SOUT4", NULL, "I2SOUT4_CH4"}, 1833 {"I2SOUT4", NULL, "I2SOUT4_CH5"}, 1834 {"I2SOUT4", NULL, "I2SOUT4_CH6"}, 1835 {"I2SOUT4", NULL, "I2SOUT4_CH7"}, 1836 {"I2SOUT4", NULL, "I2SOUT4_CH8"}, 1837 1838 {"I2SOUT4", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, 1839 {"I2SOUT4", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, 1840 {"I2SOUT4", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, 1841 {"I2SOUT4", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, 1842 {"I2SOUT4", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, 1843 {"I2SOUT4", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, 1844 {"I2SOUT4", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, 1845 {"I2SOUT4", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, 1846 {"I2SOUT4", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, 1847 {"I2SOUT4", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, 1848 {"I2SOUT4", NULL, "I2SOUT4_EN"}, 1849 {"I2SOUT4", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, 1850 {"I2SOUT4", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, 1851 1852 {"I2SOUT4", NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1853 {"I2SOUT4", NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1854 1855 {"I2SOUT4", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1856 {"I2SOUT4", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1857 {"I2SOUT4", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1858 {"I2SOUT4", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1859 {"I2SOUT4", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1860 {"I2SOUT4", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1861 {"I2SOUT4", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1862 {"I2SOUT4", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1863 {"I2SOUT4", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1864 {"I2SOUT4", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1865 {"I2SOUT4", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1866 {"I2SOUT4", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1867 {"I2SOUT4", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1868 {I2SOUT4_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1869 {I2SOUT4_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1870 /* CG */ 1871 {"I2SOUT4", NULL, "I2SOUT4_CG"}, 1872 {"I2SOUT4", NULL, "I2SIN4_CG"}, 1873 1874 /* i2sout6 */ 1875 {"I2SOUT6_CH1", "DL0_CH1", "DL0"}, 1876 {"I2SOUT6_CH2", "DL0_CH2", "DL0"}, 1877 {"I2SOUT6_CH1", "DL1_CH1", "DL1"}, 1878 {"I2SOUT6_CH2", "DL1_CH2", "DL1"}, 1879 {"I2SOUT6_CH1", "DL2_CH1", "DL2"}, 1880 {"I2SOUT6_CH2", "DL2_CH2", "DL2"}, 1881 {"I2SOUT6_CH1", "DL3_CH1", "DL3"}, 1882 {"I2SOUT6_CH2", "DL3_CH2", "DL3"}, 1883 {"I2SOUT6_CH1", "DL4_CH1", "DL4"}, 1884 {"I2SOUT6_CH2", "DL4_CH2", "DL4"}, 1885 {"I2SOUT6_CH1", "DL5_CH1", "DL5"}, 1886 {"I2SOUT6_CH2", "DL5_CH2", "DL5"}, 1887 {"I2SOUT6_CH1", "DL6_CH1", "DL6"}, 1888 {"I2SOUT6_CH2", "DL6_CH2", "DL6"}, 1889 {"I2SOUT6_CH1", "DL7_CH1", "DL7"}, 1890 {"I2SOUT6_CH2", "DL7_CH2", "DL7"}, 1891 {"I2SOUT6_CH1", "DL8_CH1", "DL8"}, 1892 {"I2SOUT6_CH2", "DL8_CH2", "DL8"}, 1893 {"I2SOUT6_CH1", "DL23_CH1", "DL23"}, 1894 {"I2SOUT6_CH2", "DL23_CH2", "DL23"}, 1895 {"I2SOUT6_CH1", "DL_24CH_CH1", "DL_24CH"}, 1896 {"I2SOUT6_CH2", "DL_24CH_CH2", "DL_24CH"}, 1897 1898 /* SOF Downlink */ 1899 {"I2SOUT6_CH1", "DL1_CH1", "SOF_DMA_DL1"}, 1900 {"I2SOUT6_CH2", "DL1_CH2", "SOF_DMA_DL1"}, 1901 {"I2SOUT6_CH1", "DL_24CH_CH1", "SOF_DMA_DL_24CH"}, 1902 {"I2SOUT6_CH2", "DL_24CH_CH2", "SOF_DMA_DL_24CH"}, 1903 1904 {"I2SOUT6", NULL, "I2SOUT6_CH1"}, 1905 {"I2SOUT6", NULL, "I2SOUT6_CH2"}, 1906 1907 {"I2SOUT6", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, 1908 {"I2SOUT6", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, 1909 {"I2SOUT6", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, 1910 {"I2SOUT6", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, 1911 {"I2SOUT6", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, 1912 {"I2SOUT6", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, 1913 {"I2SOUT6", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, 1914 {"I2SOUT6", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, 1915 {"I2SOUT6", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, 1916 {"I2SOUT6", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, 1917 {"I2SOUT6", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, 1918 {"I2SOUT6", NULL, "I2SOUT6_EN"}, 1919 {"I2SOUT6", NULL, "FMI2S_MASTER_EN", mtk_afe_i2s_share_connect}, 1920 1921 {"I2SOUT6", NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1922 {"I2SOUT6", NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1923 1924 {"I2SOUT6", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1925 {"I2SOUT6", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1926 {"I2SOUT6", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1927 {"I2SOUT6", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1928 {"I2SOUT6", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1929 {"I2SOUT6", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1930 {"I2SOUT6", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1931 {"I2SOUT6", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1932 {"I2SOUT6", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1933 {"I2SOUT6", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1934 {"I2SOUT6", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1935 {"I2SOUT6", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1936 {"I2SOUT6", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1937 {I2SOUT6_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1938 {I2SOUT6_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1939 /* CG */ 1940 {"I2SOUT6", NULL, "I2SOUT6_CG"}, 1941 {"I2SOUT6", NULL, "I2SIN6_CG"}, 1942 1943 /* fmi2s */ 1944 {"FMI2S_MASTER", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect}, 1945 {"FMI2S_MASTER", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect}, 1946 {"FMI2S_MASTER", NULL, "I2SIN2_EN", mtk_afe_i2s_share_connect}, 1947 {"FMI2S_MASTER", NULL, "I2SIN3_EN", mtk_afe_i2s_share_connect}, 1948 {"FMI2S_MASTER", NULL, "I2SIN4_EN", mtk_afe_i2s_share_connect}, 1949 {"FMI2S_MASTER", NULL, "I2SIN6_EN", mtk_afe_i2s_share_connect}, 1950 {"FMI2S_MASTER", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect}, 1951 {"FMI2S_MASTER", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect}, 1952 {"FMI2S_MASTER", NULL, "I2SOUT2_EN", mtk_afe_i2s_share_connect}, 1953 {"FMI2S_MASTER", NULL, "I2SOUT3_EN", mtk_afe_i2s_share_connect}, 1954 {"FMI2S_MASTER", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect}, 1955 {"FMI2S_MASTER", NULL, "I2SOUT6_EN", mtk_afe_i2s_share_connect}, 1956 {"FMI2S_MASTER", NULL, "FMI2S_MASTER_EN"}, 1957 1958 {"FMI2S_MASTER", NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1959 {"FMI2S_MASTER", NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1960 1961 {"FMI2S_MASTER", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1962 {"FMI2S_MASTER", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1963 {"FMI2S_MASTER", NULL, I2SIN2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1964 {"FMI2S_MASTER", NULL, I2SIN3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1965 {"FMI2S_MASTER", NULL, I2SIN4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1966 {"FMI2S_MASTER", NULL, I2SIN6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1967 {"FMI2S_MASTER", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1968 {"FMI2S_MASTER", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1969 {"FMI2S_MASTER", NULL, I2SOUT2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1970 {"FMI2S_MASTER", NULL, I2SOUT3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1971 {"FMI2S_MASTER", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1972 {"FMI2S_MASTER", NULL, I2SOUT6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1973 {"FMI2S_MASTER", NULL, FMI2S_MASTER_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1974 {FMI2S_MASTER_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1975 {FMI2S_MASTER_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1976 /* CG */ 1977 {"FMI2S_MASTER", NULL, "FMI2S_MASTER_CG"}, 1978 }; 1979 1980 /* i2s dai ops*/ 1981 static int mtk_dai_i2s_config(struct mtk_base_afe *afe, 1982 struct snd_pcm_hw_params *params, 1983 int i2s_id) 1984 { 1985 struct mt8196_afe_private *afe_priv = afe->platform_priv; 1986 struct mtk_afe_i2s_priv *i2s_priv; 1987 struct mtk_afe_i2s_priv *i2sin_priv = NULL; 1988 int id = i2s_id - MT8196_DAI_I2S_IN0; 1989 struct mtk_base_etdm_data etdm_data; 1990 unsigned int rate = params_rate(params); 1991 unsigned int rate_reg = get_etdm_inconn_rate(rate); 1992 snd_pcm_format_t format = params_format(params); 1993 unsigned int channels = params_channels(params); 1994 int ret; 1995 unsigned int i2s_con; 1996 int pad_top; 1997 1998 if (i2s_id >= MT8196_DAI_NUM || i2s_id < 0 || id < 0 || id >= DAI_I2S_NUM) 1999 return -EINVAL; 2000 2001 i2s_priv = afe_priv->dai_priv[i2s_id]; 2002 if (!i2s_priv) 2003 return -EINVAL; 2004 2005 dev_dbg(afe->dev, "id: %d, rate: %d, pcm_fmt: %d, fmt: %d, ch: %d\n", 2006 i2s_id, rate, format, i2s_priv->format, channels); 2007 2008 i2s_priv->rate = rate; 2009 etdm_data = mtk_etdm_data[id]; 2010 2011 if (is_etdm_in_pad_top(id)) 2012 pad_top = 0x3; 2013 else 2014 pad_top = 0x5; 2015 2016 switch (id) { 2017 case DAI_FMI2S_MASTER: 2018 i2s_con = I2S_IN_PAD_IO_MUX << I2SIN_PAD_SEL_SFT; 2019 i2s_con |= rate_reg << I2S_MODE_SFT; 2020 i2s_con |= I2S_FMT_I2S << I2S_FMT_SFT; 2021 i2s_con |= get_i2s_wlen(format) << I2S_WLEN_SFT; 2022 regmap_update_bits(afe->regmap, AFE_CONNSYS_I2S_CON, 2023 0xffffeffe, i2s_con); 2024 break; 2025 2026 case DAI_I2SIN0: 2027 case DAI_I2SIN1: 2028 case DAI_I2SIN2: 2029 case DAI_I2SIN3: 2030 case DAI_I2SIN4: 2031 case DAI_I2SIN6: 2032 /* ---etdm in --- */ 2033 regmap_update_bits(afe->regmap, 2034 etdm_data.init_count_reg, 2035 etdm_data.init_count_mask << etdm_data.init_count_shift, 2036 0x5 << etdm_data.init_count_shift); 2037 2038 /* 3: pad top 5: no pad top */ 2039 regmap_update_bits(afe->regmap, 2040 etdm_data.init_point_reg, 2041 etdm_data.init_point_mask << etdm_data.init_point_shift, 2042 pad_top << etdm_data.init_point_shift); 2043 2044 regmap_update_bits(afe->regmap, 2045 etdm_data.lrck_reset_reg, 2046 etdm_data.lrck_reset_mask << etdm_data.lrck_reset_shift, 2047 0x1 << etdm_data.lrck_reset_shift); 2048 2049 regmap_update_bits(afe->regmap, 2050 etdm_data.clk_source_reg, 2051 etdm_data.clk_source_mask << etdm_data.clk_source_shift, 2052 ETDM_CLK_SOURCE_APLL << etdm_data.clk_source_shift); 2053 2054 /* 0: manual 1: auto */ 2055 regmap_update_bits(afe->regmap, 2056 etdm_data.ck_en_sel_reg, 2057 etdm_data.ck_en_sel_mask << etdm_data.ck_en_sel_shift, 2058 0x1 << etdm_data.ck_en_sel_shift); 2059 2060 regmap_update_bits(afe->regmap, 2061 etdm_data.fs_timing_reg, 2062 etdm_data.fs_timing_mask << etdm_data.fs_timing_shift, 2063 get_etdm_rate(rate) << etdm_data.fs_timing_shift); 2064 2065 regmap_update_bits(afe->regmap, 2066 etdm_data.relatch_en_sel_reg, 2067 etdm_data.relatch_en_sel_mask << etdm_data.relatch_en_sel_shift, 2068 get_etdm_inconn_rate(rate) << etdm_data.relatch_en_sel_shift); 2069 2070 regmap_update_bits(afe->regmap, 2071 etdm_data.use_afifo_reg, 2072 etdm_data.use_afifo_mask << etdm_data.use_afifo_shift, 2073 0x0); 2074 2075 regmap_update_bits(afe->regmap, 2076 etdm_data.afifo_mode_reg, 2077 etdm_data.afifo_mode_mask << etdm_data.afifo_mode_shift, 2078 0x0); 2079 2080 regmap_update_bits(afe->regmap, 2081 etdm_data.almost_end_ch_reg, 2082 etdm_data.almost_end_ch_mask << etdm_data.almost_end_ch_shift, 2083 0x0); 2084 2085 regmap_update_bits(afe->regmap, 2086 etdm_data.almost_end_bit_reg, 2087 etdm_data.almost_end_bit_mask << etdm_data.almost_end_bit_shift, 2088 0x0); 2089 2090 if (is_etdm_in_pad_top(id)) { 2091 regmap_update_bits(afe->regmap, 2092 etdm_data.out2latch_time_reg, 2093 etdm_data.out2latch_time_mask << 2094 etdm_data.out2latch_time_shift, 2095 0x6 << etdm_data.out2latch_time_shift); 2096 } else { 2097 regmap_update_bits(afe->regmap, 2098 etdm_data.out2latch_time_reg, 2099 etdm_data.out2latch_time_mask << 2100 etdm_data.out2latch_time_shift, 2101 0x4 << etdm_data.out2latch_time_shift); 2102 } 2103 2104 if (id == DAI_I2SIN4) { 2105 dev_dbg(afe->dev, "i2sin4, id: %d, fmt: %d, ch: %d, ip_mode: %d, sync: %d\n", 2106 id, i2s_priv->format, channels, i2s_priv->ip_mode, i2s_priv->sync); 2107 2108 /* Fmt Mode: 0x00 i2s, 0x04 adsp_a, DSP_A mode for multi-channel */ 2109 regmap_update_bits(afe->regmap, 2110 etdm_data.tdm_mode_reg, 2111 etdm_data.tdm_mode_mask << etdm_data.tdm_mode_shift, 2112 i2s_priv->format << etdm_data.tdm_mode_shift); 2113 2114 /* set etdm ch */ 2115 regmap_update_bits(afe->regmap, 2116 etdm_data.ch_reg, 2117 etdm_data.ch_mask << etdm_data.ch_shift, 2118 (channels - 1) << etdm_data.ch_shift); 2119 2120 /* set etdm ip mode */ 2121 regmap_update_bits(afe->regmap, 2122 etdm_data.ip_mode_reg, 2123 etdm_data.ip_mode_mask << etdm_data.ip_mode_shift, 2124 i2s_priv->ip_mode << etdm_data.ip_mode_shift); 2125 2126 /* set etdm sync */ 2127 regmap_update_bits(afe->regmap, 2128 etdm_data.sync_reg, 2129 etdm_data.sync_mask << etdm_data.sync_shift, 2130 i2s_priv->sync << etdm_data.sync_shift); 2131 } else { 2132 /* default i2s */ 2133 regmap_update_bits(afe->regmap, 2134 etdm_data.tdm_mode_reg, 2135 etdm_data.tdm_mode_mask << etdm_data.tdm_mode_shift, 2136 0x0 << etdm_data.tdm_mode_shift); 2137 2138 /* set etdm sync */ 2139 regmap_update_bits(afe->regmap, 2140 etdm_data.sync_reg, 2141 etdm_data.sync_mask << etdm_data.sync_shift, 2142 0x0 << etdm_data.sync_shift); 2143 } 2144 2145 /* APLL */ 2146 regmap_update_bits(afe->regmap, 2147 etdm_data.relatch_domain_sel_reg, 2148 etdm_data.relatch_domain_sel_mask << 2149 etdm_data.relatch_domain_sel_shift, 2150 ETDM_RELATCH_SEL_APLL << etdm_data.relatch_domain_sel_shift); 2151 2152 regmap_update_bits(afe->regmap, 2153 etdm_data.bit_length_reg, 2154 etdm_data.bit_length_mask << etdm_data.bit_length_shift, 2155 get_etdm_lrck_width(format) << etdm_data.bit_length_shift); 2156 2157 regmap_update_bits(afe->regmap, 2158 etdm_data.word_length_reg, 2159 etdm_data.word_length_mask << etdm_data.word_length_shift, 2160 get_etdm_wlen(format) << etdm_data.word_length_shift); 2161 2162 /* ---etdm cowork --- */ 2163 regmap_update_bits(afe->regmap, 2164 etdm_data.cowork_reg, 2165 etdm_data.cowork_mask << etdm_data.cowork_shift, 2166 etdm_data.cowork_val << etdm_data.cowork_shift); 2167 2168 /* i2s with pad top setting */ 2169 if (is_etdm_in_pad_top(id) && etdm_data.pad_top_ck_en_reg != 0) { 2170 regmap_update_bits(afe->regmap, 2171 etdm_data.pad_top_ck_en_reg, 2172 etdm_data.pad_top_ck_en_mask << 2173 etdm_data.pad_top_ck_en_shift, 2174 0x1 << etdm_data.pad_top_ck_en_shift); 2175 2176 regmap_update_bits(afe->regmap, 2177 etdm_data.master_latch_reg, 2178 etdm_data.master_latch_mask << 2179 etdm_data.master_latch_shift, 2180 0x0); 2181 } 2182 break; 2183 2184 case DAI_I2SOUT0: 2185 case DAI_I2SOUT1: 2186 case DAI_I2SOUT2: 2187 case DAI_I2SOUT3: 2188 case DAI_I2SOUT4: 2189 case DAI_I2SOUT6: 2190 /* ---etdm out --- */ 2191 regmap_update_bits(afe->regmap, 2192 etdm_data.init_count_reg, 2193 etdm_data.init_count_mask << etdm_data.init_count_shift, 2194 0x5 << etdm_data.init_count_shift); 2195 2196 regmap_update_bits(afe->regmap, 2197 etdm_data.init_point_reg, 2198 etdm_data.init_point_mask << etdm_data.init_point_shift, 2199 0x6 << etdm_data.init_point_shift); 2200 2201 // clock speed > 22M need to set relatch time to avoid duplicate porint 2202 if (rate * channels * (get_etdm_wlen(format) + 1) >= ETDM_22M_CLOCK_THRES && 2203 get_etdm_wlen(format) >= 2) { 2204 regmap_update_bits(afe->regmap, 2205 etdm_data.in2latch_time_reg, 2206 etdm_data.in2latch_time_mask << 2207 etdm_data.in2latch_time_shift, 2208 (get_etdm_wlen(format) - 2) << 2209 etdm_data.in2latch_time_shift); 2210 } else { 2211 regmap_update_bits(afe->regmap, 2212 etdm_data.in2latch_time_reg, 2213 etdm_data.in2latch_time_mask << 2214 etdm_data.in2latch_time_shift, 2215 0x6 << etdm_data.in2latch_time_shift); 2216 } 2217 2218 regmap_update_bits(afe->regmap, 2219 etdm_data.lrck_reset_reg, 2220 etdm_data.lrck_reset_mask << etdm_data.lrck_reset_shift, 2221 0x1 << etdm_data.lrck_reset_shift); 2222 2223 regmap_update_bits(afe->regmap, 2224 etdm_data.fs_timing_reg, 2225 etdm_data.fs_timing_mask << etdm_data.fs_timing_shift, 2226 get_etdm_rate(rate) << etdm_data.fs_timing_shift); 2227 2228 regmap_update_bits(afe->regmap, 2229 etdm_data.clk_source_reg, 2230 etdm_data.clk_source_mask << etdm_data.clk_source_shift, 2231 ETDM_CLK_SOURCE_APLL << etdm_data.clk_source_shift); 2232 2233 regmap_update_bits(afe->regmap, 2234 etdm_data.relatch_en_sel_reg, 2235 etdm_data.relatch_en_sel_mask << etdm_data.relatch_en_sel_shift, 2236 get_etdm_inconn_rate(rate) << etdm_data.relatch_en_sel_shift); 2237 2238 if (id == DAI_I2SOUT4) { 2239 dev_dbg(afe->dev, "i2sout4, id: %d fmt: %d, ch: %d, sync: %d\n", 2240 id, i2s_priv->format, channels, i2s_priv->sync); 2241 2242 /* Fmt Mode: 0x00 i2s, 0x04 adsp_a, DSP_A mode for multi-channel */ 2243 regmap_update_bits(afe->regmap, 2244 etdm_data.tdm_mode_reg, 2245 etdm_data.tdm_mode_mask << etdm_data.tdm_mode_shift, 2246 i2s_priv->format << etdm_data.tdm_mode_shift); 2247 2248 /* set etdm ch */ 2249 regmap_update_bits(afe->regmap, 2250 etdm_data.ch_reg, 2251 etdm_data.ch_mask << etdm_data.ch_shift, 2252 (channels - 1) << etdm_data.ch_shift); 2253 2254 /* set etdm sync */ 2255 regmap_update_bits(afe->regmap, 2256 etdm_data.sync_reg, 2257 etdm_data.sync_mask << etdm_data.sync_shift, 2258 i2s_priv->sync << etdm_data.sync_shift); 2259 } else { 2260 regmap_update_bits(afe->regmap, 2261 etdm_data.tdm_mode_reg, 2262 etdm_data.tdm_mode_mask << etdm_data.tdm_mode_shift, 2263 0x0); 2264 } 2265 2266 /* APLL */ 2267 regmap_update_bits(afe->regmap, 2268 etdm_data.relatch_domain_sel_reg, 2269 etdm_data.relatch_domain_sel_mask << 2270 etdm_data.relatch_domain_sel_shift, 2271 ETDM_RELATCH_SEL_APLL << etdm_data.relatch_domain_sel_shift); 2272 2273 regmap_update_bits(afe->regmap, 2274 etdm_data.bit_length_reg, 2275 etdm_data.bit_length_mask << etdm_data.bit_length_shift, 2276 get_etdm_lrck_width(format) << etdm_data.bit_length_shift); 2277 2278 regmap_update_bits(afe->regmap, 2279 etdm_data.word_length_reg, 2280 etdm_data.word_length_mask << etdm_data.word_length_shift, 2281 get_etdm_wlen(format) << etdm_data.word_length_shift); 2282 2283 /* ---etdm cowork --- */ 2284 regmap_update_bits(afe->regmap, 2285 etdm_data.cowork_reg, 2286 etdm_data.cowork_mask << etdm_data.cowork_shift, 2287 etdm_data.cowork_val << etdm_data.cowork_shift); 2288 2289 /* i2s with pad top setting */ 2290 if (is_etdm_in_pad_top(id) && etdm_data.pad_top_ck_en_reg != 0) { 2291 regmap_update_bits(afe->regmap, 2292 etdm_data.pad_top_ck_en_reg, 2293 etdm_data.cowork_mask << etdm_data.pad_top_ck_en_shift, 2294 0x1 << etdm_data.pad_top_ck_en_shift); 2295 2296 regmap_update_bits(afe->regmap, 2297 etdm_data.master_latch_reg, 2298 etdm_data.master_latch_mask << 2299 etdm_data.master_latch_shift, 2300 0x0); 2301 } 2302 break; 2303 2304 default: 2305 dev_err(afe->dev, "id %d not support\n", id); 2306 return -EINVAL; 2307 } 2308 2309 /* set share i2s */ 2310 if (i2s_priv && i2s_priv->share_i2s_id >= 0) { 2311 i2sin_priv = afe_priv->dai_priv[i2s_priv->share_i2s_id]; 2312 i2sin_priv->format = i2s_priv->format; 2313 ret = mtk_dai_i2s_config(afe, params, i2s_priv->share_i2s_id); 2314 if (ret) 2315 return ret; 2316 } 2317 2318 return 0; 2319 } 2320 2321 static int mtk_dai_i2s_hw_params(struct snd_pcm_substream *substream, 2322 struct snd_pcm_hw_params *params, 2323 struct snd_soc_dai *dai) 2324 { 2325 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2326 2327 return mtk_dai_i2s_config(afe, params, dai->id); 2328 } 2329 2330 static int mtk_dai_i2s_set_sysclk(struct snd_soc_dai *dai, 2331 int clk_id, unsigned int freq, int dir) 2332 { 2333 struct mtk_base_afe *afe = dev_get_drvdata(dai->dev); 2334 struct mt8196_afe_private *afe_priv = afe->platform_priv; 2335 struct mtk_afe_i2s_priv *i2s_priv; 2336 int apll; 2337 int apll_rate; 2338 2339 if (dai->id >= MT8196_DAI_NUM || dai->id < 0 || dir != SND_SOC_CLOCK_OUT) 2340 return -EINVAL; 2341 2342 i2s_priv = afe_priv->dai_priv[dai->id]; 2343 if (!i2s_priv) 2344 return -EINVAL; 2345 2346 dev_dbg(afe->dev, "freq: %u\n", freq); 2347 2348 apll = mt8196_get_apll_by_rate(afe, freq); 2349 apll_rate = mt8196_get_apll_rate(afe, apll); 2350 2351 if (freq > apll_rate || apll_rate % freq) 2352 return -EINVAL; 2353 2354 i2s_priv->mclk_rate = freq; 2355 i2s_priv->mclk_apll = apll; 2356 2357 if (i2s_priv->share_i2s_id > 0) { 2358 struct mtk_afe_i2s_priv *share_i2s_priv; 2359 2360 share_i2s_priv = afe_priv->dai_priv[i2s_priv->share_i2s_id]; 2361 if (!share_i2s_priv) 2362 return -EINVAL; 2363 2364 share_i2s_priv->mclk_rate = i2s_priv->mclk_rate; 2365 share_i2s_priv->mclk_apll = i2s_priv->mclk_apll; 2366 } 2367 2368 return 0; 2369 } 2370 2371 static int mtk_dai_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2372 { 2373 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2374 struct mt8196_afe_private *afe_priv = afe->platform_priv; 2375 struct mtk_afe_i2s_priv *i2s_priv; 2376 2377 if (dai->id >= MT8196_DAI_NUM || dai->id < 0) 2378 return -EINVAL; 2379 2380 i2s_priv = afe_priv->dai_priv[dai->id]; 2381 if (!i2s_priv) 2382 return -EINVAL; 2383 2384 dev_dbg(afe->dev, "dai->id: %d, fmt: 0x%x\n", dai->id, fmt); 2385 2386 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2387 case SND_SOC_DAIFMT_I2S: 2388 i2s_priv->format = MTK_DAI_ETDM_FORMAT_I2S; 2389 break; 2390 case SND_SOC_DAIFMT_LEFT_J: 2391 i2s_priv->format = MTK_DAI_ETDM_FORMAT_LJ; 2392 break; 2393 case SND_SOC_DAIFMT_RIGHT_J: 2394 i2s_priv->format = MTK_DAI_ETDM_FORMAT_RJ; 2395 break; 2396 case SND_SOC_DAIFMT_DSP_A: 2397 i2s_priv->format = MTK_DAI_ETDM_FORMAT_DSPA; 2398 break; 2399 case SND_SOC_DAIFMT_DSP_B: 2400 i2s_priv->format = MTK_DAI_ETDM_FORMAT_DSPB; 2401 break; 2402 default: 2403 return -EINVAL; 2404 } 2405 2406 return 0; 2407 } 2408 2409 static const struct snd_soc_dai_ops mtk_dai_i2s_ops = { 2410 .hw_params = mtk_dai_i2s_hw_params, 2411 .set_sysclk = mtk_dai_i2s_set_sysclk, 2412 .set_fmt = mtk_dai_i2s_set_fmt, 2413 }; 2414 2415 /* dai driver */ 2416 #define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_384000) 2417 #define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S8 |\ 2418 SNDRV_PCM_FMTBIT_S16_LE |\ 2419 SNDRV_PCM_FMTBIT_S24_LE |\ 2420 SNDRV_PCM_FMTBIT_S32_LE) 2421 2422 #define MT8196_I2S_DAI(_name, _id, max_ch, dir) \ 2423 { \ 2424 .name = #_name, \ 2425 .id = _id, \ 2426 .dir = { \ 2427 .stream_name = #_name, \ 2428 .channels_min = 1, \ 2429 .channels_max = max_ch, \ 2430 .rates = MTK_ETDM_RATES, \ 2431 .formats = MTK_ETDM_FORMATS, \ 2432 }, \ 2433 .ops = &mtk_dai_i2s_ops, \ 2434 } 2435 2436 static struct snd_soc_dai_driver mtk_dai_i2s_driver[] = { 2437 /* capture */ 2438 MT8196_I2S_DAI(I2SIN0, MT8196_DAI_I2S_IN0, 2, capture), 2439 MT8196_I2S_DAI(I2SIN1, MT8196_DAI_I2S_IN1, 2, capture), 2440 MT8196_I2S_DAI(I2SIN2, MT8196_DAI_I2S_IN2, 2, capture), 2441 MT8196_I2S_DAI(I2SIN3, MT8196_DAI_I2S_IN3, 2, capture), 2442 MT8196_I2S_DAI(I2SIN4, MT8196_DAI_I2S_IN4, 8, capture), 2443 MT8196_I2S_DAI(I2SIN6, MT8196_DAI_I2S_IN6, 2, capture), 2444 MT8196_I2S_DAI(FMI2S_MASTER, MT8196_DAI_FM_I2S_MASTER, 2, capture), 2445 /* playback */ 2446 MT8196_I2S_DAI(I2SOUT0, MT8196_DAI_I2S_OUT0, 2, playback), 2447 MT8196_I2S_DAI(I2SOUT1, MT8196_DAI_I2S_OUT1, 2, playback), 2448 MT8196_I2S_DAI(I2SOUT2, MT8196_DAI_I2S_OUT2, 2, playback), 2449 MT8196_I2S_DAI(I2SOUT3, MT8196_DAI_I2S_OUT3, 2, playback), 2450 MT8196_I2S_DAI(I2SOUT4, MT8196_DAI_I2S_OUT4, 8, playback), 2451 MT8196_I2S_DAI(I2SOUT6, MT8196_DAI_I2S_OUT6, 2, playback), 2452 }; 2453 2454 static const struct mtk_afe_i2s_priv mt8196_i2s_priv[DAI_I2S_NUM] = { 2455 [DAI_I2SIN0] = { 2456 .id = MT8196_DAI_I2S_IN0, 2457 .mclk_id = MT8196_I2SIN0_MCK, 2458 .share_property_name = "i2sin0-share", 2459 .share_i2s_id = -1, 2460 }, 2461 [DAI_I2SIN1] = { 2462 .id = MT8196_DAI_I2S_IN1, 2463 .mclk_id = MT8196_I2SIN1_MCK, 2464 .share_property_name = "i2sin1-share", 2465 .share_i2s_id = -1, 2466 }, 2467 [DAI_I2SIN2] = { 2468 .id = MT8196_DAI_I2S_IN2, 2469 .mclk_id = MT8196_I2SIN0_MCK, 2470 .share_property_name = "i2sin2-share", 2471 .share_i2s_id = -1, 2472 }, 2473 [DAI_I2SIN3] = { 2474 .id = MT8196_DAI_I2S_IN3, 2475 .mclk_id = MT8196_I2SIN0_MCK, 2476 .share_property_name = "i2sin3-share", 2477 .share_i2s_id = -1, 2478 }, 2479 [DAI_I2SIN4] = { 2480 .id = MT8196_DAI_I2S_IN4, 2481 .mclk_id = MT8196_I2SIN0_MCK, 2482 .share_property_name = "i2sin4-share", 2483 .share_i2s_id = -1, 2484 .sync = 0, 2485 .ip_mode = 0, 2486 }, 2487 [DAI_I2SIN6] = { 2488 .id = MT8196_DAI_I2S_IN6, 2489 .mclk_id = MT8196_I2SIN0_MCK, 2490 .share_property_name = "i2sout6-share", 2491 .share_i2s_id = -1, 2492 }, 2493 [DAI_I2SOUT0] = { 2494 .id = MT8196_DAI_I2S_OUT0, 2495 .mclk_id = MT8196_I2SIN0_MCK, 2496 .share_property_name = "i2sout0-share", 2497 .share_i2s_id = MT8196_DAI_I2S_IN0, 2498 }, 2499 [DAI_I2SOUT1] = { 2500 .id = MT8196_DAI_I2S_OUT1, 2501 .mclk_id = MT8196_I2SIN1_MCK, 2502 .share_property_name = "i2sout1-share", 2503 .share_i2s_id = MT8196_DAI_I2S_IN1, 2504 }, 2505 [DAI_I2SOUT2] = { 2506 .id = MT8196_DAI_I2S_OUT2, 2507 .mclk_id = MT8196_I2SIN0_MCK, 2508 .share_property_name = "i2sout2-share", 2509 .share_i2s_id = MT8196_DAI_I2S_IN2, 2510 }, 2511 [DAI_I2SOUT3] = { 2512 .id = MT8196_DAI_I2S_OUT3, 2513 .mclk_id = MT8196_I2SIN0_MCK, 2514 .share_property_name = "i2sout3-share", 2515 .share_i2s_id = MT8196_DAI_I2S_IN3, 2516 }, 2517 [DAI_I2SOUT4] = { 2518 .id = MT8196_DAI_I2S_OUT4, 2519 .mclk_id = MT8196_I2SIN0_MCK, 2520 .share_property_name = "i2sout4-share", 2521 .share_i2s_id = MT8196_DAI_I2S_IN4, 2522 .sync = 0, 2523 }, 2524 [DAI_I2SOUT6] = { 2525 .id = MT8196_DAI_I2S_OUT6, 2526 .mclk_id = MT8196_I2SIN0_MCK, 2527 .share_property_name = "i2sout6-share", 2528 .share_i2s_id = MT8196_DAI_I2S_IN6, 2529 }, 2530 [DAI_FMI2S_MASTER] = { 2531 .id = MT8196_DAI_FM_I2S_MASTER, 2532 .mclk_id = MT8196_FMI2S_MCK, 2533 .share_property_name = "fmi2s-share", 2534 .share_i2s_id = -1, 2535 }, 2536 }; 2537 2538 static int mt8196_dai_i2s_get_share(struct mtk_base_afe *afe) 2539 { 2540 struct mt8196_afe_private *afe_priv = afe->platform_priv; 2541 const struct device_node *of_node = afe->dev->of_node; 2542 2543 for (int i = 0; i < DAI_I2S_NUM; i++) { 2544 const char *of_str; 2545 struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[mt8196_i2s_priv[i].id]; 2546 const char *property_name = mt8196_i2s_priv[i].share_property_name; 2547 2548 if (of_property_read_string(of_node, property_name, &of_str)) 2549 continue; 2550 2551 i2s_priv->share_i2s_id = get_i2s_id_by_name(afe, of_str); 2552 } 2553 2554 return 0; 2555 } 2556 2557 static int init_i2s_priv_data(struct mtk_base_afe *afe) 2558 { 2559 struct mt8196_afe_private *afe_priv = afe->platform_priv; 2560 struct mtk_afe_i2s_priv *i2s_priv; 2561 2562 for (int i = 0; i < DAI_I2S_NUM; i++) { 2563 int id = mt8196_i2s_priv[i].id; 2564 size_t size = sizeof(struct mtk_afe_i2s_priv); 2565 2566 if (id >= MT8196_DAI_NUM || id < 0) 2567 return -EINVAL; 2568 2569 i2s_priv = devm_kzalloc(afe->dev, size, GFP_KERNEL); 2570 if (!i2s_priv) 2571 return -ENOMEM; 2572 2573 memcpy(i2s_priv, &mt8196_i2s_priv[i], size); 2574 2575 afe_priv->dai_priv[id] = i2s_priv; 2576 } 2577 2578 return 0; 2579 } 2580 2581 int mt8196_dai_i2s_register(struct mtk_base_afe *afe) 2582 { 2583 struct mtk_base_afe_dai *dai; 2584 int ret; 2585 2586 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 2587 if (!dai) 2588 return -ENOMEM; 2589 2590 dai->dai_drivers = mtk_dai_i2s_driver; 2591 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_i2s_driver); 2592 2593 dai->controls = mtk_dai_i2s_controls; 2594 dai->num_controls = ARRAY_SIZE(mtk_dai_i2s_controls); 2595 dai->dapm_widgets = mtk_dai_i2s_widgets; 2596 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_i2s_widgets); 2597 dai->dapm_routes = mtk_dai_i2s_routes; 2598 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_i2s_routes); 2599 2600 /* set all dai i2s private data */ 2601 ret = init_i2s_priv_data(afe); 2602 if (ret) 2603 return ret; 2604 2605 /* parse share i2s */ 2606 ret = mt8196_dai_i2s_get_share(afe); 2607 if (ret) 2608 return ret; 2609 2610 list_add(&dai->list, &afe->sub_dais); 2611 2612 return 0; 2613 } 2614