1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek ALSA SoC Audio DAI ADDA Control 4 * 5 * Copyright (c) 2025 MediaTek Inc. 6 * Author: Darren Ye <darren.ye@mediatek.com> 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/regmap.h> 11 12 #include "mt8196-afe-clk.h" 13 #include "mt8196-afe-common.h" 14 #include "mt8196-interconnection.h" 15 16 enum { 17 UL_IIR_SW, 18 UL_IIR_5HZ, 19 UL_IIR_10HZ, 20 UL_IIR_25HZ, 21 UL_IIR_50HZ, 22 UL_IIR_75HZ, 23 }; 24 25 enum { 26 MTK_AFE_ADDA_UL_RATE_8K, 27 MTK_AFE_ADDA_UL_RATE_16K, 28 MTK_AFE_ADDA_UL_RATE_32K, 29 MTK_AFE_ADDA_UL_RATE_48K, 30 MTK_AFE_ADDA_UL_RATE_96K, 31 MTK_AFE_ADDA_UL_RATE_192K, 32 MTK_AFE_ADDA_UL_RATE_48K_HD, 33 }; 34 35 enum { 36 MTK_AFE_MTKAIF_RATE_8K, 37 MTK_AFE_MTKAIF_RATE_12K, 38 MTK_AFE_MTKAIF_RATE_16K, 39 MTK_AFE_MTKAIF_RATE_24K, 40 MTK_AFE_MTKAIF_RATE_32K, 41 MTK_AFE_MTKAIF_RATE_48K, 42 MTK_AFE_MTKAIF_RATE_64K, 43 MTK_AFE_MTKAIF_RATE_96K, 44 MTK_AFE_MTKAIF_RATE_128K, 45 MTK_AFE_MTKAIF_RATE_192K, 46 MTK_AFE_MTKAIF_RATE_256K, 47 MTK_AFE_MTKAIF_RATE_384K, 48 MTK_AFE_MTKAIF_RATE_11K = 0x10, 49 MTK_AFE_MTKAIF_RATE_22K, 50 MTK_AFE_MTKAIF_RATE_44K, 51 MTK_AFE_MTKAIF_RATE_88K, 52 MTK_AFE_MTKAIF_RATE_176K, 53 MTK_AFE_MTKAIF_RATE_352K, 54 }; 55 56 struct mtk_afe_adda_priv { 57 int dl_rate; 58 int ul_rate; 59 }; 60 61 static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe, 62 unsigned int rate) 63 { 64 switch (rate) { 65 case 8000: 66 return MTK_AFE_ADDA_UL_RATE_8K; 67 case 16000: 68 return MTK_AFE_ADDA_UL_RATE_16K; 69 case 32000: 70 return MTK_AFE_ADDA_UL_RATE_32K; 71 case 48000: 72 return MTK_AFE_ADDA_UL_RATE_48K; 73 case 96000: 74 return MTK_AFE_ADDA_UL_RATE_96K; 75 case 192000: 76 return MTK_AFE_ADDA_UL_RATE_192K; 77 default: 78 dev_warn(afe->dev, "rate %d invalid, use 48kHz!!!\n", rate); 79 return MTK_AFE_ADDA_UL_RATE_48K; 80 } 81 } 82 83 static unsigned int mtkaif_rate_transform(struct mtk_base_afe *afe, 84 unsigned int rate) 85 { 86 switch (rate) { 87 case 8000: 88 return MTK_AFE_MTKAIF_RATE_8K; 89 case 11025: 90 return MTK_AFE_MTKAIF_RATE_11K; 91 case 12000: 92 return MTK_AFE_MTKAIF_RATE_12K; 93 case 16000: 94 return MTK_AFE_MTKAIF_RATE_16K; 95 case 22050: 96 return MTK_AFE_MTKAIF_RATE_22K; 97 case 24000: 98 return MTK_AFE_MTKAIF_RATE_24K; 99 case 32000: 100 return MTK_AFE_MTKAIF_RATE_32K; 101 case 44100: 102 return MTK_AFE_MTKAIF_RATE_44K; 103 case 48000: 104 return MTK_AFE_MTKAIF_RATE_48K; 105 case 96000: 106 return MTK_AFE_MTKAIF_RATE_96K; 107 case 192000: 108 return MTK_AFE_MTKAIF_RATE_192K; 109 default: 110 dev_warn(afe->dev, "rate %d invalid, use 48kHz!!!\n", rate); 111 return MTK_AFE_MTKAIF_RATE_48K; 112 } 113 } 114 115 enum { 116 SUPPLY_SEQ_ADDA_AFE_ON, 117 SUPPLY_SEQ_ADDA_FIFO, 118 SUPPLY_SEQ_ADDA_AP_DMIC, 119 SUPPLY_SEQ_ADDA_UL_ON, 120 }; 121 122 static int mtk_adda_ul_src_set_dmic_phase_sync(struct mtk_base_afe *afe) 123 { 124 dev_dbg(afe->dev, "set dmic phase sync\n"); 125 // ul0~1 126 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1, 127 UL0_PHASE_SYNC_HCLK_SET_MASK_SFT, 128 0x1 << UL0_PHASE_SYNC_HCLK_SET_SFT); 129 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1, 130 UL0_PHASE_SYNC_FCLK_SET_MASK_SFT, 131 0x1 << UL0_PHASE_SYNC_FCLK_SET_SFT); 132 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1, 133 UL1_PHASE_SYNC_HCLK_SET_MASK_SFT, 134 0x1 << UL1_PHASE_SYNC_HCLK_SET_SFT); 135 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1, 136 UL1_PHASE_SYNC_FCLK_SET_MASK_SFT, 137 0x1 << UL1_PHASE_SYNC_FCLK_SET_SFT); 138 // dmic 0 139 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1, 140 DMIC0_PHASE_SYNC_FCLK_SET_MASK_SFT, 141 0x1 << DMIC0_PHASE_SYNC_FCLK_SET_SFT); 142 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1, 143 DMIC0_PHASE_SYNC_HCLK_SET_MASK_SFT, 144 0x1 << DMIC0_PHASE_SYNC_HCLK_SET_SFT); 145 // dmic 1 146 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1, 147 DMIC1_PHASE_SYNC_FCLK_SET_MASK_SFT, 148 0x1 << DMIC1_PHASE_SYNC_FCLK_SET_SFT); 149 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1, 150 DMIC1_PHASE_SYNC_HCLK_SET_MASK_SFT, 151 0x1 << DMIC1_PHASE_SYNC_HCLK_SET_SFT); 152 // ul0~1 phase sync clock 153 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, 154 DMIC1_PHASE_HCLK_SEL_MASK_SFT, 155 0x1 << DMIC1_PHASE_HCLK_SEL_SFT); 156 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, 157 DMIC1_PHASE_FCLK_SEL_MASK_SFT, 158 0x1 << DMIC1_PHASE_FCLK_SEL_SFT); 159 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, 160 DMIC0_PHASE_HCLK_SEL_MASK_SFT, 161 0x1 << DMIC0_PHASE_HCLK_SEL_SFT); 162 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, 163 DMIC0_PHASE_FCLK_SEL_MASK_SFT, 164 0x1 << DMIC0_PHASE_FCLK_SEL_SFT); 165 // dmic 0 166 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, 167 UL1_PHASE_HCLK_SEL_MASK_SFT, 168 0x2 << UL1_PHASE_HCLK_SEL_SFT); 169 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, 170 UL1_PHASE_FCLK_SEL_MASK_SFT, 171 0x2 << UL1_PHASE_FCLK_SEL_SFT); 172 // dmic 1 173 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, 174 UL0_PHASE_HCLK_SEL_MASK_SFT, 175 0x2 << UL0_PHASE_HCLK_SEL_SFT); 176 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, 177 UL0_PHASE_FCLK_SEL_MASK_SFT, 178 0x2 << UL0_PHASE_FCLK_SEL_SFT); 179 180 return 0; 181 } 182 183 static int mtk_adda_ul_src_set_dmic_phase_sync_clock(struct mtk_base_afe *afe) 184 { 185 dev_dbg(afe->dev, "dmic turn on phase sync clk\n"); 186 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, 187 UL_PHASE_SYNC_HCLK_1_ON_MASK_SFT, 188 0x1 << UL_PHASE_SYNC_HCLK_1_ON_SFT); 189 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, 190 UL_PHASE_SYNC_HCLK_0_ON_MASK_SFT, 191 0x1 << UL_PHASE_SYNC_HCLK_0_ON_SFT); 192 193 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, 194 UL_PHASE_SYNC_FCLK_1_ON_MASK_SFT, 195 0x1 << UL_PHASE_SYNC_FCLK_1_ON_SFT); 196 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON0, 197 UL_PHASE_SYNC_FCLK_0_ON_MASK_SFT, 198 0x1 << UL_PHASE_SYNC_FCLK_0_ON_SFT); 199 200 return 0; 201 } 202 203 static int mtk_adda_ul_src_enable_dmic(struct mtk_base_afe *afe, int id) 204 { 205 unsigned int reg_con0 = 0, reg_con1 = 0; 206 207 dev_dbg(afe->dev, "id: %d\n", id); 208 209 switch (id) { 210 case MT8196_DAI_ADDA: 211 case MT8196_DAI_AP_DMIC: 212 reg_con0 = AFE_ADDA_UL0_SRC_CON0; 213 reg_con1 = AFE_ADDA_UL0_SRC_CON1; 214 break; 215 case MT8196_DAI_ADDA_CH34: 216 case MT8196_DAI_AP_DMIC_CH34: 217 reg_con0 = AFE_ADDA_UL1_SRC_CON0; 218 reg_con1 = AFE_ADDA_UL1_SRC_CON1; 219 break; 220 default: 221 return -EINVAL; 222 } 223 224 switch (id) { 225 case MT8196_DAI_AP_DMIC: 226 dev_dbg(afe->dev, "clear mtkaifv4 ul ch1ch2 mux\n"); 227 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, 228 MTKAIFV4_UL_CH1CH2_IN_EN_SEL_MASK_SFT, 229 0x0 << MTKAIFV4_UL_CH1CH2_IN_EN_SEL_SFT); 230 break; 231 case MT8196_DAI_AP_DMIC_CH34: 232 dev_dbg(afe->dev, "clear mtkaifv4 ul ch3ch4 mux\n"); 233 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, 234 MTKAIFV4_UL_CH3CH4_IN_EN_SEL_MASK_SFT, 235 0x0 << MTKAIFV4_UL_CH3CH4_IN_EN_SEL_SFT); 236 break; 237 default: 238 return -EINVAL; 239 } 240 241 /* choose Phase */ 242 regmap_update_bits(afe->regmap, reg_con0, 243 UL_DMIC_PHASE_SEL_CH1_MASK_SFT, 244 0x0 << UL_DMIC_PHASE_SEL_CH1_SFT); 245 regmap_update_bits(afe->regmap, reg_con0, 246 UL_DMIC_PHASE_SEL_CH2_MASK_SFT, 247 0x4 << UL_DMIC_PHASE_SEL_CH2_SFT); 248 249 /* dmic mode, 3.25M*/ 250 regmap_update_bits(afe->regmap, reg_con0, 251 DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT, 252 0x0); 253 regmap_update_bits(afe->regmap, reg_con0, 254 DMIC_LOW_POWER_MODE_CTL_MASK_SFT, 255 0x0); 256 257 /* turn on dmic, ch1, ch2 */ 258 regmap_update_bits(afe->regmap, reg_con0, 259 UL_SDM_3_LEVEL_CTL_MASK_SFT, 260 0x1 << UL_SDM_3_LEVEL_CTL_SFT); 261 regmap_update_bits(afe->regmap, reg_con0, 262 UL_MODE_3P25M_CH1_CTL_MASK_SFT, 263 0x1 << UL_MODE_3P25M_CH1_CTL_SFT); 264 regmap_update_bits(afe->regmap, reg_con0, 265 UL_MODE_3P25M_CH2_CTL_MASK_SFT, 266 0x1 << UL_MODE_3P25M_CH2_CTL_SFT); 267 268 /* ul gain: gain = 0x7fff/positive_gain = 0x0/gain_mode = 0x10 */ 269 regmap_update_bits(afe->regmap, reg_con1, 270 ADDA_UL_GAIN_VALUE_MASK_SFT, 271 0x7fff << ADDA_UL_GAIN_VALUE_SFT); 272 regmap_update_bits(afe->regmap, reg_con1, 273 ADDA_UL_POSTIVEGAIN_MASK_SFT, 274 0x0 << ADDA_UL_POSTIVEGAIN_SFT); 275 /* gain_mode = 0x10: Add 0.5 gain at CIC output */ 276 regmap_update_bits(afe->regmap, reg_con1, 277 GAIN_MODE_MASK_SFT, 278 0x02 << GAIN_MODE_SFT); 279 return 0; 280 } 281 282 static int mtk_adda_sleep_on_pmd_event(struct snd_soc_dapm_widget *w, 283 struct snd_kcontrol *kcontrol, int event) 284 { 285 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 286 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 287 288 dev_dbg(afe->dev, "name %s, event 0x%x\n", w->name, event); 289 290 switch (event) { 291 case SND_SOC_DAPM_PRE_PMU: 292 break; 293 case SND_SOC_DAPM_POST_PMD: 294 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 295 usleep_range(120, 130); 296 break; 297 default: 298 break; 299 } 300 301 return 0; 302 } 303 304 /* ADDA UL MUX */ 305 #define ADDA_UL_MUX_MASK 0x3 306 enum { 307 ADDA_UL_MUX_MTKAIF = 0, 308 ADDA_UL_MUX_AP_DMIC, 309 ADDA_UL_MUX_AP_DMIC_MULTICH, 310 }; 311 312 static const char *const adda_ul_mux_map[] = { 313 "MTKAIF", "AP_DMIC", "AP_DMIC_MULTI_CH", 314 }; 315 316 static int adda_ul_map_value[] = { 317 ADDA_UL_MUX_MTKAIF, 318 ADDA_UL_MUX_AP_DMIC, 319 ADDA_UL_MUX_AP_DMIC_MULTICH, 320 }; 321 322 static SOC_VALUE_ENUM_SINGLE_DECL(adda_ul_mux_map_enum, 323 SND_SOC_NOPM, 324 0, 325 ADDA_UL_MUX_MASK, 326 adda_ul_mux_map, 327 adda_ul_map_value); 328 329 static const struct snd_kcontrol_new adda_ul_mux_control = 330 SOC_DAPM_ENUM("ADDA_UL_MUX Select", adda_ul_mux_map_enum); 331 332 static const struct snd_kcontrol_new adda_ch34_ul_mux_control = 333 SOC_DAPM_ENUM("ADDA_CH34_UL_MUX Select", adda_ul_mux_map_enum); 334 335 static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = { 336 /* inter-connections */ 337 SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON, 338 AUDIO_ENGEN_CON0, AUDIO_F3P25M_EN_ON_SFT, 0, 339 NULL, 0), 340 SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON, 341 AFE_ADDA_UL0_SRC_CON0, 342 UL_SRC_ON_TMP_CTL_SFT, 0, 343 mtk_adda_sleep_on_pmd_event, 344 SND_SOC_DAPM_POST_PMD), 345 SND_SOC_DAPM_SUPPLY_S("ADDA CH34 Capture Enable", SUPPLY_SEQ_ADDA_UL_ON, 346 AFE_ADDA_UL1_SRC_CON0, 347 UL_SRC_ON_TMP_CTL_SFT, 0, 348 mtk_adda_sleep_on_pmd_event, 349 SND_SOC_DAPM_POST_PMD), 350 SND_SOC_DAPM_SUPPLY_S("AP_DMIC_EN", SUPPLY_SEQ_ADDA_AP_DMIC, 351 AFE_ADDA_UL0_SRC_CON0, 352 UL_AP_DMIC_ON_SFT, 0, 353 mtk_adda_sleep_on_pmd_event, 354 SND_SOC_DAPM_POST_PMD), 355 SND_SOC_DAPM_SUPPLY_S("AP_DMIC_CH34_EN", SUPPLY_SEQ_ADDA_AP_DMIC, 356 AFE_ADDA_UL1_SRC_CON0, 357 UL_AP_DMIC_ON_SFT, 0, 358 mtk_adda_sleep_on_pmd_event, 359 SND_SOC_DAPM_POST_PMD), 360 SND_SOC_DAPM_SUPPLY_S("ADDA_FIFO", SUPPLY_SEQ_ADDA_FIFO, 361 AFE_ADDA_UL0_SRC_CON1, 362 FIFO_SOFT_RST_SFT, 1, 363 NULL, 0), 364 SND_SOC_DAPM_SUPPLY_S("ADDA_CH34_FIFO", SUPPLY_SEQ_ADDA_FIFO, 365 AFE_ADDA_UL1_SRC_CON1, 366 FIFO_SOFT_RST_SFT, 1, 367 NULL, 0), 368 SND_SOC_DAPM_MUX("ADDA_UL_Mux", SND_SOC_NOPM, 0, 0, 369 &adda_ul_mux_control), 370 SND_SOC_DAPM_MUX("ADDA_CH34_UL_Mux", SND_SOC_NOPM, 0, 0, 371 &adda_ch34_ul_mux_control), 372 SND_SOC_DAPM_INPUT("AP_DMIC_INPUT"), 373 }; 374 375 static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = { 376 /* capture */ 377 {"ADDA_UL_Mux", "MTKAIF", "ADDA Capture"}, 378 {"ADDA_UL_Mux", "AP_DMIC", "AP DMIC Capture"}, 379 {"ADDA_UL_Mux", "AP_DMIC_MULTI_CH", "AP DMIC MULTICH Capture"}, 380 381 {"ADDA_CH34_UL_Mux", "MTKAIF", "ADDA CH34 Capture"}, 382 {"ADDA_CH34_UL_Mux", "AP_DMIC", "AP DMIC CH34 Capture"}, 383 {"ADDA_CH34_UL_Mux", "AP_DMIC_MULTI_CH", "AP DMIC MULTICH Capture"}, 384 385 {"AP DMIC Capture", NULL, "ADDA Enable"}, 386 {"AP DMIC Capture", NULL, "ADDA Capture Enable"}, 387 {"AP DMIC Capture", NULL, "ADDA_FIFO"}, 388 {"AP DMIC Capture", NULL, "AP_DMIC_EN"}, 389 390 {"AP DMIC CH34 Capture", NULL, "ADDA Enable"}, 391 {"AP DMIC CH34 Capture", NULL, "ADDA CH34 Capture Enable"}, 392 {"AP DMIC CH34 Capture", NULL, "ADDA_CH34_FIFO"}, 393 {"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_EN"}, 394 395 {"AP DMIC MULTICH Capture", NULL, "ADDA Enable"}, 396 {"AP DMIC MULTICH Capture", NULL, "ADDA Capture Enable"}, 397 {"AP DMIC MULTICH Capture", NULL, "ADDA CH34 Capture Enable"}, 398 {"AP DMIC MULTICH Capture", NULL, "ADDA_FIFO"}, 399 {"AP DMIC MULTICH Capture", NULL, "ADDA_CH34_FIFO"}, 400 {"AP DMIC MULTICH Capture", NULL, "AP_DMIC_EN"}, 401 {"AP DMIC MULTICH Capture", NULL, "AP_DMIC_CH34_EN"}, 402 403 {"AP DMIC Capture", NULL, "AP_DMIC_INPUT"}, 404 {"AP DMIC CH34 Capture", NULL, "AP_DMIC_INPUT"}, 405 {"AP DMIC MULTICH Capture", NULL, "AP_DMIC_INPUT"}, 406 }; 407 408 /* dai ops */ 409 static int set_playback_hw_params(struct snd_pcm_hw_params *params, 410 struct snd_soc_dai *dai) 411 { 412 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 413 struct mt8196_afe_private *afe_priv = afe->platform_priv; 414 unsigned int rate = params_rate(params); 415 struct mtk_afe_adda_priv *adda_priv; 416 unsigned int mtkaif_rate = 0; 417 int id = dai->id; 418 419 adda_priv = afe_priv->dai_priv[id]; 420 if (!adda_priv) 421 return -EINVAL; 422 423 adda_priv->dl_rate = rate; 424 425 /* get mtkaif dl rate */ 426 mtkaif_rate = mtkaif_rate_transform(afe, adda_priv->dl_rate); 427 428 if (id == MT8196_DAI_ADDA) { 429 /* MTKAIF sample rate config */ 430 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_TX_CFG0, 431 MTKAIFV4_TXIF_INPUT_MODE_MASK_SFT, 432 mtkaif_rate << MTKAIFV4_TXIF_INPUT_MODE_SFT); 433 /* AFE_ADDA_MTKAIFV4_TX_CFG0 */ 434 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_TX_CFG0, 435 MTKAIFV4_TXIF_FOUR_CHANNEL_MASK_SFT, 436 0x0 << MTKAIFV4_TXIF_FOUR_CHANNEL_SFT); 437 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_TX_CFG0, 438 MTKAIFV4_ADDA_OUT_EN_SEL_MASK_SFT, 439 0x1 << MTKAIFV4_ADDA_OUT_EN_SEL_SFT); 440 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_TX_CFG0, 441 MTKAIFV4_ADDA6_OUT_EN_SEL_MASK_SFT, 442 0x1 << MTKAIFV4_ADDA6_OUT_EN_SEL_SFT); 443 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_TX_CFG0, 444 MTKAIFV4_TXIF_V4_MASK_SFT, 445 0x1 << MTKAIFV4_TXIF_V4_SFT); 446 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_TX_CFG0, 447 MTKAIFV4_TXIF_EN_SEL_MASK_SFT, 448 0x0 << MTKAIFV4_TXIF_EN_SEL_SFT); 449 /* clean predistortion */ 450 } else { 451 /* MTKAIF sample rate config */ 452 regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_TX_CFG0, 453 ADDA6_MTKAIFV4_TXIF_INPUT_MODE_MASK_SFT, 454 mtkaif_rate << ADDA6_MTKAIFV4_TXIF_INPUT_MODE_SFT); 455 /* AFE_ADDA6_MTKAIFV4_TX_CFG0 */ 456 regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_TX_CFG0, 457 ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_MASK_SFT, 458 0x0 << ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_SFT); 459 regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_TX_CFG0, 460 ADDA6_MTKAIFV4_TXIF_EN_SEL_MASK_SFT, 461 0x1 << ADDA6_MTKAIFV4_TXIF_EN_SEL_SFT); 462 } 463 464 return 0; 465 }; 466 467 static int set_capture_hw_params(struct snd_pcm_hw_params *params, 468 struct snd_soc_dai *dai) 469 { 470 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 471 struct mt8196_afe_private *afe_priv = afe->platform_priv; 472 unsigned int rate = params_rate(params); 473 struct mtk_afe_adda_priv *adda_priv; 474 unsigned int voice_mode = 0; 475 unsigned int ul_src_con0 = 0; 476 unsigned int mtkaif_rate = 0; 477 int id = dai->id; 478 479 adda_priv = afe_priv->dai_priv[id]; 480 if (!adda_priv) 481 return -EINVAL; 482 483 adda_priv->ul_rate = rate; 484 485 /* get mtkaif dl rate */ 486 mtkaif_rate = mtkaif_rate_transform(afe, adda_priv->ul_rate); 487 488 voice_mode = adda_ul_rate_transform(afe, rate); 489 490 ul_src_con0 |= (voice_mode << 17) & (0x7 << 17); 491 492 /* enable iir */ 493 ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) & 494 UL_IIR_ON_TMP_CTL_MASK_SFT; 495 ul_src_con0 |= (UL_IIR_SW << UL_IIRMODE_CTL_SFT) & 496 UL_IIRMODE_CTL_MASK_SFT; 497 498 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, 499 MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT, 500 mtkaif_rate << MTKAIFV4_RXIF_INPUT_MODE_SFT); 501 502 regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_RX_CFG0, 503 ADDA6_MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT, 504 mtkaif_rate << ADDA6_MTKAIFV4_RXIF_INPUT_MODE_SFT); 505 506 switch (id) { 507 case MT8196_DAI_ADDA: 508 case MT8196_DAI_AP_DMIC: 509 case MT8196_DAI_AP_DMIC_MULTICH: 510 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, 511 MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT, 512 mtkaif_rate << MTKAIFV4_RXIF_INPUT_MODE_SFT); 513 /* AFE_ADDA_MTKAIFV4_RX_CFG0 */ 514 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, 515 MTKAIFV4_RXIF_FOUR_CHANNEL_MASK_SFT, 516 0x1 << MTKAIFV4_RXIF_FOUR_CHANNEL_SFT); 517 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, 518 MTKAIFV4_RXIF_EN_SEL_MASK_SFT, 519 0x0 << MTKAIFV4_RXIF_EN_SEL_SFT); 520 /* [28] loopback mode 521 * 0: loopback adda tx to adda rx 522 * 1: loopback adda6 tx to adda rx 523 */ 524 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, 525 MTKAIFV4_TXIF_EN_SEL_MASK_SFT, 526 0x0 << MTKAIFV4_TXIF_EN_SEL_SFT); 527 528 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, 529 MTKAIFV4_UL_CH1CH2_IN_EN_SEL_MASK_SFT, 530 0x1 << MTKAIFV4_UL_CH1CH2_IN_EN_SEL_SFT); 531 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, 532 MTKAIFV4_UL_CH3CH4_IN_EN_SEL_MASK_SFT, 533 0x1 << MTKAIFV4_UL_CH3CH4_IN_EN_SEL_SFT); 534 535 /* 35Hz @ 48k */ 536 regmap_write(afe->regmap, 537 AFE_ADDA_UL1_IIR_COEF_02_01, 0x00000000); 538 regmap_write(afe->regmap, 539 AFE_ADDA_UL1_IIR_COEF_04_03, 0x00003FB8); 540 regmap_write(afe->regmap, 541 AFE_ADDA_UL1_IIR_COEF_06_05, 0x3FB80000); 542 regmap_write(afe->regmap, 543 AFE_ADDA_UL1_IIR_COEF_08_07, 0x3FB80000); 544 regmap_write(afe->regmap, 545 AFE_ADDA_UL1_IIR_COEF_10_09, 0x0000C048); 546 547 regmap_write(afe->regmap, 548 AFE_ADDA_UL1_SRC_CON0, ul_src_con0); 549 550 /* mtkaif_rxif_data_mode = 0, amic */ 551 regmap_update_bits(afe->regmap, 552 AFE_MTKAIF1_RX_CFG0, 553 0x1 << 0, 554 0x0 << 0); 555 556 /* 35Hz @ 48k */ 557 regmap_write(afe->regmap, 558 AFE_ADDA_UL0_IIR_COEF_02_01, 0x00000000); 559 regmap_write(afe->regmap, 560 AFE_ADDA_UL0_IIR_COEF_04_03, 0x00003FB8); 561 regmap_write(afe->regmap, 562 AFE_ADDA_UL0_IIR_COEF_06_05, 0x3FB80000); 563 regmap_write(afe->regmap, 564 AFE_ADDA_UL0_IIR_COEF_08_07, 0x3FB80000); 565 regmap_write(afe->regmap, 566 AFE_ADDA_UL0_IIR_COEF_10_09, 0x0000C048); 567 568 regmap_write(afe->regmap, 569 AFE_ADDA_UL0_SRC_CON0, ul_src_con0); 570 571 /* mtkaif_rxif_data_mode = 0, amic */ 572 regmap_update_bits(afe->regmap, 573 AFE_MTKAIF0_RX_CFG0, 574 0x1 << 0, 575 0x0 << 0); 576 break; 577 case MT8196_DAI_ADDA_CH34: 578 case MT8196_DAI_AP_DMIC_CH34: 579 /* AFE_ADDA_MTKAIFV4_RX_CFG0 */ 580 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, 581 MTKAIFV4_RXIF_FOUR_CHANNEL_MASK_SFT, 582 0x1 << MTKAIFV4_RXIF_FOUR_CHANNEL_SFT); 583 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, 584 MTKAIFV4_RXIF_EN_SEL_MASK_SFT, 585 0x0 << MTKAIFV4_RXIF_EN_SEL_SFT); 586 587 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, 588 MTKAIFV4_UL_CH1CH2_IN_EN_SEL_MASK_SFT, 589 0x1 << MTKAIFV4_UL_CH1CH2_IN_EN_SEL_SFT); 590 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, 591 MTKAIFV4_UL_CH3CH4_IN_EN_SEL_MASK_SFT, 592 0x1 << MTKAIFV4_UL_CH3CH4_IN_EN_SEL_SFT); 593 594 /* 35Hz @ 48k */ 595 regmap_write(afe->regmap, 596 AFE_ADDA_UL1_IIR_COEF_02_01, 0x00000000); 597 regmap_write(afe->regmap, 598 AFE_ADDA_UL1_IIR_COEF_04_03, 0x00003FB8); 599 regmap_write(afe->regmap, 600 AFE_ADDA_UL1_IIR_COEF_06_05, 0x3FB80000); 601 regmap_write(afe->regmap, 602 AFE_ADDA_UL1_IIR_COEF_08_07, 0x3FB80000); 603 regmap_write(afe->regmap, 604 AFE_ADDA_UL1_IIR_COEF_10_09, 0x0000C048); 605 606 regmap_write(afe->regmap, 607 AFE_ADDA_UL1_SRC_CON0, ul_src_con0); 608 609 /* mtkaif_rxif_data_mode = 0, amic */ 610 regmap_update_bits(afe->regmap, 611 AFE_MTKAIF1_RX_CFG0, 612 0x1 << 0, 613 0x0 << 0); 614 break; 615 case MT8196_DAI_ADDA_CH56: 616 regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_RX_CFG0, 617 ADDA6_MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT, 618 mtkaif_rate << ADDA6_MTKAIFV4_RXIF_INPUT_MODE_SFT); 619 /* AFE_ADDA6_MTKAIFV4_RX_CFG0 */ 620 regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_RX_CFG0, 621 ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_MASK_SFT, 622 0x1 << ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_SFT); 623 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIFV4_RX_CFG0, 624 MTKAIFV4_UL_CH5CH6_IN_EN_SEL_MASK_SFT, 625 0x1 << MTKAIFV4_UL_CH5CH6_IN_EN_SEL_SFT); 626 regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIFV4_RX_CFG0, 627 ADDA6_MTKAIFV4_RXIF_EN_SEL_MASK_SFT, 628 0x1 << ADDA6_MTKAIFV4_RXIF_EN_SEL_SFT); 629 break; 630 default: 631 break; 632 } 633 634 /* ap dmic */ 635 switch (id) { 636 case MT8196_DAI_AP_DMIC: 637 case MT8196_DAI_AP_DMIC_CH34: 638 mtk_adda_ul_src_enable_dmic(afe, id); 639 break; 640 case MT8196_DAI_AP_DMIC_MULTICH: 641 regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1, 642 DMIC_CLK_PHASE_SYNC_SET_MASK_SFT, 643 0x1 << DMIC_CLK_PHASE_SYNC_SET_SFT); 644 mtk_adda_ul_src_set_dmic_phase_sync(afe); 645 mtk_adda_ul_src_enable_dmic(afe, MT8196_DAI_AP_DMIC); 646 mtk_adda_ul_src_enable_dmic(afe, MT8196_DAI_AP_DMIC_CH34); 647 mtk_adda_ul_src_set_dmic_phase_sync_clock(afe); 648 break; 649 default: 650 break; 651 } 652 653 return 0; 654 }; 655 656 static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream, 657 struct snd_pcm_hw_params *params, 658 struct snd_soc_dai *dai) 659 { 660 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 661 int id = dai->id; 662 663 if (id >= MT8196_DAI_NUM || id < 0) 664 return -EINVAL; 665 666 dev_dbg(afe->dev, "id %d, stream %d, rate %d\n", 667 id, substream->stream, params_rate(params)); 668 669 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 670 return set_playback_hw_params(params, dai); 671 else 672 return set_capture_hw_params(params, dai); 673 674 return 0; 675 } 676 677 static const struct snd_soc_dai_ops mtk_dai_adda_ops = { 678 .hw_params = mtk_dai_adda_hw_params, 679 }; 680 681 /* dai driver */ 682 #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\ 683 SNDRV_PCM_RATE_96000 |\ 684 SNDRV_PCM_RATE_192000) 685 686 #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 687 SNDRV_PCM_RATE_16000 |\ 688 SNDRV_PCM_RATE_32000 |\ 689 SNDRV_PCM_RATE_48000 |\ 690 SNDRV_PCM_RATE_96000 |\ 691 SNDRV_PCM_RATE_192000) 692 693 #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 694 SNDRV_PCM_FMTBIT_S24_LE |\ 695 SNDRV_PCM_FMTBIT_S32_LE) 696 697 static struct snd_soc_dai_driver mtk_dai_adda_driver[] = { 698 { 699 .name = "ADDA", 700 .id = MT8196_DAI_ADDA, 701 .playback = { 702 .stream_name = "ADDA Playback", 703 .channels_min = 1, 704 .channels_max = 2, 705 .rates = MTK_ADDA_PLAYBACK_RATES, 706 .formats = MTK_ADDA_FORMATS, 707 }, 708 .capture = { 709 .stream_name = "ADDA Capture", 710 .channels_min = 1, 711 .channels_max = 2, 712 .rates = MTK_ADDA_CAPTURE_RATES, 713 .formats = MTK_ADDA_FORMATS, 714 }, 715 .ops = &mtk_dai_adda_ops, 716 }, 717 { 718 .name = "ADDA_CH34", 719 .id = MT8196_DAI_ADDA_CH34, 720 .playback = { 721 .stream_name = "ADDA CH34 Playback", 722 .channels_min = 1, 723 .channels_max = 2, 724 .rates = MTK_ADDA_PLAYBACK_RATES, 725 .formats = MTK_ADDA_FORMATS, 726 }, 727 .capture = { 728 .stream_name = "ADDA CH34 Capture", 729 .channels_min = 1, 730 .channels_max = 2, 731 .rates = MTK_ADDA_CAPTURE_RATES, 732 .formats = MTK_ADDA_FORMATS, 733 }, 734 .ops = &mtk_dai_adda_ops, 735 }, 736 { 737 .name = "ADDA_CH56", 738 .id = MT8196_DAI_ADDA_CH56, 739 .capture = { 740 .stream_name = "ADDA CH56 Capture", 741 .channels_min = 1, 742 .channels_max = 2, 743 .rates = MTK_ADDA_CAPTURE_RATES, 744 .formats = MTK_ADDA_FORMATS, 745 }, 746 .ops = &mtk_dai_adda_ops, 747 }, 748 { 749 .name = "AP_DMIC", 750 .id = MT8196_DAI_AP_DMIC, 751 .capture = { 752 .stream_name = "AP DMIC Capture", 753 .channels_min = 1, 754 .channels_max = 2, 755 .rates = MTK_ADDA_CAPTURE_RATES, 756 .formats = MTK_ADDA_FORMATS, 757 }, 758 .ops = &mtk_dai_adda_ops, 759 }, 760 { 761 .name = "AP_DMIC_CH34", 762 .id = MT8196_DAI_AP_DMIC_CH34, 763 .capture = { 764 .stream_name = "AP DMIC CH34 Capture", 765 .channels_min = 1, 766 .channels_max = 2, 767 .rates = MTK_ADDA_CAPTURE_RATES, 768 .formats = MTK_ADDA_FORMATS, 769 }, 770 .ops = &mtk_dai_adda_ops, 771 }, 772 /* 773 * Multich DMIC combines two DMIC controllers for use together, 774 * so AP_DMIC and Multich DMIC cannot be used at the same time. 775 */ 776 { 777 .name = "AP_DMIC_MULTICH", 778 .id = MT8196_DAI_AP_DMIC_MULTICH, 779 .capture = { 780 .stream_name = "AP DMIC MULTICH Capture", 781 .channels_min = 1, 782 .channels_max = 4, 783 .rates = MTK_ADDA_CAPTURE_RATES, 784 .formats = MTK_ADDA_FORMATS, 785 }, 786 .ops = &mtk_dai_adda_ops, 787 }, 788 }; 789 790 static int init_adda_priv_data(struct mtk_base_afe *afe) 791 { 792 struct mt8196_afe_private *afe_priv = afe->platform_priv; 793 struct mtk_afe_adda_priv *adda_priv; 794 static const int adda_dai_list[] = { 795 MT8196_DAI_ADDA, 796 MT8196_DAI_ADDA_CH34, 797 MT8196_DAI_ADDA_CH56, 798 MT8196_DAI_AP_DMIC_MULTICH 799 }; 800 int i; 801 802 for (i = 0; i < ARRAY_SIZE(adda_dai_list); i++) { 803 adda_priv = devm_kzalloc(afe->dev, 804 sizeof(struct mtk_afe_adda_priv), 805 GFP_KERNEL); 806 if (!adda_priv) 807 return -ENOMEM; 808 809 afe_priv->dai_priv[adda_dai_list[i]] = adda_priv; 810 } 811 812 /* ap dmic priv share with adda */ 813 afe_priv->dai_priv[MT8196_DAI_AP_DMIC] = 814 afe_priv->dai_priv[MT8196_DAI_ADDA]; 815 afe_priv->dai_priv[MT8196_DAI_AP_DMIC_CH34] = 816 afe_priv->dai_priv[MT8196_DAI_ADDA_CH34]; 817 818 return 0; 819 } 820 821 int mt8196_dai_adda_register(struct mtk_base_afe *afe) 822 { 823 struct mtk_base_afe_dai *dai; 824 int ret; 825 826 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 827 if (!dai) 828 return -ENOMEM; 829 830 dai->dai_drivers = mtk_dai_adda_driver; 831 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver); 832 dai->dapm_widgets = mtk_dai_adda_widgets; 833 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets); 834 dai->dapm_routes = mtk_dai_adda_routes; 835 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes); 836 837 ret = init_adda_priv_data(afe); 838 if (ret) 839 return ret; 840 841 list_add(&dai->list, &afe->sub_dais); 842 843 return 0; 844 } 845 846