1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Mediatek ALSA SoC AFE platform driver for 8196 4 * 5 * Copyright (c) 2025 MediaTek Inc. 6 * Author: Darren Ye <darren.ye@mediatek.com> 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_address.h> 14 #include <linux/of_device.h> 15 #include <linux/of_reserved_mem.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 19 #include <sound/pcm.h> 20 #include <sound/soc.h> 21 22 #include "mt8196-afe-clk.h" 23 #include "mt8196-afe-common.h" 24 #include "mt8196-interconnection.h" 25 26 #include "../common/mtk-afe-fe-dai.h" 27 #include "../common/mtk-afe-platform-driver.h" 28 29 static const struct snd_pcm_hardware mt8196_afe_hardware = { 30 .info = (SNDRV_PCM_INFO_MMAP | 31 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP | 32 SNDRV_PCM_INFO_INTERLEAVED | 33 SNDRV_PCM_INFO_MMAP_VALID), 34 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 35 SNDRV_PCM_FMTBIT_S24_LE | 36 SNDRV_PCM_FMTBIT_S32_LE), 37 .period_bytes_min = 96, 38 .period_bytes_max = 4 * 48 * 1024, 39 .periods_min = 2, 40 .periods_max = 256, 41 .buffer_bytes_max = 256 * 1024, 42 .fifo_size = 0, 43 }; 44 45 static unsigned int mt8196_rate_transform(struct device *dev, 46 unsigned int rate) 47 { 48 switch (rate) { 49 case 8000: 50 return MTK_AFE_IPM2P0_RATE_8K; 51 case 11025: 52 return MTK_AFE_IPM2P0_RATE_11K; 53 case 12000: 54 return MTK_AFE_IPM2P0_RATE_12K; 55 case 16000: 56 return MTK_AFE_IPM2P0_RATE_16K; 57 case 22050: 58 return MTK_AFE_IPM2P0_RATE_22K; 59 case 24000: 60 return MTK_AFE_IPM2P0_RATE_24K; 61 case 32000: 62 return MTK_AFE_IPM2P0_RATE_32K; 63 case 44100: 64 return MTK_AFE_IPM2P0_RATE_44K; 65 case 48000: 66 return MTK_AFE_IPM2P0_RATE_48K; 67 case 88200: 68 return MTK_AFE_IPM2P0_RATE_88K; 69 case 96000: 70 return MTK_AFE_IPM2P0_RATE_96K; 71 case 176400: 72 return MTK_AFE_IPM2P0_RATE_176K; 73 case 192000: 74 return MTK_AFE_IPM2P0_RATE_192K; 75 /* not support 260K */ 76 case 352800: 77 return MTK_AFE_IPM2P0_RATE_352K; 78 case 384000: 79 return MTK_AFE_IPM2P0_RATE_384K; 80 default: 81 dev_err(dev, "rate %u invalid, use %d!!!\n", 82 rate, MTK_AFE_IPM2P0_RATE_48K); 83 return MTK_AFE_IPM2P0_RATE_48K; 84 } 85 } 86 87 static int mt8196_set_cm(struct mtk_base_afe *afe, int id, 88 bool update, bool swap, unsigned int ch) 89 { 90 struct mt8196_afe_private *afe_priv = afe->platform_priv; 91 unsigned int rate = afe_priv->cm_rate[id]; 92 unsigned int rate_val = mt8196_rate_transform(afe->dev, rate); 93 unsigned int ch_pair = ch / 2; 94 unsigned int update_val; 95 int reg = AFE_CM0_CON0 + 0x10 * id; 96 97 if (update && ch_pair) 98 update_val = (26000000 / rate - 10) / ch_pair - 1; 99 else 100 update_val = 0x64; 101 102 dev_dbg(afe->dev, "CM%d, rate %d, update %d, swap %d, ch %d, update_val: %d\n", 103 id, rate, update, swap, ch, update_val); 104 105 /* update cnt */ 106 regmap_update_bits(afe->regmap, reg, 107 AFE_CM_UPDATE_CNT_MASK << AFE_CM_UPDATE_CNT_SFT, 108 update_val << AFE_CM_UPDATE_CNT_SFT); 109 110 /* rate */ 111 regmap_update_bits(afe->regmap, reg, 112 AFE_CM_1X_EN_SEL_FS_MASK << AFE_CM_1X_EN_SEL_FS_SFT, 113 rate_val << AFE_CM_1X_EN_SEL_FS_SFT); 114 115 /* ch num */ 116 ch = ch - 1; 117 regmap_update_bits(afe->regmap, reg, 118 AFE_CM_CH_NUM_MASK << AFE_CM_CH_NUM_SFT, 119 ch << AFE_CM_CH_NUM_SFT); 120 121 /* swap */ 122 regmap_update_bits(afe->regmap, reg, 123 AFE_CM_BYTE_SWAP_MASK << AFE_CM_BYTE_SWAP_SFT, 124 swap << AFE_CM_BYTE_SWAP_SFT); 125 126 return 0; 127 } 128 129 static int mt8196_enable_cm_bypass(struct mtk_base_afe *afe, int id, bool en) 130 { 131 return regmap_update_bits(afe->regmap, 132 AFE_CM0_CON0 + 0x10 * id, 133 AFE_CM_BYPASS_MODE_MASK << AFE_CM_BYPASS_MODE_SFT, 134 en << AFE_CM_BYPASS_MODE_SFT); 135 } 136 137 static int mt8196_fe_startup(struct snd_pcm_substream *substream, 138 struct snd_soc_dai *dai) 139 { 140 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 141 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 142 struct snd_pcm_runtime *runtime = substream->runtime; 143 struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); 144 int memif_num = cpu_dai->id; 145 struct mtk_base_afe_memif *memif = &afe->memif[memif_num]; 146 const struct snd_pcm_hardware *mtk_afe_hardware = afe->mtk_afe_hardware; 147 int ret; 148 149 dev_dbg(afe->dev, "memif_num: %d.\n", memif_num); 150 151 memif->substream = substream; 152 153 snd_pcm_hw_constraint_step(substream->runtime, 0, 154 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 16); 155 156 if (memif_num == MT8196_MEMIF_VUL_CM0) 157 snd_pcm_hw_constraint_step(substream->runtime, 0, 158 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 16); 159 160 snd_soc_set_runtime_hwparams(substream, mtk_afe_hardware); 161 162 ret = snd_pcm_hw_constraint_integer(runtime, 163 SNDRV_PCM_HW_PARAM_PERIODS); 164 if (ret < 0) 165 dev_warn(afe->dev, "snd_pcm_hw_constraint_integer failed\n"); 166 167 /* dynamic allocate irq to memif */ 168 if (memif->irq_usage < 0) { 169 int irq_id = mtk_dynamic_irq_acquire(afe); 170 171 if (irq_id != afe->irqs_size) { 172 /* link */ 173 memif->irq_usage = irq_id; 174 } else { 175 dev_err(afe->dev, "no more asys irq\n"); 176 ret = -EBUSY; 177 } 178 } 179 return ret; 180 } 181 182 static void mt8196_fe_shutdown(struct snd_pcm_substream *substream, 183 struct snd_soc_dai *dai) 184 { 185 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 186 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 187 struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); 188 int memif_num = cpu_dai->id; 189 struct mtk_base_afe_memif *memif = &afe->memif[memif_num]; 190 int irq_id = memif->irq_usage; 191 192 dev_dbg(afe->dev, "memif_num: %d.\n", memif_num); 193 194 memif->substream = NULL; 195 196 if (!memif->const_irq) { 197 mtk_dynamic_irq_release(afe, irq_id); 198 memif->irq_usage = -1; 199 memif->substream = NULL; 200 } 201 } 202 203 static int mt8196_fe_hw_params(struct snd_pcm_substream *substream, 204 struct snd_pcm_hw_params *params, 205 struct snd_soc_dai *dai) 206 { 207 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 208 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 209 unsigned int channels = params_channels(params); 210 struct mt8196_afe_private *afe_priv = afe->platform_priv; 211 int id = snd_soc_rtd_to_cpu(rtd, 0)->id; 212 struct mtk_base_afe_memif *memif = &afe->memif[id]; 213 const struct mtk_base_memif_data *data = memif->data; 214 int cm; 215 216 afe_priv->cm_channels = channels; 217 218 /* set channels */ 219 if (data->ch_num_shift >= 0) { 220 regmap_update_bits(afe->regmap, data->ch_num_reg, 221 data->ch_num_maskbit << data->ch_num_shift, 222 channels << data->ch_num_shift); 223 } 224 225 switch (id) { 226 case MT8196_MEMIF_VUL8: 227 case MT8196_MEMIF_VUL_CM0: 228 cm = CM0; 229 break; 230 case MT8196_MEMIF_VUL9: 231 case MT8196_MEMIF_VUL_CM1: 232 cm = CM1; 233 break; 234 case MT8196_MEMIF_VUL10: 235 case MT8196_MEMIF_VUL_CM2: 236 cm = CM2; 237 break; 238 default: 239 cm = CM0; 240 break; 241 } 242 243 afe_priv->cm_rate[cm] = params_rate(params); 244 245 return mtk_afe_fe_hw_params(substream, params, dai); 246 } 247 248 static int mt8196_fe_trigger(struct snd_pcm_substream *substream, int cmd, 249 struct snd_soc_dai *dai) 250 { 251 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 252 struct snd_pcm_runtime *const runtime = substream->runtime; 253 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 254 int id = snd_soc_rtd_to_cpu(rtd, 0)->id; 255 struct mtk_base_afe_memif *memif = &afe->memif[id]; 256 int irq_id = memif->irq_usage; 257 struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id]; 258 const struct mtk_base_irq_data *irq_data = irqs->irq_data; 259 unsigned int counter = runtime->period_size; 260 unsigned int rate = runtime->rate; 261 unsigned int tmp_reg; 262 int fs; 263 int ret; 264 265 dev_dbg(afe->dev, "%s cmd %d, irq_id %d\n", memif->data->name, cmd, irq_id); 266 267 switch (cmd) { 268 case SNDRV_PCM_TRIGGER_START: 269 case SNDRV_PCM_TRIGGER_RESUME: 270 dev_dbg(afe->dev, "%s cmd %d, id %d\n", memif->data->name, cmd, id); 271 272 ret = mtk_memif_set_enable(afe, id); 273 if (ret) { 274 dev_err(afe->dev, "id %d, memif enable fail.\n", id); 275 return ret; 276 } 277 278 /* 279 * for small latency record 280 * ul memif need read some data before irq enable. 281 * the context of this ops triger is atmoic, so it cannot sleep. 282 */ 283 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 284 if ((runtime->period_size * 1000) / rate <= 10) 285 udelay(300); 286 287 regmap_update_bits(afe->regmap, 288 irq_data->irq_cnt_reg, 289 irq_data->irq_cnt_maskbit << irq_data->irq_cnt_shift, 290 counter << irq_data->irq_cnt_shift); 291 292 /* set irq fs */ 293 fs = afe->irq_fs(substream, rate); 294 if (fs < 0) 295 return -EINVAL; 296 297 if (irq_data->irq_fs_reg >= 0) 298 regmap_update_bits(afe->regmap, 299 irq_data->irq_fs_reg, 300 irq_data->irq_fs_maskbit << irq_data->irq_fs_shift, 301 fs << irq_data->irq_fs_shift); 302 303 /* enable interrupt */ 304 regmap_update_bits(afe->regmap, 305 irq_data->irq_en_reg, 306 1 << irq_data->irq_en_shift, 307 1 << irq_data->irq_en_shift); 308 309 return 0; 310 case SNDRV_PCM_TRIGGER_STOP: 311 case SNDRV_PCM_TRIGGER_SUSPEND: 312 ret = mtk_memif_set_disable(afe, id); 313 if (ret) 314 dev_warn(afe->dev, "id %d, memif disable fail\n", id); 315 316 /* disable interrupt */ 317 regmap_update_bits(afe->regmap, 318 irq_data->irq_en_reg, 319 1 << irq_data->irq_en_shift, 320 0 << irq_data->irq_en_shift); 321 322 /* 323 * clear pending IRQ, if the register read as one, there is no need to write 324 * one to clear operaton. 325 */ 326 regmap_read(afe->regmap, irq_data->irq_clr_reg, &tmp_reg); 327 regmap_update_bits(afe->regmap, irq_data->irq_clr_reg, 328 AFE_IRQ_CLR_CFG_MASK_SFT | AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT, 329 tmp_reg ^ (AFE_IRQ_CLR_CFG_MASK_SFT | 330 AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT)); 331 332 return ret; 333 default: 334 return -EINVAL; 335 } 336 } 337 338 static int mt8196_memif_fs(struct snd_pcm_substream *substream, 339 unsigned int rate) 340 { 341 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 342 struct snd_soc_component *component = 343 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 344 struct mtk_base_afe *afe = NULL; 345 unsigned int rate_reg; 346 347 if (!component) 348 return -EINVAL; 349 350 afe = snd_soc_component_get_drvdata(component); 351 if (!afe) 352 return -EINVAL; 353 354 rate_reg = mt8196_rate_transform(afe->dev, rate); 355 356 return rate_reg; 357 } 358 359 static int mt8196_get_dai_fs(struct mtk_base_afe *afe, 360 int dai_id, unsigned int rate) 361 { 362 return mt8196_rate_transform(afe->dev, rate); 363 } 364 365 static int mt8196_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) 366 { 367 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 368 struct snd_soc_component *component = 369 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 370 struct mtk_base_afe *afe = NULL; 371 372 if (!component) 373 return -EINVAL; 374 afe = snd_soc_component_get_drvdata(component); 375 return mt8196_rate_transform(afe->dev, rate); 376 } 377 378 static int mt8196_get_memif_pbuf_size(struct snd_pcm_substream *substream) 379 { 380 struct snd_pcm_runtime *runtime = substream->runtime; 381 382 if ((runtime->period_size * 1000) / runtime->rate > 10) 383 return MT8196_MEMIF_PBUF_SIZE_256_BYTES; 384 else 385 return MT8196_MEMIF_PBUF_SIZE_32_BYTES; 386 } 387 388 /* FE DAIs */ 389 static const struct snd_soc_dai_ops mt8196_memif_dai_ops = { 390 .startup = mt8196_fe_startup, 391 .shutdown = mt8196_fe_shutdown, 392 .hw_params = mt8196_fe_hw_params, 393 .hw_free = mtk_afe_fe_hw_free, 394 .prepare = mtk_afe_fe_prepare, 395 .trigger = mt8196_fe_trigger, 396 }; 397 398 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\ 399 SNDRV_PCM_RATE_88200 |\ 400 SNDRV_PCM_RATE_96000 |\ 401 SNDRV_PCM_RATE_176400 |\ 402 SNDRV_PCM_RATE_192000) 403 404 #define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\ 405 SNDRV_PCM_RATE_16000 |\ 406 SNDRV_PCM_RATE_32000 |\ 407 SNDRV_PCM_RATE_48000) 408 409 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 410 SNDRV_PCM_FMTBIT_S24_LE |\ 411 SNDRV_PCM_FMTBIT_S32_LE) 412 413 #define MT8196_FE_DAI(_name, _id, max_ch, dir) \ 414 { \ 415 .name = #_name, \ 416 .id = _id, \ 417 .dir = { \ 418 .stream_name = #_name, \ 419 .channels_min = 1, \ 420 .channels_max = max_ch, \ 421 .rates = MTK_PCM_RATES, \ 422 .formats = MTK_PCM_FORMATS, \ 423 }, \ 424 .ops = &mt8196_memif_dai_ops, \ 425 } 426 427 static struct snd_soc_dai_driver mt8196_memif_dai_driver[] = { 428 /* FE DAIs: memory intefaces to CPU */ 429 /* Playback */ 430 MT8196_FE_DAI(DL0, MT8196_MEMIF_DL0, 2, playback), 431 MT8196_FE_DAI(DL1, MT8196_MEMIF_DL1, 2, playback), 432 MT8196_FE_DAI(DL2, MT8196_MEMIF_DL2, 2, playback), 433 MT8196_FE_DAI(DL3, MT8196_MEMIF_DL3, 2, playback), 434 MT8196_FE_DAI(DL4, MT8196_MEMIF_DL4, 2, playback), 435 MT8196_FE_DAI(DL5, MT8196_MEMIF_DL5, 2, playback), 436 MT8196_FE_DAI(DL6, MT8196_MEMIF_DL6, 2, playback), 437 MT8196_FE_DAI(DL7, MT8196_MEMIF_DL7, 2, playback), 438 MT8196_FE_DAI(DL8, MT8196_MEMIF_DL8, 2, playback), 439 MT8196_FE_DAI(DL23, MT8196_MEMIF_DL23, 2, playback), 440 MT8196_FE_DAI(DL24, MT8196_MEMIF_DL24, 2, playback), 441 MT8196_FE_DAI(DL25, MT8196_MEMIF_DL25, 2, playback), 442 MT8196_FE_DAI(DL26, MT8196_MEMIF_DL26, 2, playback), 443 MT8196_FE_DAI(DL_4CH, MT8196_MEMIF_DL_4CH, 4, playback), 444 MT8196_FE_DAI(DL_24CH, MT8196_MEMIF_DL_24CH, 8, playback), 445 MT8196_FE_DAI(HDMI, MT8196_MEMIF_HDMI, 8, playback), 446 /* Capture */ 447 MT8196_FE_DAI(UL0, MT8196_MEMIF_VUL0, 2, capture), 448 MT8196_FE_DAI(UL1, MT8196_MEMIF_VUL1, 2, capture), 449 MT8196_FE_DAI(UL2, MT8196_MEMIF_VUL2, 2, capture), 450 MT8196_FE_DAI(UL3, MT8196_MEMIF_VUL3, 2, capture), 451 MT8196_FE_DAI(UL4, MT8196_MEMIF_VUL4, 2, capture), 452 MT8196_FE_DAI(UL5, MT8196_MEMIF_VUL5, 2, capture), 453 MT8196_FE_DAI(UL6, MT8196_MEMIF_VUL6, 2, capture), 454 MT8196_FE_DAI(UL7, MT8196_MEMIF_VUL7, 2, capture), 455 MT8196_FE_DAI(UL8, MT8196_MEMIF_VUL8, 2, capture), 456 MT8196_FE_DAI(UL9, MT8196_MEMIF_VUL9, 16, capture), 457 MT8196_FE_DAI(UL10, MT8196_MEMIF_VUL10, 2, capture), 458 MT8196_FE_DAI(UL24, MT8196_MEMIF_VUL24, 2, capture), 459 MT8196_FE_DAI(UL25, MT8196_MEMIF_VUL25, 2, capture), 460 MT8196_FE_DAI(UL26, MT8196_MEMIF_VUL26, 2, capture), 461 MT8196_FE_DAI(UL_CM0, MT8196_MEMIF_VUL_CM0, 8, capture), 462 MT8196_FE_DAI(UL_CM1, MT8196_MEMIF_VUL_CM1, 16, capture), 463 MT8196_FE_DAI(UL_CM2, MT8196_MEMIF_VUL_CM2, 32, capture), 464 MT8196_FE_DAI(UL_ETDM_IN0, MT8196_MEMIF_ETDM_IN0, 2, capture), 465 MT8196_FE_DAI(UL_ETDM_IN1, MT8196_MEMIF_ETDM_IN1, 2, capture), 466 MT8196_FE_DAI(UL_ETDM_IN2, MT8196_MEMIF_ETDM_IN2, 2, capture), 467 MT8196_FE_DAI(UL_ETDM_IN3, MT8196_MEMIF_ETDM_IN3, 2, capture), 468 MT8196_FE_DAI(UL_ETDM_IN4, MT8196_MEMIF_ETDM_IN4, 2, capture), 469 MT8196_FE_DAI(UL_ETDM_IN6, MT8196_MEMIF_ETDM_IN6, 2, capture), 470 }; 471 472 static int ul_cm0_event(struct snd_soc_dapm_widget *w, 473 struct snd_kcontrol *kcontrol, 474 int event) 475 { 476 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 477 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 478 struct mt8196_afe_private *afe_priv = afe->platform_priv; 479 unsigned int channels = afe_priv->cm_channels; 480 481 dev_dbg(afe->dev, "event 0x%x, name %s, channels %u\n", 482 event, w->name, channels); 483 484 switch (event) { 485 case SND_SOC_DAPM_PRE_PMU: 486 mt8196_enable_cm_bypass(afe, CM0, false); 487 mt8196_set_cm(afe, CM0, true, false, channels); 488 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 489 PDN_CM0_MASK_SFT, 0 << PDN_CM0_SFT); 490 break; 491 case SND_SOC_DAPM_POST_PMD: 492 mt8196_enable_cm_bypass(afe, CM0, true); 493 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 494 PDN_CM0_MASK_SFT, 1 << PDN_CM0_SFT); 495 break; 496 default: 497 break; 498 } 499 500 return 0; 501 } 502 503 static int ul_cm1_event(struct snd_soc_dapm_widget *w, 504 struct snd_kcontrol *kcontrol, 505 int event) 506 { 507 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 508 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 509 struct mt8196_afe_private *afe_priv = afe->platform_priv; 510 unsigned int channels = afe_priv->cm_channels; 511 512 dev_dbg(afe->dev, "event 0x%x, name %s, channels %u\n", 513 event, w->name, channels); 514 515 switch (event) { 516 case SND_SOC_DAPM_PRE_PMU: 517 mt8196_enable_cm_bypass(afe, CM1, false); 518 mt8196_set_cm(afe, CM1, true, false, channels); 519 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 520 PDN_CM1_MASK_SFT, 0 << PDN_CM1_SFT); 521 break; 522 case SND_SOC_DAPM_POST_PMD: 523 mt8196_enable_cm_bypass(afe, CM1, true); 524 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 525 PDN_CM1_MASK_SFT, 1 << PDN_CM1_SFT); 526 break; 527 default: 528 break; 529 } 530 531 return 0; 532 } 533 534 static int ul_cm2_event(struct snd_soc_dapm_widget *w, 535 struct snd_kcontrol *kcontrol, 536 int event) 537 { 538 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 539 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 540 struct mt8196_afe_private *afe_priv = afe->platform_priv; 541 unsigned int channels = afe_priv->cm_channels; 542 543 dev_dbg(afe->dev, "event 0x%x, name %s, channels %u\n", 544 event, w->name, channels); 545 546 switch (event) { 547 case SND_SOC_DAPM_PRE_PMU: 548 mt8196_enable_cm_bypass(afe, CM2, false); 549 mt8196_set_cm(afe, CM2, true, false, channels); 550 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 551 PDN_CM2_MASK_SFT, 0 << PDN_CM2_SFT); 552 break; 553 case SND_SOC_DAPM_POST_PMD: 554 mt8196_enable_cm_bypass(afe, CM2, true); 555 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 556 PDN_CM2_MASK_SFT, 1 << PDN_CM2_SFT); 557 break; 558 default: 559 break; 560 } 561 562 return 0; 563 } 564 565 /* 566 * dma widget & routes 567 * The mixer controls and routes are by no means fully implemented, 568 * only the ones that are intended to be used are, as other wise a fully 569 * interconnected switch bar mixer would introduce way too many unused 570 * controls. 571 */ 572 static const struct snd_kcontrol_new memif_ul0_ch1_mix[] = { 573 /* Normal record */ 574 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN018_0, 575 I_ADDA_UL_CH1, 1, 0), 576 }; 577 578 static const struct snd_kcontrol_new memif_ul0_ch2_mix[] = { 579 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN019_0, 580 I_ADDA_UL_CH2, 1, 0), 581 }; 582 583 static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = { 584 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN4_CH1", AFE_CONN020_4, 585 I_I2SIN4_CH1, 1, 0), 586 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH1", AFE_CONN020_5, 587 I_I2SIN6_CH1, 1, 0), 588 }; 589 590 static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = { 591 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN4_CH2", AFE_CONN021_4, 592 I_I2SIN4_CH2, 1, 0), 593 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH2", AFE_CONN021_5, 594 I_I2SIN6_CH2, 1, 0), 595 }; 596 597 static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = { 598 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN022_0, 599 I_ADDA_UL_CH3, 1, 0), 600 }; 601 602 static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = { 603 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN023_0, 604 I_ADDA_UL_CH4, 1, 0), 605 }; 606 607 static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = { 608 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN024_4, 609 I_I2SIN0_CH1, 1, 0), 610 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH1", AFE_CONN024_4, 611 I_I2SIN1_CH1, 1, 0), 612 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN3_CH1", AFE_CONN024_4, 613 I_I2SIN3_CH1, 1, 0), 614 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN4_CH1", AFE_CONN024_4, 615 I_I2SIN4_CH1, 1, 0), 616 }; 617 618 static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = { 619 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN025_4, 620 I_I2SIN0_CH2, 1, 0), 621 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH2", AFE_CONN025_4, 622 I_I2SIN1_CH2, 1, 0), 623 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN3_CH2", AFE_CONN025_4, 624 I_I2SIN3_CH2, 1, 0), 625 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN4_CH2", AFE_CONN025_4, 626 I_I2SIN4_CH2, 1, 0), 627 }; 628 629 static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = { 630 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN026_0, 631 I_ADDA_UL_CH1, 1, 0), 632 SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN026_1, 633 I_DL0_CH1, 1, 0), 634 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN026_1, 635 I_DL1_CH1, 1, 0), 636 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN026_1, 637 I_DL6_CH1, 1, 0), 638 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN026_1, 639 I_DL2_CH1, 1, 0), 640 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN026_1, 641 I_DL3_CH1, 1, 0), 642 SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN026_1, 643 I_DL_24CH_CH1, 1, 0), 644 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN026_4, 645 I_I2SIN0_CH1, 1, 0), 646 }; 647 648 static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = { 649 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN027_0, 650 I_ADDA_UL_CH2, 1, 0), 651 SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN027_1, 652 I_DL0_CH2, 1, 0), 653 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN027_1, 654 I_DL1_CH2, 1, 0), 655 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN027_1, 656 I_DL6_CH2, 1, 0), 657 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN027_1, 658 I_DL2_CH2, 1, 0), 659 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN027_1, 660 I_DL3_CH2, 1, 0), 661 SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN027_1, 662 I_DL_24CH_CH2, 1, 0), 663 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN027_4, 664 I_I2SIN0_CH2, 1, 0), 665 }; 666 667 static const struct snd_kcontrol_new memif_ul5_ch1_mix[] = { 668 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN3_CH1", AFE_CONN028_4, 669 I_I2SIN3_CH1, 1, 0), 670 }; 671 672 static const struct snd_kcontrol_new memif_ul5_ch2_mix[] = { 673 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN3_CH2", AFE_CONN029_4, 674 I_I2SIN3_CH2, 1, 0), 675 }; 676 677 static const struct snd_kcontrol_new memif_ul6_ch1_mix[] = { 678 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN030_0, 679 I_ADDA_UL_CH1, 1, 0), 680 }; 681 682 static const struct snd_kcontrol_new memif_ul6_ch2_mix[] = { 683 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN031_0, 684 I_ADDA_UL_CH2, 1, 0), 685 }; 686 687 static const struct snd_kcontrol_new memif_ul7_ch1_mix[] = { 688 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN032_0, 689 I_ADDA_UL_CH1, 1, 0), 690 }; 691 692 static const struct snd_kcontrol_new memif_ul7_ch2_mix[] = { 693 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN033_0, 694 I_ADDA_UL_CH2, 1, 0), 695 }; 696 697 static const struct snd_kcontrol_new memif_ul8_ch1_mix[] = { 698 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN034_0, 699 I_ADDA_UL_CH1, 1, 0), 700 }; 701 702 static const struct snd_kcontrol_new memif_ul8_ch2_mix[] = { 703 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN035_0, 704 I_ADDA_UL_CH1, 1, 0), 705 }; 706 707 static const struct snd_kcontrol_new memif_ul9_ch1_mix[] = { 708 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN036_0, 709 I_ADDA_UL_CH1, 1, 0), 710 }; 711 712 static const struct snd_kcontrol_new memif_ul9_ch2_mix[] = { 713 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN037_0, 714 I_ADDA_UL_CH2, 1, 0), 715 }; 716 717 static const struct snd_kcontrol_new memif_ul10_ch1_mix[] = { 718 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN038_0, 719 I_ADDA_UL_CH1, 1, 0), 720 }; 721 722 static const struct snd_kcontrol_new memif_ul10_ch2_mix[] = { 723 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN039_0, 724 I_ADDA_UL_CH2, 1, 0), 725 }; 726 727 static const struct snd_kcontrol_new memif_ul24_ch1_mix[] = { 728 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN066_4, 729 I_I2SIN0_CH1, 1, 0), 730 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH1", AFE_CONN066_5, 731 I_I2SIN6_CH1, 1, 0), 732 }; 733 734 static const struct snd_kcontrol_new memif_ul24_ch2_mix[] = { 735 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN067_4, 736 I_I2SIN0_CH2, 1, 0), 737 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH2", AFE_CONN067_5, 738 I_I2SIN6_CH2, 1, 0), 739 }; 740 741 static const struct snd_kcontrol_new memif_ul25_ch1_mix[] = { 742 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN068_4, 743 I_I2SIN0_CH1, 1, 0), 744 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH1", AFE_CONN068_5, 745 I_I2SIN6_CH1, 1, 0), 746 }; 747 748 static const struct snd_kcontrol_new memif_ul25_ch2_mix[] = { 749 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN069_4, 750 I_I2SIN0_CH2, 1, 0), 751 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH2", AFE_CONN069_5, 752 I_I2SIN6_CH2, 1, 0), 753 }; 754 755 static const struct snd_kcontrol_new memif_ul26_ch1_mix[] = { 756 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN070_4, 757 I_I2SIN0_CH1, 1, 0), 758 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH1", AFE_CONN070_5, 759 I_I2SIN6_CH1, 1, 0), 760 }; 761 762 static const struct snd_kcontrol_new memif_ul26_ch2_mix[] = { 763 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN071_4, 764 I_I2SIN0_CH2, 1, 0), 765 SOC_DAPM_SINGLE_AUTODISABLE("I2SIN6_CH2", AFE_CONN071_5, 766 I_I2SIN6_CH2, 1, 0), 767 }; 768 769 static const struct snd_kcontrol_new memif_ul_cm0_ch1_mix[] = { 770 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN040_0, 771 I_ADDA_UL_CH1, 1, 0), 772 }; 773 774 static const struct snd_kcontrol_new memif_ul_cm0_ch2_mix[] = { 775 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN041_0, 776 I_ADDA_UL_CH2, 1, 0), 777 }; 778 779 static const struct snd_kcontrol_new memif_ul_cm0_ch3_mix[] = { 780 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN042_0, 781 I_ADDA_UL_CH3, 1, 0), 782 }; 783 784 static const struct snd_kcontrol_new memif_ul_cm0_ch4_mix[] = { 785 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN043_0, 786 I_ADDA_UL_CH4, 1, 0), 787 }; 788 789 static const struct snd_kcontrol_new memif_ul_cm0_ch5_mix[] = { 790 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN044_0, 791 I_ADDA_UL_CH1, 1, 0), 792 }; 793 794 static const struct snd_kcontrol_new memif_ul_cm0_ch6_mix[] = { 795 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN045_0, 796 I_ADDA_UL_CH1, 1, 0), 797 }; 798 799 static const struct snd_kcontrol_new memif_ul_cm0_ch7_mix[] = { 800 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN046_0, 801 I_ADDA_UL_CH1, 1, 0), 802 }; 803 804 static const struct snd_kcontrol_new memif_ul_cm0_ch8_mix[] = { 805 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN047_0, 806 I_ADDA_UL_CH1, 1, 0), 807 }; 808 809 static const struct snd_kcontrol_new memif_ul_cm1_ch1_mix[] = { 810 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN048_0, 811 I_ADDA_UL_CH1, 1, 0), 812 }; 813 814 static const struct snd_kcontrol_new memif_ul_cm1_ch2_mix[] = { 815 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN049_0, 816 I_ADDA_UL_CH2, 1, 0), 817 }; 818 819 static const struct snd_kcontrol_new memif_ul_cm1_ch3_mix[] = { 820 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN050_0, 821 I_ADDA_UL_CH3, 1, 0), 822 }; 823 824 static const struct snd_kcontrol_new memif_ul_cm1_ch4_mix[] = { 825 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN051_0, 826 I_ADDA_UL_CH4, 1, 0), 827 }; 828 829 static const struct snd_kcontrol_new memif_ul_cm1_ch5_mix[] = { 830 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN052_0, 831 I_ADDA_UL_CH1, 1, 0), 832 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN052_0, 833 I_ADDA_UL_CH2, 1, 0), 834 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN052_0, 835 I_ADDA_UL_CH3, 1, 0), 836 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN052_0, 837 I_ADDA_UL_CH4, 1, 0), 838 }; 839 840 static const struct snd_kcontrol_new memif_ul_cm1_ch6_mix[] = { 841 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN053_0, 842 I_ADDA_UL_CH1, 1, 0), 843 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN053_0, 844 I_ADDA_UL_CH2, 1, 0), 845 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN053_0, 846 I_ADDA_UL_CH3, 1, 0), 847 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN053_0, 848 I_ADDA_UL_CH4, 1, 0), 849 }; 850 851 static const struct snd_kcontrol_new memif_ul_cm1_ch7_mix[] = { 852 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN054_0, 853 I_ADDA_UL_CH1, 1, 0), 854 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN054_0, 855 I_ADDA_UL_CH2, 1, 0), 856 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN054_0, 857 I_ADDA_UL_CH3, 1, 0), 858 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN054_0, 859 I_ADDA_UL_CH4, 1, 0), 860 }; 861 862 static const struct snd_kcontrol_new memif_ul_cm1_ch8_mix[] = { 863 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN055_0, 864 I_ADDA_UL_CH1, 1, 0), 865 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN055_0, 866 I_ADDA_UL_CH2, 1, 0), 867 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN055_0, 868 I_ADDA_UL_CH3, 1, 0), 869 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN055_0, 870 I_ADDA_UL_CH4, 1, 0), 871 }; 872 873 static const struct snd_kcontrol_new memif_ul_cm1_ch9_mix[] = { 874 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN056_0, 875 I_ADDA_UL_CH1, 1, 0), 876 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN056_0, 877 I_ADDA_UL_CH2, 1, 0), 878 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN056_0, 879 I_ADDA_UL_CH3, 1, 0), 880 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN056_0, 881 I_ADDA_UL_CH4, 1, 0), 882 }; 883 884 static const struct snd_kcontrol_new memif_ul_cm1_ch10_mix[] = { 885 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN057_0, 886 I_ADDA_UL_CH1, 1, 0), 887 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN057_0, 888 I_ADDA_UL_CH2, 1, 0), 889 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN057_0, 890 I_ADDA_UL_CH3, 1, 0), 891 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN057_0, 892 I_ADDA_UL_CH4, 1, 0), 893 }; 894 895 static const struct snd_kcontrol_new memif_ul_cm1_ch11_mix[] = { 896 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN058_0, 897 I_ADDA_UL_CH1, 1, 0), 898 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN058_0, 899 I_ADDA_UL_CH2, 1, 0), 900 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN058_0, 901 I_ADDA_UL_CH3, 1, 0), 902 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN058_0, 903 I_ADDA_UL_CH4, 1, 0), 904 }; 905 906 static const struct snd_kcontrol_new memif_ul_cm1_ch12_mix[] = { 907 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN059_0, 908 I_ADDA_UL_CH1, 1, 0), 909 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN059_0, 910 I_ADDA_UL_CH2, 1, 0), 911 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN059_0, 912 I_ADDA_UL_CH3, 1, 0), 913 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN059_0, 914 I_ADDA_UL_CH4, 1, 0), 915 }; 916 917 static const struct snd_kcontrol_new memif_ul_cm1_ch13_mix[] = { 918 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN060_0, 919 I_ADDA_UL_CH1, 1, 0), 920 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN060_0, 921 I_ADDA_UL_CH2, 1, 0), 922 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN060_0, 923 I_ADDA_UL_CH3, 1, 0), 924 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN060_0, 925 I_ADDA_UL_CH4, 1, 0), 926 }; 927 928 static const struct snd_kcontrol_new memif_ul_cm1_ch14_mix[] = { 929 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN061_0, 930 I_ADDA_UL_CH1, 1, 0), 931 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN061_0, 932 I_ADDA_UL_CH2, 1, 0), 933 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN061_0, 934 I_ADDA_UL_CH3, 1, 0), 935 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN061_0, 936 I_ADDA_UL_CH4, 1, 0), 937 }; 938 939 static const struct snd_kcontrol_new memif_ul_cm1_ch15_mix[] = { 940 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN062_0, 941 I_ADDA_UL_CH1, 1, 0), 942 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN062_0, 943 I_ADDA_UL_CH2, 1, 0), 944 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN062_0, 945 I_ADDA_UL_CH3, 1, 0), 946 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN062_0, 947 I_ADDA_UL_CH4, 1, 0), 948 }; 949 950 static const struct snd_kcontrol_new memif_ul_cm1_ch16_mix[] = { 951 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN063_0, 952 I_ADDA_UL_CH1, 1, 0), 953 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN063_0, 954 I_ADDA_UL_CH2, 1, 0), 955 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN063_0, 956 I_ADDA_UL_CH3, 1, 0), 957 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN063_0, 958 I_ADDA_UL_CH4, 1, 0), 959 }; 960 961 static const struct snd_kcontrol_new memif_ul_cm2_ch1_mix[] = { 962 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN064_0, I_ADDA_UL_CH1, 1, 0), 963 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN064_0, I_ADDA_UL_CH2, 1, 0), 964 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN064_0, I_ADDA_UL_CH3, 1, 0), 965 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN064_0, I_ADDA_UL_CH4, 1, 0), 966 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN064_0, I_ADDA_UL_CH5, 1, 0), 967 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN064_0, I_ADDA_UL_CH6, 1, 0), 968 }; 969 970 static const struct snd_kcontrol_new memif_ul_cm2_ch2_mix[] = { 971 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN065_0, I_ADDA_UL_CH1, 1, 0), 972 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN065_0, I_ADDA_UL_CH2, 1, 0), 973 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN065_0, I_ADDA_UL_CH3, 1, 0), 974 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN065_0, I_ADDA_UL_CH4, 1, 0), 975 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN065_0, I_ADDA_UL_CH5, 1, 0), 976 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN065_0, I_ADDA_UL_CH6, 1, 0), 977 }; 978 979 static const struct snd_kcontrol_new memif_ul_cm2_ch3_mix[] = { 980 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN066_0, I_ADDA_UL_CH1, 1, 0), 981 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN066_0, I_ADDA_UL_CH2, 1, 0), 982 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN066_0, I_ADDA_UL_CH3, 1, 0), 983 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN066_0, I_ADDA_UL_CH4, 1, 0), 984 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN066_0, I_ADDA_UL_CH5, 1, 0), 985 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN066_0, I_ADDA_UL_CH6, 1, 0) 986 }; 987 988 static const struct snd_kcontrol_new memif_ul_cm2_ch4_mix[] = { 989 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN067_0, I_ADDA_UL_CH1, 1, 0), 990 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN067_0, I_ADDA_UL_CH2, 1, 0), 991 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN067_0, I_ADDA_UL_CH3, 1, 0), 992 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN067_0, I_ADDA_UL_CH4, 1, 0), 993 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN067_0, I_ADDA_UL_CH5, 1, 0), 994 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN067_0, I_ADDA_UL_CH6, 1, 0) 995 }; 996 997 static const struct snd_kcontrol_new memif_ul_cm2_ch5_mix[] = { 998 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN068_0, I_ADDA_UL_CH1, 1, 0), 999 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN068_0, I_ADDA_UL_CH2, 1, 0), 1000 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN068_0, I_ADDA_UL_CH3, 1, 0), 1001 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN068_0, I_ADDA_UL_CH4, 1, 0), 1002 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN068_0, I_ADDA_UL_CH5, 1, 0), 1003 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN068_0, I_ADDA_UL_CH6, 1, 0) 1004 }; 1005 1006 static const struct snd_kcontrol_new memif_ul_cm2_ch6_mix[] = { 1007 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN069_0, I_ADDA_UL_CH1, 1, 0), 1008 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN069_0, I_ADDA_UL_CH2, 1, 0), 1009 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN069_0, I_ADDA_UL_CH3, 1, 0), 1010 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN069_0, I_ADDA_UL_CH4, 1, 0), 1011 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN069_0, I_ADDA_UL_CH5, 1, 0), 1012 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN069_0, I_ADDA_UL_CH6, 1, 0) 1013 }; 1014 1015 static const struct snd_kcontrol_new memif_ul_cm2_ch7_mix[] = { 1016 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN070_0, I_ADDA_UL_CH1, 1, 0), 1017 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN070_0, I_ADDA_UL_CH2, 1, 0), 1018 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN070_0, I_ADDA_UL_CH3, 1, 0), 1019 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN070_0, I_ADDA_UL_CH4, 1, 0), 1020 }; 1021 1022 static const struct snd_kcontrol_new memif_ul_cm2_ch8_mix[] = { 1023 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN071_0, I_ADDA_UL_CH1, 1, 0), 1024 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN071_0, I_ADDA_UL_CH2, 1, 0), 1025 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN071_0, I_ADDA_UL_CH3, 1, 0), 1026 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN071_0, I_ADDA_UL_CH4, 1, 0), 1027 }; 1028 1029 static const struct snd_kcontrol_new memif_ul_cm2_ch9_mix[] = { 1030 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN072_0, I_ADDA_UL_CH1, 1, 0), 1031 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN072_0, I_ADDA_UL_CH2, 1, 0), 1032 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN072_0, I_ADDA_UL_CH3, 1, 0), 1033 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN072_0, I_ADDA_UL_CH4, 1, 0), 1034 }; 1035 1036 static const struct snd_kcontrol_new memif_ul_cm2_ch10_mix[] = { 1037 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN073_0, I_ADDA_UL_CH1, 1, 0), 1038 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN073_0, I_ADDA_UL_CH2, 1, 0), 1039 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN073_0, I_ADDA_UL_CH3, 1, 0), 1040 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN073_0, I_ADDA_UL_CH4, 1, 0), 1041 }; 1042 1043 static const struct snd_kcontrol_new memif_ul_cm2_ch11_mix[] = { 1044 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN074_0, I_ADDA_UL_CH1, 1, 0), 1045 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN074_0, I_ADDA_UL_CH2, 1, 0), 1046 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN074_0, I_ADDA_UL_CH3, 1, 0), 1047 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN074_0, I_ADDA_UL_CH4, 1, 0), 1048 }; 1049 1050 static const struct snd_kcontrol_new memif_ul_cm2_ch12_mix[] = { 1051 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN075_0, I_ADDA_UL_CH1, 1, 0), 1052 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN075_0, I_ADDA_UL_CH2, 1, 0), 1053 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN075_0, I_ADDA_UL_CH3, 1, 0), 1054 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN075_0, I_ADDA_UL_CH4, 1, 0), 1055 }; 1056 1057 static const struct snd_kcontrol_new memif_ul_cm2_ch13_mix[] = { 1058 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN076_0, I_ADDA_UL_CH1, 1, 0), 1059 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN076_0, I_ADDA_UL_CH2, 1, 0), 1060 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN076_0, I_ADDA_UL_CH3, 1, 0), 1061 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN076_0, I_ADDA_UL_CH4, 1, 0), 1062 }; 1063 1064 static const struct snd_kcontrol_new memif_ul_cm2_ch14_mix[] = { 1065 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN077_0, I_ADDA_UL_CH1, 1, 0), 1066 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN077_0, I_ADDA_UL_CH2, 1, 0), 1067 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN077_0, I_ADDA_UL_CH3, 1, 0), 1068 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN077_0, I_ADDA_UL_CH4, 1, 0), 1069 }; 1070 1071 static const struct snd_kcontrol_new memif_ul_cm2_ch15_mix[] = { 1072 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN078_0, I_ADDA_UL_CH1, 1, 0), 1073 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN078_0, I_ADDA_UL_CH2, 1, 0), 1074 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN078_0, I_ADDA_UL_CH3, 1, 0), 1075 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN078_0, I_ADDA_UL_CH4, 1, 0), 1076 }; 1077 1078 static const struct snd_kcontrol_new memif_ul_cm2_ch16_mix[] = { 1079 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN079_0, I_ADDA_UL_CH1, 1, 0), 1080 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN079_0, I_ADDA_UL_CH2, 1, 0), 1081 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN079_0, I_ADDA_UL_CH3, 1, 0), 1082 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN079_0, I_ADDA_UL_CH4, 1, 0), 1083 }; 1084 1085 static const struct snd_kcontrol_new memif_ul_cm2_ch17_mix[] = { 1086 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN080_0, I_ADDA_UL_CH1, 1, 0), 1087 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN080_0, I_ADDA_UL_CH2, 1, 0), 1088 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN080_0, I_ADDA_UL_CH3, 1, 0), 1089 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN080_0, I_ADDA_UL_CH4, 1, 0), 1090 }; 1091 1092 static const struct snd_kcontrol_new memif_ul_cm2_ch18_mix[] = { 1093 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN081_0, I_ADDA_UL_CH1, 1, 0), 1094 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN081_0, I_ADDA_UL_CH2, 1, 0), 1095 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN081_0, I_ADDA_UL_CH3, 1, 0), 1096 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN081_0, I_ADDA_UL_CH4, 1, 0), 1097 }; 1098 1099 static const struct snd_kcontrol_new memif_ul_cm2_ch19_mix[] = { 1100 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN082_0, I_ADDA_UL_CH1, 1, 0), 1101 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN082_0, I_ADDA_UL_CH2, 1, 0), 1102 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN082_0, I_ADDA_UL_CH3, 1, 0), 1103 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN082_0, I_ADDA_UL_CH4, 1, 0), 1104 }; 1105 1106 static const struct snd_kcontrol_new memif_ul_cm2_ch20_mix[] = { 1107 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN083_0, I_ADDA_UL_CH1, 1, 0), 1108 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN083_0, I_ADDA_UL_CH2, 1, 0), 1109 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN083_0, I_ADDA_UL_CH3, 1, 0), 1110 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN083_0, I_ADDA_UL_CH4, 1, 0), 1111 }; 1112 1113 static const struct snd_kcontrol_new memif_ul_cm2_ch21_mix[] = { 1114 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN084_0, I_ADDA_UL_CH1, 1, 0), 1115 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN084_0, I_ADDA_UL_CH2, 1, 0), 1116 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN084_0, I_ADDA_UL_CH3, 1, 0), 1117 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN084_0, I_ADDA_UL_CH4, 1, 0), 1118 }; 1119 1120 static const struct snd_kcontrol_new memif_ul_cm2_ch22_mix[] = { 1121 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN085_0, I_ADDA_UL_CH1, 1, 0), 1122 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN085_0, I_ADDA_UL_CH2, 1, 0), 1123 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN085_0, I_ADDA_UL_CH3, 1, 0), 1124 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN085_0, I_ADDA_UL_CH4, 1, 0), 1125 }; 1126 1127 static const struct snd_kcontrol_new memif_ul_cm2_ch23_mix[] = { 1128 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN086_0, I_ADDA_UL_CH1, 1, 0), 1129 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN086_0, I_ADDA_UL_CH2, 1, 0), 1130 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN086_0, I_ADDA_UL_CH3, 1, 0), 1131 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN086_0, I_ADDA_UL_CH4, 1, 0), 1132 }; 1133 1134 static const struct snd_kcontrol_new memif_ul_cm2_ch24_mix[] = { 1135 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN087_0, I_ADDA_UL_CH1, 1, 0), 1136 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN087_0, I_ADDA_UL_CH2, 1, 0), 1137 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN087_0, I_ADDA_UL_CH3, 1, 0), 1138 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN087_0, I_ADDA_UL_CH4, 1, 0), 1139 }; 1140 1141 static const struct snd_kcontrol_new memif_ul_cm2_ch25_mix[] = { 1142 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN088_0, I_ADDA_UL_CH1, 1, 0), 1143 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN088_0, I_ADDA_UL_CH2, 1, 0), 1144 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN088_0, I_ADDA_UL_CH3, 1, 0), 1145 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN088_0, I_ADDA_UL_CH4, 1, 0), 1146 }; 1147 1148 static const struct snd_kcontrol_new memif_ul_cm2_ch26_mix[] = { 1149 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN089_0, I_ADDA_UL_CH1, 1, 0), 1150 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN089_0, I_ADDA_UL_CH2, 1, 0), 1151 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN089_0, I_ADDA_UL_CH3, 1, 0), 1152 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN089_0, I_ADDA_UL_CH4, 1, 0), 1153 }; 1154 1155 static const struct snd_kcontrol_new memif_ul_cm2_ch27_mix[] = { 1156 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN090_0, I_ADDA_UL_CH1, 1, 0), 1157 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN090_0, I_ADDA_UL_CH2, 1, 0), 1158 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN090_0, I_ADDA_UL_CH3, 1, 0), 1159 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN090_0, I_ADDA_UL_CH4, 1, 0), 1160 }; 1161 1162 static const struct snd_kcontrol_new memif_ul_cm2_ch28_mix[] = { 1163 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN091_0, I_ADDA_UL_CH1, 1, 0), 1164 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN091_0, I_ADDA_UL_CH2, 1, 0), 1165 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN091_0, I_ADDA_UL_CH3, 1, 0), 1166 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN091_0, I_ADDA_UL_CH4, 1, 0), 1167 }; 1168 1169 static const struct snd_kcontrol_new memif_ul_cm2_ch29_mix[] = { 1170 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN092_0, I_ADDA_UL_CH1, 1, 0), 1171 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN092_0, I_ADDA_UL_CH2, 1, 0), 1172 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN092_0, I_ADDA_UL_CH3, 1, 0), 1173 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN092_0, I_ADDA_UL_CH4, 1, 0), 1174 }; 1175 1176 static const struct snd_kcontrol_new memif_ul_cm2_ch30_mix[] = { 1177 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN093_0, I_ADDA_UL_CH1, 1, 0), 1178 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN093_0, I_ADDA_UL_CH2, 1, 0), 1179 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN093_0, I_ADDA_UL_CH3, 1, 0), 1180 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN093_0, I_ADDA_UL_CH4, 1, 0), 1181 }; 1182 1183 static const struct snd_kcontrol_new memif_ul_cm2_ch31_mix[] = { 1184 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN094_0, I_ADDA_UL_CH1, 1, 0), 1185 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN094_0, I_ADDA_UL_CH2, 1, 0), 1186 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN094_0, I_ADDA_UL_CH3, 1, 0), 1187 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN094_0, I_ADDA_UL_CH4, 1, 0), 1188 }; 1189 1190 static const struct snd_kcontrol_new memif_ul_cm2_ch32_mix[] = { 1191 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN095_0, I_ADDA_UL_CH1, 1, 0), 1192 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN095_0, I_ADDA_UL_CH2, 1, 0), 1193 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN095_0, I_ADDA_UL_CH3, 1, 0), 1194 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN095_0, I_ADDA_UL_CH4, 1, 0), 1195 }; 1196 1197 static const char * const cm0_mux_map[] = { 1198 "UL8_2CH_PATH", 1199 "CM0_8CH_PATH", 1200 }; 1201 1202 static const char * const cm1_mux_map[] = { 1203 "UL9_2CH_PATH", 1204 "CM1_16CH_PATH", 1205 }; 1206 1207 static const char * const cm2_mux_map[] = { 1208 "UL10_2CH_PATH", 1209 "CM2_32CH_PATH", 1210 }; 1211 1212 static SOC_ENUM_SINGLE_DECL(ul_cm0_mux_map_enum, AFE_CM0_CON0, 1213 AFE_CM0_OUTPUT_MUX_SFT, cm0_mux_map); 1214 1215 static SOC_ENUM_SINGLE_DECL(ul_cm1_mux_map_enum, AFE_CM1_CON0, 1216 AFE_CM1_OUTPUT_MUX_SFT, cm1_mux_map); 1217 1218 static SOC_ENUM_SINGLE_DECL(ul_cm2_mux_map_enum, AFE_CM2_CON0, 1219 AFE_CM2_OUTPUT_MUX_SFT, cm2_mux_map); 1220 1221 static const struct snd_kcontrol_new ul_cm0_mux_control = 1222 SOC_DAPM_ENUM("CM0_UL_MUX Route", ul_cm0_mux_map_enum); 1223 1224 static const struct snd_kcontrol_new ul_cm1_mux_control = 1225 SOC_DAPM_ENUM("CM1_UL_MUX Route", ul_cm1_mux_map_enum); 1226 1227 static const struct snd_kcontrol_new ul_cm2_mux_control = 1228 SOC_DAPM_ENUM("CM2_UL_MUX Route", ul_cm2_mux_map_enum); 1229 1230 static const struct snd_soc_dapm_widget mt8196_memif_widgets[] = { 1231 /* inter-connections */ 1232 SND_SOC_DAPM_MIXER("UL0_CH1", SND_SOC_NOPM, 0, 0, 1233 memif_ul0_ch1_mix, ARRAY_SIZE(memif_ul0_ch1_mix)), 1234 SND_SOC_DAPM_MIXER("UL0_CH2", SND_SOC_NOPM, 0, 0, 1235 memif_ul0_ch2_mix, ARRAY_SIZE(memif_ul0_ch2_mix)), 1236 1237 SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0, 1238 memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)), 1239 SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0, 1240 memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)), 1241 1242 SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0, 1243 memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)), 1244 SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0, 1245 memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)), 1246 1247 SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0, 1248 memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)), 1249 SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0, 1250 memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)), 1251 1252 SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0, 1253 memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)), 1254 SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0, 1255 memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)), 1256 1257 SND_SOC_DAPM_MIXER("UL5_CH1", SND_SOC_NOPM, 0, 0, 1258 memif_ul5_ch1_mix, ARRAY_SIZE(memif_ul5_ch1_mix)), 1259 SND_SOC_DAPM_MIXER("UL5_CH2", SND_SOC_NOPM, 0, 0, 1260 memif_ul5_ch2_mix, ARRAY_SIZE(memif_ul5_ch2_mix)), 1261 1262 SND_SOC_DAPM_MIXER("UL6_CH1", SND_SOC_NOPM, 0, 0, 1263 memif_ul6_ch1_mix, ARRAY_SIZE(memif_ul6_ch1_mix)), 1264 SND_SOC_DAPM_MIXER("UL6_CH2", SND_SOC_NOPM, 0, 0, 1265 memif_ul6_ch2_mix, ARRAY_SIZE(memif_ul6_ch2_mix)), 1266 1267 SND_SOC_DAPM_MIXER("UL7_CH1", SND_SOC_NOPM, 0, 0, 1268 memif_ul7_ch1_mix, ARRAY_SIZE(memif_ul7_ch1_mix)), 1269 SND_SOC_DAPM_MIXER("UL7_CH2", SND_SOC_NOPM, 0, 0, 1270 memif_ul7_ch2_mix, ARRAY_SIZE(memif_ul7_ch2_mix)), 1271 1272 SND_SOC_DAPM_MIXER("UL8_CH1", SND_SOC_NOPM, 0, 0, 1273 memif_ul8_ch1_mix, ARRAY_SIZE(memif_ul8_ch1_mix)), 1274 SND_SOC_DAPM_MIXER("UL8_CH2", SND_SOC_NOPM, 0, 0, 1275 memif_ul8_ch2_mix, ARRAY_SIZE(memif_ul8_ch2_mix)), 1276 1277 SND_SOC_DAPM_MIXER("UL9_CH1", SND_SOC_NOPM, 0, 0, 1278 memif_ul9_ch1_mix, ARRAY_SIZE(memif_ul9_ch1_mix)), 1279 SND_SOC_DAPM_MIXER("UL9_CH2", SND_SOC_NOPM, 0, 0, 1280 memif_ul9_ch2_mix, ARRAY_SIZE(memif_ul9_ch2_mix)), 1281 1282 SND_SOC_DAPM_MIXER("UL10_CH1", SND_SOC_NOPM, 0, 0, 1283 memif_ul10_ch1_mix, ARRAY_SIZE(memif_ul10_ch1_mix)), 1284 SND_SOC_DAPM_MIXER("UL10_CH2", SND_SOC_NOPM, 0, 0, 1285 memif_ul10_ch2_mix, ARRAY_SIZE(memif_ul10_ch2_mix)), 1286 1287 SND_SOC_DAPM_MIXER("UL24_CH1", SND_SOC_NOPM, 0, 0, 1288 memif_ul24_ch1_mix, ARRAY_SIZE(memif_ul24_ch1_mix)), 1289 SND_SOC_DAPM_MIXER("UL24_CH2", SND_SOC_NOPM, 0, 0, 1290 memif_ul24_ch2_mix, ARRAY_SIZE(memif_ul24_ch2_mix)), 1291 1292 SND_SOC_DAPM_MIXER("UL25_CH1", SND_SOC_NOPM, 0, 0, 1293 memif_ul25_ch1_mix, ARRAY_SIZE(memif_ul25_ch1_mix)), 1294 SND_SOC_DAPM_MIXER("UL25_CH2", SND_SOC_NOPM, 0, 0, 1295 memif_ul25_ch2_mix, ARRAY_SIZE(memif_ul25_ch2_mix)), 1296 1297 SND_SOC_DAPM_MIXER("UL26_CH1", SND_SOC_NOPM, 0, 0, 1298 memif_ul26_ch1_mix, ARRAY_SIZE(memif_ul26_ch1_mix)), 1299 SND_SOC_DAPM_MIXER("UL26_CH2", SND_SOC_NOPM, 0, 0, 1300 memif_ul26_ch2_mix, ARRAY_SIZE(memif_ul26_ch2_mix)), 1301 1302 SND_SOC_DAPM_MIXER("UL_CM0_CH1", SND_SOC_NOPM, 0, 0, 1303 memif_ul_cm0_ch1_mix, ARRAY_SIZE(memif_ul_cm0_ch1_mix)), 1304 SND_SOC_DAPM_MIXER("UL_CM0_CH2", SND_SOC_NOPM, 0, 0, 1305 memif_ul_cm0_ch2_mix, ARRAY_SIZE(memif_ul_cm0_ch2_mix)), 1306 SND_SOC_DAPM_MIXER("UL_CM0_CH3", SND_SOC_NOPM, 0, 0, 1307 memif_ul_cm0_ch3_mix, ARRAY_SIZE(memif_ul_cm0_ch3_mix)), 1308 SND_SOC_DAPM_MIXER("UL_CM0_CH4", SND_SOC_NOPM, 0, 0, 1309 memif_ul_cm0_ch4_mix, ARRAY_SIZE(memif_ul_cm0_ch4_mix)), 1310 SND_SOC_DAPM_MIXER("UL_CM0_CH5", SND_SOC_NOPM, 0, 0, 1311 memif_ul_cm0_ch5_mix, ARRAY_SIZE(memif_ul_cm0_ch5_mix)), 1312 SND_SOC_DAPM_MIXER("UL_CM0_CH6", SND_SOC_NOPM, 0, 0, 1313 memif_ul_cm0_ch6_mix, ARRAY_SIZE(memif_ul_cm0_ch6_mix)), 1314 SND_SOC_DAPM_MIXER("UL_CM0_CH7", SND_SOC_NOPM, 0, 0, 1315 memif_ul_cm0_ch7_mix, ARRAY_SIZE(memif_ul_cm0_ch7_mix)), 1316 SND_SOC_DAPM_MIXER("UL_CM0_CH8", SND_SOC_NOPM, 0, 0, 1317 memif_ul_cm0_ch8_mix, ARRAY_SIZE(memif_ul_cm0_ch8_mix)), 1318 SND_SOC_DAPM_MUX("CM0_UL_MUX", SND_SOC_NOPM, 0, 0, 1319 &ul_cm0_mux_control), 1320 1321 SND_SOC_DAPM_MIXER("UL_CM1_CH1", SND_SOC_NOPM, 0, 0, 1322 memif_ul_cm1_ch1_mix, ARRAY_SIZE(memif_ul_cm1_ch1_mix)), 1323 SND_SOC_DAPM_MIXER("UL_CM1_CH2", SND_SOC_NOPM, 0, 0, 1324 memif_ul_cm1_ch2_mix, ARRAY_SIZE(memif_ul_cm1_ch2_mix)), 1325 SND_SOC_DAPM_MIXER("UL_CM1_CH3", SND_SOC_NOPM, 0, 0, 1326 memif_ul_cm1_ch3_mix, ARRAY_SIZE(memif_ul_cm1_ch3_mix)), 1327 SND_SOC_DAPM_MIXER("UL_CM1_CH4", SND_SOC_NOPM, 0, 0, 1328 memif_ul_cm1_ch4_mix, ARRAY_SIZE(memif_ul_cm1_ch4_mix)), 1329 SND_SOC_DAPM_MIXER("UL_CM1_CH5", SND_SOC_NOPM, 0, 0, 1330 memif_ul_cm1_ch5_mix, ARRAY_SIZE(memif_ul_cm1_ch5_mix)), 1331 SND_SOC_DAPM_MIXER("UL_CM1_CH6", SND_SOC_NOPM, 0, 0, 1332 memif_ul_cm1_ch6_mix, ARRAY_SIZE(memif_ul_cm1_ch6_mix)), 1333 SND_SOC_DAPM_MIXER("UL_CM1_CH7", SND_SOC_NOPM, 0, 0, 1334 memif_ul_cm1_ch7_mix, ARRAY_SIZE(memif_ul_cm1_ch7_mix)), 1335 SND_SOC_DAPM_MIXER("UL_CM1_CH8", SND_SOC_NOPM, 0, 0, 1336 memif_ul_cm1_ch8_mix, ARRAY_SIZE(memif_ul_cm1_ch8_mix)), 1337 SND_SOC_DAPM_MIXER("UL_CM1_CH9", SND_SOC_NOPM, 0, 0, 1338 memif_ul_cm1_ch9_mix, ARRAY_SIZE(memif_ul_cm1_ch9_mix)), 1339 SND_SOC_DAPM_MIXER("UL_CM1_CH10", SND_SOC_NOPM, 0, 0, 1340 memif_ul_cm1_ch10_mix, ARRAY_SIZE(memif_ul_cm1_ch10_mix)), 1341 SND_SOC_DAPM_MIXER("UL_CM1_CH11", SND_SOC_NOPM, 0, 0, 1342 memif_ul_cm1_ch11_mix, ARRAY_SIZE(memif_ul_cm1_ch11_mix)), 1343 SND_SOC_DAPM_MIXER("UL_CM1_CH12", SND_SOC_NOPM, 0, 0, 1344 memif_ul_cm1_ch12_mix, ARRAY_SIZE(memif_ul_cm1_ch12_mix)), 1345 SND_SOC_DAPM_MIXER("UL_CM1_CH13", SND_SOC_NOPM, 0, 0, 1346 memif_ul_cm1_ch13_mix, ARRAY_SIZE(memif_ul_cm1_ch13_mix)), 1347 SND_SOC_DAPM_MIXER("UL_CM1_CH14", SND_SOC_NOPM, 0, 0, 1348 memif_ul_cm1_ch14_mix, ARRAY_SIZE(memif_ul_cm1_ch14_mix)), 1349 SND_SOC_DAPM_MIXER("UL_CM1_CH15", SND_SOC_NOPM, 0, 0, 1350 memif_ul_cm1_ch15_mix, ARRAY_SIZE(memif_ul_cm1_ch15_mix)), 1351 SND_SOC_DAPM_MIXER("UL_CM1_CH16", SND_SOC_NOPM, 0, 0, 1352 memif_ul_cm1_ch16_mix, ARRAY_SIZE(memif_ul_cm1_ch16_mix)), 1353 SND_SOC_DAPM_MUX("CM1_UL_MUX", SND_SOC_NOPM, 0, 0, 1354 &ul_cm1_mux_control), 1355 1356 SND_SOC_DAPM_MIXER("UL_CM2_CH1", SND_SOC_NOPM, 0, 0, 1357 memif_ul_cm2_ch1_mix, ARRAY_SIZE(memif_ul_cm2_ch1_mix)), 1358 SND_SOC_DAPM_MIXER("UL_CM2_CH2", SND_SOC_NOPM, 0, 0, 1359 memif_ul_cm2_ch2_mix, ARRAY_SIZE(memif_ul_cm2_ch2_mix)), 1360 SND_SOC_DAPM_MIXER("UL_CM2_CH3", SND_SOC_NOPM, 0, 0, 1361 memif_ul_cm2_ch3_mix, ARRAY_SIZE(memif_ul_cm2_ch3_mix)), 1362 SND_SOC_DAPM_MIXER("UL_CM2_CH4", SND_SOC_NOPM, 0, 0, 1363 memif_ul_cm2_ch4_mix, ARRAY_SIZE(memif_ul_cm2_ch4_mix)), 1364 SND_SOC_DAPM_MIXER("UL_CM2_CH5", SND_SOC_NOPM, 0, 0, 1365 memif_ul_cm2_ch5_mix, ARRAY_SIZE(memif_ul_cm2_ch5_mix)), 1366 SND_SOC_DAPM_MIXER("UL_CM2_CH6", SND_SOC_NOPM, 0, 0, 1367 memif_ul_cm2_ch6_mix, ARRAY_SIZE(memif_ul_cm2_ch6_mix)), 1368 SND_SOC_DAPM_MIXER("UL_CM2_CH7", SND_SOC_NOPM, 0, 0, 1369 memif_ul_cm2_ch7_mix, ARRAY_SIZE(memif_ul_cm2_ch7_mix)), 1370 SND_SOC_DAPM_MIXER("UL_CM2_CH8", SND_SOC_NOPM, 0, 0, 1371 memif_ul_cm2_ch8_mix, ARRAY_SIZE(memif_ul_cm2_ch8_mix)), 1372 SND_SOC_DAPM_MIXER("UL_CM2_CH9", SND_SOC_NOPM, 0, 0, 1373 memif_ul_cm2_ch9_mix, ARRAY_SIZE(memif_ul_cm2_ch9_mix)), 1374 SND_SOC_DAPM_MIXER("UL_CM2_CH10", SND_SOC_NOPM, 0, 0, 1375 memif_ul_cm2_ch10_mix, ARRAY_SIZE(memif_ul_cm2_ch10_mix)), 1376 SND_SOC_DAPM_MIXER("UL_CM2_CH11", SND_SOC_NOPM, 0, 0, 1377 memif_ul_cm2_ch11_mix, ARRAY_SIZE(memif_ul_cm2_ch11_mix)), 1378 SND_SOC_DAPM_MIXER("UL_CM2_CH12", SND_SOC_NOPM, 0, 0, 1379 memif_ul_cm2_ch12_mix, ARRAY_SIZE(memif_ul_cm2_ch12_mix)), 1380 SND_SOC_DAPM_MIXER("UL_CM2_CH13", SND_SOC_NOPM, 0, 0, 1381 memif_ul_cm2_ch13_mix, ARRAY_SIZE(memif_ul_cm2_ch13_mix)), 1382 SND_SOC_DAPM_MIXER("UL_CM2_CH14", SND_SOC_NOPM, 0, 0, 1383 memif_ul_cm2_ch14_mix, ARRAY_SIZE(memif_ul_cm2_ch14_mix)), 1384 SND_SOC_DAPM_MIXER("UL_CM2_CH15", SND_SOC_NOPM, 0, 0, 1385 memif_ul_cm2_ch15_mix, ARRAY_SIZE(memif_ul_cm2_ch15_mix)), 1386 SND_SOC_DAPM_MIXER("UL_CM2_CH16", SND_SOC_NOPM, 0, 0, 1387 memif_ul_cm2_ch16_mix, ARRAY_SIZE(memif_ul_cm2_ch16_mix)), 1388 SND_SOC_DAPM_MIXER("UL_CM2_CH17", SND_SOC_NOPM, 0, 0, 1389 memif_ul_cm2_ch17_mix, ARRAY_SIZE(memif_ul_cm2_ch17_mix)), 1390 SND_SOC_DAPM_MIXER("UL_CM2_CH18", SND_SOC_NOPM, 0, 0, 1391 memif_ul_cm2_ch18_mix, ARRAY_SIZE(memif_ul_cm2_ch18_mix)), 1392 SND_SOC_DAPM_MIXER("UL_CM2_CH19", SND_SOC_NOPM, 0, 0, 1393 memif_ul_cm2_ch19_mix, ARRAY_SIZE(memif_ul_cm2_ch19_mix)), 1394 SND_SOC_DAPM_MIXER("UL_CM2_CH20", SND_SOC_NOPM, 0, 0, 1395 memif_ul_cm2_ch20_mix, ARRAY_SIZE(memif_ul_cm2_ch20_mix)), 1396 SND_SOC_DAPM_MIXER("UL_CM2_CH21", SND_SOC_NOPM, 0, 0, 1397 memif_ul_cm2_ch21_mix, ARRAY_SIZE(memif_ul_cm2_ch21_mix)), 1398 SND_SOC_DAPM_MIXER("UL_CM2_CH22", SND_SOC_NOPM, 0, 0, 1399 memif_ul_cm2_ch22_mix, ARRAY_SIZE(memif_ul_cm2_ch22_mix)), 1400 SND_SOC_DAPM_MIXER("UL_CM2_CH23", SND_SOC_NOPM, 0, 0, 1401 memif_ul_cm2_ch23_mix, ARRAY_SIZE(memif_ul_cm2_ch23_mix)), 1402 SND_SOC_DAPM_MIXER("UL_CM2_CH24", SND_SOC_NOPM, 0, 0, 1403 memif_ul_cm2_ch24_mix, ARRAY_SIZE(memif_ul_cm2_ch24_mix)), 1404 SND_SOC_DAPM_MIXER("UL_CM2_CH25", SND_SOC_NOPM, 0, 0, 1405 memif_ul_cm2_ch25_mix, ARRAY_SIZE(memif_ul_cm2_ch25_mix)), 1406 SND_SOC_DAPM_MIXER("UL_CM2_CH26", SND_SOC_NOPM, 0, 0, 1407 memif_ul_cm2_ch26_mix, ARRAY_SIZE(memif_ul_cm2_ch26_mix)), 1408 SND_SOC_DAPM_MIXER("UL_CM2_CH27", SND_SOC_NOPM, 0, 0, 1409 memif_ul_cm2_ch27_mix, ARRAY_SIZE(memif_ul_cm2_ch27_mix)), 1410 SND_SOC_DAPM_MIXER("UL_CM2_CH28", SND_SOC_NOPM, 0, 0, 1411 memif_ul_cm2_ch28_mix, ARRAY_SIZE(memif_ul_cm2_ch28_mix)), 1412 SND_SOC_DAPM_MIXER("UL_CM2_CH29", SND_SOC_NOPM, 0, 0, 1413 memif_ul_cm2_ch29_mix, ARRAY_SIZE(memif_ul_cm2_ch29_mix)), 1414 SND_SOC_DAPM_MIXER("UL_CM2_CH30", SND_SOC_NOPM, 0, 0, 1415 memif_ul_cm2_ch30_mix, ARRAY_SIZE(memif_ul_cm2_ch30_mix)), 1416 SND_SOC_DAPM_MIXER("UL_CM2_CH31", SND_SOC_NOPM, 0, 0, 1417 memif_ul_cm2_ch31_mix, ARRAY_SIZE(memif_ul_cm2_ch31_mix)), 1418 SND_SOC_DAPM_MIXER("UL_CM2_CH32", SND_SOC_NOPM, 0, 0, 1419 memif_ul_cm2_ch32_mix, ARRAY_SIZE(memif_ul_cm2_ch32_mix)), 1420 SND_SOC_DAPM_MUX("CM2_UL_MUX", SND_SOC_NOPM, 0, 0, 1421 &ul_cm2_mux_control), 1422 1423 SND_SOC_DAPM_SUPPLY("CM0_Enable", 1424 AFE_CM0_CON0, AFE_CM0_ON_SFT, 0, 1425 ul_cm0_event, 1426 SND_SOC_DAPM_PRE_PMU | 1427 SND_SOC_DAPM_PRE_PMD), 1428 1429 SND_SOC_DAPM_SUPPLY("CM1_Enable", 1430 AFE_CM1_CON0, AFE_CM1_ON_SFT, 0, 1431 ul_cm1_event, 1432 SND_SOC_DAPM_PRE_PMU | 1433 SND_SOC_DAPM_PRE_PMD), 1434 1435 SND_SOC_DAPM_SUPPLY("CM2_Enable", 1436 AFE_CM2_CON0, AFE_CM2_ON_SFT, 0, 1437 ul_cm2_event, 1438 SND_SOC_DAPM_PRE_PMU | 1439 SND_SOC_DAPM_PRE_PMD), 1440 1441 /* dynamic pinctrl */ 1442 SND_SOC_DAPM_PINCTRL("I2S3_PIN", "aud-gpio-i2s3-on", "aud-gpio-i2s3-off"), 1443 SND_SOC_DAPM_PINCTRL("I2S4_PIN", "aud-gpio-i2s4-on", "aud-gpio-i2s4-off"), 1444 SND_SOC_DAPM_PINCTRL("I2S6_PIN", "aud-gpio-i2s6-on", "aud-gpio-i2s6-off"), 1445 SND_SOC_DAPM_PINCTRL("AP_DMIC0_PIN", "aud-gpio-ap-dmic-on", "aud-gpio-ap-dmic-off"), 1446 SND_SOC_DAPM_PINCTRL("AP_DMIC1_PIN", "aud-gpio-ap-dmic1-on", "aud-gpio-ap-dmic1-off"), 1447 }; 1448 1449 static const struct snd_soc_dapm_route mt8196_memif_routes[] = { 1450 {"UL0", NULL, "UL0_CH1"}, 1451 {"UL0", NULL, "UL0_CH2"}, 1452 /* Normal record */ 1453 {"UL0_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, 1454 {"UL0_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, 1455 1456 {"UL1", NULL, "UL1_CH1"}, 1457 {"UL1", NULL, "UL1_CH2"}, 1458 {"UL1_CH1", "I2SIN4_CH1", "I2SIN4"}, 1459 {"UL1_CH2", "I2SIN4_CH2", "I2SIN4"}, 1460 {"UL1_CH1", "I2SIN6_CH1", "I2SIN6"}, 1461 {"UL1_CH2", "I2SIN6_CH2", "I2SIN6"}, 1462 1463 {"UL2", NULL, "UL2_CH1"}, 1464 {"UL2", NULL, "UL2_CH2"}, 1465 {"UL2_CH1", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, 1466 {"UL2_CH2", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, 1467 1468 {"UL3", NULL, "UL3_CH1"}, 1469 {"UL3", NULL, "UL3_CH2"}, 1470 {"UL3_CH1", "I2SIN0_CH1", "I2SIN0"}, 1471 {"UL3_CH2", "I2SIN0_CH2", "I2SIN0"}, 1472 {"UL3_CH1", "I2SIN1_CH1", "I2SIN1"}, 1473 {"UL3_CH2", "I2SIN1_CH2", "I2SIN1"}, 1474 {"UL3_CH1", "I2SIN3_CH1", "I2SIN3"}, 1475 {"UL3_CH2", "I2SIN3_CH2", "I2SIN3"}, 1476 {"UL3_CH1", "I2SIN4_CH1", "I2SIN4"}, 1477 {"UL3_CH2", "I2SIN4_CH2", "I2SIN4"}, 1478 1479 {"UL4", NULL, "UL4_CH1"}, 1480 {"UL4", NULL, "UL4_CH2"}, 1481 {"UL4_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, 1482 {"UL4_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, 1483 {"UL4_CH1", "I2SIN0_CH1", "I2SIN0"}, 1484 {"UL4_CH2", "I2SIN0_CH2", "I2SIN0"}, 1485 1486 {"UL5", NULL, "UL5_CH1"}, 1487 {"UL5", NULL, "UL5_CH2"}, 1488 {"UL5_CH1", "I2SIN3_CH1", "I2SIN3"}, 1489 {"UL5_CH2", "I2SIN3_CH2", "I2SIN3"}, 1490 1491 {"UL6", NULL, "UL6_CH1"}, 1492 {"UL6", NULL, "UL6_CH2"}, 1493 {"UL6_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, 1494 {"UL6_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, 1495 1496 {"UL7", NULL, "UL7_CH1"}, 1497 {"UL7", NULL, "UL7_CH2"}, 1498 {"UL7_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, 1499 {"UL7_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, 1500 1501 {"UL8", NULL, "CM0_UL_MUX"}, 1502 {"CM0_UL_MUX", "UL8_2CH_PATH", "UL8_CH1"}, 1503 {"CM0_UL_MUX", "UL8_2CH_PATH", "UL8_CH2"}, 1504 {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH1"}, 1505 {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH2"}, 1506 {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH3"}, 1507 {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH4"}, 1508 {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH5"}, 1509 {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH6"}, 1510 {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH7"}, 1511 {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH8"}, 1512 1513 {"UL_CM0", NULL, "CM0_Enable"}, 1514 1515 /* UL9 */ 1516 {"UL9", NULL, "CM1_UL_MUX"}, 1517 {"CM1_UL_MUX", "UL9_2CH_PATH", "UL9_CH1"}, 1518 {"CM1_UL_MUX", "UL9_2CH_PATH", "UL9_CH2"}, 1519 {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH1"}, 1520 {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH2"}, 1521 {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH3"}, 1522 {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH4"}, 1523 {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH5"}, 1524 {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH6"}, 1525 {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH7"}, 1526 {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH8"}, 1527 {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH9"}, 1528 {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH10"}, 1529 {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH11"}, 1530 {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH12"}, 1531 {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH13"}, 1532 {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH14"}, 1533 {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH15"}, 1534 {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH16"}, 1535 1536 {"UL_CM1", NULL, "CM1_Enable"}, 1537 1538 {"UL9_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, 1539 {"UL9_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, 1540 1541 {"UL10", NULL, "CM2_UL_MUX"}, 1542 {"CM2_UL_MUX", "UL10_2CH_PATH", "UL10_CH1"}, 1543 {"CM2_UL_MUX", "UL10_2CH_PATH", "UL10_CH2"}, 1544 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH1"}, 1545 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH2"}, 1546 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH3"}, 1547 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH4"}, 1548 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH5"}, 1549 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH6"}, 1550 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH7"}, 1551 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH8"}, 1552 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH9"}, 1553 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH10"}, 1554 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH11"}, 1555 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH12"}, 1556 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH13"}, 1557 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH14"}, 1558 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH15"}, 1559 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH16"}, 1560 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH17"}, 1561 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH18"}, 1562 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH19"}, 1563 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH20"}, 1564 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH21"}, 1565 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH22"}, 1566 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH23"}, 1567 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH24"}, 1568 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH25"}, 1569 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH26"}, 1570 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH27"}, 1571 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH28"}, 1572 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH29"}, 1573 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH30"}, 1574 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH31"}, 1575 {"CM2_UL_MUX", "CM2_32CH_PATH", "UL_CM2_CH32"}, 1576 1577 {"UL_CM2", NULL, "CM2_Enable"}, 1578 1579 {"UL10_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, 1580 {"UL10_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, 1581 1582 {"UL24", NULL, "UL24_CH1"}, 1583 {"UL24", NULL, "UL24_CH2"}, 1584 {"UL24_CH1", "I2SIN6_CH1", "I2SIN6"}, 1585 {"UL24_CH2", "I2SIN6_CH2", "I2SIN6"}, 1586 {"UL24_CH1", "I2SIN0_CH1", "I2SIN0"}, 1587 {"UL24_CH2", "I2SIN0_CH2", "I2SIN0"}, 1588 1589 {"UL25", NULL, "UL25_CH1"}, 1590 {"UL25", NULL, "UL25_CH2"}, 1591 {"UL25_CH1", "I2SIN6_CH1", "I2SIN6"}, 1592 {"UL25_CH2", "I2SIN6_CH2", "I2SIN6"}, 1593 {"UL25_CH1", "I2SIN0_CH1", "I2SIN0"}, 1594 {"UL25_CH2", "I2SIN0_CH2", "I2SIN0"}, 1595 1596 {"UL26", NULL, "UL26_CH1"}, 1597 {"UL26", NULL, "UL26_CH2"}, 1598 {"UL26_CH1", "I2SIN6_CH1", "I2SIN6"}, 1599 {"UL26_CH2", "I2SIN6_CH2", "I2SIN6"}, 1600 {"UL26_CH1", "I2SIN0_CH1", "I2SIN0"}, 1601 {"UL26_CH2", "I2SIN0_CH2", "I2SIN0"}, 1602 1603 {"UL_CM0", NULL, "UL_CM0_CH1"}, 1604 {"UL_CM0", NULL, "UL_CM0_CH2"}, 1605 {"UL_CM0", NULL, "UL_CM0_CH3"}, 1606 {"UL_CM0", NULL, "UL_CM0_CH4"}, 1607 {"UL_CM0", NULL, "UL_CM0_CH5"}, 1608 {"UL_CM0", NULL, "UL_CM0_CH6"}, 1609 {"UL_CM0", NULL, "UL_CM0_CH7"}, 1610 {"UL_CM0", NULL, "UL_CM0_CH8"}, 1611 {"UL_CM0_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, 1612 {"UL_CM0_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, 1613 {"UL_CM0_CH3", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, 1614 {"UL_CM0_CH4", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, 1615 1616 {"UL_CM1", NULL, "UL_CM1_CH1"}, 1617 {"UL_CM1", NULL, "UL_CM1_CH2"}, 1618 {"UL_CM1", NULL, "UL_CM1_CH3"}, 1619 {"UL_CM1", NULL, "UL_CM1_CH4"}, 1620 {"UL_CM1", NULL, "UL_CM1_CH5"}, 1621 {"UL_CM1", NULL, "UL_CM1_CH6"}, 1622 {"UL_CM1", NULL, "UL_CM1_CH7"}, 1623 {"UL_CM1", NULL, "UL_CM1_CH8"}, 1624 {"UL_CM1", NULL, "UL_CM1_CH9"}, 1625 {"UL_CM1", NULL, "UL_CM1_CH10"}, 1626 {"UL_CM1", NULL, "UL_CM1_CH11"}, 1627 {"UL_CM1", NULL, "UL_CM1_CH12"}, 1628 {"UL_CM1", NULL, "UL_CM1_CH13"}, 1629 {"UL_CM1", NULL, "UL_CM1_CH14"}, 1630 {"UL_CM1", NULL, "UL_CM1_CH15"}, 1631 {"UL_CM1", NULL, "UL_CM1_CH16"}, 1632 {"UL_CM1_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, 1633 {"UL_CM1_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, 1634 {"UL_CM1_CH3", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, 1635 {"UL_CM1_CH4", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, 1636 1637 {"UL_CM2", NULL, "UL_CM2_CH1"}, 1638 {"UL_CM2", NULL, "UL_CM2_CH2"}, 1639 {"UL_CM2", NULL, "UL_CM2_CH3"}, 1640 {"UL_CM2", NULL, "UL_CM2_CH4"}, 1641 {"UL_CM2", NULL, "UL_CM2_CH5"}, 1642 {"UL_CM2", NULL, "UL_CM2_CH6"}, 1643 {"UL_CM2", NULL, "UL_CM2_CH7"}, 1644 {"UL_CM2", NULL, "UL_CM2_CH8"}, 1645 {"UL_CM2", NULL, "UL_CM2_CH9"}, 1646 {"UL_CM2", NULL, "UL_CM2_CH10"}, 1647 {"UL_CM2", NULL, "UL_CM2_CH11"}, 1648 {"UL_CM2", NULL, "UL_CM2_CH12"}, 1649 {"UL_CM2", NULL, "UL_CM2_CH13"}, 1650 {"UL_CM2", NULL, "UL_CM2_CH14"}, 1651 {"UL_CM2", NULL, "UL_CM2_CH15"}, 1652 {"UL_CM2", NULL, "UL_CM2_CH16"}, 1653 {"UL_CM2", NULL, "UL_CM2_CH17"}, 1654 {"UL_CM2", NULL, "UL_CM2_CH18"}, 1655 {"UL_CM2", NULL, "UL_CM2_CH19"}, 1656 {"UL_CM2", NULL, "UL_CM2_CH20"}, 1657 {"UL_CM2", NULL, "UL_CM2_CH21"}, 1658 {"UL_CM2", NULL, "UL_CM2_CH22"}, 1659 {"UL_CM2", NULL, "UL_CM2_CH23"}, 1660 {"UL_CM2", NULL, "UL_CM2_CH24"}, 1661 {"UL_CM2", NULL, "UL_CM2_CH25"}, 1662 {"UL_CM2", NULL, "UL_CM2_CH26"}, 1663 {"UL_CM2", NULL, "UL_CM2_CH27"}, 1664 {"UL_CM2", NULL, "UL_CM2_CH28"}, 1665 {"UL_CM2", NULL, "UL_CM2_CH29"}, 1666 {"UL_CM2", NULL, "UL_CM2_CH30"}, 1667 {"UL_CM2", NULL, "UL_CM2_CH31"}, 1668 {"UL_CM2", NULL, "UL_CM2_CH32"}, 1669 {"UL_CM2_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, 1670 {"UL_CM2_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, 1671 {"UL_CM2_CH3", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, 1672 {"UL_CM2_CH4", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, 1673 1674 /* Audio Pin */ 1675 {"I2SOUT4", NULL, "I2S4_PIN"}, 1676 {"I2SIN4", NULL, "I2S4_PIN"}, 1677 {"I2SOUT6", NULL, "I2S6_PIN"}, 1678 {"I2SIN6", NULL, "I2S6_PIN"}, 1679 {"I2SOUT3", NULL, "I2S3_PIN"}, 1680 {"I2SIN3", NULL, "I2S3_PIN"}, 1681 {"AP DMIC Capture", NULL, "AP_DMIC0_PIN"}, 1682 {"AP DMIC CH34 Capture", NULL, "AP_DMIC1_PIN"}, 1683 }; 1684 1685 #define MT8196_DL_MEMIF(_id) \ 1686 [MT8196_MEMIF_##_id] = { \ 1687 .name = #_id, \ 1688 .id = MT8196_MEMIF_##_id, \ 1689 .reg_ofs_base = AFE_##_id##_BASE, \ 1690 .reg_ofs_cur = AFE_##_id##_CUR, \ 1691 .reg_ofs_end = AFE_##_id##_END, \ 1692 .reg_ofs_base_msb = AFE_##_id##_BASE_MSB, \ 1693 .reg_ofs_cur_msb = AFE_##_id##_CUR_MSB, \ 1694 .reg_ofs_end_msb = AFE_##_id##_END_MSB, \ 1695 .fs_reg = AFE_##_id##_CON0, \ 1696 .fs_shift = _id##_SEL_FS_SFT, \ 1697 .fs_maskbit = _id##_SEL_FS_MASK, \ 1698 .mono_reg = AFE_##_id##_CON0, \ 1699 .mono_shift = _id##_MONO_SFT, \ 1700 .enable_reg = AFE_##_id##_CON0, \ 1701 .enable_shift = _id##_ON_SFT, \ 1702 .hd_reg = AFE_##_id##_CON0, \ 1703 .hd_shift = _id##_HD_MODE_SFT, \ 1704 .hd_align_reg = AFE_##_id##_CON0, \ 1705 .hd_align_mshift = _id##_HALIGN_SFT, \ 1706 .agent_disable_reg = -1, \ 1707 .agent_disable_shift = -1, \ 1708 .msb_reg = -1, \ 1709 .msb_shift = -1, \ 1710 .pbuf_reg = AFE_##_id##_CON0, \ 1711 .pbuf_mask = _id##_PBUF_SIZE_MASK, \ 1712 .pbuf_shift = _id##_PBUF_SIZE_SFT, \ 1713 .minlen_reg = AFE_##_id##_CON0, \ 1714 .minlen_mask = _id##_MINLEN_MASK, \ 1715 .minlen_shift = _id##_MINLEN_SFT, \ 1716 } 1717 1718 #define MT8196_MULTI_DL_MEMIF(_id) \ 1719 [MT8196_MEMIF_##_id] = { \ 1720 .name = #_id, \ 1721 .id = MT8196_MEMIF_##_id, \ 1722 .reg_ofs_base = AFE_##_id##_BASE, \ 1723 .reg_ofs_cur = AFE_##_id##_CUR, \ 1724 .reg_ofs_end = AFE_##_id##_END, \ 1725 .reg_ofs_base_msb = AFE_##_id##_BASE_MSB, \ 1726 .reg_ofs_cur_msb = AFE_##_id##_CUR_MSB, \ 1727 .reg_ofs_end_msb = AFE_##_id##_END_MSB, \ 1728 .fs_reg = AFE_##_id##_CON0, \ 1729 .fs_shift = _id##_SEL_FS_SFT, \ 1730 .fs_maskbit = _id##_SEL_FS_MASK, \ 1731 .mono_reg = -1, \ 1732 .mono_shift = -1, \ 1733 .enable_reg = AFE_##_id##_CON0, \ 1734 .enable_shift = _id##_ON_SFT, \ 1735 .hd_reg = AFE_##_id##_CON0, \ 1736 .hd_shift = _id##_HD_MODE_SFT, \ 1737 .hd_align_reg = AFE_##_id##_CON0, \ 1738 .hd_align_mshift = _id##_HALIGN_SFT, \ 1739 .agent_disable_reg = -1, \ 1740 .agent_disable_shift = -1, \ 1741 .msb_reg = -1, \ 1742 .msb_shift = -1, \ 1743 .pbuf_reg = AFE_##_id##_CON0, \ 1744 .pbuf_mask = _id##_PBUF_SIZE_MASK, \ 1745 .pbuf_shift = _id##_PBUF_SIZE_SFT, \ 1746 .minlen_reg = AFE_##_id##_CON0, \ 1747 .minlen_mask = _id##_MINLEN_MASK, \ 1748 .minlen_shift = _id##_MINLEN_SFT, \ 1749 .ch_num_reg = AFE_##_id##_CON0, \ 1750 .ch_num_maskbit = _id##_NUM_MASK, \ 1751 .ch_num_shift = _id##_NUM_SFT, \ 1752 } 1753 1754 #define MT8196_UL_MEMIF(_id, _fs_shift, _fs_maskbit, _mono_shift) \ 1755 [MT8196_MEMIF_##_id] = { \ 1756 .name = #_id, \ 1757 .id = MT8196_MEMIF_##_id, \ 1758 .reg_ofs_base = AFE_##_id##_BASE, \ 1759 .reg_ofs_cur = AFE_##_id##_CUR, \ 1760 .reg_ofs_end = AFE_##_id##_END, \ 1761 .reg_ofs_base_msb = AFE_##_id##_BASE_MSB, \ 1762 .reg_ofs_cur_msb = AFE_##_id##_CUR_MSB, \ 1763 .reg_ofs_end_msb = AFE_##_id##_END_MSB, \ 1764 .fs_reg = AFE_##_id##_CON0, \ 1765 .fs_shift = _fs_shift, \ 1766 .fs_maskbit = _fs_maskbit, \ 1767 .mono_reg = AFE_##_id##_CON0, \ 1768 .mono_shift = _mono_shift, \ 1769 .enable_reg = AFE_##_id##_CON0, \ 1770 .enable_shift = _id##_ON_SFT, \ 1771 .hd_reg = AFE_##_id##_CON0, \ 1772 .hd_shift = _id##_HD_MODE_SFT, \ 1773 .hd_align_reg = AFE_##_id##_CON0, \ 1774 .hd_align_mshift = _id##_HALIGN_SFT, \ 1775 .agent_disable_reg = -1, \ 1776 .agent_disable_shift = -1, \ 1777 .msb_reg = -1, \ 1778 .msb_shift = -1, \ 1779 } 1780 1781 /* For convenience with macros: missing register fields */ 1782 #define HDMI_SEL_FS_SFT -1 1783 #define HDMI_SEL_FS_MASK -1 1784 1785 /* For convenience with macros: register name differences */ 1786 #define AFE_HDMI_BASE AFE_HDMI_OUT_BASE 1787 #define AFE_HDMI_CUR AFE_HDMI_OUT_CUR 1788 #define AFE_HDMI_END AFE_HDMI_OUT_END 1789 #define AFE_HDMI_BASE_MSB AFE_HDMI_OUT_BASE_MSB 1790 #define AFE_HDMI_CUR_MSB AFE_HDMI_OUT_CUR_MSB 1791 #define AFE_HDMI_END_MSB AFE_HDMI_OUT_END_MSB 1792 #define AFE_HDMI_CON0 AFE_HDMI_OUT_CON0 1793 #define HDMI_ON_SFT HDMI_OUT_ON_SFT 1794 #define HDMI_HD_MODE_SFT HDMI_OUT_HD_MODE_SFT 1795 #define HDMI_HALIGN_SFT HDMI_OUT_HALIGN_SFT 1796 #define HDMI_PBUF_SIZE_MASK HDMI_OUT_PBUF_SIZE_MASK 1797 #define HDMI_PBUF_SIZE_SFT HDMI_OUT_PBUF_SIZE_SFT 1798 #define HDMI_MINLEN_MASK HDMI_OUT_MINLEN_MASK 1799 #define HDMI_MINLEN_SFT HDMI_OUT_MINLEN_SFT 1800 #define HDMI_NUM_MASK HDMI_CH_NUM_MASK 1801 #define HDMI_NUM_SFT HDMI_CH_NUM_SFT 1802 1803 static const struct mtk_base_memif_data memif_data[MT8196_MEMIF_NUM] = { 1804 MT8196_DL_MEMIF(DL0), 1805 MT8196_DL_MEMIF(DL1), 1806 MT8196_DL_MEMIF(DL2), 1807 MT8196_DL_MEMIF(DL3), 1808 MT8196_DL_MEMIF(DL4), 1809 MT8196_DL_MEMIF(DL5), 1810 MT8196_DL_MEMIF(DL6), 1811 MT8196_DL_MEMIF(DL7), 1812 MT8196_DL_MEMIF(DL8), 1813 MT8196_DL_MEMIF(DL23), 1814 MT8196_DL_MEMIF(DL24), 1815 MT8196_DL_MEMIF(DL25), 1816 MT8196_DL_MEMIF(DL26), 1817 MT8196_MULTI_DL_MEMIF(DL_4CH), 1818 MT8196_MULTI_DL_MEMIF(DL_24CH), 1819 MT8196_MULTI_DL_MEMIF(HDMI), 1820 MT8196_UL_MEMIF(VUL0, VUL0_SEL_FS_SFT, VUL0_SEL_FS_MASK, VUL0_MONO_SFT), 1821 MT8196_UL_MEMIF(VUL1, VUL1_SEL_FS_SFT, VUL1_SEL_FS_MASK, VUL1_MONO_SFT), 1822 MT8196_UL_MEMIF(VUL2, VUL2_SEL_FS_SFT, VUL2_SEL_FS_MASK, VUL2_MONO_SFT), 1823 MT8196_UL_MEMIF(VUL3, VUL3_SEL_FS_SFT, VUL3_SEL_FS_MASK, VUL3_MONO_SFT), 1824 MT8196_UL_MEMIF(VUL4, VUL4_SEL_FS_SFT, VUL4_SEL_FS_MASK, VUL4_MONO_SFT), 1825 MT8196_UL_MEMIF(VUL5, VUL5_SEL_FS_SFT, VUL5_SEL_FS_MASK, VUL5_MONO_SFT), 1826 MT8196_UL_MEMIF(VUL6, VUL6_SEL_FS_SFT, VUL6_SEL_FS_MASK, VUL6_MONO_SFT), 1827 MT8196_UL_MEMIF(VUL7, VUL7_SEL_FS_SFT, VUL7_SEL_FS_MASK, VUL7_MONO_SFT), 1828 MT8196_UL_MEMIF(VUL8, VUL8_SEL_FS_SFT, VUL8_SEL_FS_MASK, VUL8_MONO_SFT), 1829 MT8196_UL_MEMIF(VUL9, VUL9_SEL_FS_SFT, VUL9_SEL_FS_MASK, VUL9_MONO_SFT), 1830 MT8196_UL_MEMIF(VUL10, VUL10_SEL_FS_SFT, VUL10_SEL_FS_MASK, VUL10_MONO_SFT), 1831 MT8196_UL_MEMIF(VUL24, VUL24_SEL_FS_SFT, VUL24_SEL_FS_MASK, VUL24_MONO_SFT), 1832 MT8196_UL_MEMIF(VUL25, VUL25_SEL_FS_SFT, VUL25_SEL_FS_MASK, VUL25_MONO_SFT), 1833 MT8196_UL_MEMIF(VUL26, VUL26_SEL_FS_SFT, VUL26_SEL_FS_MASK, VUL26_MONO_SFT), 1834 MT8196_UL_MEMIF(VUL_CM0, -1, -1, -1), 1835 MT8196_UL_MEMIF(VUL_CM1, -1, -1, -1), 1836 MT8196_UL_MEMIF(VUL_CM2, -1, -1, -1), 1837 MT8196_UL_MEMIF(ETDM_IN0, REG_FS_TIMING_SEL_SFT, REG_FS_TIMING_SEL_MASK, -1), 1838 MT8196_UL_MEMIF(ETDM_IN1, REG_FS_TIMING_SEL_SFT, REG_FS_TIMING_SEL_MASK, -1), 1839 MT8196_UL_MEMIF(ETDM_IN2, REG_FS_TIMING_SEL_SFT, REG_FS_TIMING_SEL_MASK, -1), 1840 MT8196_UL_MEMIF(ETDM_IN3, REG_FS_TIMING_SEL_SFT, REG_FS_TIMING_SEL_MASK, -1), 1841 MT8196_UL_MEMIF(ETDM_IN4, REG_FS_TIMING_SEL_SFT, REG_FS_TIMING_SEL_MASK, -1), 1842 MT8196_UL_MEMIF(ETDM_IN6, REG_FS_TIMING_SEL_SFT, REG_FS_TIMING_SEL_MASK, -1), 1843 }; 1844 1845 #define MT8196_AFE_IRQ(_id) \ 1846 [MT8196_IRQ_##_id] = { \ 1847 .id = MT8196_IRQ_##_id, \ 1848 .irq_cnt_reg = AFE_IRQ##_id##_MCU_CFG1, \ 1849 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, \ 1850 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, \ 1851 .irq_fs_reg = AFE_IRQ##_id##_MCU_CFG0, \ 1852 .irq_fs_shift = AFE_IRQ##_id##_MCU_FS_SFT, \ 1853 .irq_fs_maskbit = AFE_IRQ##_id##_MCU_FS_MASK, \ 1854 .irq_en_reg = AFE_IRQ##_id##_MCU_CFG0, \ 1855 .irq_en_shift = AFE_IRQ##_id##_MCU_ON_SFT, \ 1856 .irq_clr_reg = AFE_IRQ##_id##_MCU_CFG1, \ 1857 .irq_clr_shift = AFE_IRQ##_id##_CLR_CFG_SFT, \ 1858 } 1859 1860 #define MT8196_AFE_TDM_IRQ(_id) \ 1861 [MT8196_IRQ_##_id] = { \ 1862 .id = MT8196_CUS_IRQ_TDM, \ 1863 .irq_cnt_reg = AFE_CUSTOM_IRQ0_MCU_CFG1, \ 1864 .irq_cnt_shift = AFE_CUSTOM_IRQ0_MCU_CNT_SFT, \ 1865 .irq_cnt_maskbit = AFE_CUSTOM_IRQ0_MCU_CNT_MASK, \ 1866 .irq_fs_reg = -1, \ 1867 .irq_fs_shift = -1, \ 1868 .irq_fs_maskbit = -1, \ 1869 .irq_en_reg = AFE_CUSTOM_IRQ0_MCU_CFG0, \ 1870 .irq_en_shift = AFE_CUSTOM_IRQ0_MCU_ON_SFT, \ 1871 .irq_clr_reg = AFE_CUSTOM_IRQ0_MCU_CFG1, \ 1872 .irq_clr_shift = AFE_CUSTOM_IRQ0_CLR_CFG_SFT, \ 1873 } 1874 1875 static const struct mtk_base_irq_data irq_data[MT8196_IRQ_NUM] = { 1876 MT8196_AFE_IRQ(0), 1877 MT8196_AFE_IRQ(1), 1878 MT8196_AFE_IRQ(2), 1879 MT8196_AFE_IRQ(3), 1880 MT8196_AFE_IRQ(4), 1881 MT8196_AFE_IRQ(5), 1882 MT8196_AFE_IRQ(6), 1883 MT8196_AFE_IRQ(7), 1884 MT8196_AFE_IRQ(8), 1885 MT8196_AFE_IRQ(9), 1886 MT8196_AFE_IRQ(10), 1887 MT8196_AFE_IRQ(11), 1888 MT8196_AFE_IRQ(12), 1889 MT8196_AFE_IRQ(13), 1890 MT8196_AFE_IRQ(14), 1891 MT8196_AFE_IRQ(15), 1892 MT8196_AFE_IRQ(16), 1893 MT8196_AFE_IRQ(17), 1894 MT8196_AFE_IRQ(18), 1895 MT8196_AFE_IRQ(19), 1896 MT8196_AFE_IRQ(20), 1897 MT8196_AFE_IRQ(21), 1898 MT8196_AFE_IRQ(22), 1899 MT8196_AFE_IRQ(23), 1900 MT8196_AFE_IRQ(24), 1901 MT8196_AFE_IRQ(25), 1902 MT8196_AFE_IRQ(26), 1903 MT8196_AFE_TDM_IRQ(31), 1904 }; 1905 1906 static const int memif_irq_usage[MT8196_MEMIF_NUM] = { 1907 /* TODO: verify each memif & irq */ 1908 [MT8196_MEMIF_DL0] = MT8196_IRQ_0, 1909 [MT8196_MEMIF_DL1] = MT8196_IRQ_1, 1910 [MT8196_MEMIF_DL2] = MT8196_IRQ_2, 1911 [MT8196_MEMIF_DL3] = MT8196_IRQ_3, 1912 [MT8196_MEMIF_DL4] = MT8196_IRQ_4, 1913 [MT8196_MEMIF_DL5] = MT8196_IRQ_5, 1914 [MT8196_MEMIF_DL6] = MT8196_IRQ_6, 1915 [MT8196_MEMIF_DL7] = MT8196_IRQ_7, 1916 [MT8196_MEMIF_DL8] = MT8196_IRQ_8, 1917 [MT8196_MEMIF_DL23] = MT8196_IRQ_9, 1918 [MT8196_MEMIF_DL24] = MT8196_IRQ_10, 1919 [MT8196_MEMIF_DL25] = MT8196_IRQ_11, 1920 [MT8196_MEMIF_DL26] = MT8196_IRQ_0, 1921 [MT8196_MEMIF_DL_4CH] = MT8196_IRQ_0, 1922 [MT8196_MEMIF_DL_24CH] = MT8196_IRQ_12, 1923 [MT8196_MEMIF_VUL0] = MT8196_IRQ_13, 1924 [MT8196_MEMIF_VUL1] = MT8196_IRQ_14, 1925 [MT8196_MEMIF_VUL2] = MT8196_IRQ_15, 1926 [MT8196_MEMIF_VUL3] = MT8196_IRQ_16, 1927 [MT8196_MEMIF_VUL4] = MT8196_IRQ_17, 1928 [MT8196_MEMIF_VUL5] = MT8196_IRQ_18, 1929 [MT8196_MEMIF_VUL6] = MT8196_IRQ_19, 1930 [MT8196_MEMIF_VUL7] = MT8196_IRQ_20, 1931 [MT8196_MEMIF_VUL8] = MT8196_IRQ_21, 1932 [MT8196_MEMIF_VUL9] = MT8196_IRQ_22, 1933 [MT8196_MEMIF_VUL10] = MT8196_IRQ_23, 1934 [MT8196_MEMIF_VUL24] = MT8196_IRQ_24, 1935 [MT8196_MEMIF_VUL25] = MT8196_IRQ_25, 1936 [MT8196_MEMIF_VUL26] = MT8196_IRQ_0, 1937 [MT8196_MEMIF_VUL_CM0] = MT8196_IRQ_26, 1938 [MT8196_MEMIF_VUL_CM1] = MT8196_IRQ_0, 1939 [MT8196_MEMIF_VUL_CM2] = MT8196_IRQ_0, 1940 [MT8196_MEMIF_ETDM_IN0] = MT8196_IRQ_0, 1941 [MT8196_MEMIF_ETDM_IN1] = MT8196_IRQ_0, 1942 [MT8196_MEMIF_ETDM_IN2] = MT8196_IRQ_0, 1943 [MT8196_MEMIF_ETDM_IN3] = MT8196_IRQ_0, 1944 [MT8196_MEMIF_ETDM_IN4] = MT8196_IRQ_0, 1945 [MT8196_MEMIF_ETDM_IN6] = MT8196_IRQ_0, 1946 [MT8196_MEMIF_HDMI] = MT8196_IRQ_31 1947 }; 1948 1949 static bool mt8196_is_volatile_reg(struct device *dev, unsigned int reg) 1950 { 1951 /* these auto-gen reg has read-only bit, so put it as volatile */ 1952 /* volatile reg cannot be cached, so cannot be set when power off */ 1953 switch (reg) { 1954 case AUDIO_TOP_CON0 ... AUDIO_TOP_CON4: 1955 case AFE_APLL1_TUNER_MON0: 1956 case AFE_APLL2_TUNER_MON0: 1957 case AFE_SPM_CONTROL_ACK: 1958 case AUDIO_TOP_IP_VERSION: 1959 case AUDIO_ENGEN_CON0_MON: 1960 case AUD_TOP_MON_RG: 1961 case AFE_CONNSYS_I2S_IPM_VER_MON: 1962 case AFE_CONNSYS_I2S_MON: 1963 case AFE_PCM_INTF_MON: 1964 case AFE_PCM_TOP_IP_VERSION: 1965 case AFE_IRQ_MCU_STATUS: 1966 case AFE_CUSTOM_IRQ_MCU_STATUS: 1967 case AFE_IRQ_MCU_MON0 ... AFE_IRQ26_CNT_MON: 1968 case AFE_CUSTOM_IRQ0_CNT_MON: 1969 case AFE_STF_MON: 1970 case AFE_STF_IP_VERSION: 1971 case AFE_CM0_MON: 1972 case AFE_CM0_IP_VERSION: 1973 case AFE_CM1_MON: 1974 case AFE_CM1_IP_VERSION: 1975 case AFE_ADDA_UL0_SRC_DEBUG_MON0 ... AFE_ADDA_UL0_SRC_MON1: 1976 case AFE_ADDA_UL0_IP_VERSION: 1977 case AFE_ADDA_UL1_SRC_DEBUG_MON0 ... AFE_ADDA_UL1_SRC_MON1: 1978 case AFE_ADDA_UL1_IP_VERSION: 1979 case AFE_MTKAIF_IPM_VER_MON: 1980 case AFE_MTKAIF_MON: 1981 case AFE_AUD_PAD_TOP_MON: 1982 case AFE_ADDA_MTKAIFV4_MON0 ... AFE_ADDA6_MTKAIFV4_MON0: 1983 case ETDM_IN0_MON: 1984 case ETDM_IN1_MON: 1985 case ETDM_IN2_MON: 1986 case ETDM_IN4_MON: 1987 case ETDM_IN6_MON: 1988 case ETDM_OUT0_MON: 1989 case ETDM_OUT1_MON: 1990 case ETDM_OUT2_MON: 1991 case ETDM_OUT4_MON: 1992 case ETDM_OUT6_MON: 1993 case AFE_DPTX_MON: 1994 case AFE_TDM_TOP_IP_VERSION: 1995 case AFE_CONN_MON0 ... AFE_CONN_MON5: 1996 case AFE_CBIP_SLV_DECODER_MON0 ... AFE_CBIP_SLV_MUX_MON1: 1997 case AFE_DL0_CUR_MSB ... AFE_DL0_CUR: 1998 case AFE_DL0_RCH_MON ... AFE_DL0_LCH_MON: 1999 case AFE_DL1_CUR_MSB ... AFE_DL1_CUR: 2000 case AFE_DL1_RCH_MON ... AFE_DL1_LCH_MON: 2001 case AFE_DL2_CUR_MSB ... AFE_DL2_CUR: 2002 case AFE_DL2_RCH_MON ... AFE_DL2_LCH_MON: 2003 case AFE_DL3_CUR_MSB ... AFE_DL3_CUR: 2004 case AFE_DL3_RCH_MON ... AFE_DL3_LCH_MON: 2005 case AFE_DL4_CUR_MSB ... AFE_DL4_CUR: 2006 case AFE_DL4_RCH_MON ... AFE_DL4_LCH_MON: 2007 case AFE_DL5_CUR_MSB ... AFE_DL5_CUR: 2008 case AFE_DL5_RCH_MON ... AFE_DL5_LCH_MON: 2009 case AFE_DL6_CUR_MSB ... AFE_DL6_CUR: 2010 case AFE_DL6_RCH_MON ... AFE_DL6_LCH_MON: 2011 case AFE_DL7_CUR_MSB ... AFE_DL7_CUR: 2012 case AFE_DL7_RCH_MON ... AFE_DL7_LCH_MON: 2013 case AFE_DL8_CUR_MSB ... AFE_DL8_CUR: 2014 case AFE_DL8_RCH_MON ... AFE_DL8_LCH_MON: 2015 case AFE_DL_24CH_CUR_MSB ... AFE_DL_24CH_CUR: 2016 case AFE_DL_4CH_CUR_MSB ... AFE_DL_4CH_CUR: 2017 case AFE_DL23_CUR_MSB ... AFE_DL23_CUR: 2018 case AFE_DL23_RCH_MON ... AFE_DL23_LCH_MON: 2019 case AFE_DL24_CUR_MSB ... AFE_DL24_CUR: 2020 case AFE_DL24_RCH_MON ... AFE_DL24_LCH_MON: 2021 case AFE_DL25_CUR_MSB ... AFE_DL25_CUR: 2022 case AFE_DL25_RCH_MON ... AFE_DL25_LCH_MON: 2023 case AFE_DL26_CUR_MSB ... AFE_DL26_CUR: 2024 case AFE_DL26_RCH_MON ... AFE_DL26_LCH_MON: 2025 case AFE_VUL0_CUR_MSB ... AFE_VUL0_CUR: 2026 case AFE_VUL1_CUR_MSB ... AFE_VUL1_CUR: 2027 case AFE_VUL2_CUR_MSB ... AFE_VUL2_CUR: 2028 case AFE_VUL3_CUR_MSB ... AFE_VUL3_CUR: 2029 case AFE_VUL4_CUR_MSB ... AFE_VUL4_CUR: 2030 case AFE_VUL5_CUR_MSB ... AFE_VUL5_CUR: 2031 case AFE_VUL6_CUR_MSB ... AFE_VUL6_CUR: 2032 case AFE_VUL7_CUR_MSB ... AFE_VUL7_CUR: 2033 case AFE_VUL8_CUR_MSB ... AFE_VUL8_CUR: 2034 case AFE_VUL9_CUR_MSB ... AFE_VUL9_CUR: 2035 case AFE_VUL10_CUR_MSB ... AFE_VUL10_CUR: 2036 case AFE_VUL24_CUR_MSB ... AFE_VUL24_CUR: 2037 case AFE_VUL25_CUR_MSB ... AFE_VUL25_CUR: 2038 case AFE_VUL25_RCH_MON ... AFE_VUL25_LCH_MON: 2039 case AFE_VUL26_CUR_MSB ... AFE_VUL26_CUR: 2040 case AFE_VUL_CM0_BASE_MSB ... AFE_VUL_CM0_CON0: 2041 case AFE_VUL_CM1_CUR_MSB ... AFE_VUL_CM1_CUR: 2042 case AFE_VUL_CM2_CUR_MSB ... AFE_VUL_CM2_CUR: 2043 case AFE_ETDM_IN0_CUR_MSB ... AFE_ETDM_IN0_CUR: 2044 case AFE_ETDM_IN1_CUR_MSB ... AFE_ETDM_IN1_CUR: 2045 case AFE_ETDM_IN2_CUR_MSB ... AFE_ETDM_IN2_CUR: 2046 case AFE_ETDM_IN3_CUR_MSB ... AFE_ETDM_IN3_CUR: 2047 case AFE_ETDM_IN4_CUR_MSB ... AFE_ETDM_IN4_CUR: 2048 case AFE_ETDM_IN6_CUR_MSB ... AFE_ETDM_IN6_CUR: 2049 case AFE_HDMI_OUT_CUR_MSB ... AFE_HDMI_OUT_CUR: 2050 case AFE_HDMI_OUT_END: 2051 case AFE_PROT_SIDEBAND0_MON ... AFE_DOMAIN_SIDEBAND9_MON: 2052 case AFE_PCM0_INTF_CON1_MASK_MON ... AFE_ADDA_UL1_SRC_CON0_MASK_MON: 2053 case AFE_IRQ_MCU_EN ... AFE_IRQ_MCU_DSP2_EN: 2054 case AFE_CUSTOM_IRQ_MCU_EN: 2055 case AFE_DL5_CON0: 2056 case AFE_DL6_CON0: 2057 case AFE_DL23_CON0: 2058 case AFE_DL_24CH_CON0: 2059 case AFE_VUL1_CON0: 2060 case AFE_VUL3_CON0: 2061 case AFE_VUL4_CON0: 2062 case AFE_VUL5_CON0: 2063 case AFE_VUL9_CON0: 2064 case AFE_VUL25_CON0: 2065 case AFE_IRQ0_MCU_CFG0 ... AFE_IRQ26_MCU_CFG1: 2066 return true; 2067 default: 2068 return false; 2069 }; 2070 } 2071 2072 static const struct regmap_config mt8196_afe_regmap_config = { 2073 .reg_bits = 32, 2074 .reg_stride = 4, 2075 .val_bits = 32, 2076 2077 .volatile_reg = mt8196_is_volatile_reg, 2078 2079 .max_register = AFE_MAX_REGISTER, 2080 .num_reg_defaults_raw = AFE_MAX_REGISTER, 2081 2082 .cache_type = REGCACHE_FLAT, 2083 }; 2084 2085 static irqreturn_t mt8196_afe_irq_handler(int irq_id, void *dev) 2086 { 2087 struct mtk_base_afe *afe = dev; 2088 struct mtk_base_afe_irq *irq; 2089 u32 status; 2090 u32 status_mcu; 2091 u32 mcu_en; 2092 u32 cus_status; 2093 u32 cus_status_mcu; 2094 u32 cus_mcu_en; 2095 u32 tmp_reg; 2096 int ret, cus_ret; 2097 int i; 2098 struct timespec64 ts64; 2099 u64 t1, t2; 2100 /* one interrupt period = 5ms */ 2101 const u64 timeout_limit = 5000000; 2102 2103 /* get irq that is sent to MCU */ 2104 regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en); 2105 regmap_read(afe->regmap, AFE_CUSTOM_IRQ_MCU_EN, &cus_mcu_en); 2106 2107 ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status); 2108 cus_ret = regmap_read(afe->regmap, AFE_CUSTOM_IRQ_MCU_STATUS, &cus_status); 2109 /* only care IRQ which is sent to MCU */ 2110 status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS; 2111 cus_status_mcu = cus_status & cus_mcu_en & AFE_IRQ_STATUS_BITS; 2112 if ((ret || !status_mcu) && (cus_ret || !cus_status_mcu)) { 2113 dev_err(afe->dev, "ret %d, sat 0x%x, en 0x%x,csat 0x%x, cen 0x%x\n", 2114 ret, status, mcu_en, cus_status_mcu, cus_mcu_en); 2115 return IRQ_NONE; 2116 } 2117 2118 ktime_get_ts64(&ts64); 2119 t1 = ktime_get_ns(); 2120 2121 for (i = 0; i < MT8196_MEMIF_NUM; i++) { 2122 struct mtk_base_afe_memif *memif = &afe->memif[i]; 2123 2124 if (!memif->substream) 2125 continue; 2126 2127 if (memif->irq_usage < 0) 2128 continue; 2129 irq = &afe->irqs[memif->irq_usage]; 2130 2131 if (i == MT8196_MEMIF_HDMI) { 2132 if (cus_status_mcu & BIT(irq->irq_data->id)) 2133 snd_pcm_period_elapsed(memif->substream); 2134 } else { 2135 if (status_mcu & BIT(irq->irq_data->id)) 2136 snd_pcm_period_elapsed(memif->substream); 2137 } 2138 } 2139 2140 ktime_get_ts64(&ts64); 2141 t2 = ktime_get_ns(); 2142 t2 = t2 - t1; /* in ns (10^9) */ 2143 2144 if (t2 > timeout_limit) 2145 dev_warn(afe->dev, "IRQ handler exceeded time limit by %llu ns\n", 2146 t2 - timeout_limit); 2147 2148 /* clear irq */ 2149 for (i = 0; i < MT8196_IRQ_NUM; ++i) { 2150 /* cus_status_mcu only bit0 is used for TDM */ 2151 if ((status_mcu & BIT(i)) || (cus_status_mcu & 0x1)) { 2152 regmap_read(afe->regmap, irq_data[i].irq_clr_reg, &tmp_reg); 2153 regmap_update_bits(afe->regmap, irq_data[i].irq_clr_reg, 2154 AFE_IRQ_CLR_CFG_MASK_SFT | 2155 AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT, 2156 tmp_reg ^ (AFE_IRQ_CLR_CFG_MASK_SFT | 2157 AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT)); 2158 } 2159 } 2160 2161 return IRQ_HANDLED; 2162 } 2163 2164 static int mt8196_afe_runtime_suspend(struct device *dev) 2165 { 2166 struct mtk_base_afe *afe = dev_get_drvdata(dev); 2167 unsigned int value; 2168 unsigned int tmp_reg; 2169 int ret, i; 2170 2171 if (!afe->regmap) { 2172 dev_err(afe->dev, "skip regmap\n"); 2173 goto skip_regmap; 2174 } 2175 2176 /* disable AFE */ 2177 mt8196_afe_disable_main_clock(afe); 2178 2179 ret = regmap_read_poll_timeout(afe->regmap, 2180 AUDIO_ENGEN_CON0_MON, 2181 value, 2182 (value & AUDIO_ENGEN_MON_SFT) == 0, 2183 20, 2184 1 * 1000 * 1000); 2185 dev_dbg(afe->dev, "read_poll ret %d\n", ret); 2186 if (ret) 2187 dev_warn(afe->dev, "ret %d\n", ret); 2188 2189 /* make sure all irq status are cleared */ 2190 for (i = 0; i < MT8196_IRQ_NUM; ++i) { 2191 regmap_read(afe->regmap, irq_data[i].irq_clr_reg, &tmp_reg); 2192 regmap_update_bits(afe->regmap, irq_data[i].irq_clr_reg, 2193 AFE_IRQ_CLR_CFG_MASK_SFT | AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT, 2194 tmp_reg ^ (AFE_IRQ_CLR_CFG_MASK_SFT | 2195 AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT)); 2196 } 2197 2198 /* reset audio 26M request */ 2199 regmap_update_bits(afe->regmap, 2200 AFE_SPM_CONTROL_REQ, 0x1, 0x0); 2201 2202 /* cache only */ 2203 regcache_cache_only(afe->regmap, true); 2204 regcache_mark_dirty(afe->regmap); 2205 2206 skip_regmap: 2207 mt8196_afe_disable_reg_rw_clk(afe); 2208 return 0; 2209 } 2210 2211 static int mt8196_afe_runtime_resume(struct device *dev) 2212 { 2213 struct mtk_base_afe *afe = dev_get_drvdata(dev); 2214 int ret = 0; 2215 2216 ret = mt8196_afe_enable_reg_rw_clk(afe); 2217 if (ret) 2218 return ret; 2219 2220 if (!afe->regmap) { 2221 dev_warn(afe->dev, "skip regmap\n"); 2222 goto skip_regmap; 2223 } 2224 regcache_cache_only(afe->regmap, false); 2225 regcache_sync(afe->regmap); 2226 2227 /* set audio 26M request */ 2228 regmap_update_bits(afe->regmap, AFE_SPM_CONTROL_REQ, 0x1, 0x1); 2229 regmap_update_bits(afe->regmap, AFE_CBIP_CFG0, 0x1, 0x1); 2230 2231 /* force cpu use 8_24 format when writing 32bit data */ 2232 regmap_update_bits(afe->regmap, AFE_MEMIF_CON0, 2233 CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT); 2234 2235 /* enable AFE */ 2236 mt8196_afe_enable_main_clock(afe); 2237 2238 skip_regmap: 2239 return 0; 2240 } 2241 2242 static int mt8196_afe_component_probe(struct snd_soc_component *component) 2243 { 2244 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 2245 int ret; 2246 2247 /* enable clock for regcache get default value from hw */ 2248 ret = pm_runtime_resume_and_get(afe->dev); 2249 if (ret) 2250 return dev_err_probe(afe->dev, ret, "failed to resume device\n"); 2251 2252 mtk_afe_add_sub_dai_control(component); 2253 pm_runtime_put_sync(afe->dev); 2254 2255 return 0; 2256 } 2257 2258 static int mt8196_afe_pcm_open(struct snd_soc_component *component, 2259 struct snd_pcm_substream *substream) 2260 { 2261 /* set the wait_for_avail to 2 sec*/ 2262 substream->wait_time = msecs_to_jiffies(2 * 1000); 2263 2264 return 0; 2265 } 2266 2267 static void mt8196_afe_pcm_free(struct snd_soc_component *component, struct snd_pcm *pcm) 2268 { 2269 snd_pcm_lib_preallocate_free_for_all(pcm); 2270 } 2271 2272 static const struct snd_soc_component_driver mt8196_afe_component = { 2273 .name = AFE_PCM_NAME, 2274 .probe = mt8196_afe_component_probe, 2275 .pcm_new = mtk_afe_pcm_new, 2276 .pcm_free = mt8196_afe_pcm_free, 2277 .open = mt8196_afe_pcm_open, 2278 .pointer = mtk_afe_pcm_pointer, 2279 }; 2280 2281 static int mt8196_dai_memif_register(struct mtk_base_afe *afe) 2282 { 2283 struct mtk_base_afe_dai *dai; 2284 2285 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 2286 if (!dai) 2287 return -ENOMEM; 2288 2289 list_add(&dai->list, &afe->sub_dais); 2290 2291 dai->dai_drivers = mt8196_memif_dai_driver; 2292 dai->num_dai_drivers = ARRAY_SIZE(mt8196_memif_dai_driver); 2293 dai->dapm_widgets = mt8196_memif_widgets; 2294 dai->num_dapm_widgets = ARRAY_SIZE(mt8196_memif_widgets); 2295 dai->dapm_routes = mt8196_memif_routes; 2296 dai->num_dapm_routes = ARRAY_SIZE(mt8196_memif_routes); 2297 return 0; 2298 } 2299 2300 typedef int (*dai_register_cb)(struct mtk_base_afe *); 2301 static const dai_register_cb dai_register_cbs[] = { 2302 mt8196_dai_adda_register, 2303 mt8196_dai_i2s_register, 2304 mt8196_dai_tdm_register, 2305 mt8196_dai_memif_register, 2306 }; 2307 2308 static const struct reg_sequence mt8196_cg_patch[] = { 2309 { AUDIO_TOP_CON4, 0x361c }, 2310 }; 2311 2312 static void mt8196_afe_release_reserved_mem(void *data) 2313 { 2314 of_reserved_mem_device_release(data); 2315 } 2316 2317 static int mt8196_afe_pcm_dev_probe(struct platform_device *pdev) 2318 { 2319 int ret, i; 2320 unsigned int tmp_reg; 2321 int irq_id; 2322 struct mtk_base_afe *afe; 2323 struct mt8196_afe_private *afe_priv; 2324 struct device *dev = &pdev->dev; 2325 2326 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34)); 2327 if (ret) 2328 return ret; 2329 2330 ret = of_reserved_mem_device_init(dev); 2331 if (ret) { 2332 dev_err(dev, "failed to assign memory region: %d\n", ret); 2333 } else { 2334 ret = devm_add_action_or_reset(dev, mt8196_afe_release_reserved_mem, dev); 2335 if (ret) 2336 return ret; 2337 } 2338 2339 afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL); 2340 if (!afe) 2341 return -ENOMEM; 2342 2343 platform_set_drvdata(pdev, afe); 2344 2345 afe->platform_priv = devm_kzalloc(dev, sizeof(*afe_priv), 2346 GFP_KERNEL); 2347 if (!afe->platform_priv) 2348 return -ENOMEM; 2349 2350 afe_priv = afe->platform_priv; 2351 afe->dev = dev; 2352 2353 afe->base_addr = devm_platform_ioremap_resource(pdev, 0); 2354 if (IS_ERR(afe->base_addr)) 2355 return dev_err_probe(dev, PTR_ERR(afe->base_addr), 2356 "AFE base_addr not found\n"); 2357 2358 /* init audio related clock */ 2359 ret = mt8196_init_clock(afe); 2360 if (ret) 2361 return dev_err_probe(dev, ret, "init clock error.\n"); 2362 2363 /* init memif */ 2364 /* IPM2.0 no need banding */ 2365 afe->memif_32bit_supported = 1; 2366 afe->memif_size = MT8196_MEMIF_NUM; 2367 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), 2368 GFP_KERNEL); 2369 2370 if (!afe->memif) 2371 return -ENOMEM; 2372 2373 for (i = 0; i < afe->memif_size; i++) { 2374 afe->memif[i].data = &memif_data[i]; 2375 afe->memif[i].irq_usage = memif_irq_usage[i]; 2376 afe->memif[i].const_irq = 1; 2377 } 2378 2379 mutex_init(&afe->irq_alloc_lock); 2380 2381 /* init irq */ 2382 afe->irqs_size = MT8196_IRQ_NUM; 2383 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs), 2384 GFP_KERNEL); 2385 2386 if (!afe->irqs) 2387 return -ENOMEM; 2388 2389 for (i = 0; i < afe->irqs_size; i++) 2390 afe->irqs[i].irq_data = &irq_data[i]; 2391 2392 /* request irq */ 2393 irq_id = platform_get_irq(pdev, 0); 2394 if (irq_id < 0) 2395 return dev_err_probe(dev, irq_id, "no irq found"); 2396 2397 ret = devm_request_irq(dev, irq_id, mt8196_afe_irq_handler, 2398 IRQF_TRIGGER_NONE, 2399 "Afe_ISR_Handle", afe); 2400 if (ret) 2401 return dev_err_probe(dev, ret, "could not request_irq for Afe_ISR_Handle\n"); 2402 2403 /* init sub_dais */ 2404 INIT_LIST_HEAD(&afe->sub_dais); 2405 2406 for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) { 2407 ret = dai_register_cbs[i](afe); 2408 if (ret) 2409 return dev_err_probe(dev, ret, "dai register i %d fail\n", i); 2410 } 2411 2412 /* init dai_driver and component_driver */ 2413 ret = mtk_afe_combine_sub_dai(afe); 2414 if (ret) 2415 return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n"); 2416 2417 /* others */ 2418 afe->mtk_afe_hardware = &mt8196_afe_hardware; 2419 afe->memif_fs = mt8196_memif_fs; 2420 afe->irq_fs = mt8196_irq_fs; 2421 afe->get_dai_fs = mt8196_get_dai_fs; 2422 afe->get_memif_pbuf_size = mt8196_get_memif_pbuf_size; 2423 2424 afe->runtime_resume = mt8196_afe_runtime_resume; 2425 afe->runtime_suspend = mt8196_afe_runtime_suspend; 2426 2427 ret = devm_pm_runtime_enable(dev); 2428 if (ret) 2429 return ret; 2430 2431 /* 2432 * Audio device is part of genpd. Registering it as a syscore device ensure 2433 * the proper power-on sequence of the AFE device. 2434 */ 2435 dev_pm_syscore_device(dev, true); 2436 2437 /* enable clock for regcache get default value from hw */ 2438 ret = pm_runtime_resume_and_get(dev); 2439 if (ret) 2440 return dev_err_probe(dev, ret, "failed to resume device\n"); 2441 2442 afe->regmap = devm_regmap_init_mmio(dev, afe->base_addr, 2443 &mt8196_afe_regmap_config); 2444 if (IS_ERR(afe->regmap)) { 2445 ret = PTR_ERR(afe->regmap); 2446 goto err_pm_put; 2447 } 2448 2449 ret = regmap_register_patch(afe->regmap, mt8196_cg_patch, 2450 ARRAY_SIZE(mt8196_cg_patch)); 2451 if (ret < 0) { 2452 dev_err(dev, "Failed to apply cg patch\n"); 2453 goto err_pm_put; 2454 } 2455 2456 regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &tmp_reg); 2457 regmap_write(afe->regmap, AFE_IRQ_MCU_EN, 0xffffffff); 2458 regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &tmp_reg); 2459 2460 pm_runtime_put_sync(dev); 2461 2462 regcache_cache_only(afe->regmap, true); 2463 regcache_mark_dirty(afe->regmap); 2464 2465 /* register component */ 2466 ret = devm_snd_soc_register_component(dev, 2467 &mt8196_afe_component, 2468 afe->dai_drivers, 2469 afe->num_dai_drivers); 2470 if (ret) { 2471 dev_err(dev, "afe component err\n"); 2472 return ret; 2473 } 2474 2475 return 0; 2476 2477 err_pm_put: 2478 pm_runtime_put_sync(dev); 2479 return ret; 2480 } 2481 2482 static void mt8196_afe_pcm_dev_remove(struct platform_device *pdev) 2483 { 2484 struct mtk_base_afe *afe = platform_get_drvdata(pdev); 2485 struct device *dev = &pdev->dev; 2486 2487 if (!pm_runtime_status_suspended(dev)) 2488 mt8196_afe_runtime_suspend(dev); 2489 2490 mt8196_afe_disable_main_clock(afe); 2491 /* disable afe clock */ 2492 mt8196_afe_disable_reg_rw_clk(afe); 2493 } 2494 2495 static const struct of_device_id mt8196_afe_pcm_dt_match[] = { 2496 { .compatible = "mediatek,mt8196-afe", }, 2497 { /* sentinel */ }, 2498 }; 2499 MODULE_DEVICE_TABLE(of, mt8196_afe_pcm_dt_match); 2500 2501 static const struct dev_pm_ops mt8196_afe_pm_ops = { 2502 SET_RUNTIME_PM_OPS(mt8196_afe_runtime_suspend, 2503 mt8196_afe_runtime_resume, NULL) 2504 }; 2505 2506 static struct platform_driver mt8196_afe_pcm_driver = { 2507 .driver = { 2508 .name = "mt8196-afe", 2509 .of_match_table = mt8196_afe_pcm_dt_match, 2510 .pm = &mt8196_afe_pm_ops, 2511 }, 2512 .probe = mt8196_afe_pcm_dev_probe, 2513 .remove = mt8196_afe_pcm_dev_remove, 2514 }; 2515 module_platform_driver(mt8196_afe_pcm_driver); 2516 2517 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8196"); 2518 MODULE_AUTHOR("Darren Ye <darren.ye@mediatek.com>"); 2519 MODULE_LICENSE("GPL"); 2520