1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * mt8196-afe-common.h -- Mediatek 8196 audio driver definitions 4 * 5 * Copyright (c) 2025 MediaTek Inc. 6 * Author: Darren Ye <darren.ye@mediatek.com> 7 */ 8 9 #ifndef _MT_8196_AFE_COMMON_H_ 10 #define _MT_8196_AFE_COMMON_H_ 11 #include <sound/pcm.h> 12 #include <sound/soc.h> 13 14 #include "mt8196-reg.h" 15 #include "../common/mtk-base-afe.h" 16 17 /* HW IPM 2.0 */ 18 enum { 19 MTK_AFE_IPM2P0_RATE_8K = 0x0, 20 MTK_AFE_IPM2P0_RATE_11K = 0x1, 21 MTK_AFE_IPM2P0_RATE_12K = 0x2, 22 MTK_AFE_IPM2P0_RATE_16K = 0x4, 23 MTK_AFE_IPM2P0_RATE_22K = 0x5, 24 MTK_AFE_IPM2P0_RATE_24K = 0x6, 25 MTK_AFE_IPM2P0_RATE_32K = 0x8, 26 MTK_AFE_IPM2P0_RATE_44K = 0x9, 27 MTK_AFE_IPM2P0_RATE_48K = 0xa, 28 MTK_AFE_IPM2P0_RATE_88K = 0xd, 29 MTK_AFE_IPM2P0_RATE_96K = 0xe, 30 MTK_AFE_IPM2P0_RATE_176K = 0x11, 31 MTK_AFE_IPM2P0_RATE_192K = 0x12, 32 MTK_AFE_IPM2P0_RATE_352K = 0x15, 33 MTK_AFE_IPM2P0_RATE_384K = 0x16, 34 }; 35 36 enum { 37 MTKAIF_PROTOCOL_1, 38 MTKAIF_PROTOCOL_2, 39 MTKAIF_PROTOCOL_2_CLK_P2, 40 }; 41 42 enum { 43 MT8196_MEMIF_DL0, 44 MT8196_MEMIF_DL1, 45 MT8196_MEMIF_DL2, 46 MT8196_MEMIF_DL3, 47 MT8196_MEMIF_DL4, 48 MT8196_MEMIF_DL5, 49 MT8196_MEMIF_DL6, 50 MT8196_MEMIF_DL7, 51 MT8196_MEMIF_DL8, 52 MT8196_MEMIF_DL23, 53 MT8196_MEMIF_DL24, 54 MT8196_MEMIF_DL25, 55 MT8196_MEMIF_DL26, 56 MT8196_MEMIF_DL_4CH, 57 MT8196_MEMIF_DL_24CH, 58 MT8196_MEMIF_VUL0, 59 MT8196_MEMIF_VUL1, 60 MT8196_MEMIF_VUL2, 61 MT8196_MEMIF_VUL3, 62 MT8196_MEMIF_VUL4, 63 MT8196_MEMIF_VUL5, 64 MT8196_MEMIF_VUL6, 65 MT8196_MEMIF_VUL7, 66 MT8196_MEMIF_VUL8, 67 MT8196_MEMIF_VUL9, 68 MT8196_MEMIF_VUL10, 69 MT8196_MEMIF_VUL24, 70 MT8196_MEMIF_VUL25, 71 MT8196_MEMIF_VUL26, 72 MT8196_MEMIF_VUL_CM0, 73 MT8196_MEMIF_VUL_CM1, 74 MT8196_MEMIF_VUL_CM2, 75 MT8196_MEMIF_ETDM_IN0, 76 MT8196_MEMIF_ETDM_IN1, 77 MT8196_MEMIF_ETDM_IN2, 78 MT8196_MEMIF_ETDM_IN3, 79 MT8196_MEMIF_ETDM_IN4, 80 MT8196_MEMIF_ETDM_IN6, 81 MT8196_MEMIF_HDMI, 82 MT8196_MEMIF_NUM, 83 MT8196_DAI_ADDA = MT8196_MEMIF_NUM, 84 MT8196_DAI_ADDA_CH34, 85 MT8196_DAI_ADDA_CH56, 86 MT8196_DAI_AP_DMIC, 87 MT8196_DAI_AP_DMIC_CH34, 88 MT8196_DAI_AP_DMIC_MULTICH, 89 MT8196_DAI_I2S_IN0, 90 MT8196_DAI_I2S_IN1, 91 MT8196_DAI_I2S_IN2, 92 MT8196_DAI_I2S_IN3, 93 MT8196_DAI_I2S_IN4, 94 MT8196_DAI_I2S_IN6, 95 MT8196_DAI_I2S_OUT0, 96 MT8196_DAI_I2S_OUT1, 97 MT8196_DAI_I2S_OUT2, 98 MT8196_DAI_I2S_OUT3, 99 MT8196_DAI_I2S_OUT4, 100 MT8196_DAI_I2S_OUT6, 101 MT8196_DAI_FM_I2S_MASTER, 102 MT8196_DAI_TDM, 103 MT8196_DAI_TDM_DPTX, 104 MT8196_DAI_NUM, 105 }; 106 107 #define MT8196_DAI_I2S_MAX_NUM 13 //depends each platform's max i2s num 108 109 /* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */ 110 enum { 111 MT8196_IRQ_0, 112 MT8196_IRQ_1, 113 MT8196_IRQ_2, 114 MT8196_IRQ_3, 115 MT8196_IRQ_4, 116 MT8196_IRQ_5, 117 MT8196_IRQ_6, 118 MT8196_IRQ_7, 119 MT8196_IRQ_8, 120 MT8196_IRQ_9, 121 MT8196_IRQ_10, 122 MT8196_IRQ_11, 123 MT8196_IRQ_12, 124 MT8196_IRQ_13, 125 MT8196_IRQ_14, 126 MT8196_IRQ_15, 127 MT8196_IRQ_16, 128 MT8196_IRQ_17, 129 MT8196_IRQ_18, 130 MT8196_IRQ_19, 131 MT8196_IRQ_20, 132 MT8196_IRQ_21, 133 MT8196_IRQ_22, 134 MT8196_IRQ_23, 135 MT8196_IRQ_24, 136 MT8196_IRQ_25, 137 MT8196_IRQ_26, 138 MT8196_IRQ_31, /* used only for TDM */ 139 MT8196_IRQ_NUM, 140 }; 141 142 /* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */ 143 enum { 144 MT8196_CUS_IRQ_TDM, /* used only for TDM */ 145 MT8196_CUS_IRQ_NUM, 146 }; 147 148 enum { 149 /* AUDIO_ENGEN_CON0 */ 150 MT8196_AUDIO_26M_EN_ON, 151 MT8196_AUDIO_F3P25M_EN_ON, 152 MT8196_AUDIO_APLL1_EN_ON, 153 MT8196_AUDIO_APLL2_EN_ON, 154 MT8196_AUDIO_F26M_EN_RST, 155 MT8196_MULTI_USER_RST, 156 MT8196_MULTI_USER_BYPASS, 157 /* AUDIO_TOP_CON4 */ 158 MT8196_CG_AUDIO_HOPPING_CK, 159 MT8196_CG_AUDIO_F26M_CK, 160 MT8196_CG_APLL1_CK, 161 MT8196_CG_APLL2_CK, 162 MT8196_PDN_APLL_TUNER2, 163 MT8196_PDN_APLL_TUNER1, 164 MT8196_AUDIO_CG_NUM, 165 }; 166 167 /* MCLK */ 168 enum { 169 MT8196_I2SIN0_MCK, 170 MT8196_I2SIN1_MCK, 171 MT8196_FMI2S_MCK, 172 MT8196_TDMOUT_MCK, 173 MT8196_TDMOUT_BCK, 174 MT8196_MCK_NUM, 175 }; 176 177 /* CM*/ 178 enum { 179 CM0, 180 CM1, 181 CM2, 182 CM_NUM, 183 }; 184 185 struct clk; 186 struct mtk_base_afe; 187 188 struct mt8196_afe_private { 189 struct clk **clk; 190 /* dai */ 191 void *dai_priv[MT8196_DAI_NUM]; 192 /* mck */ 193 int mck_rate[MT8196_MCK_NUM]; 194 /* channel merge */ 195 u32 cm_rate[CM_NUM]; 196 u32 cm_channels; 197 }; 198 199 int mt8196_dai_adda_register(struct mtk_base_afe *afe); 200 int mt8196_dai_i2s_register(struct mtk_base_afe *afe); 201 int mt8196_dai_tdm_register(struct mtk_base_afe *afe); 202 int mt8196_dai_set_priv(struct mtk_base_afe *afe, int id, 203 int priv_size, const void *priv_data); 204 205 #endif 206