1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * mt8196-afe-clk.h -- Mediatek MT8196 AFE Clock Control definitions 4 * 5 * Copyright (c) 2025 MediaTek Inc. 6 * Author: Darren Ye <darren.ye@mediatek.com> 7 */ 8 9 #ifndef _MT8196_AFE_CLOCK_CTRL_H_ 10 #define _MT8196_AFE_CLOCK_CTRL_H_ 11 12 #define MT8196_AFE_26M 26000000 13 #define MT8196_AUD_ENG1_CLK 45158400 14 #define MT8196_AUD_ENG2_CLK 49152000 15 16 /* APLL */ 17 #define APLL1_W_NAME "APLL1" 18 #define APLL2_W_NAME "APLL2" 19 20 enum { 21 MT8196_APLL1 = 0, 22 MT8196_APLL2, 23 }; 24 25 enum { 26 /* vlp clk */ 27 MT8196_CLK_VLP_MUX_AUDIOINTBUS, 28 MT8196_CLK_VLP_MUX_AUD_ENG1, 29 MT8196_CLK_VLP_MUX_AUD_ENG2, 30 MT8196_CLK_VLP_MUX_AUDIO_H, 31 /* pll */ 32 MT8196_CLK_TOP_APLL1_CK, 33 MT8196_CLK_TOP_APLL2_CK, 34 /* divider */ 35 MT8196_CLK_TOP_APLL12_DIV_I2SIN0, 36 MT8196_CLK_TOP_APLL12_DIV_I2SIN1, 37 MT8196_CLK_TOP_APLL12_DIV_FMI2S, 38 MT8196_CLK_TOP_APLL12_DIV_TDMOUT_M, 39 MT8196_CLK_TOP_APLL12_DIV_TDMOUT_B, 40 /* mux */ 41 MT8196_CLK_TOP_ADSP_SEL, 42 MT8196_CLK_NUM, 43 }; 44 45 struct mtk_base_afe; 46 47 int mt8196_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate); 48 int mt8196_mck_disable(struct mtk_base_afe *afe, int mck_id); 49 int mt8196_get_apll_rate(struct mtk_base_afe *afe, int apll); 50 int mt8196_get_apll_by_rate(struct mtk_base_afe *afe, int rate); 51 int mt8196_get_apll_by_name(struct mtk_base_afe *afe, const char *name); 52 int mt8196_init_clock(struct mtk_base_afe *afe); 53 int mt8196_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk); 54 void mt8196_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk); 55 int mt8196_apll1_enable(struct mtk_base_afe *afe); 56 void mt8196_apll1_disable(struct mtk_base_afe *afe); 57 int mt8196_apll2_enable(struct mtk_base_afe *afe); 58 void mt8196_apll2_disable(struct mtk_base_afe *afe); 59 int mt8196_afe_enable_main_clock(struct mtk_base_afe *afe); 60 int mt8196_afe_disable_main_clock(struct mtk_base_afe *afe); 61 int mt8196_afe_enable_reg_rw_clk(struct mtk_base_afe *afe); 62 int mt8196_afe_disable_reg_rw_clk(struct mtk_base_afe *afe); 63 64 #endif 65