1*81f8f29aSCyril Chao /* SPDX-License-Identifier: GPL-2.0 */ 2*81f8f29aSCyril Chao /* 3*81f8f29aSCyril Chao * Mediatek MT8189 audio driver interconnection definition 4*81f8f29aSCyril Chao * 5*81f8f29aSCyril Chao * Copyright (c) 2025 MediaTek Inc. 6*81f8f29aSCyril Chao * Author: Darren Ye <darren.ye@mediatek.com> 7*81f8f29aSCyril Chao */ 8*81f8f29aSCyril Chao 9*81f8f29aSCyril Chao #ifndef _MT8189_INTERCONNECTION_H_ 10*81f8f29aSCyril Chao #define _MT8189_INTERCONNECTION_H_ 11*81f8f29aSCyril Chao 12*81f8f29aSCyril Chao /* in port define */ 13*81f8f29aSCyril Chao #define I_CONNSYS_I2S_CH1 0 14*81f8f29aSCyril Chao #define I_CONNSYS_I2S_CH2 1 15*81f8f29aSCyril Chao #define I_GAIN0_OUT_CH1 6 16*81f8f29aSCyril Chao #define I_GAIN0_OUT_CH2 7 17*81f8f29aSCyril Chao #define I_GAIN1_OUT_CH1 8 18*81f8f29aSCyril Chao #define I_GAIN1_OUT_CH2 9 19*81f8f29aSCyril Chao #define I_GAIN2_OUT_CH1 10 20*81f8f29aSCyril Chao #define I_GAIN2_OUT_CH2 11 21*81f8f29aSCyril Chao #define I_GAIN3_OUT_CH1 12 22*81f8f29aSCyril Chao #define I_GAIN3_OUT_CH2 13 23*81f8f29aSCyril Chao #define I_STF_CH1 14 24*81f8f29aSCyril Chao #define I_ADDA_UL_CH1 16 25*81f8f29aSCyril Chao #define I_ADDA_UL_CH2 17 26*81f8f29aSCyril Chao #define I_ADDA_UL_CH3 18 27*81f8f29aSCyril Chao #define I_ADDA_UL_CH4 19 28*81f8f29aSCyril Chao #define I_UL_PROX_CH1 20 29*81f8f29aSCyril Chao #define I_UL_PROX_CH2 21 30*81f8f29aSCyril Chao #define I_ADDA_UL_CH5 24 31*81f8f29aSCyril Chao #define I_ADDA_UL_CH6 25 32*81f8f29aSCyril Chao #define I_DMIC0_CH1 28 33*81f8f29aSCyril Chao #define I_DMIC0_CH2 29 34*81f8f29aSCyril Chao #define I_DMIC1_CH1 30 35*81f8f29aSCyril Chao #define I_DMIC1_CH2 31 36*81f8f29aSCyril Chao 37*81f8f29aSCyril Chao /* in port define >= 32 */ 38*81f8f29aSCyril Chao #define I_32_OFFSET 32 39*81f8f29aSCyril Chao #define I_DL0_CH1 (32 - I_32_OFFSET) 40*81f8f29aSCyril Chao #define I_DL0_CH2 (33 - I_32_OFFSET) 41*81f8f29aSCyril Chao #define I_DL1_CH1 (34 - I_32_OFFSET) 42*81f8f29aSCyril Chao #define I_DL1_CH2 (35 - I_32_OFFSET) 43*81f8f29aSCyril Chao #define I_DL2_CH1 (36 - I_32_OFFSET) 44*81f8f29aSCyril Chao #define I_DL2_CH2 (37 - I_32_OFFSET) 45*81f8f29aSCyril Chao #define I_DL3_CH1 (38 - I_32_OFFSET) 46*81f8f29aSCyril Chao #define I_DL3_CH2 (39 - I_32_OFFSET) 47*81f8f29aSCyril Chao #define I_DL4_CH1 (40 - I_32_OFFSET) 48*81f8f29aSCyril Chao #define I_DL4_CH2 (41 - I_32_OFFSET) 49*81f8f29aSCyril Chao #define I_DL5_CH1 (42 - I_32_OFFSET) 50*81f8f29aSCyril Chao #define I_DL5_CH2 (43 - I_32_OFFSET) 51*81f8f29aSCyril Chao #define I_DL6_CH1 (44 - I_32_OFFSET) 52*81f8f29aSCyril Chao #define I_DL6_CH2 (45 - I_32_OFFSET) 53*81f8f29aSCyril Chao #define I_DL7_CH1 (46 - I_32_OFFSET) 54*81f8f29aSCyril Chao #define I_DL7_CH2 (47 - I_32_OFFSET) 55*81f8f29aSCyril Chao #define I_DL8_CH1 (48 - I_32_OFFSET) 56*81f8f29aSCyril Chao #define I_DL8_CH2 (49 - I_32_OFFSET) 57*81f8f29aSCyril Chao #define I_DL_24CH_CH1 (54 - I_32_OFFSET) 58*81f8f29aSCyril Chao #define I_DL_24CH_CH2 (55 - I_32_OFFSET) 59*81f8f29aSCyril Chao #define I_DL_24CH_CH3 (56 - I_32_OFFSET) 60*81f8f29aSCyril Chao #define I_DL_24CH_CH4 (57 - I_32_OFFSET) 61*81f8f29aSCyril Chao #define I_DL_24CH_CH5 (58 - I_32_OFFSET) 62*81f8f29aSCyril Chao #define I_DL_24CH_CH6 (59 - I_32_OFFSET) 63*81f8f29aSCyril Chao #define I_DL_24CH_CH7 (60 - I_32_OFFSET) 64*81f8f29aSCyril Chao #define I_DL_24CH_CH8 (61 - I_32_OFFSET) 65*81f8f29aSCyril Chao 66*81f8f29aSCyril Chao /* in port define >= 64 */ 67*81f8f29aSCyril Chao #define I_64_OFFSET 64 68*81f8f29aSCyril Chao #define I_DL23_CH1 (78 - I_64_OFFSET) 69*81f8f29aSCyril Chao #define I_DL23_CH2 (79 - I_64_OFFSET) 70*81f8f29aSCyril Chao #define I_DL24_CH1 (80 - I_64_OFFSET) 71*81f8f29aSCyril Chao #define I_DL24_CH2 (81 - I_64_OFFSET) 72*81f8f29aSCyril Chao #define I_DL25_CH1 (82 - I_64_OFFSET) 73*81f8f29aSCyril Chao #define I_DL25_CH2 (83 - I_64_OFFSET) 74*81f8f29aSCyril Chao 75*81f8f29aSCyril Chao /* in port define >= 128 */ 76*81f8f29aSCyril Chao #define I_128_OFFSET 128 77*81f8f29aSCyril Chao #define I_PCM_0_CAP_CH1 (130 - I_128_OFFSET) 78*81f8f29aSCyril Chao #define I_PCM_0_CAP_CH2 (131 - I_128_OFFSET) 79*81f8f29aSCyril Chao #define I_I2SIN0_CH1 (134 - I_128_OFFSET) 80*81f8f29aSCyril Chao #define I_I2SIN0_CH2 (135 - I_128_OFFSET) 81*81f8f29aSCyril Chao #define I_I2SIN1_CH1 (136 - I_128_OFFSET) 82*81f8f29aSCyril Chao #define I_I2SIN1_CH2 (137 - I_128_OFFSET) 83*81f8f29aSCyril Chao 84*81f8f29aSCyril Chao /* in port define >= 192 */ 85*81f8f29aSCyril Chao #define I_192_OFFSET 192 86*81f8f29aSCyril Chao #define I_SRC_0_OUT_CH1 (198 - I_192_OFFSET) 87*81f8f29aSCyril Chao #define I_SRC_0_OUT_CH2 (199 - I_192_OFFSET) 88*81f8f29aSCyril Chao #define I_SRC_1_OUT_CH1 (200 - I_192_OFFSET) 89*81f8f29aSCyril Chao #define I_SRC_1_OUT_CH2 (201 - I_192_OFFSET) 90*81f8f29aSCyril Chao #define I_SRC_2_OUT_CH1 (202 - I_192_OFFSET) 91*81f8f29aSCyril Chao #define I_SRC_2_OUT_CH2 (203 - I_192_OFFSET) 92*81f8f29aSCyril Chao #define I_SRC_3_OUT_CH1 (204 - I_192_OFFSET) 93*81f8f29aSCyril Chao #define I_SRC_3_OUT_CH2 (205 - I_192_OFFSET) 94*81f8f29aSCyril Chao #define I_SRC_4_OUT_CH1 (206 - I_192_OFFSET) 95*81f8f29aSCyril Chao #define I_SRC_4_OUT_CH2 (207 - I_192_OFFSET) 96*81f8f29aSCyril Chao 97*81f8f29aSCyril Chao #endif 98