1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Mediatek MT8189 audio driver interconnection definition 4 * 5 * Copyright (c) 2025 MediaTek Inc. 6 * Author: Darren Ye <darren.ye@mediatek.com> 7 */ 8 9 #ifndef _MT8189_INTERCONNECTION_H_ 10 #define _MT8189_INTERCONNECTION_H_ 11 12 /* in port define */ 13 #define I_CONNSYS_I2S_CH1 0 14 #define I_CONNSYS_I2S_CH2 1 15 #define I_GAIN0_OUT_CH1 6 16 #define I_GAIN0_OUT_CH2 7 17 #define I_GAIN1_OUT_CH1 8 18 #define I_GAIN1_OUT_CH2 9 19 #define I_GAIN2_OUT_CH1 10 20 #define I_GAIN2_OUT_CH2 11 21 #define I_GAIN3_OUT_CH1 12 22 #define I_GAIN3_OUT_CH2 13 23 #define I_STF_CH1 14 24 #define I_ADDA_UL_CH1 16 25 #define I_ADDA_UL_CH2 17 26 #define I_ADDA_UL_CH3 18 27 #define I_ADDA_UL_CH4 19 28 #define I_UL_PROX_CH1 20 29 #define I_UL_PROX_CH2 21 30 #define I_ADDA_UL_CH5 24 31 #define I_ADDA_UL_CH6 25 32 #define I_DMIC0_CH1 28 33 #define I_DMIC0_CH2 29 34 #define I_DMIC1_CH1 30 35 #define I_DMIC1_CH2 31 36 37 /* in port define >= 32 */ 38 #define I_32_OFFSET 32 39 #define I_DL0_CH1 (32 - I_32_OFFSET) 40 #define I_DL0_CH2 (33 - I_32_OFFSET) 41 #define I_DL1_CH1 (34 - I_32_OFFSET) 42 #define I_DL1_CH2 (35 - I_32_OFFSET) 43 #define I_DL2_CH1 (36 - I_32_OFFSET) 44 #define I_DL2_CH2 (37 - I_32_OFFSET) 45 #define I_DL3_CH1 (38 - I_32_OFFSET) 46 #define I_DL3_CH2 (39 - I_32_OFFSET) 47 #define I_DL4_CH1 (40 - I_32_OFFSET) 48 #define I_DL4_CH2 (41 - I_32_OFFSET) 49 #define I_DL5_CH1 (42 - I_32_OFFSET) 50 #define I_DL5_CH2 (43 - I_32_OFFSET) 51 #define I_DL6_CH1 (44 - I_32_OFFSET) 52 #define I_DL6_CH2 (45 - I_32_OFFSET) 53 #define I_DL7_CH1 (46 - I_32_OFFSET) 54 #define I_DL7_CH2 (47 - I_32_OFFSET) 55 #define I_DL8_CH1 (48 - I_32_OFFSET) 56 #define I_DL8_CH2 (49 - I_32_OFFSET) 57 #define I_DL_24CH_CH1 (54 - I_32_OFFSET) 58 #define I_DL_24CH_CH2 (55 - I_32_OFFSET) 59 #define I_DL_24CH_CH3 (56 - I_32_OFFSET) 60 #define I_DL_24CH_CH4 (57 - I_32_OFFSET) 61 #define I_DL_24CH_CH5 (58 - I_32_OFFSET) 62 #define I_DL_24CH_CH6 (59 - I_32_OFFSET) 63 #define I_DL_24CH_CH7 (60 - I_32_OFFSET) 64 #define I_DL_24CH_CH8 (61 - I_32_OFFSET) 65 66 /* in port define >= 64 */ 67 #define I_64_OFFSET 64 68 #define I_DL23_CH1 (78 - I_64_OFFSET) 69 #define I_DL23_CH2 (79 - I_64_OFFSET) 70 #define I_DL24_CH1 (80 - I_64_OFFSET) 71 #define I_DL24_CH2 (81 - I_64_OFFSET) 72 #define I_DL25_CH1 (82 - I_64_OFFSET) 73 #define I_DL25_CH2 (83 - I_64_OFFSET) 74 75 /* in port define >= 128 */ 76 #define I_128_OFFSET 128 77 #define I_PCM_0_CAP_CH1 (130 - I_128_OFFSET) 78 #define I_PCM_0_CAP_CH2 (131 - I_128_OFFSET) 79 #define I_I2SIN0_CH1 (134 - I_128_OFFSET) 80 #define I_I2SIN0_CH2 (135 - I_128_OFFSET) 81 #define I_I2SIN1_CH1 (136 - I_128_OFFSET) 82 #define I_I2SIN1_CH2 (137 - I_128_OFFSET) 83 84 /* in port define >= 192 */ 85 #define I_192_OFFSET 192 86 #define I_SRC_0_OUT_CH1 (198 - I_192_OFFSET) 87 #define I_SRC_0_OUT_CH2 (199 - I_192_OFFSET) 88 #define I_SRC_1_OUT_CH1 (200 - I_192_OFFSET) 89 #define I_SRC_1_OUT_CH2 (201 - I_192_OFFSET) 90 #define I_SRC_2_OUT_CH1 (202 - I_192_OFFSET) 91 #define I_SRC_2_OUT_CH2 (203 - I_192_OFFSET) 92 #define I_SRC_3_OUT_CH1 (204 - I_192_OFFSET) 93 #define I_SRC_3_OUT_CH2 (205 - I_192_OFFSET) 94 #define I_SRC_4_OUT_CH1 (206 - I_192_OFFSET) 95 #define I_SRC_4_OUT_CH2 (207 - I_192_OFFSET) 96 97 #endif 98