1 /* 2 * wm8903.c -- WM8903 ALSA SoC Audio driver 3 * 4 * Copyright 2008 Wolfson Microelectronics 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * TODO: 13 * - TDM mode configuration. 14 * - Digital microphone support. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/moduleparam.h> 19 #include <linux/init.h> 20 #include <linux/completion.h> 21 #include <linux/delay.h> 22 #include <linux/pm.h> 23 #include <linux/i2c.h> 24 #include <linux/platform_device.h> 25 #include <linux/slab.h> 26 #include <sound/core.h> 27 #include <sound/jack.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/tlv.h> 31 #include <sound/soc.h> 32 #include <sound/soc-dapm.h> 33 #include <sound/initval.h> 34 #include <sound/wm8903.h> 35 36 #include "wm8903.h" 37 38 /* Register defaults at reset */ 39 static u16 wm8903_reg_defaults[] = { 40 0x8903, /* R0 - SW Reset and ID */ 41 0x0000, /* R1 - Revision Number */ 42 0x0000, /* R2 */ 43 0x0000, /* R3 */ 44 0x0018, /* R4 - Bias Control 0 */ 45 0x0000, /* R5 - VMID Control 0 */ 46 0x0000, /* R6 - Mic Bias Control 0 */ 47 0x0000, /* R7 */ 48 0x0001, /* R8 - Analogue DAC 0 */ 49 0x0000, /* R9 */ 50 0x0001, /* R10 - Analogue ADC 0 */ 51 0x0000, /* R11 */ 52 0x0000, /* R12 - Power Management 0 */ 53 0x0000, /* R13 - Power Management 1 */ 54 0x0000, /* R14 - Power Management 2 */ 55 0x0000, /* R15 - Power Management 3 */ 56 0x0000, /* R16 - Power Management 4 */ 57 0x0000, /* R17 - Power Management 5 */ 58 0x0000, /* R18 - Power Management 6 */ 59 0x0000, /* R19 */ 60 0x0400, /* R20 - Clock Rates 0 */ 61 0x0D07, /* R21 - Clock Rates 1 */ 62 0x0000, /* R22 - Clock Rates 2 */ 63 0x0000, /* R23 */ 64 0x0050, /* R24 - Audio Interface 0 */ 65 0x0242, /* R25 - Audio Interface 1 */ 66 0x0008, /* R26 - Audio Interface 2 */ 67 0x0022, /* R27 - Audio Interface 3 */ 68 0x0000, /* R28 */ 69 0x0000, /* R29 */ 70 0x00C0, /* R30 - DAC Digital Volume Left */ 71 0x00C0, /* R31 - DAC Digital Volume Right */ 72 0x0000, /* R32 - DAC Digital 0 */ 73 0x0000, /* R33 - DAC Digital 1 */ 74 0x0000, /* R34 */ 75 0x0000, /* R35 */ 76 0x00C0, /* R36 - ADC Digital Volume Left */ 77 0x00C0, /* R37 - ADC Digital Volume Right */ 78 0x0000, /* R38 - ADC Digital 0 */ 79 0x0073, /* R39 - Digital Microphone 0 */ 80 0x09BF, /* R40 - DRC 0 */ 81 0x3241, /* R41 - DRC 1 */ 82 0x0020, /* R42 - DRC 2 */ 83 0x0000, /* R43 - DRC 3 */ 84 0x0085, /* R44 - Analogue Left Input 0 */ 85 0x0085, /* R45 - Analogue Right Input 0 */ 86 0x0044, /* R46 - Analogue Left Input 1 */ 87 0x0044, /* R47 - Analogue Right Input 1 */ 88 0x0000, /* R48 */ 89 0x0000, /* R49 */ 90 0x0008, /* R50 - Analogue Left Mix 0 */ 91 0x0004, /* R51 - Analogue Right Mix 0 */ 92 0x0000, /* R52 - Analogue Spk Mix Left 0 */ 93 0x0000, /* R53 - Analogue Spk Mix Left 1 */ 94 0x0000, /* R54 - Analogue Spk Mix Right 0 */ 95 0x0000, /* R55 - Analogue Spk Mix Right 1 */ 96 0x0000, /* R56 */ 97 0x002D, /* R57 - Analogue OUT1 Left */ 98 0x002D, /* R58 - Analogue OUT1 Right */ 99 0x0039, /* R59 - Analogue OUT2 Left */ 100 0x0039, /* R60 - Analogue OUT2 Right */ 101 0x0100, /* R61 */ 102 0x0139, /* R62 - Analogue OUT3 Left */ 103 0x0139, /* R63 - Analogue OUT3 Right */ 104 0x0000, /* R64 */ 105 0x0000, /* R65 - Analogue SPK Output Control 0 */ 106 0x0000, /* R66 */ 107 0x0010, /* R67 - DC Servo 0 */ 108 0x0100, /* R68 */ 109 0x00A4, /* R69 - DC Servo 2 */ 110 0x0807, /* R70 */ 111 0x0000, /* R71 */ 112 0x0000, /* R72 */ 113 0x0000, /* R73 */ 114 0x0000, /* R74 */ 115 0x0000, /* R75 */ 116 0x0000, /* R76 */ 117 0x0000, /* R77 */ 118 0x0000, /* R78 */ 119 0x000E, /* R79 */ 120 0x0000, /* R80 */ 121 0x0000, /* R81 */ 122 0x0000, /* R82 */ 123 0x0000, /* R83 */ 124 0x0000, /* R84 */ 125 0x0000, /* R85 */ 126 0x0000, /* R86 */ 127 0x0006, /* R87 */ 128 0x0000, /* R88 */ 129 0x0000, /* R89 */ 130 0x0000, /* R90 - Analogue HP 0 */ 131 0x0060, /* R91 */ 132 0x0000, /* R92 */ 133 0x0000, /* R93 */ 134 0x0000, /* R94 - Analogue Lineout 0 */ 135 0x0060, /* R95 */ 136 0x0000, /* R96 */ 137 0x0000, /* R97 */ 138 0x0000, /* R98 - Charge Pump 0 */ 139 0x1F25, /* R99 */ 140 0x2B19, /* R100 */ 141 0x01C0, /* R101 */ 142 0x01EF, /* R102 */ 143 0x2B00, /* R103 */ 144 0x0000, /* R104 - Class W 0 */ 145 0x01C0, /* R105 */ 146 0x1C10, /* R106 */ 147 0x0000, /* R107 */ 148 0x0000, /* R108 - Write Sequencer 0 */ 149 0x0000, /* R109 - Write Sequencer 1 */ 150 0x0000, /* R110 - Write Sequencer 2 */ 151 0x0000, /* R111 - Write Sequencer 3 */ 152 0x0000, /* R112 - Write Sequencer 4 */ 153 0x0000, /* R113 */ 154 0x0000, /* R114 - Control Interface */ 155 0x0000, /* R115 */ 156 0x00A8, /* R116 - GPIO Control 1 */ 157 0x00A8, /* R117 - GPIO Control 2 */ 158 0x00A8, /* R118 - GPIO Control 3 */ 159 0x0220, /* R119 - GPIO Control 4 */ 160 0x01A0, /* R120 - GPIO Control 5 */ 161 0x0000, /* R121 - Interrupt Status 1 */ 162 0xFFFF, /* R122 - Interrupt Status 1 Mask */ 163 0x0000, /* R123 - Interrupt Polarity 1 */ 164 0x0000, /* R124 */ 165 0x0003, /* R125 */ 166 0x0000, /* R126 - Interrupt Control */ 167 0x0000, /* R127 */ 168 0x0005, /* R128 */ 169 0x0000, /* R129 - Control Interface Test 1 */ 170 0x0000, /* R130 */ 171 0x0000, /* R131 */ 172 0x0000, /* R132 */ 173 0x0000, /* R133 */ 174 0x0000, /* R134 */ 175 0x03FF, /* R135 */ 176 0x0007, /* R136 */ 177 0x0040, /* R137 */ 178 0x0000, /* R138 */ 179 0x0000, /* R139 */ 180 0x0000, /* R140 */ 181 0x0000, /* R141 */ 182 0x0000, /* R142 */ 183 0x0000, /* R143 */ 184 0x0000, /* R144 */ 185 0x0000, /* R145 */ 186 0x0000, /* R146 */ 187 0x0000, /* R147 */ 188 0x4000, /* R148 */ 189 0x6810, /* R149 - Charge Pump Test 1 */ 190 0x0004, /* R150 */ 191 0x0000, /* R151 */ 192 0x0000, /* R152 */ 193 0x0000, /* R153 */ 194 0x0000, /* R154 */ 195 0x0000, /* R155 */ 196 0x0000, /* R156 */ 197 0x0000, /* R157 */ 198 0x0000, /* R158 */ 199 0x0000, /* R159 */ 200 0x0000, /* R160 */ 201 0x0000, /* R161 */ 202 0x0000, /* R162 */ 203 0x0000, /* R163 */ 204 0x0028, /* R164 - Clock Rate Test 4 */ 205 0x0004, /* R165 */ 206 0x0000, /* R166 */ 207 0x0060, /* R167 */ 208 0x0000, /* R168 */ 209 0x0000, /* R169 */ 210 0x0000, /* R170 */ 211 0x0000, /* R171 */ 212 0x0000, /* R172 - Analogue Output Bias 0 */ 213 }; 214 215 struct wm8903_priv { 216 struct snd_soc_codec codec; 217 u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)]; 218 219 int sysclk; 220 221 /* Reference counts */ 222 int class_w_users; 223 int playback_active; 224 int capture_active; 225 226 struct completion wseq; 227 228 struct snd_soc_jack *mic_jack; 229 int mic_det; 230 int mic_short; 231 int mic_last_report; 232 int mic_delay; 233 234 struct snd_pcm_substream *master_substream; 235 struct snd_pcm_substream *slave_substream; 236 }; 237 238 static int wm8903_volatile_register(unsigned int reg) 239 { 240 switch (reg) { 241 case WM8903_SW_RESET_AND_ID: 242 case WM8903_REVISION_NUMBER: 243 case WM8903_INTERRUPT_STATUS_1: 244 case WM8903_WRITE_SEQUENCER_4: 245 return 1; 246 247 default: 248 return 0; 249 } 250 } 251 252 static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start) 253 { 254 u16 reg[5]; 255 struct i2c_client *i2c = codec->control_data; 256 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 257 258 BUG_ON(start > 48); 259 260 /* Enable the sequencer if it's not already on */ 261 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0); 262 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 263 reg[0] | WM8903_WSEQ_ENA); 264 265 dev_dbg(&i2c->dev, "Starting sequence at %d\n", start); 266 267 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3, 268 start | WM8903_WSEQ_START); 269 270 /* Wait for it to complete. If we have the interrupt wired up then 271 * that will break us out of the poll early. 272 */ 273 do { 274 wait_for_completion_timeout(&wm8903->wseq, 275 msecs_to_jiffies(10)); 276 277 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4); 278 } while (reg[4] & WM8903_WSEQ_BUSY); 279 280 dev_dbg(&i2c->dev, "Sequence complete\n"); 281 282 /* Disable the sequencer again if we enabled it */ 283 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]); 284 285 return 0; 286 } 287 288 static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache) 289 { 290 int i; 291 292 /* There really ought to be something better we can do here :/ */ 293 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++) 294 cache[i] = codec->hw_read(codec, i); 295 } 296 297 static void wm8903_reset(struct snd_soc_codec *codec) 298 { 299 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0); 300 memcpy(codec->reg_cache, wm8903_reg_defaults, 301 sizeof(wm8903_reg_defaults)); 302 } 303 304 #define WM8903_OUTPUT_SHORT 0x8 305 #define WM8903_OUTPUT_OUT 0x4 306 #define WM8903_OUTPUT_INT 0x2 307 #define WM8903_OUTPUT_IN 0x1 308 309 static int wm8903_cp_event(struct snd_soc_dapm_widget *w, 310 struct snd_kcontrol *kcontrol, int event) 311 { 312 WARN_ON(event != SND_SOC_DAPM_POST_PMU); 313 mdelay(4); 314 315 return 0; 316 } 317 318 /* 319 * Event for headphone and line out amplifier power changes. Special 320 * power up/down sequences are required in order to maximise pop/click 321 * performance. 322 */ 323 static int wm8903_output_event(struct snd_soc_dapm_widget *w, 324 struct snd_kcontrol *kcontrol, int event) 325 { 326 struct snd_soc_codec *codec = w->codec; 327 u16 val; 328 u16 reg; 329 u16 dcs_reg; 330 u16 dcs_bit; 331 int shift; 332 333 switch (w->reg) { 334 case WM8903_POWER_MANAGEMENT_2: 335 reg = WM8903_ANALOGUE_HP_0; 336 dcs_bit = 0 + w->shift; 337 break; 338 case WM8903_POWER_MANAGEMENT_3: 339 reg = WM8903_ANALOGUE_LINEOUT_0; 340 dcs_bit = 2 + w->shift; 341 break; 342 default: 343 BUG(); 344 return -EINVAL; /* Spurious warning from some compilers */ 345 } 346 347 switch (w->shift) { 348 case 0: 349 shift = 0; 350 break; 351 case 1: 352 shift = 4; 353 break; 354 default: 355 BUG(); 356 return -EINVAL; /* Spurious warning from some compilers */ 357 } 358 359 if (event & SND_SOC_DAPM_PRE_PMU) { 360 val = snd_soc_read(codec, reg); 361 362 /* Short the output */ 363 val &= ~(WM8903_OUTPUT_SHORT << shift); 364 snd_soc_write(codec, reg, val); 365 } 366 367 if (event & SND_SOC_DAPM_POST_PMU) { 368 val = snd_soc_read(codec, reg); 369 370 val |= (WM8903_OUTPUT_IN << shift); 371 snd_soc_write(codec, reg, val); 372 373 val |= (WM8903_OUTPUT_INT << shift); 374 snd_soc_write(codec, reg, val); 375 376 /* Turn on the output ENA_OUTP */ 377 val |= (WM8903_OUTPUT_OUT << shift); 378 snd_soc_write(codec, reg, val); 379 380 /* Enable the DC servo */ 381 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0); 382 dcs_reg |= dcs_bit; 383 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg); 384 385 /* Remove the short */ 386 val |= (WM8903_OUTPUT_SHORT << shift); 387 snd_soc_write(codec, reg, val); 388 } 389 390 if (event & SND_SOC_DAPM_PRE_PMD) { 391 val = snd_soc_read(codec, reg); 392 393 /* Short the output */ 394 val &= ~(WM8903_OUTPUT_SHORT << shift); 395 snd_soc_write(codec, reg, val); 396 397 /* Disable the DC servo */ 398 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0); 399 dcs_reg &= ~dcs_bit; 400 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg); 401 402 /* Then disable the intermediate and output stages */ 403 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT | 404 WM8903_OUTPUT_IN) << shift); 405 snd_soc_write(codec, reg, val); 406 } 407 408 return 0; 409 } 410 411 /* 412 * When used with DAC outputs only the WM8903 charge pump supports 413 * operation in class W mode, providing very low power consumption 414 * when used with digital sources. Enable and disable this mode 415 * automatically depending on the mixer configuration. 416 * 417 * All the relevant controls are simple switches. 418 */ 419 static int wm8903_class_w_put(struct snd_kcontrol *kcontrol, 420 struct snd_ctl_elem_value *ucontrol) 421 { 422 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); 423 struct snd_soc_codec *codec = widget->codec; 424 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 425 struct i2c_client *i2c = codec->control_data; 426 u16 reg; 427 int ret; 428 429 reg = snd_soc_read(codec, WM8903_CLASS_W_0); 430 431 /* Turn it off if we're about to enable bypass */ 432 if (ucontrol->value.integer.value[0]) { 433 if (wm8903->class_w_users == 0) { 434 dev_dbg(&i2c->dev, "Disabling Class W\n"); 435 snd_soc_write(codec, WM8903_CLASS_W_0, reg & 436 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V)); 437 } 438 wm8903->class_w_users++; 439 } 440 441 /* Implement the change */ 442 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 443 444 /* If we've just disabled the last bypass path turn Class W on */ 445 if (!ucontrol->value.integer.value[0]) { 446 if (wm8903->class_w_users == 1) { 447 dev_dbg(&i2c->dev, "Enabling Class W\n"); 448 snd_soc_write(codec, WM8903_CLASS_W_0, reg | 449 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); 450 } 451 wm8903->class_w_users--; 452 } 453 454 dev_dbg(&i2c->dev, "Bypass use count now %d\n", 455 wm8903->class_w_users); 456 457 return ret; 458 } 459 460 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \ 461 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 462 .info = snd_soc_info_volsw, \ 463 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \ 464 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 465 466 467 /* ALSA can only do steps of .01dB */ 468 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 469 470 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0); 471 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); 472 473 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0); 474 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0); 475 static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0); 476 static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0); 477 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0); 478 479 static const char *drc_slope_text[] = { 480 "1", "1/2", "1/4", "1/8", "1/16", "0" 481 }; 482 483 static const struct soc_enum drc_slope_r0 = 484 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text); 485 486 static const struct soc_enum drc_slope_r1 = 487 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text); 488 489 static const char *drc_attack_text[] = { 490 "instantaneous", 491 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms", 492 "46.4ms", "92.8ms", "185.6ms" 493 }; 494 495 static const struct soc_enum drc_attack = 496 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text); 497 498 static const char *drc_decay_text[] = { 499 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s", 500 "23.87s", "47.56s" 501 }; 502 503 static const struct soc_enum drc_decay = 504 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text); 505 506 static const char *drc_ff_delay_text[] = { 507 "5 samples", "9 samples" 508 }; 509 510 static const struct soc_enum drc_ff_delay = 511 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text); 512 513 static const char *drc_qr_decay_text[] = { 514 "0.725ms", "1.45ms", "5.8ms" 515 }; 516 517 static const struct soc_enum drc_qr_decay = 518 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text); 519 520 static const char *drc_smoothing_text[] = { 521 "Low", "Medium", "High" 522 }; 523 524 static const struct soc_enum drc_smoothing = 525 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text); 526 527 static const char *soft_mute_text[] = { 528 "Fast (fs/2)", "Slow (fs/32)" 529 }; 530 531 static const struct soc_enum soft_mute = 532 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text); 533 534 static const char *mute_mode_text[] = { 535 "Hard", "Soft" 536 }; 537 538 static const struct soc_enum mute_mode = 539 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text); 540 541 static const char *dac_deemphasis_text[] = { 542 "Disabled", "32kHz", "44.1kHz", "48kHz" 543 }; 544 545 static const struct soc_enum dac_deemphasis = 546 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text); 547 548 static const char *companding_text[] = { 549 "ulaw", "alaw" 550 }; 551 552 static const struct soc_enum dac_companding = 553 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text); 554 555 static const struct soc_enum adc_companding = 556 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text); 557 558 static const char *input_mode_text[] = { 559 "Single-Ended", "Differential Line", "Differential Mic" 560 }; 561 562 static const struct soc_enum linput_mode_enum = 563 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text); 564 565 static const struct soc_enum rinput_mode_enum = 566 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text); 567 568 static const char *linput_mux_text[] = { 569 "IN1L", "IN2L", "IN3L" 570 }; 571 572 static const struct soc_enum linput_enum = 573 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text); 574 575 static const struct soc_enum linput_inv_enum = 576 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text); 577 578 static const char *rinput_mux_text[] = { 579 "IN1R", "IN2R", "IN3R" 580 }; 581 582 static const struct soc_enum rinput_enum = 583 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text); 584 585 static const struct soc_enum rinput_inv_enum = 586 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text); 587 588 589 static const char *sidetone_text[] = { 590 "None", "Left", "Right" 591 }; 592 593 static const struct soc_enum lsidetone_enum = 594 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text); 595 596 static const struct soc_enum rsidetone_enum = 597 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text); 598 599 static const struct snd_kcontrol_new wm8903_snd_controls[] = { 600 601 /* Input PGAs - No TLV since the scale depends on PGA mode */ 602 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0, 603 7, 1, 1), 604 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0, 605 0, 31, 0), 606 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1, 607 6, 1, 0), 608 609 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0, 610 7, 1, 1), 611 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0, 612 0, 31, 0), 613 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1, 614 6, 1, 0), 615 616 /* ADCs */ 617 SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0), 618 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0), 619 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1), 620 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1, 621 drc_tlv_thresh), 622 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp), 623 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min), 624 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max), 625 SOC_ENUM("DRC Attack Rate", drc_attack), 626 SOC_ENUM("DRC Decay Rate", drc_decay), 627 SOC_ENUM("DRC FF Delay", drc_ff_delay), 628 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0), 629 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0), 630 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max), 631 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay), 632 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0), 633 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0), 634 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing), 635 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup), 636 637 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT, 638 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv), 639 SOC_ENUM("ADC Companding Mode", adc_companding), 640 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0), 641 642 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8, 643 12, 0, digital_sidetone_tlv), 644 645 /* DAC */ 646 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT, 647 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), 648 SOC_ENUM("DAC Soft Mute Rate", soft_mute), 649 SOC_ENUM("DAC Mute Mode", mute_mode), 650 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0), 651 SOC_ENUM("DAC De-emphasis", dac_deemphasis), 652 SOC_ENUM("DAC Companding Mode", dac_companding), 653 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0), 654 655 /* Headphones */ 656 SOC_DOUBLE_R("Headphone Switch", 657 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 658 8, 1, 1), 659 SOC_DOUBLE_R("Headphone ZC Switch", 660 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 661 6, 1, 0), 662 SOC_DOUBLE_R_TLV("Headphone Volume", 663 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 664 0, 63, 0, out_tlv), 665 666 /* Line out */ 667 SOC_DOUBLE_R("Line Out Switch", 668 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 669 8, 1, 1), 670 SOC_DOUBLE_R("Line Out ZC Switch", 671 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 672 6, 1, 0), 673 SOC_DOUBLE_R_TLV("Line Out Volume", 674 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 675 0, 63, 0, out_tlv), 676 677 /* Speaker */ 678 SOC_DOUBLE_R("Speaker Switch", 679 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1), 680 SOC_DOUBLE_R("Speaker ZC Switch", 681 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0), 682 SOC_DOUBLE_R_TLV("Speaker Volume", 683 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 684 0, 63, 0, out_tlv), 685 }; 686 687 static const struct snd_kcontrol_new linput_mode_mux = 688 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum); 689 690 static const struct snd_kcontrol_new rinput_mode_mux = 691 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum); 692 693 static const struct snd_kcontrol_new linput_mux = 694 SOC_DAPM_ENUM("Left Input Mux", linput_enum); 695 696 static const struct snd_kcontrol_new linput_inv_mux = 697 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum); 698 699 static const struct snd_kcontrol_new rinput_mux = 700 SOC_DAPM_ENUM("Right Input Mux", rinput_enum); 701 702 static const struct snd_kcontrol_new rinput_inv_mux = 703 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum); 704 705 static const struct snd_kcontrol_new lsidetone_mux = 706 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum); 707 708 static const struct snd_kcontrol_new rsidetone_mux = 709 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum); 710 711 static const struct snd_kcontrol_new left_output_mixer[] = { 712 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0), 713 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0), 714 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0), 715 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0), 716 }; 717 718 static const struct snd_kcontrol_new right_output_mixer[] = { 719 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0), 720 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0), 721 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0), 722 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0), 723 }; 724 725 static const struct snd_kcontrol_new left_speaker_mixer[] = { 726 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0), 727 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0), 728 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0), 729 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 730 0, 1, 0), 731 }; 732 733 static const struct snd_kcontrol_new right_speaker_mixer[] = { 734 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0), 735 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0), 736 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 737 1, 1, 0), 738 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 739 0, 1, 0), 740 }; 741 742 static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = { 743 SND_SOC_DAPM_INPUT("IN1L"), 744 SND_SOC_DAPM_INPUT("IN1R"), 745 SND_SOC_DAPM_INPUT("IN2L"), 746 SND_SOC_DAPM_INPUT("IN2R"), 747 SND_SOC_DAPM_INPUT("IN3L"), 748 SND_SOC_DAPM_INPUT("IN3R"), 749 750 SND_SOC_DAPM_OUTPUT("HPOUTL"), 751 SND_SOC_DAPM_OUTPUT("HPOUTR"), 752 SND_SOC_DAPM_OUTPUT("LINEOUTL"), 753 SND_SOC_DAPM_OUTPUT("LINEOUTR"), 754 SND_SOC_DAPM_OUTPUT("LOP"), 755 SND_SOC_DAPM_OUTPUT("LON"), 756 SND_SOC_DAPM_OUTPUT("ROP"), 757 SND_SOC_DAPM_OUTPUT("RON"), 758 759 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0), 760 761 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux), 762 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0, 763 &linput_inv_mux), 764 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux), 765 766 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux), 767 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0, 768 &rinput_inv_mux), 769 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux), 770 771 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0), 772 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0), 773 774 SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0), 775 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0), 776 777 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux), 778 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux), 779 780 SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0), 781 SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0), 782 783 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0, 784 left_output_mixer, ARRAY_SIZE(left_output_mixer)), 785 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0, 786 right_output_mixer, ARRAY_SIZE(right_output_mixer)), 787 788 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0, 789 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 790 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0, 791 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 792 793 SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2, 794 1, 0, NULL, 0, wm8903_output_event, 795 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 796 SND_SOC_DAPM_PRE_PMD), 797 SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2, 798 0, 0, NULL, 0, wm8903_output_event, 799 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 800 SND_SOC_DAPM_PRE_PMD), 801 802 SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0, 803 NULL, 0, wm8903_output_event, 804 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 805 SND_SOC_DAPM_PRE_PMD), 806 SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0, 807 NULL, 0, wm8903_output_event, 808 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 809 SND_SOC_DAPM_PRE_PMD), 810 811 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0, 812 NULL, 0), 813 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0, 814 NULL, 0), 815 816 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0, 817 wm8903_cp_event, SND_SOC_DAPM_POST_PMU), 818 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0), 819 }; 820 821 static const struct snd_soc_dapm_route intercon[] = { 822 823 { "Left Input Mux", "IN1L", "IN1L" }, 824 { "Left Input Mux", "IN2L", "IN2L" }, 825 { "Left Input Mux", "IN3L", "IN3L" }, 826 827 { "Left Input Inverting Mux", "IN1L", "IN1L" }, 828 { "Left Input Inverting Mux", "IN2L", "IN2L" }, 829 { "Left Input Inverting Mux", "IN3L", "IN3L" }, 830 831 { "Right Input Mux", "IN1R", "IN1R" }, 832 { "Right Input Mux", "IN2R", "IN2R" }, 833 { "Right Input Mux", "IN3R", "IN3R" }, 834 835 { "Right Input Inverting Mux", "IN1R", "IN1R" }, 836 { "Right Input Inverting Mux", "IN2R", "IN2R" }, 837 { "Right Input Inverting Mux", "IN3R", "IN3R" }, 838 839 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" }, 840 { "Left Input Mode Mux", "Differential Line", 841 "Left Input Mux" }, 842 { "Left Input Mode Mux", "Differential Line", 843 "Left Input Inverting Mux" }, 844 { "Left Input Mode Mux", "Differential Mic", 845 "Left Input Mux" }, 846 { "Left Input Mode Mux", "Differential Mic", 847 "Left Input Inverting Mux" }, 848 849 { "Right Input Mode Mux", "Single-Ended", 850 "Right Input Inverting Mux" }, 851 { "Right Input Mode Mux", "Differential Line", 852 "Right Input Mux" }, 853 { "Right Input Mode Mux", "Differential Line", 854 "Right Input Inverting Mux" }, 855 { "Right Input Mode Mux", "Differential Mic", 856 "Right Input Mux" }, 857 { "Right Input Mode Mux", "Differential Mic", 858 "Right Input Inverting Mux" }, 859 860 { "Left Input PGA", NULL, "Left Input Mode Mux" }, 861 { "Right Input PGA", NULL, "Right Input Mode Mux" }, 862 863 { "ADCL", NULL, "Left Input PGA" }, 864 { "ADCL", NULL, "CLK_DSP" }, 865 { "ADCR", NULL, "Right Input PGA" }, 866 { "ADCR", NULL, "CLK_DSP" }, 867 868 { "DACL Sidetone", "Left", "ADCL" }, 869 { "DACL Sidetone", "Right", "ADCR" }, 870 { "DACR Sidetone", "Left", "ADCL" }, 871 { "DACR Sidetone", "Right", "ADCR" }, 872 873 { "DACL", NULL, "DACL Sidetone" }, 874 { "DACL", NULL, "CLK_DSP" }, 875 { "DACR", NULL, "DACR Sidetone" }, 876 { "DACR", NULL, "CLK_DSP" }, 877 878 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" }, 879 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" }, 880 { "Left Output Mixer", "DACL Switch", "DACL" }, 881 { "Left Output Mixer", "DACR Switch", "DACR" }, 882 883 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" }, 884 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" }, 885 { "Right Output Mixer", "DACL Switch", "DACL" }, 886 { "Right Output Mixer", "DACR Switch", "DACR" }, 887 888 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, 889 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, 890 { "Left Speaker Mixer", "DACL Switch", "DACL" }, 891 { "Left Speaker Mixer", "DACR Switch", "DACR" }, 892 893 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, 894 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, 895 { "Right Speaker Mixer", "DACL Switch", "DACL" }, 896 { "Right Speaker Mixer", "DACR Switch", "DACR" }, 897 898 { "Left Line Output PGA", NULL, "Left Output Mixer" }, 899 { "Right Line Output PGA", NULL, "Right Output Mixer" }, 900 901 { "Left Headphone Output PGA", NULL, "Left Output Mixer" }, 902 { "Right Headphone Output PGA", NULL, "Right Output Mixer" }, 903 904 { "Left Speaker PGA", NULL, "Left Speaker Mixer" }, 905 { "Right Speaker PGA", NULL, "Right Speaker Mixer" }, 906 907 { "HPOUTL", NULL, "Left Headphone Output PGA" }, 908 { "HPOUTR", NULL, "Right Headphone Output PGA" }, 909 910 { "LINEOUTL", NULL, "Left Line Output PGA" }, 911 { "LINEOUTR", NULL, "Right Line Output PGA" }, 912 913 { "LOP", NULL, "Left Speaker PGA" }, 914 { "LON", NULL, "Left Speaker PGA" }, 915 916 { "ROP", NULL, "Right Speaker PGA" }, 917 { "RON", NULL, "Right Speaker PGA" }, 918 919 { "Left Headphone Output PGA", NULL, "Charge Pump" }, 920 { "Right Headphone Output PGA", NULL, "Charge Pump" }, 921 { "Left Line Output PGA", NULL, "Charge Pump" }, 922 { "Right Line Output PGA", NULL, "Charge Pump" }, 923 }; 924 925 static int wm8903_add_widgets(struct snd_soc_codec *codec) 926 { 927 snd_soc_dapm_new_controls(codec, wm8903_dapm_widgets, 928 ARRAY_SIZE(wm8903_dapm_widgets)); 929 930 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 931 932 return 0; 933 } 934 935 static int wm8903_set_bias_level(struct snd_soc_codec *codec, 936 enum snd_soc_bias_level level) 937 { 938 struct i2c_client *i2c = codec->control_data; 939 u16 reg, reg2; 940 941 switch (level) { 942 case SND_SOC_BIAS_ON: 943 case SND_SOC_BIAS_PREPARE: 944 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0); 945 reg &= ~(WM8903_VMID_RES_MASK); 946 reg |= WM8903_VMID_RES_50K; 947 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg); 948 break; 949 950 case SND_SOC_BIAS_STANDBY: 951 if (codec->bias_level == SND_SOC_BIAS_OFF) { 952 snd_soc_write(codec, WM8903_CLOCK_RATES_2, 953 WM8903_CLK_SYS_ENA); 954 955 /* Change DC servo dither level in startup sequence */ 956 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11); 957 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257); 958 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2); 959 960 wm8903_run_sequence(codec, 0); 961 wm8903_sync_reg_cache(codec, codec->reg_cache); 962 963 /* Enable low impedence charge pump output */ 964 reg = snd_soc_read(codec, 965 WM8903_CONTROL_INTERFACE_TEST_1); 966 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1, 967 reg | WM8903_TEST_KEY); 968 reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1); 969 snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1, 970 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK); 971 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1, 972 reg); 973 974 /* By default no bypass paths are enabled so 975 * enable Class W support. 976 */ 977 dev_dbg(&i2c->dev, "Enabling Class W\n"); 978 snd_soc_write(codec, WM8903_CLASS_W_0, reg | 979 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); 980 } 981 982 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0); 983 reg &= ~(WM8903_VMID_RES_MASK); 984 reg |= WM8903_VMID_RES_250K; 985 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg); 986 break; 987 988 case SND_SOC_BIAS_OFF: 989 wm8903_run_sequence(codec, 32); 990 reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2); 991 reg &= ~WM8903_CLK_SYS_ENA; 992 snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg); 993 break; 994 } 995 996 codec->bias_level = level; 997 998 return 0; 999 } 1000 1001 static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1002 int clk_id, unsigned int freq, int dir) 1003 { 1004 struct snd_soc_codec *codec = codec_dai->codec; 1005 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1006 1007 wm8903->sysclk = freq; 1008 1009 return 0; 1010 } 1011 1012 static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai, 1013 unsigned int fmt) 1014 { 1015 struct snd_soc_codec *codec = codec_dai->codec; 1016 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1); 1017 1018 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK | 1019 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV); 1020 1021 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1022 case SND_SOC_DAIFMT_CBS_CFS: 1023 break; 1024 case SND_SOC_DAIFMT_CBS_CFM: 1025 aif1 |= WM8903_LRCLK_DIR; 1026 break; 1027 case SND_SOC_DAIFMT_CBM_CFM: 1028 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR; 1029 break; 1030 case SND_SOC_DAIFMT_CBM_CFS: 1031 aif1 |= WM8903_BCLK_DIR; 1032 break; 1033 default: 1034 return -EINVAL; 1035 } 1036 1037 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1038 case SND_SOC_DAIFMT_DSP_A: 1039 aif1 |= 0x3; 1040 break; 1041 case SND_SOC_DAIFMT_DSP_B: 1042 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV; 1043 break; 1044 case SND_SOC_DAIFMT_I2S: 1045 aif1 |= 0x2; 1046 break; 1047 case SND_SOC_DAIFMT_RIGHT_J: 1048 aif1 |= 0x1; 1049 break; 1050 case SND_SOC_DAIFMT_LEFT_J: 1051 break; 1052 default: 1053 return -EINVAL; 1054 } 1055 1056 /* Clock inversion */ 1057 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1058 case SND_SOC_DAIFMT_DSP_A: 1059 case SND_SOC_DAIFMT_DSP_B: 1060 /* frame inversion not valid for DSP modes */ 1061 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1062 case SND_SOC_DAIFMT_NB_NF: 1063 break; 1064 case SND_SOC_DAIFMT_IB_NF: 1065 aif1 |= WM8903_AIF_BCLK_INV; 1066 break; 1067 default: 1068 return -EINVAL; 1069 } 1070 break; 1071 case SND_SOC_DAIFMT_I2S: 1072 case SND_SOC_DAIFMT_RIGHT_J: 1073 case SND_SOC_DAIFMT_LEFT_J: 1074 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1075 case SND_SOC_DAIFMT_NB_NF: 1076 break; 1077 case SND_SOC_DAIFMT_IB_IF: 1078 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV; 1079 break; 1080 case SND_SOC_DAIFMT_IB_NF: 1081 aif1 |= WM8903_AIF_BCLK_INV; 1082 break; 1083 case SND_SOC_DAIFMT_NB_IF: 1084 aif1 |= WM8903_AIF_LRCLK_INV; 1085 break; 1086 default: 1087 return -EINVAL; 1088 } 1089 break; 1090 default: 1091 return -EINVAL; 1092 } 1093 1094 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); 1095 1096 return 0; 1097 } 1098 1099 static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1100 { 1101 struct snd_soc_codec *codec = codec_dai->codec; 1102 u16 reg; 1103 1104 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); 1105 1106 if (mute) 1107 reg |= WM8903_DAC_MUTE; 1108 else 1109 reg &= ~WM8903_DAC_MUTE; 1110 1111 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg); 1112 1113 return 0; 1114 } 1115 1116 /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended 1117 * for optimal performance so we list the lower rates first and match 1118 * on the last match we find. */ 1119 static struct { 1120 int div; 1121 int rate; 1122 int mode; 1123 int mclk_div; 1124 } clk_sys_ratios[] = { 1125 { 64, 0x0, 0x0, 1 }, 1126 { 68, 0x0, 0x1, 1 }, 1127 { 125, 0x0, 0x2, 1 }, 1128 { 128, 0x1, 0x0, 1 }, 1129 { 136, 0x1, 0x1, 1 }, 1130 { 192, 0x2, 0x0, 1 }, 1131 { 204, 0x2, 0x1, 1 }, 1132 1133 { 64, 0x0, 0x0, 2 }, 1134 { 68, 0x0, 0x1, 2 }, 1135 { 125, 0x0, 0x2, 2 }, 1136 { 128, 0x1, 0x0, 2 }, 1137 { 136, 0x1, 0x1, 2 }, 1138 { 192, 0x2, 0x0, 2 }, 1139 { 204, 0x2, 0x1, 2 }, 1140 1141 { 250, 0x2, 0x2, 1 }, 1142 { 256, 0x3, 0x0, 1 }, 1143 { 272, 0x3, 0x1, 1 }, 1144 { 384, 0x4, 0x0, 1 }, 1145 { 408, 0x4, 0x1, 1 }, 1146 { 375, 0x4, 0x2, 1 }, 1147 { 512, 0x5, 0x0, 1 }, 1148 { 544, 0x5, 0x1, 1 }, 1149 { 500, 0x5, 0x2, 1 }, 1150 { 768, 0x6, 0x0, 1 }, 1151 { 816, 0x6, 0x1, 1 }, 1152 { 750, 0x6, 0x2, 1 }, 1153 { 1024, 0x7, 0x0, 1 }, 1154 { 1088, 0x7, 0x1, 1 }, 1155 { 1000, 0x7, 0x2, 1 }, 1156 { 1408, 0x8, 0x0, 1 }, 1157 { 1496, 0x8, 0x1, 1 }, 1158 { 1536, 0x9, 0x0, 1 }, 1159 { 1632, 0x9, 0x1, 1 }, 1160 { 1500, 0x9, 0x2, 1 }, 1161 1162 { 250, 0x2, 0x2, 2 }, 1163 { 256, 0x3, 0x0, 2 }, 1164 { 272, 0x3, 0x1, 2 }, 1165 { 384, 0x4, 0x0, 2 }, 1166 { 408, 0x4, 0x1, 2 }, 1167 { 375, 0x4, 0x2, 2 }, 1168 { 512, 0x5, 0x0, 2 }, 1169 { 544, 0x5, 0x1, 2 }, 1170 { 500, 0x5, 0x2, 2 }, 1171 { 768, 0x6, 0x0, 2 }, 1172 { 816, 0x6, 0x1, 2 }, 1173 { 750, 0x6, 0x2, 2 }, 1174 { 1024, 0x7, 0x0, 2 }, 1175 { 1088, 0x7, 0x1, 2 }, 1176 { 1000, 0x7, 0x2, 2 }, 1177 { 1408, 0x8, 0x0, 2 }, 1178 { 1496, 0x8, 0x1, 2 }, 1179 { 1536, 0x9, 0x0, 2 }, 1180 { 1632, 0x9, 0x1, 2 }, 1181 { 1500, 0x9, 0x2, 2 }, 1182 }; 1183 1184 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */ 1185 static struct { 1186 int ratio; 1187 int div; 1188 } bclk_divs[] = { 1189 { 10, 0 }, 1190 { 20, 2 }, 1191 { 30, 3 }, 1192 { 40, 4 }, 1193 { 50, 5 }, 1194 { 60, 7 }, 1195 { 80, 8 }, 1196 { 100, 9 }, 1197 { 120, 11 }, 1198 { 160, 12 }, 1199 { 200, 13 }, 1200 { 220, 14 }, 1201 { 240, 15 }, 1202 { 300, 17 }, 1203 { 320, 18 }, 1204 { 440, 19 }, 1205 { 480, 20 }, 1206 }; 1207 1208 /* Sample rates for DSP */ 1209 static struct { 1210 int rate; 1211 int value; 1212 } sample_rates[] = { 1213 { 8000, 0 }, 1214 { 11025, 1 }, 1215 { 12000, 2 }, 1216 { 16000, 3 }, 1217 { 22050, 4 }, 1218 { 24000, 5 }, 1219 { 32000, 6 }, 1220 { 44100, 7 }, 1221 { 48000, 8 }, 1222 { 88200, 9 }, 1223 { 96000, 10 }, 1224 { 0, 0 }, 1225 }; 1226 1227 static int wm8903_startup(struct snd_pcm_substream *substream, 1228 struct snd_soc_dai *dai) 1229 { 1230 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1231 struct snd_soc_device *socdev = rtd->socdev; 1232 struct snd_soc_codec *codec = socdev->card->codec; 1233 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1234 struct i2c_client *i2c = codec->control_data; 1235 struct snd_pcm_runtime *master_runtime; 1236 1237 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1238 wm8903->playback_active++; 1239 else 1240 wm8903->capture_active++; 1241 1242 /* The DAI has shared clocks so if we already have a playback or 1243 * capture going then constrain this substream to match it. 1244 */ 1245 if (wm8903->master_substream) { 1246 master_runtime = wm8903->master_substream->runtime; 1247 1248 dev_dbg(&i2c->dev, "Constraining to %d bits\n", 1249 master_runtime->sample_bits); 1250 1251 snd_pcm_hw_constraint_minmax(substream->runtime, 1252 SNDRV_PCM_HW_PARAM_SAMPLE_BITS, 1253 master_runtime->sample_bits, 1254 master_runtime->sample_bits); 1255 1256 wm8903->slave_substream = substream; 1257 } else 1258 wm8903->master_substream = substream; 1259 1260 return 0; 1261 } 1262 1263 static void wm8903_shutdown(struct snd_pcm_substream *substream, 1264 struct snd_soc_dai *dai) 1265 { 1266 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1267 struct snd_soc_device *socdev = rtd->socdev; 1268 struct snd_soc_codec *codec = socdev->card->codec; 1269 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1270 1271 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1272 wm8903->playback_active--; 1273 else 1274 wm8903->capture_active--; 1275 1276 if (wm8903->master_substream == substream) 1277 wm8903->master_substream = wm8903->slave_substream; 1278 1279 wm8903->slave_substream = NULL; 1280 } 1281 1282 static int wm8903_hw_params(struct snd_pcm_substream *substream, 1283 struct snd_pcm_hw_params *params, 1284 struct snd_soc_dai *dai) 1285 { 1286 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1287 struct snd_soc_device *socdev = rtd->socdev; 1288 struct snd_soc_codec *codec = socdev->card->codec; 1289 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1290 struct i2c_client *i2c = codec->control_data; 1291 int fs = params_rate(params); 1292 int bclk; 1293 int bclk_div; 1294 int i; 1295 int dsp_config; 1296 int clk_config; 1297 int best_val; 1298 int cur_val; 1299 int clk_sys; 1300 1301 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1); 1302 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2); 1303 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3); 1304 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0); 1305 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1); 1306 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); 1307 1308 if (substream == wm8903->slave_substream) { 1309 dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n"); 1310 return 0; 1311 } 1312 1313 /* Enable sloping stopband filter for low sample rates */ 1314 if (fs <= 24000) 1315 dac_digital1 |= WM8903_DAC_SB_FILT; 1316 else 1317 dac_digital1 &= ~WM8903_DAC_SB_FILT; 1318 1319 /* Configure sample rate logic for DSP - choose nearest rate */ 1320 dsp_config = 0; 1321 best_val = abs(sample_rates[dsp_config].rate - fs); 1322 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1323 cur_val = abs(sample_rates[i].rate - fs); 1324 if (cur_val <= best_val) { 1325 dsp_config = i; 1326 best_val = cur_val; 1327 } 1328 } 1329 1330 /* Constraints should stop us hitting this but let's make sure */ 1331 if (wm8903->capture_active) 1332 switch (sample_rates[dsp_config].rate) { 1333 case 88200: 1334 case 96000: 1335 dev_err(&i2c->dev, "%dHz unsupported by ADC\n", 1336 fs); 1337 return -EINVAL; 1338 1339 default: 1340 break; 1341 } 1342 1343 dev_dbg(&i2c->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate); 1344 clock1 &= ~WM8903_SAMPLE_RATE_MASK; 1345 clock1 |= sample_rates[dsp_config].value; 1346 1347 aif1 &= ~WM8903_AIF_WL_MASK; 1348 bclk = 2 * fs; 1349 switch (params_format(params)) { 1350 case SNDRV_PCM_FORMAT_S16_LE: 1351 bclk *= 16; 1352 break; 1353 case SNDRV_PCM_FORMAT_S20_3LE: 1354 bclk *= 20; 1355 aif1 |= 0x4; 1356 break; 1357 case SNDRV_PCM_FORMAT_S24_LE: 1358 bclk *= 24; 1359 aif1 |= 0x8; 1360 break; 1361 case SNDRV_PCM_FORMAT_S32_LE: 1362 bclk *= 32; 1363 aif1 |= 0xc; 1364 break; 1365 default: 1366 return -EINVAL; 1367 } 1368 1369 dev_dbg(&i2c->dev, "MCLK = %dHz, target sample rate = %dHz\n", 1370 wm8903->sysclk, fs); 1371 1372 /* We may not have an MCLK which allows us to generate exactly 1373 * the clock we want, particularly with USB derived inputs, so 1374 * approximate. 1375 */ 1376 clk_config = 0; 1377 best_val = abs((wm8903->sysclk / 1378 (clk_sys_ratios[0].mclk_div * 1379 clk_sys_ratios[0].div)) - fs); 1380 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) { 1381 cur_val = abs((wm8903->sysclk / 1382 (clk_sys_ratios[i].mclk_div * 1383 clk_sys_ratios[i].div)) - fs); 1384 1385 if (cur_val <= best_val) { 1386 clk_config = i; 1387 best_val = cur_val; 1388 } 1389 } 1390 1391 if (clk_sys_ratios[clk_config].mclk_div == 2) { 1392 clock0 |= WM8903_MCLKDIV2; 1393 clk_sys = wm8903->sysclk / 2; 1394 } else { 1395 clock0 &= ~WM8903_MCLKDIV2; 1396 clk_sys = wm8903->sysclk; 1397 } 1398 1399 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK | 1400 WM8903_CLK_SYS_MODE_MASK); 1401 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT; 1402 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT; 1403 1404 dev_dbg(&i2c->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n", 1405 clk_sys_ratios[clk_config].rate, 1406 clk_sys_ratios[clk_config].mode, 1407 clk_sys_ratios[clk_config].div); 1408 1409 dev_dbg(&i2c->dev, "Actual CLK_SYS = %dHz\n", clk_sys); 1410 1411 /* We may not get quite the right frequency if using 1412 * approximate clocks so look for the closest match that is 1413 * higher than the target (we need to ensure that there enough 1414 * BCLKs to clock out the samples). 1415 */ 1416 bclk_div = 0; 1417 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk; 1418 i = 1; 1419 while (i < ARRAY_SIZE(bclk_divs)) { 1420 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk; 1421 if (cur_val < 0) /* BCLK table is sorted */ 1422 break; 1423 bclk_div = i; 1424 best_val = cur_val; 1425 i++; 1426 } 1427 1428 aif2 &= ~WM8903_BCLK_DIV_MASK; 1429 aif3 &= ~WM8903_LRCLK_RATE_MASK; 1430 1431 dev_dbg(&i2c->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n", 1432 bclk_divs[bclk_div].ratio / 10, bclk, 1433 (clk_sys * 10) / bclk_divs[bclk_div].ratio); 1434 1435 aif2 |= bclk_divs[bclk_div].div; 1436 aif3 |= bclk / fs; 1437 1438 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0); 1439 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1); 1440 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); 1441 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2); 1442 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3); 1443 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1); 1444 1445 return 0; 1446 } 1447 1448 /** 1449 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ 1450 * 1451 * @codec: WM8903 codec 1452 * @jack: jack to report detection events on 1453 * @det: value to report for presence detection 1454 * @shrt: value to report for short detection 1455 * 1456 * Enable microphone detection via IRQ on the WM8903. If GPIOs are 1457 * being used to bring out signals to the processor then only platform 1458 * data configuration is needed for WM8903 and processor GPIOs should 1459 * be configured using snd_soc_jack_add_gpios() instead. 1460 * 1461 * The current threasholds for detection should be configured using 1462 * micdet_cfg in the platform data. Using this function will force on 1463 * the microphone bias for the device. 1464 */ 1465 int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 1466 int det, int shrt) 1467 { 1468 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1469 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT; 1470 1471 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n", 1472 det, shrt); 1473 1474 /* Store the configuration */ 1475 wm8903->mic_jack = jack; 1476 wm8903->mic_det = det; 1477 wm8903->mic_short = shrt; 1478 1479 /* Enable interrupts we've got a report configured for */ 1480 if (det) 1481 irq_mask &= ~WM8903_MICDET_EINT; 1482 if (shrt) 1483 irq_mask &= ~WM8903_MICSHRT_EINT; 1484 1485 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK, 1486 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT, 1487 irq_mask); 1488 1489 if (det && shrt) { 1490 /* Enable mic detection, this may not have been set through 1491 * platform data (eg, if the defaults are OK). */ 1492 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0, 1493 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA); 1494 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0, 1495 WM8903_MICDET_ENA, WM8903_MICDET_ENA); 1496 } else { 1497 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0, 1498 WM8903_MICDET_ENA, 0); 1499 } 1500 1501 return 0; 1502 } 1503 EXPORT_SYMBOL_GPL(wm8903_mic_detect); 1504 1505 static irqreturn_t wm8903_irq(int irq, void *data) 1506 { 1507 struct wm8903_priv *wm8903 = data; 1508 struct snd_soc_codec *codec = &wm8903->codec; 1509 int mic_report; 1510 int int_pol; 1511 int int_val = 0; 1512 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK); 1513 1514 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask; 1515 1516 if (int_val & WM8903_WSEQ_BUSY_EINT) { 1517 dev_dbg(codec->dev, "Write sequencer done\n"); 1518 complete(&wm8903->wseq); 1519 } 1520 1521 /* 1522 * The rest is microphone jack detection. We need to manually 1523 * invert the polarity of the interrupt after each event - to 1524 * simplify the code keep track of the last state we reported 1525 * and just invert the relevant bits in both the report and 1526 * the polarity register. 1527 */ 1528 mic_report = wm8903->mic_last_report; 1529 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1); 1530 1531 if (int_val & WM8903_MICSHRT_EINT) { 1532 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol); 1533 1534 mic_report ^= wm8903->mic_short; 1535 int_pol ^= WM8903_MICSHRT_INV; 1536 } 1537 1538 if (int_val & WM8903_MICDET_EINT) { 1539 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol); 1540 1541 mic_report ^= wm8903->mic_det; 1542 int_pol ^= WM8903_MICDET_INV; 1543 1544 msleep(wm8903->mic_delay); 1545 } 1546 1547 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1, 1548 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol); 1549 1550 snd_soc_jack_report(wm8903->mic_jack, mic_report, 1551 wm8903->mic_short | wm8903->mic_det); 1552 1553 wm8903->mic_last_report = mic_report; 1554 1555 return IRQ_HANDLED; 1556 } 1557 1558 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\ 1559 SNDRV_PCM_RATE_11025 | \ 1560 SNDRV_PCM_RATE_16000 | \ 1561 SNDRV_PCM_RATE_22050 | \ 1562 SNDRV_PCM_RATE_32000 | \ 1563 SNDRV_PCM_RATE_44100 | \ 1564 SNDRV_PCM_RATE_48000 | \ 1565 SNDRV_PCM_RATE_88200 | \ 1566 SNDRV_PCM_RATE_96000) 1567 1568 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 1569 SNDRV_PCM_RATE_11025 | \ 1570 SNDRV_PCM_RATE_16000 | \ 1571 SNDRV_PCM_RATE_22050 | \ 1572 SNDRV_PCM_RATE_32000 | \ 1573 SNDRV_PCM_RATE_44100 | \ 1574 SNDRV_PCM_RATE_48000) 1575 1576 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1577 SNDRV_PCM_FMTBIT_S20_3LE |\ 1578 SNDRV_PCM_FMTBIT_S24_LE) 1579 1580 static struct snd_soc_dai_ops wm8903_dai_ops = { 1581 .startup = wm8903_startup, 1582 .shutdown = wm8903_shutdown, 1583 .hw_params = wm8903_hw_params, 1584 .digital_mute = wm8903_digital_mute, 1585 .set_fmt = wm8903_set_dai_fmt, 1586 .set_sysclk = wm8903_set_dai_sysclk, 1587 }; 1588 1589 struct snd_soc_dai wm8903_dai = { 1590 .name = "WM8903", 1591 .playback = { 1592 .stream_name = "Playback", 1593 .channels_min = 2, 1594 .channels_max = 2, 1595 .rates = WM8903_PLAYBACK_RATES, 1596 .formats = WM8903_FORMATS, 1597 }, 1598 .capture = { 1599 .stream_name = "Capture", 1600 .channels_min = 2, 1601 .channels_max = 2, 1602 .rates = WM8903_CAPTURE_RATES, 1603 .formats = WM8903_FORMATS, 1604 }, 1605 .ops = &wm8903_dai_ops, 1606 .symmetric_rates = 1, 1607 }; 1608 EXPORT_SYMBOL_GPL(wm8903_dai); 1609 1610 static int wm8903_suspend(struct platform_device *pdev, pm_message_t state) 1611 { 1612 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1613 struct snd_soc_codec *codec = socdev->card->codec; 1614 1615 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); 1616 1617 return 0; 1618 } 1619 1620 static int wm8903_resume(struct platform_device *pdev) 1621 { 1622 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1623 struct snd_soc_codec *codec = socdev->card->codec; 1624 struct i2c_client *i2c = codec->control_data; 1625 int i; 1626 u16 *reg_cache = codec->reg_cache; 1627 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults), 1628 GFP_KERNEL); 1629 1630 /* Bring the codec back up to standby first to minimise pop/clicks */ 1631 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1632 1633 /* Sync back everything else */ 1634 if (tmp_cache) { 1635 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++) 1636 if (tmp_cache[i] != reg_cache[i]) 1637 snd_soc_write(codec, i, tmp_cache[i]); 1638 kfree(tmp_cache); 1639 } else { 1640 dev_err(&i2c->dev, "Failed to allocate temporary cache\n"); 1641 } 1642 1643 return 0; 1644 } 1645 1646 static struct snd_soc_codec *wm8903_codec; 1647 1648 static __devinit int wm8903_i2c_probe(struct i2c_client *i2c, 1649 const struct i2c_device_id *id) 1650 { 1651 struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev); 1652 struct wm8903_priv *wm8903; 1653 struct snd_soc_codec *codec; 1654 int ret, i; 1655 int trigger, irq_pol; 1656 u16 val; 1657 1658 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL); 1659 if (wm8903 == NULL) 1660 return -ENOMEM; 1661 1662 codec = &wm8903->codec; 1663 1664 mutex_init(&codec->mutex); 1665 INIT_LIST_HEAD(&codec->dapm_widgets); 1666 INIT_LIST_HEAD(&codec->dapm_paths); 1667 1668 codec->dev = &i2c->dev; 1669 codec->name = "WM8903"; 1670 codec->owner = THIS_MODULE; 1671 codec->bias_level = SND_SOC_BIAS_OFF; 1672 codec->set_bias_level = wm8903_set_bias_level; 1673 codec->dai = &wm8903_dai; 1674 codec->num_dai = 1; 1675 codec->reg_cache_size = ARRAY_SIZE(wm8903->reg_cache); 1676 codec->reg_cache = &wm8903->reg_cache[0]; 1677 snd_soc_codec_set_drvdata(codec, wm8903); 1678 codec->volatile_register = wm8903_volatile_register; 1679 init_completion(&wm8903->wseq); 1680 1681 i2c_set_clientdata(i2c, codec); 1682 codec->control_data = i2c; 1683 1684 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C); 1685 if (ret != 0) { 1686 dev_err(&i2c->dev, "Failed to set cache I/O: %d\n", ret); 1687 goto err; 1688 } 1689 1690 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID); 1691 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) { 1692 dev_err(&i2c->dev, 1693 "Device with ID register %x is not a WM8903\n", val); 1694 return -ENODEV; 1695 } 1696 1697 val = snd_soc_read(codec, WM8903_REVISION_NUMBER); 1698 dev_info(&i2c->dev, "WM8903 revision %d\n", 1699 val & WM8903_CHIP_REV_MASK); 1700 1701 wm8903_reset(codec); 1702 1703 /* Set up GPIOs and microphone detection */ 1704 if (pdata) { 1705 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) { 1706 if (!pdata->gpio_cfg[i]) 1707 continue; 1708 1709 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i, 1710 pdata->gpio_cfg[i] & 0xffff); 1711 } 1712 1713 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0, 1714 pdata->micdet_cfg); 1715 1716 /* Microphone detection needs the WSEQ clock */ 1717 if (pdata->micdet_cfg) 1718 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0, 1719 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA); 1720 1721 wm8903->mic_delay = pdata->micdet_delay; 1722 } 1723 1724 if (i2c->irq) { 1725 if (pdata && pdata->irq_active_low) { 1726 trigger = IRQF_TRIGGER_LOW; 1727 irq_pol = WM8903_IRQ_POL; 1728 } else { 1729 trigger = IRQF_TRIGGER_HIGH; 1730 irq_pol = 0; 1731 } 1732 1733 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL, 1734 WM8903_IRQ_POL, irq_pol); 1735 1736 ret = request_threaded_irq(i2c->irq, NULL, wm8903_irq, 1737 trigger | IRQF_ONESHOT, 1738 "wm8903", wm8903); 1739 if (ret != 0) { 1740 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", 1741 ret); 1742 goto err; 1743 } 1744 1745 /* Enable write sequencer interrupts */ 1746 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK, 1747 WM8903_IM_WSEQ_BUSY_EINT, 0); 1748 } 1749 1750 /* power on device */ 1751 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1752 1753 /* Latch volume update bits */ 1754 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT); 1755 val |= WM8903_ADCVU; 1756 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val); 1757 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val); 1758 1759 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT); 1760 val |= WM8903_DACVU; 1761 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val); 1762 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val); 1763 1764 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT); 1765 val |= WM8903_HPOUTVU; 1766 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val); 1767 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val); 1768 1769 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT); 1770 val |= WM8903_LINEOUTVU; 1771 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val); 1772 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val); 1773 1774 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT); 1775 val |= WM8903_SPKVU; 1776 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val); 1777 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val); 1778 1779 /* Enable DAC soft mute by default */ 1780 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); 1781 val |= WM8903_DAC_MUTEMODE; 1782 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val); 1783 1784 wm8903_dai.dev = &i2c->dev; 1785 wm8903_codec = codec; 1786 1787 ret = snd_soc_register_codec(codec); 1788 if (ret != 0) { 1789 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret); 1790 goto err_irq; 1791 } 1792 1793 ret = snd_soc_register_dai(&wm8903_dai); 1794 if (ret != 0) { 1795 dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret); 1796 goto err_codec; 1797 } 1798 1799 return ret; 1800 1801 err_codec: 1802 snd_soc_unregister_codec(codec); 1803 err_irq: 1804 if (i2c->irq) 1805 free_irq(i2c->irq, wm8903); 1806 err: 1807 wm8903_codec = NULL; 1808 kfree(wm8903); 1809 return ret; 1810 } 1811 1812 static __devexit int wm8903_i2c_remove(struct i2c_client *client) 1813 { 1814 struct snd_soc_codec *codec = i2c_get_clientdata(client); 1815 struct wm8903_priv *priv = snd_soc_codec_get_drvdata(codec); 1816 1817 snd_soc_unregister_dai(&wm8903_dai); 1818 snd_soc_unregister_codec(codec); 1819 1820 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); 1821 1822 if (client->irq) 1823 free_irq(client->irq, priv); 1824 1825 kfree(priv); 1826 1827 wm8903_codec = NULL; 1828 wm8903_dai.dev = NULL; 1829 1830 return 0; 1831 } 1832 1833 /* i2c codec control layer */ 1834 static const struct i2c_device_id wm8903_i2c_id[] = { 1835 { "wm8903", 0 }, 1836 { } 1837 }; 1838 MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id); 1839 1840 static struct i2c_driver wm8903_i2c_driver = { 1841 .driver = { 1842 .name = "WM8903", 1843 .owner = THIS_MODULE, 1844 }, 1845 .probe = wm8903_i2c_probe, 1846 .remove = __devexit_p(wm8903_i2c_remove), 1847 .id_table = wm8903_i2c_id, 1848 }; 1849 1850 static int wm8903_probe(struct platform_device *pdev) 1851 { 1852 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1853 int ret = 0; 1854 1855 if (!wm8903_codec) { 1856 dev_err(&pdev->dev, "I2C device not yet probed\n"); 1857 goto err; 1858 } 1859 1860 socdev->card->codec = wm8903_codec; 1861 1862 /* register pcms */ 1863 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 1864 if (ret < 0) { 1865 dev_err(&pdev->dev, "failed to create pcms\n"); 1866 goto err; 1867 } 1868 1869 snd_soc_add_controls(socdev->card->codec, wm8903_snd_controls, 1870 ARRAY_SIZE(wm8903_snd_controls)); 1871 wm8903_add_widgets(socdev->card->codec); 1872 1873 return ret; 1874 1875 err: 1876 return ret; 1877 } 1878 1879 /* power down chip */ 1880 static int wm8903_remove(struct platform_device *pdev) 1881 { 1882 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1883 struct snd_soc_codec *codec = socdev->card->codec; 1884 1885 if (codec->control_data) 1886 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); 1887 1888 snd_soc_free_pcms(socdev); 1889 snd_soc_dapm_free(socdev); 1890 1891 return 0; 1892 } 1893 1894 struct snd_soc_codec_device soc_codec_dev_wm8903 = { 1895 .probe = wm8903_probe, 1896 .remove = wm8903_remove, 1897 .suspend = wm8903_suspend, 1898 .resume = wm8903_resume, 1899 }; 1900 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8903); 1901 1902 static int __init wm8903_modinit(void) 1903 { 1904 return i2c_add_driver(&wm8903_i2c_driver); 1905 } 1906 module_init(wm8903_modinit); 1907 1908 static void __exit wm8903_exit(void) 1909 { 1910 i2c_del_driver(&wm8903_i2c_driver); 1911 } 1912 module_exit(wm8903_exit); 1913 1914 MODULE_DESCRIPTION("ASoC WM8903 driver"); 1915 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>"); 1916 MODULE_LICENSE("GPL"); 1917