1 /* 2 * wm8903.c -- WM8903 ALSA SoC Audio driver 3 * 4 * Copyright 2008 Wolfson Microelectronics 5 * Copyright 2011 NVIDIA, Inc. 6 * 7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * TODO: 14 * - TDM mode configuration. 15 * - Digital microphone support. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/moduleparam.h> 20 #include <linux/init.h> 21 #include <linux/completion.h> 22 #include <linux/delay.h> 23 #include <linux/gpio.h> 24 #include <linux/pm.h> 25 #include <linux/i2c.h> 26 #include <linux/regmap.h> 27 #include <linux/slab.h> 28 #include <linux/irq.h> 29 #include <sound/core.h> 30 #include <sound/jack.h> 31 #include <sound/pcm.h> 32 #include <sound/pcm_params.h> 33 #include <sound/tlv.h> 34 #include <sound/soc.h> 35 #include <sound/initval.h> 36 #include <sound/wm8903.h> 37 #include <trace/events/asoc.h> 38 39 #include "wm8903.h" 40 41 /* Register defaults at reset */ 42 static const struct reg_default wm8903_reg_defaults[] = { 43 { 4, 0x0018 }, /* R4 - Bias Control 0 */ 44 { 5, 0x0000 }, /* R5 - VMID Control 0 */ 45 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */ 46 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */ 47 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */ 48 { 12, 0x0000 }, /* R12 - Power Management 0 */ 49 { 13, 0x0000 }, /* R13 - Power Management 1 */ 50 { 14, 0x0000 }, /* R14 - Power Management 2 */ 51 { 15, 0x0000 }, /* R15 - Power Management 3 */ 52 { 16, 0x0000 }, /* R16 - Power Management 4 */ 53 { 17, 0x0000 }, /* R17 - Power Management 5 */ 54 { 18, 0x0000 }, /* R18 - Power Management 6 */ 55 { 20, 0x0400 }, /* R20 - Clock Rates 0 */ 56 { 21, 0x0D07 }, /* R21 - Clock Rates 1 */ 57 { 22, 0x0000 }, /* R22 - Clock Rates 2 */ 58 { 24, 0x0050 }, /* R24 - Audio Interface 0 */ 59 { 25, 0x0242 }, /* R25 - Audio Interface 1 */ 60 { 26, 0x0008 }, /* R26 - Audio Interface 2 */ 61 { 27, 0x0022 }, /* R27 - Audio Interface 3 */ 62 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */ 63 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */ 64 { 32, 0x0000 }, /* R32 - DAC Digital 0 */ 65 { 33, 0x0000 }, /* R33 - DAC Digital 1 */ 66 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */ 67 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */ 68 { 38, 0x0000 }, /* R38 - ADC Digital 0 */ 69 { 39, 0x0073 }, /* R39 - Digital Microphone 0 */ 70 { 40, 0x09BF }, /* R40 - DRC 0 */ 71 { 41, 0x3241 }, /* R41 - DRC 1 */ 72 { 42, 0x0020 }, /* R42 - DRC 2 */ 73 { 43, 0x0000 }, /* R43 - DRC 3 */ 74 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */ 75 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */ 76 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */ 77 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */ 78 { 50, 0x0008 }, /* R50 - Analogue Left Mix 0 */ 79 { 51, 0x0004 }, /* R51 - Analogue Right Mix 0 */ 80 { 52, 0x0000 }, /* R52 - Analogue Spk Mix Left 0 */ 81 { 53, 0x0000 }, /* R53 - Analogue Spk Mix Left 1 */ 82 { 54, 0x0000 }, /* R54 - Analogue Spk Mix Right 0 */ 83 { 55, 0x0000 }, /* R55 - Analogue Spk Mix Right 1 */ 84 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */ 85 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */ 86 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */ 87 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */ 88 { 62, 0x0139 }, /* R62 - Analogue OUT3 Left */ 89 { 63, 0x0139 }, /* R63 - Analogue OUT3 Right */ 90 { 64, 0x0000 }, /* R65 - Analogue SPK Output Control 0 */ 91 { 67, 0x0010 }, /* R67 - DC Servo 0 */ 92 { 69, 0x00A4 }, /* R69 - DC Servo 2 */ 93 { 90, 0x0000 }, /* R90 - Analogue HP 0 */ 94 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */ 95 { 98, 0x0000 }, /* R98 - Charge Pump 0 */ 96 { 104, 0x0000 }, /* R104 - Class W 0 */ 97 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */ 98 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */ 99 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */ 100 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */ 101 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */ 102 { 114, 0x0000 }, /* R114 - Control Interface */ 103 { 116, 0x00A8 }, /* R116 - GPIO Control 1 */ 104 { 117, 0x00A8 }, /* R117 - GPIO Control 2 */ 105 { 118, 0x00A8 }, /* R118 - GPIO Control 3 */ 106 { 119, 0x0220 }, /* R119 - GPIO Control 4 */ 107 { 120, 0x01A0 }, /* R120 - GPIO Control 5 */ 108 { 122, 0xFFFF }, /* R122 - Interrupt Status 1 Mask */ 109 { 123, 0x0000 }, /* R123 - Interrupt Polarity 1 */ 110 { 126, 0x0000 }, /* R126 - Interrupt Control */ 111 { 129, 0x0000 }, /* R129 - Control Interface Test 1 */ 112 { 149, 0x6810 }, /* R149 - Charge Pump Test 1 */ 113 { 164, 0x0028 }, /* R164 - Clock Rate Test 4 */ 114 { 172, 0x0000 }, /* R172 - Analogue Output Bias 0 */ 115 }; 116 117 struct wm8903_priv { 118 struct wm8903_platform_data *pdata; 119 struct snd_soc_codec *codec; 120 struct regmap *regmap; 121 122 int sysclk; 123 int irq; 124 125 int fs; 126 int deemph; 127 128 int dcs_pending; 129 int dcs_cache[4]; 130 131 /* Reference count */ 132 int class_w_users; 133 134 struct snd_soc_jack *mic_jack; 135 int mic_det; 136 int mic_short; 137 int mic_last_report; 138 int mic_delay; 139 140 #ifdef CONFIG_GPIOLIB 141 struct gpio_chip gpio_chip; 142 #endif 143 }; 144 145 static bool wm8903_readable_register(struct device *dev, unsigned int reg) 146 { 147 switch (reg) { 148 case WM8903_SW_RESET_AND_ID: 149 case WM8903_REVISION_NUMBER: 150 case WM8903_BIAS_CONTROL_0: 151 case WM8903_VMID_CONTROL_0: 152 case WM8903_MIC_BIAS_CONTROL_0: 153 case WM8903_ANALOGUE_DAC_0: 154 case WM8903_ANALOGUE_ADC_0: 155 case WM8903_POWER_MANAGEMENT_0: 156 case WM8903_POWER_MANAGEMENT_1: 157 case WM8903_POWER_MANAGEMENT_2: 158 case WM8903_POWER_MANAGEMENT_3: 159 case WM8903_POWER_MANAGEMENT_4: 160 case WM8903_POWER_MANAGEMENT_5: 161 case WM8903_POWER_MANAGEMENT_6: 162 case WM8903_CLOCK_RATES_0: 163 case WM8903_CLOCK_RATES_1: 164 case WM8903_CLOCK_RATES_2: 165 case WM8903_AUDIO_INTERFACE_0: 166 case WM8903_AUDIO_INTERFACE_1: 167 case WM8903_AUDIO_INTERFACE_2: 168 case WM8903_AUDIO_INTERFACE_3: 169 case WM8903_DAC_DIGITAL_VOLUME_LEFT: 170 case WM8903_DAC_DIGITAL_VOLUME_RIGHT: 171 case WM8903_DAC_DIGITAL_0: 172 case WM8903_DAC_DIGITAL_1: 173 case WM8903_ADC_DIGITAL_VOLUME_LEFT: 174 case WM8903_ADC_DIGITAL_VOLUME_RIGHT: 175 case WM8903_ADC_DIGITAL_0: 176 case WM8903_DIGITAL_MICROPHONE_0: 177 case WM8903_DRC_0: 178 case WM8903_DRC_1: 179 case WM8903_DRC_2: 180 case WM8903_DRC_3: 181 case WM8903_ANALOGUE_LEFT_INPUT_0: 182 case WM8903_ANALOGUE_RIGHT_INPUT_0: 183 case WM8903_ANALOGUE_LEFT_INPUT_1: 184 case WM8903_ANALOGUE_RIGHT_INPUT_1: 185 case WM8903_ANALOGUE_LEFT_MIX_0: 186 case WM8903_ANALOGUE_RIGHT_MIX_0: 187 case WM8903_ANALOGUE_SPK_MIX_LEFT_0: 188 case WM8903_ANALOGUE_SPK_MIX_LEFT_1: 189 case WM8903_ANALOGUE_SPK_MIX_RIGHT_0: 190 case WM8903_ANALOGUE_SPK_MIX_RIGHT_1: 191 case WM8903_ANALOGUE_OUT1_LEFT: 192 case WM8903_ANALOGUE_OUT1_RIGHT: 193 case WM8903_ANALOGUE_OUT2_LEFT: 194 case WM8903_ANALOGUE_OUT2_RIGHT: 195 case WM8903_ANALOGUE_OUT3_LEFT: 196 case WM8903_ANALOGUE_OUT3_RIGHT: 197 case WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0: 198 case WM8903_DC_SERVO_0: 199 case WM8903_DC_SERVO_2: 200 case WM8903_DC_SERVO_READBACK_1: 201 case WM8903_DC_SERVO_READBACK_2: 202 case WM8903_DC_SERVO_READBACK_3: 203 case WM8903_DC_SERVO_READBACK_4: 204 case WM8903_ANALOGUE_HP_0: 205 case WM8903_ANALOGUE_LINEOUT_0: 206 case WM8903_CHARGE_PUMP_0: 207 case WM8903_CLASS_W_0: 208 case WM8903_WRITE_SEQUENCER_0: 209 case WM8903_WRITE_SEQUENCER_1: 210 case WM8903_WRITE_SEQUENCER_2: 211 case WM8903_WRITE_SEQUENCER_3: 212 case WM8903_WRITE_SEQUENCER_4: 213 case WM8903_CONTROL_INTERFACE: 214 case WM8903_GPIO_CONTROL_1: 215 case WM8903_GPIO_CONTROL_2: 216 case WM8903_GPIO_CONTROL_3: 217 case WM8903_GPIO_CONTROL_4: 218 case WM8903_GPIO_CONTROL_5: 219 case WM8903_INTERRUPT_STATUS_1: 220 case WM8903_INTERRUPT_STATUS_1_MASK: 221 case WM8903_INTERRUPT_POLARITY_1: 222 case WM8903_INTERRUPT_CONTROL: 223 case WM8903_CLOCK_RATE_TEST_4: 224 case WM8903_ANALOGUE_OUTPUT_BIAS_0: 225 return true; 226 default: 227 return false; 228 } 229 } 230 231 static bool wm8903_volatile_register(struct device *dev, unsigned int reg) 232 { 233 switch (reg) { 234 case WM8903_SW_RESET_AND_ID: 235 case WM8903_REVISION_NUMBER: 236 case WM8903_INTERRUPT_STATUS_1: 237 case WM8903_WRITE_SEQUENCER_4: 238 case WM8903_DC_SERVO_READBACK_1: 239 case WM8903_DC_SERVO_READBACK_2: 240 case WM8903_DC_SERVO_READBACK_3: 241 case WM8903_DC_SERVO_READBACK_4: 242 return 1; 243 244 default: 245 return 0; 246 } 247 } 248 249 static int wm8903_cp_event(struct snd_soc_dapm_widget *w, 250 struct snd_kcontrol *kcontrol, int event) 251 { 252 WARN_ON(event != SND_SOC_DAPM_POST_PMU); 253 mdelay(4); 254 255 return 0; 256 } 257 258 static int wm8903_dcs_event(struct snd_soc_dapm_widget *w, 259 struct snd_kcontrol *kcontrol, int event) 260 { 261 struct snd_soc_codec *codec = w->codec; 262 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 263 264 switch (event) { 265 case SND_SOC_DAPM_POST_PMU: 266 wm8903->dcs_pending |= 1 << w->shift; 267 break; 268 case SND_SOC_DAPM_PRE_PMD: 269 snd_soc_update_bits(codec, WM8903_DC_SERVO_0, 270 1 << w->shift, 0); 271 break; 272 } 273 274 return 0; 275 } 276 277 #define WM8903_DCS_MODE_WRITE_STOP 0 278 #define WM8903_DCS_MODE_START_STOP 2 279 280 static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm, 281 enum snd_soc_dapm_type event, int subseq) 282 { 283 struct snd_soc_codec *codec = container_of(dapm, 284 struct snd_soc_codec, dapm); 285 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 286 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP; 287 int i, val; 288 289 /* Complete any pending DC servo starts */ 290 if (wm8903->dcs_pending) { 291 dev_dbg(codec->dev, "Starting DC servo for %x\n", 292 wm8903->dcs_pending); 293 294 /* If we've no cached values then we need to do startup */ 295 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) { 296 if (!(wm8903->dcs_pending & (1 << i))) 297 continue; 298 299 if (wm8903->dcs_cache[i]) { 300 dev_dbg(codec->dev, 301 "Restore DC servo %d value %x\n", 302 3 - i, wm8903->dcs_cache[i]); 303 304 snd_soc_write(codec, WM8903_DC_SERVO_4 + i, 305 wm8903->dcs_cache[i] & 0xff); 306 } else { 307 dev_dbg(codec->dev, 308 "Calibrate DC servo %d\n", 3 - i); 309 dcs_mode = WM8903_DCS_MODE_START_STOP; 310 } 311 } 312 313 /* Don't trust the cache for analogue */ 314 if (wm8903->class_w_users) 315 dcs_mode = WM8903_DCS_MODE_START_STOP; 316 317 snd_soc_update_bits(codec, WM8903_DC_SERVO_2, 318 WM8903_DCS_MODE_MASK, dcs_mode); 319 320 snd_soc_update_bits(codec, WM8903_DC_SERVO_0, 321 WM8903_DCS_ENA_MASK, wm8903->dcs_pending); 322 323 switch (dcs_mode) { 324 case WM8903_DCS_MODE_WRITE_STOP: 325 break; 326 327 case WM8903_DCS_MODE_START_STOP: 328 msleep(270); 329 330 /* Cache the measured offsets for digital */ 331 if (wm8903->class_w_users) 332 break; 333 334 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) { 335 if (!(wm8903->dcs_pending & (1 << i))) 336 continue; 337 338 val = snd_soc_read(codec, 339 WM8903_DC_SERVO_READBACK_1 + i); 340 dev_dbg(codec->dev, "DC servo %d: %x\n", 341 3 - i, val); 342 wm8903->dcs_cache[i] = val; 343 } 344 break; 345 346 default: 347 pr_warn("DCS mode %d delay not set\n", dcs_mode); 348 break; 349 } 350 351 wm8903->dcs_pending = 0; 352 } 353 } 354 355 /* 356 * When used with DAC outputs only the WM8903 charge pump supports 357 * operation in class W mode, providing very low power consumption 358 * when used with digital sources. Enable and disable this mode 359 * automatically depending on the mixer configuration. 360 * 361 * All the relevant controls are simple switches. 362 */ 363 static int wm8903_class_w_put(struct snd_kcontrol *kcontrol, 364 struct snd_ctl_elem_value *ucontrol) 365 { 366 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); 367 struct snd_soc_dapm_widget *widget = wlist->widgets[0]; 368 struct snd_soc_codec *codec = widget->codec; 369 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 370 u16 reg; 371 int ret; 372 373 reg = snd_soc_read(codec, WM8903_CLASS_W_0); 374 375 /* Turn it off if we're about to enable bypass */ 376 if (ucontrol->value.integer.value[0]) { 377 if (wm8903->class_w_users == 0) { 378 dev_dbg(codec->dev, "Disabling Class W\n"); 379 snd_soc_write(codec, WM8903_CLASS_W_0, reg & 380 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V)); 381 } 382 wm8903->class_w_users++; 383 } 384 385 /* Implement the change */ 386 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 387 388 /* If we've just disabled the last bypass path turn Class W on */ 389 if (!ucontrol->value.integer.value[0]) { 390 if (wm8903->class_w_users == 1) { 391 dev_dbg(codec->dev, "Enabling Class W\n"); 392 snd_soc_write(codec, WM8903_CLASS_W_0, reg | 393 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); 394 } 395 wm8903->class_w_users--; 396 } 397 398 dev_dbg(codec->dev, "Bypass use count now %d\n", 399 wm8903->class_w_users); 400 401 return ret; 402 } 403 404 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \ 405 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 406 .info = snd_soc_info_volsw, \ 407 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \ 408 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 409 410 411 static int wm8903_deemph[] = { 0, 32000, 44100, 48000 }; 412 413 static int wm8903_set_deemph(struct snd_soc_codec *codec) 414 { 415 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 416 int val, i, best; 417 418 /* If we're using deemphasis select the nearest available sample 419 * rate. 420 */ 421 if (wm8903->deemph) { 422 best = 1; 423 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) { 424 if (abs(wm8903_deemph[i] - wm8903->fs) < 425 abs(wm8903_deemph[best] - wm8903->fs)) 426 best = i; 427 } 428 429 val = best << WM8903_DEEMPH_SHIFT; 430 } else { 431 best = 0; 432 val = 0; 433 } 434 435 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n", 436 best, wm8903_deemph[best]); 437 438 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1, 439 WM8903_DEEMPH_MASK, val); 440 } 441 442 static int wm8903_get_deemph(struct snd_kcontrol *kcontrol, 443 struct snd_ctl_elem_value *ucontrol) 444 { 445 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 446 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 447 448 ucontrol->value.enumerated.item[0] = wm8903->deemph; 449 450 return 0; 451 } 452 453 static int wm8903_put_deemph(struct snd_kcontrol *kcontrol, 454 struct snd_ctl_elem_value *ucontrol) 455 { 456 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 457 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 458 int deemph = ucontrol->value.enumerated.item[0]; 459 int ret = 0; 460 461 if (deemph > 1) 462 return -EINVAL; 463 464 mutex_lock(&codec->mutex); 465 if (wm8903->deemph != deemph) { 466 wm8903->deemph = deemph; 467 468 wm8903_set_deemph(codec); 469 470 ret = 1; 471 } 472 mutex_unlock(&codec->mutex); 473 474 return ret; 475 } 476 477 /* ALSA can only do steps of .01dB */ 478 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 479 480 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0); 481 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); 482 483 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0); 484 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0); 485 static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0); 486 static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0); 487 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0); 488 489 static const char *hpf_mode_text[] = { 490 "Hi-fi", "Voice 1", "Voice 2", "Voice 3" 491 }; 492 493 static const struct soc_enum hpf_mode = 494 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text); 495 496 static const char *osr_text[] = { 497 "Low power", "High performance" 498 }; 499 500 static const struct soc_enum adc_osr = 501 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text); 502 503 static const struct soc_enum dac_osr = 504 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text); 505 506 static const char *drc_slope_text[] = { 507 "1", "1/2", "1/4", "1/8", "1/16", "0" 508 }; 509 510 static const struct soc_enum drc_slope_r0 = 511 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text); 512 513 static const struct soc_enum drc_slope_r1 = 514 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text); 515 516 static const char *drc_attack_text[] = { 517 "instantaneous", 518 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms", 519 "46.4ms", "92.8ms", "185.6ms" 520 }; 521 522 static const struct soc_enum drc_attack = 523 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text); 524 525 static const char *drc_decay_text[] = { 526 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s", 527 "23.87s", "47.56s" 528 }; 529 530 static const struct soc_enum drc_decay = 531 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text); 532 533 static const char *drc_ff_delay_text[] = { 534 "5 samples", "9 samples" 535 }; 536 537 static const struct soc_enum drc_ff_delay = 538 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text); 539 540 static const char *drc_qr_decay_text[] = { 541 "0.725ms", "1.45ms", "5.8ms" 542 }; 543 544 static const struct soc_enum drc_qr_decay = 545 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text); 546 547 static const char *drc_smoothing_text[] = { 548 "Low", "Medium", "High" 549 }; 550 551 static const struct soc_enum drc_smoothing = 552 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text); 553 554 static const char *soft_mute_text[] = { 555 "Fast (fs/2)", "Slow (fs/32)" 556 }; 557 558 static const struct soc_enum soft_mute = 559 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text); 560 561 static const char *mute_mode_text[] = { 562 "Hard", "Soft" 563 }; 564 565 static const struct soc_enum mute_mode = 566 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text); 567 568 static const char *companding_text[] = { 569 "ulaw", "alaw" 570 }; 571 572 static const struct soc_enum dac_companding = 573 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text); 574 575 static const struct soc_enum adc_companding = 576 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text); 577 578 static const char *input_mode_text[] = { 579 "Single-Ended", "Differential Line", "Differential Mic" 580 }; 581 582 static const struct soc_enum linput_mode_enum = 583 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text); 584 585 static const struct soc_enum rinput_mode_enum = 586 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text); 587 588 static const char *linput_mux_text[] = { 589 "IN1L", "IN2L", "IN3L" 590 }; 591 592 static const struct soc_enum linput_enum = 593 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text); 594 595 static const struct soc_enum linput_inv_enum = 596 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text); 597 598 static const char *rinput_mux_text[] = { 599 "IN1R", "IN2R", "IN3R" 600 }; 601 602 static const struct soc_enum rinput_enum = 603 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text); 604 605 static const struct soc_enum rinput_inv_enum = 606 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text); 607 608 609 static const char *sidetone_text[] = { 610 "None", "Left", "Right" 611 }; 612 613 static const struct soc_enum lsidetone_enum = 614 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text); 615 616 static const struct soc_enum rsidetone_enum = 617 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text); 618 619 static const char *adcinput_text[] = { 620 "ADC", "DMIC" 621 }; 622 623 static const struct soc_enum adcinput_enum = 624 SOC_ENUM_SINGLE(WM8903_CLOCK_RATE_TEST_4, 9, 2, adcinput_text); 625 626 static const char *aif_text[] = { 627 "Left", "Right" 628 }; 629 630 static const struct soc_enum lcapture_enum = 631 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 7, 2, aif_text); 632 633 static const struct soc_enum rcapture_enum = 634 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 6, 2, aif_text); 635 636 static const struct soc_enum lplay_enum = 637 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 5, 2, aif_text); 638 639 static const struct soc_enum rplay_enum = 640 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 4, 2, aif_text); 641 642 static const struct snd_kcontrol_new wm8903_snd_controls[] = { 643 644 /* Input PGAs - No TLV since the scale depends on PGA mode */ 645 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0, 646 7, 1, 1), 647 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0, 648 0, 31, 0), 649 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1, 650 6, 1, 0), 651 652 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0, 653 7, 1, 1), 654 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0, 655 0, 31, 0), 656 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1, 657 6, 1, 0), 658 659 /* ADCs */ 660 SOC_ENUM("ADC OSR", adc_osr), 661 SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0), 662 SOC_ENUM("HPF Mode", hpf_mode), 663 SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0), 664 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0), 665 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1), 666 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1, 667 drc_tlv_thresh), 668 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp), 669 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min), 670 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max), 671 SOC_ENUM("DRC Attack Rate", drc_attack), 672 SOC_ENUM("DRC Decay Rate", drc_decay), 673 SOC_ENUM("DRC FF Delay", drc_ff_delay), 674 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0), 675 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0), 676 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max), 677 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay), 678 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0), 679 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0), 680 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing), 681 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup), 682 683 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT, 684 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), 685 SOC_ENUM("ADC Companding Mode", adc_companding), 686 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0), 687 688 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8, 689 12, 0, digital_sidetone_tlv), 690 691 /* DAC */ 692 SOC_ENUM("DAC OSR", dac_osr), 693 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT, 694 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), 695 SOC_ENUM("DAC Soft Mute Rate", soft_mute), 696 SOC_ENUM("DAC Mute Mode", mute_mode), 697 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0), 698 SOC_ENUM("DAC Companding Mode", dac_companding), 699 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0), 700 SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0, 701 wm8903_get_deemph, wm8903_put_deemph), 702 703 /* Headphones */ 704 SOC_DOUBLE_R("Headphone Switch", 705 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 706 8, 1, 1), 707 SOC_DOUBLE_R("Headphone ZC Switch", 708 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 709 6, 1, 0), 710 SOC_DOUBLE_R_TLV("Headphone Volume", 711 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 712 0, 63, 0, out_tlv), 713 714 /* Line out */ 715 SOC_DOUBLE_R("Line Out Switch", 716 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 717 8, 1, 1), 718 SOC_DOUBLE_R("Line Out ZC Switch", 719 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 720 6, 1, 0), 721 SOC_DOUBLE_R_TLV("Line Out Volume", 722 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 723 0, 63, 0, out_tlv), 724 725 /* Speaker */ 726 SOC_DOUBLE_R("Speaker Switch", 727 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1), 728 SOC_DOUBLE_R("Speaker ZC Switch", 729 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0), 730 SOC_DOUBLE_R_TLV("Speaker Volume", 731 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 732 0, 63, 0, out_tlv), 733 }; 734 735 static const struct snd_kcontrol_new linput_mode_mux = 736 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum); 737 738 static const struct snd_kcontrol_new rinput_mode_mux = 739 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum); 740 741 static const struct snd_kcontrol_new linput_mux = 742 SOC_DAPM_ENUM("Left Input Mux", linput_enum); 743 744 static const struct snd_kcontrol_new linput_inv_mux = 745 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum); 746 747 static const struct snd_kcontrol_new rinput_mux = 748 SOC_DAPM_ENUM("Right Input Mux", rinput_enum); 749 750 static const struct snd_kcontrol_new rinput_inv_mux = 751 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum); 752 753 static const struct snd_kcontrol_new lsidetone_mux = 754 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum); 755 756 static const struct snd_kcontrol_new rsidetone_mux = 757 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum); 758 759 static const struct snd_kcontrol_new adcinput_mux = 760 SOC_DAPM_ENUM("ADC Input", adcinput_enum); 761 762 static const struct snd_kcontrol_new lcapture_mux = 763 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum); 764 765 static const struct snd_kcontrol_new rcapture_mux = 766 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum); 767 768 static const struct snd_kcontrol_new lplay_mux = 769 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum); 770 771 static const struct snd_kcontrol_new rplay_mux = 772 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum); 773 774 static const struct snd_kcontrol_new left_output_mixer[] = { 775 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0), 776 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0), 777 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0), 778 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0), 779 }; 780 781 static const struct snd_kcontrol_new right_output_mixer[] = { 782 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0), 783 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0), 784 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0), 785 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0), 786 }; 787 788 static const struct snd_kcontrol_new left_speaker_mixer[] = { 789 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0), 790 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0), 791 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0), 792 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 793 0, 1, 0), 794 }; 795 796 static const struct snd_kcontrol_new right_speaker_mixer[] = { 797 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0), 798 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0), 799 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 800 1, 1, 0), 801 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 802 0, 1, 0), 803 }; 804 805 static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = { 806 SND_SOC_DAPM_INPUT("IN1L"), 807 SND_SOC_DAPM_INPUT("IN1R"), 808 SND_SOC_DAPM_INPUT("IN2L"), 809 SND_SOC_DAPM_INPUT("IN2R"), 810 SND_SOC_DAPM_INPUT("IN3L"), 811 SND_SOC_DAPM_INPUT("IN3R"), 812 SND_SOC_DAPM_INPUT("DMICDAT"), 813 814 SND_SOC_DAPM_OUTPUT("HPOUTL"), 815 SND_SOC_DAPM_OUTPUT("HPOUTR"), 816 SND_SOC_DAPM_OUTPUT("LINEOUTL"), 817 SND_SOC_DAPM_OUTPUT("LINEOUTR"), 818 SND_SOC_DAPM_OUTPUT("LOP"), 819 SND_SOC_DAPM_OUTPUT("LON"), 820 SND_SOC_DAPM_OUTPUT("ROP"), 821 SND_SOC_DAPM_OUTPUT("RON"), 822 823 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0), 824 825 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux), 826 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0, 827 &linput_inv_mux), 828 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux), 829 830 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux), 831 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0, 832 &rinput_inv_mux), 833 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux), 834 835 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0), 836 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0), 837 838 SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux), 839 SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux), 840 841 SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0), 842 SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0), 843 844 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux), 845 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux), 846 847 SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0), 848 SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0), 849 850 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux), 851 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux), 852 853 SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0), 854 SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0), 855 856 SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux), 857 SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux), 858 859 SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0), 860 SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0), 861 862 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0, 863 left_output_mixer, ARRAY_SIZE(left_output_mixer)), 864 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0, 865 right_output_mixer, ARRAY_SIZE(right_output_mixer)), 866 867 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0, 868 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 869 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0, 870 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 871 872 SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2, 873 1, 0, NULL, 0), 874 SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2, 875 0, 0, NULL, 0), 876 877 SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0, 878 NULL, 0), 879 SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0, 880 NULL, 0), 881 882 SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0), 883 SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0), 884 SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0), 885 SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0), 886 SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0), 887 SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0), 888 SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0), 889 SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0), 890 891 SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0, 892 NULL, 0), 893 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0, 894 NULL, 0), 895 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0, 896 NULL, 0), 897 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0, 898 NULL, 0), 899 SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0, 900 NULL, 0), 901 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0, 902 NULL, 0), 903 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0, 904 NULL, 0), 905 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0, 906 NULL, 0), 907 908 SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0), 909 SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event, 910 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 911 SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event, 912 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 913 SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event, 914 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 915 SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event, 916 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 917 918 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0, 919 NULL, 0), 920 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0, 921 NULL, 0), 922 923 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0, 924 wm8903_cp_event, SND_SOC_DAPM_POST_PMU), 925 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0), 926 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0), 927 }; 928 929 static const struct snd_soc_dapm_route wm8903_intercon[] = { 930 931 { "CLK_DSP", NULL, "CLK_SYS" }, 932 { "MICBIAS", NULL, "CLK_SYS" }, 933 { "HPL_DCS", NULL, "CLK_SYS" }, 934 { "HPR_DCS", NULL, "CLK_SYS" }, 935 { "LINEOUTL_DCS", NULL, "CLK_SYS" }, 936 { "LINEOUTR_DCS", NULL, "CLK_SYS" }, 937 938 { "Left Input Mux", "IN1L", "IN1L" }, 939 { "Left Input Mux", "IN2L", "IN2L" }, 940 { "Left Input Mux", "IN3L", "IN3L" }, 941 942 { "Left Input Inverting Mux", "IN1L", "IN1L" }, 943 { "Left Input Inverting Mux", "IN2L", "IN2L" }, 944 { "Left Input Inverting Mux", "IN3L", "IN3L" }, 945 946 { "Right Input Mux", "IN1R", "IN1R" }, 947 { "Right Input Mux", "IN2R", "IN2R" }, 948 { "Right Input Mux", "IN3R", "IN3R" }, 949 950 { "Right Input Inverting Mux", "IN1R", "IN1R" }, 951 { "Right Input Inverting Mux", "IN2R", "IN2R" }, 952 { "Right Input Inverting Mux", "IN3R", "IN3R" }, 953 954 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" }, 955 { "Left Input Mode Mux", "Differential Line", 956 "Left Input Mux" }, 957 { "Left Input Mode Mux", "Differential Line", 958 "Left Input Inverting Mux" }, 959 { "Left Input Mode Mux", "Differential Mic", 960 "Left Input Mux" }, 961 { "Left Input Mode Mux", "Differential Mic", 962 "Left Input Inverting Mux" }, 963 964 { "Right Input Mode Mux", "Single-Ended", 965 "Right Input Inverting Mux" }, 966 { "Right Input Mode Mux", "Differential Line", 967 "Right Input Mux" }, 968 { "Right Input Mode Mux", "Differential Line", 969 "Right Input Inverting Mux" }, 970 { "Right Input Mode Mux", "Differential Mic", 971 "Right Input Mux" }, 972 { "Right Input Mode Mux", "Differential Mic", 973 "Right Input Inverting Mux" }, 974 975 { "Left Input PGA", NULL, "Left Input Mode Mux" }, 976 { "Right Input PGA", NULL, "Right Input Mode Mux" }, 977 978 { "Left ADC Input", "ADC", "Left Input PGA" }, 979 { "Left ADC Input", "DMIC", "DMICDAT" }, 980 { "Right ADC Input", "ADC", "Right Input PGA" }, 981 { "Right ADC Input", "DMIC", "DMICDAT" }, 982 983 { "Left Capture Mux", "Left", "ADCL" }, 984 { "Left Capture Mux", "Right", "ADCR" }, 985 986 { "Right Capture Mux", "Left", "ADCL" }, 987 { "Right Capture Mux", "Right", "ADCR" }, 988 989 { "AIFTXL", NULL, "Left Capture Mux" }, 990 { "AIFTXR", NULL, "Right Capture Mux" }, 991 992 { "ADCL", NULL, "Left ADC Input" }, 993 { "ADCL", NULL, "CLK_DSP" }, 994 { "ADCR", NULL, "Right ADC Input" }, 995 { "ADCR", NULL, "CLK_DSP" }, 996 997 { "Left Playback Mux", "Left", "AIFRXL" }, 998 { "Left Playback Mux", "Right", "AIFRXR" }, 999 1000 { "Right Playback Mux", "Left", "AIFRXL" }, 1001 { "Right Playback Mux", "Right", "AIFRXR" }, 1002 1003 { "DACL Sidetone", "Left", "ADCL" }, 1004 { "DACL Sidetone", "Right", "ADCR" }, 1005 { "DACR Sidetone", "Left", "ADCL" }, 1006 { "DACR Sidetone", "Right", "ADCR" }, 1007 1008 { "DACL", NULL, "Left Playback Mux" }, 1009 { "DACL", NULL, "DACL Sidetone" }, 1010 { "DACL", NULL, "CLK_DSP" }, 1011 1012 { "DACR", NULL, "Right Playback Mux" }, 1013 { "DACR", NULL, "DACR Sidetone" }, 1014 { "DACR", NULL, "CLK_DSP" }, 1015 1016 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" }, 1017 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" }, 1018 { "Left Output Mixer", "DACL Switch", "DACL" }, 1019 { "Left Output Mixer", "DACR Switch", "DACR" }, 1020 1021 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" }, 1022 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" }, 1023 { "Right Output Mixer", "DACL Switch", "DACL" }, 1024 { "Right Output Mixer", "DACR Switch", "DACR" }, 1025 1026 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, 1027 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, 1028 { "Left Speaker Mixer", "DACL Switch", "DACL" }, 1029 { "Left Speaker Mixer", "DACR Switch", "DACR" }, 1030 1031 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, 1032 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, 1033 { "Right Speaker Mixer", "DACL Switch", "DACL" }, 1034 { "Right Speaker Mixer", "DACR Switch", "DACR" }, 1035 1036 { "Left Line Output PGA", NULL, "Left Output Mixer" }, 1037 { "Right Line Output PGA", NULL, "Right Output Mixer" }, 1038 1039 { "Left Headphone Output PGA", NULL, "Left Output Mixer" }, 1040 { "Right Headphone Output PGA", NULL, "Right Output Mixer" }, 1041 1042 { "Left Speaker PGA", NULL, "Left Speaker Mixer" }, 1043 { "Right Speaker PGA", NULL, "Right Speaker Mixer" }, 1044 1045 { "HPL_ENA", NULL, "Left Headphone Output PGA" }, 1046 { "HPR_ENA", NULL, "Right Headphone Output PGA" }, 1047 { "HPL_ENA_DLY", NULL, "HPL_ENA" }, 1048 { "HPR_ENA_DLY", NULL, "HPR_ENA" }, 1049 { "LINEOUTL_ENA", NULL, "Left Line Output PGA" }, 1050 { "LINEOUTR_ENA", NULL, "Right Line Output PGA" }, 1051 { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" }, 1052 { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" }, 1053 1054 { "HPL_DCS", NULL, "DCS Master" }, 1055 { "HPR_DCS", NULL, "DCS Master" }, 1056 { "LINEOUTL_DCS", NULL, "DCS Master" }, 1057 { "LINEOUTR_DCS", NULL, "DCS Master" }, 1058 1059 { "HPL_DCS", NULL, "HPL_ENA_DLY" }, 1060 { "HPR_DCS", NULL, "HPR_ENA_DLY" }, 1061 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" }, 1062 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" }, 1063 1064 { "HPL_ENA_OUTP", NULL, "HPL_DCS" }, 1065 { "HPR_ENA_OUTP", NULL, "HPR_DCS" }, 1066 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" }, 1067 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" }, 1068 1069 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" }, 1070 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" }, 1071 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" }, 1072 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" }, 1073 1074 { "HPOUTL", NULL, "HPL_RMV_SHORT" }, 1075 { "HPOUTR", NULL, "HPR_RMV_SHORT" }, 1076 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" }, 1077 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" }, 1078 1079 { "LOP", NULL, "Left Speaker PGA" }, 1080 { "LON", NULL, "Left Speaker PGA" }, 1081 1082 { "ROP", NULL, "Right Speaker PGA" }, 1083 { "RON", NULL, "Right Speaker PGA" }, 1084 1085 { "Left Headphone Output PGA", NULL, "Charge Pump" }, 1086 { "Right Headphone Output PGA", NULL, "Charge Pump" }, 1087 { "Left Line Output PGA", NULL, "Charge Pump" }, 1088 { "Right Line Output PGA", NULL, "Charge Pump" }, 1089 }; 1090 1091 static int wm8903_set_bias_level(struct snd_soc_codec *codec, 1092 enum snd_soc_bias_level level) 1093 { 1094 switch (level) { 1095 case SND_SOC_BIAS_ON: 1096 break; 1097 1098 case SND_SOC_BIAS_PREPARE: 1099 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1100 WM8903_VMID_RES_MASK, 1101 WM8903_VMID_RES_50K); 1102 break; 1103 1104 case SND_SOC_BIAS_STANDBY: 1105 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1106 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0, 1107 WM8903_POBCTRL | WM8903_ISEL_MASK | 1108 WM8903_STARTUP_BIAS_ENA | 1109 WM8903_BIAS_ENA, 1110 WM8903_POBCTRL | 1111 (2 << WM8903_ISEL_SHIFT) | 1112 WM8903_STARTUP_BIAS_ENA); 1113 1114 snd_soc_update_bits(codec, 1115 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0, 1116 WM8903_SPK_DISCHARGE, 1117 WM8903_SPK_DISCHARGE); 1118 1119 msleep(33); 1120 1121 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5, 1122 WM8903_SPKL_ENA | WM8903_SPKR_ENA, 1123 WM8903_SPKL_ENA | WM8903_SPKR_ENA); 1124 1125 snd_soc_update_bits(codec, 1126 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0, 1127 WM8903_SPK_DISCHARGE, 0); 1128 1129 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1130 WM8903_VMID_TIE_ENA | 1131 WM8903_BUFIO_ENA | 1132 WM8903_VMID_IO_ENA | 1133 WM8903_VMID_SOFT_MASK | 1134 WM8903_VMID_RES_MASK | 1135 WM8903_VMID_BUF_ENA, 1136 WM8903_VMID_TIE_ENA | 1137 WM8903_BUFIO_ENA | 1138 WM8903_VMID_IO_ENA | 1139 (2 << WM8903_VMID_SOFT_SHIFT) | 1140 WM8903_VMID_RES_250K | 1141 WM8903_VMID_BUF_ENA); 1142 1143 msleep(129); 1144 1145 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5, 1146 WM8903_SPKL_ENA | WM8903_SPKR_ENA, 1147 0); 1148 1149 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1150 WM8903_VMID_SOFT_MASK, 0); 1151 1152 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1153 WM8903_VMID_RES_MASK, 1154 WM8903_VMID_RES_50K); 1155 1156 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0, 1157 WM8903_BIAS_ENA | WM8903_POBCTRL, 1158 WM8903_BIAS_ENA); 1159 1160 /* By default no bypass paths are enabled so 1161 * enable Class W support. 1162 */ 1163 dev_dbg(codec->dev, "Enabling Class W\n"); 1164 snd_soc_update_bits(codec, WM8903_CLASS_W_0, 1165 WM8903_CP_DYN_FREQ | 1166 WM8903_CP_DYN_V, 1167 WM8903_CP_DYN_FREQ | 1168 WM8903_CP_DYN_V); 1169 } 1170 1171 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1172 WM8903_VMID_RES_MASK, 1173 WM8903_VMID_RES_250K); 1174 break; 1175 1176 case SND_SOC_BIAS_OFF: 1177 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0, 1178 WM8903_BIAS_ENA, 0); 1179 1180 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1181 WM8903_VMID_SOFT_MASK, 1182 2 << WM8903_VMID_SOFT_SHIFT); 1183 1184 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1185 WM8903_VMID_BUF_ENA, 0); 1186 1187 msleep(290); 1188 1189 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1190 WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA | 1191 WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK | 1192 WM8903_VMID_SOFT_MASK | 1193 WM8903_VMID_BUF_ENA, 0); 1194 1195 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0, 1196 WM8903_STARTUP_BIAS_ENA, 0); 1197 break; 1198 } 1199 1200 codec->dapm.bias_level = level; 1201 1202 return 0; 1203 } 1204 1205 static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1206 int clk_id, unsigned int freq, int dir) 1207 { 1208 struct snd_soc_codec *codec = codec_dai->codec; 1209 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1210 1211 wm8903->sysclk = freq; 1212 1213 return 0; 1214 } 1215 1216 static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai, 1217 unsigned int fmt) 1218 { 1219 struct snd_soc_codec *codec = codec_dai->codec; 1220 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1); 1221 1222 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK | 1223 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV); 1224 1225 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1226 case SND_SOC_DAIFMT_CBS_CFS: 1227 break; 1228 case SND_SOC_DAIFMT_CBS_CFM: 1229 aif1 |= WM8903_LRCLK_DIR; 1230 break; 1231 case SND_SOC_DAIFMT_CBM_CFM: 1232 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR; 1233 break; 1234 case SND_SOC_DAIFMT_CBM_CFS: 1235 aif1 |= WM8903_BCLK_DIR; 1236 break; 1237 default: 1238 return -EINVAL; 1239 } 1240 1241 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1242 case SND_SOC_DAIFMT_DSP_A: 1243 aif1 |= 0x3; 1244 break; 1245 case SND_SOC_DAIFMT_DSP_B: 1246 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV; 1247 break; 1248 case SND_SOC_DAIFMT_I2S: 1249 aif1 |= 0x2; 1250 break; 1251 case SND_SOC_DAIFMT_RIGHT_J: 1252 aif1 |= 0x1; 1253 break; 1254 case SND_SOC_DAIFMT_LEFT_J: 1255 break; 1256 default: 1257 return -EINVAL; 1258 } 1259 1260 /* Clock inversion */ 1261 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1262 case SND_SOC_DAIFMT_DSP_A: 1263 case SND_SOC_DAIFMT_DSP_B: 1264 /* frame inversion not valid for DSP modes */ 1265 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1266 case SND_SOC_DAIFMT_NB_NF: 1267 break; 1268 case SND_SOC_DAIFMT_IB_NF: 1269 aif1 |= WM8903_AIF_BCLK_INV; 1270 break; 1271 default: 1272 return -EINVAL; 1273 } 1274 break; 1275 case SND_SOC_DAIFMT_I2S: 1276 case SND_SOC_DAIFMT_RIGHT_J: 1277 case SND_SOC_DAIFMT_LEFT_J: 1278 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1279 case SND_SOC_DAIFMT_NB_NF: 1280 break; 1281 case SND_SOC_DAIFMT_IB_IF: 1282 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV; 1283 break; 1284 case SND_SOC_DAIFMT_IB_NF: 1285 aif1 |= WM8903_AIF_BCLK_INV; 1286 break; 1287 case SND_SOC_DAIFMT_NB_IF: 1288 aif1 |= WM8903_AIF_LRCLK_INV; 1289 break; 1290 default: 1291 return -EINVAL; 1292 } 1293 break; 1294 default: 1295 return -EINVAL; 1296 } 1297 1298 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); 1299 1300 return 0; 1301 } 1302 1303 static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1304 { 1305 struct snd_soc_codec *codec = codec_dai->codec; 1306 u16 reg; 1307 1308 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); 1309 1310 if (mute) 1311 reg |= WM8903_DAC_MUTE; 1312 else 1313 reg &= ~WM8903_DAC_MUTE; 1314 1315 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg); 1316 1317 return 0; 1318 } 1319 1320 /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended 1321 * for optimal performance so we list the lower rates first and match 1322 * on the last match we find. */ 1323 static struct { 1324 int div; 1325 int rate; 1326 int mode; 1327 int mclk_div; 1328 } clk_sys_ratios[] = { 1329 { 64, 0x0, 0x0, 1 }, 1330 { 68, 0x0, 0x1, 1 }, 1331 { 125, 0x0, 0x2, 1 }, 1332 { 128, 0x1, 0x0, 1 }, 1333 { 136, 0x1, 0x1, 1 }, 1334 { 192, 0x2, 0x0, 1 }, 1335 { 204, 0x2, 0x1, 1 }, 1336 1337 { 64, 0x0, 0x0, 2 }, 1338 { 68, 0x0, 0x1, 2 }, 1339 { 125, 0x0, 0x2, 2 }, 1340 { 128, 0x1, 0x0, 2 }, 1341 { 136, 0x1, 0x1, 2 }, 1342 { 192, 0x2, 0x0, 2 }, 1343 { 204, 0x2, 0x1, 2 }, 1344 1345 { 250, 0x2, 0x2, 1 }, 1346 { 256, 0x3, 0x0, 1 }, 1347 { 272, 0x3, 0x1, 1 }, 1348 { 384, 0x4, 0x0, 1 }, 1349 { 408, 0x4, 0x1, 1 }, 1350 { 375, 0x4, 0x2, 1 }, 1351 { 512, 0x5, 0x0, 1 }, 1352 { 544, 0x5, 0x1, 1 }, 1353 { 500, 0x5, 0x2, 1 }, 1354 { 768, 0x6, 0x0, 1 }, 1355 { 816, 0x6, 0x1, 1 }, 1356 { 750, 0x6, 0x2, 1 }, 1357 { 1024, 0x7, 0x0, 1 }, 1358 { 1088, 0x7, 0x1, 1 }, 1359 { 1000, 0x7, 0x2, 1 }, 1360 { 1408, 0x8, 0x0, 1 }, 1361 { 1496, 0x8, 0x1, 1 }, 1362 { 1536, 0x9, 0x0, 1 }, 1363 { 1632, 0x9, 0x1, 1 }, 1364 { 1500, 0x9, 0x2, 1 }, 1365 1366 { 250, 0x2, 0x2, 2 }, 1367 { 256, 0x3, 0x0, 2 }, 1368 { 272, 0x3, 0x1, 2 }, 1369 { 384, 0x4, 0x0, 2 }, 1370 { 408, 0x4, 0x1, 2 }, 1371 { 375, 0x4, 0x2, 2 }, 1372 { 512, 0x5, 0x0, 2 }, 1373 { 544, 0x5, 0x1, 2 }, 1374 { 500, 0x5, 0x2, 2 }, 1375 { 768, 0x6, 0x0, 2 }, 1376 { 816, 0x6, 0x1, 2 }, 1377 { 750, 0x6, 0x2, 2 }, 1378 { 1024, 0x7, 0x0, 2 }, 1379 { 1088, 0x7, 0x1, 2 }, 1380 { 1000, 0x7, 0x2, 2 }, 1381 { 1408, 0x8, 0x0, 2 }, 1382 { 1496, 0x8, 0x1, 2 }, 1383 { 1536, 0x9, 0x0, 2 }, 1384 { 1632, 0x9, 0x1, 2 }, 1385 { 1500, 0x9, 0x2, 2 }, 1386 }; 1387 1388 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */ 1389 static struct { 1390 int ratio; 1391 int div; 1392 } bclk_divs[] = { 1393 { 10, 0 }, 1394 { 20, 2 }, 1395 { 30, 3 }, 1396 { 40, 4 }, 1397 { 50, 5 }, 1398 { 60, 7 }, 1399 { 80, 8 }, 1400 { 100, 9 }, 1401 { 120, 11 }, 1402 { 160, 12 }, 1403 { 200, 13 }, 1404 { 220, 14 }, 1405 { 240, 15 }, 1406 { 300, 17 }, 1407 { 320, 18 }, 1408 { 440, 19 }, 1409 { 480, 20 }, 1410 }; 1411 1412 /* Sample rates for DSP */ 1413 static struct { 1414 int rate; 1415 int value; 1416 } sample_rates[] = { 1417 { 8000, 0 }, 1418 { 11025, 1 }, 1419 { 12000, 2 }, 1420 { 16000, 3 }, 1421 { 22050, 4 }, 1422 { 24000, 5 }, 1423 { 32000, 6 }, 1424 { 44100, 7 }, 1425 { 48000, 8 }, 1426 { 88200, 9 }, 1427 { 96000, 10 }, 1428 { 0, 0 }, 1429 }; 1430 1431 static int wm8903_hw_params(struct snd_pcm_substream *substream, 1432 struct snd_pcm_hw_params *params, 1433 struct snd_soc_dai *dai) 1434 { 1435 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1436 struct snd_soc_codec *codec =rtd->codec; 1437 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1438 int fs = params_rate(params); 1439 int bclk; 1440 int bclk_div; 1441 int i; 1442 int dsp_config; 1443 int clk_config; 1444 int best_val; 1445 int cur_val; 1446 int clk_sys; 1447 1448 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1); 1449 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2); 1450 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3); 1451 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0); 1452 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1); 1453 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); 1454 1455 /* Enable sloping stopband filter for low sample rates */ 1456 if (fs <= 24000) 1457 dac_digital1 |= WM8903_DAC_SB_FILT; 1458 else 1459 dac_digital1 &= ~WM8903_DAC_SB_FILT; 1460 1461 /* Configure sample rate logic for DSP - choose nearest rate */ 1462 dsp_config = 0; 1463 best_val = abs(sample_rates[dsp_config].rate - fs); 1464 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1465 cur_val = abs(sample_rates[i].rate - fs); 1466 if (cur_val <= best_val) { 1467 dsp_config = i; 1468 best_val = cur_val; 1469 } 1470 } 1471 1472 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate); 1473 clock1 &= ~WM8903_SAMPLE_RATE_MASK; 1474 clock1 |= sample_rates[dsp_config].value; 1475 1476 aif1 &= ~WM8903_AIF_WL_MASK; 1477 bclk = 2 * fs; 1478 switch (params_format(params)) { 1479 case SNDRV_PCM_FORMAT_S16_LE: 1480 bclk *= 16; 1481 break; 1482 case SNDRV_PCM_FORMAT_S20_3LE: 1483 bclk *= 20; 1484 aif1 |= 0x4; 1485 break; 1486 case SNDRV_PCM_FORMAT_S24_LE: 1487 bclk *= 24; 1488 aif1 |= 0x8; 1489 break; 1490 case SNDRV_PCM_FORMAT_S32_LE: 1491 bclk *= 32; 1492 aif1 |= 0xc; 1493 break; 1494 default: 1495 return -EINVAL; 1496 } 1497 1498 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n", 1499 wm8903->sysclk, fs); 1500 1501 /* We may not have an MCLK which allows us to generate exactly 1502 * the clock we want, particularly with USB derived inputs, so 1503 * approximate. 1504 */ 1505 clk_config = 0; 1506 best_val = abs((wm8903->sysclk / 1507 (clk_sys_ratios[0].mclk_div * 1508 clk_sys_ratios[0].div)) - fs); 1509 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) { 1510 cur_val = abs((wm8903->sysclk / 1511 (clk_sys_ratios[i].mclk_div * 1512 clk_sys_ratios[i].div)) - fs); 1513 1514 if (cur_val <= best_val) { 1515 clk_config = i; 1516 best_val = cur_val; 1517 } 1518 } 1519 1520 if (clk_sys_ratios[clk_config].mclk_div == 2) { 1521 clock0 |= WM8903_MCLKDIV2; 1522 clk_sys = wm8903->sysclk / 2; 1523 } else { 1524 clock0 &= ~WM8903_MCLKDIV2; 1525 clk_sys = wm8903->sysclk; 1526 } 1527 1528 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK | 1529 WM8903_CLK_SYS_MODE_MASK); 1530 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT; 1531 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT; 1532 1533 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n", 1534 clk_sys_ratios[clk_config].rate, 1535 clk_sys_ratios[clk_config].mode, 1536 clk_sys_ratios[clk_config].div); 1537 1538 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys); 1539 1540 /* We may not get quite the right frequency if using 1541 * approximate clocks so look for the closest match that is 1542 * higher than the target (we need to ensure that there enough 1543 * BCLKs to clock out the samples). 1544 */ 1545 bclk_div = 0; 1546 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk; 1547 i = 1; 1548 while (i < ARRAY_SIZE(bclk_divs)) { 1549 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk; 1550 if (cur_val < 0) /* BCLK table is sorted */ 1551 break; 1552 bclk_div = i; 1553 best_val = cur_val; 1554 i++; 1555 } 1556 1557 aif2 &= ~WM8903_BCLK_DIV_MASK; 1558 aif3 &= ~WM8903_LRCLK_RATE_MASK; 1559 1560 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n", 1561 bclk_divs[bclk_div].ratio / 10, bclk, 1562 (clk_sys * 10) / bclk_divs[bclk_div].ratio); 1563 1564 aif2 |= bclk_divs[bclk_div].div; 1565 aif3 |= bclk / fs; 1566 1567 wm8903->fs = params_rate(params); 1568 wm8903_set_deemph(codec); 1569 1570 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0); 1571 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1); 1572 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); 1573 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2); 1574 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3); 1575 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1); 1576 1577 return 0; 1578 } 1579 1580 /** 1581 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ 1582 * 1583 * @codec: WM8903 codec 1584 * @jack: jack to report detection events on 1585 * @det: value to report for presence detection 1586 * @shrt: value to report for short detection 1587 * 1588 * Enable microphone detection via IRQ on the WM8903. If GPIOs are 1589 * being used to bring out signals to the processor then only platform 1590 * data configuration is needed for WM8903 and processor GPIOs should 1591 * be configured using snd_soc_jack_add_gpios() instead. 1592 * 1593 * The current threasholds for detection should be configured using 1594 * micdet_cfg in the platform data. Using this function will force on 1595 * the microphone bias for the device. 1596 */ 1597 int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 1598 int det, int shrt) 1599 { 1600 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1601 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT; 1602 1603 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n", 1604 det, shrt); 1605 1606 /* Store the configuration */ 1607 wm8903->mic_jack = jack; 1608 wm8903->mic_det = det; 1609 wm8903->mic_short = shrt; 1610 1611 /* Enable interrupts we've got a report configured for */ 1612 if (det) 1613 irq_mask &= ~WM8903_MICDET_EINT; 1614 if (shrt) 1615 irq_mask &= ~WM8903_MICSHRT_EINT; 1616 1617 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK, 1618 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT, 1619 irq_mask); 1620 1621 if (det || shrt) { 1622 /* Enable mic detection, this may not have been set through 1623 * platform data (eg, if the defaults are OK). */ 1624 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0, 1625 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA); 1626 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0, 1627 WM8903_MICDET_ENA, WM8903_MICDET_ENA); 1628 } else { 1629 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0, 1630 WM8903_MICDET_ENA, 0); 1631 } 1632 1633 return 0; 1634 } 1635 EXPORT_SYMBOL_GPL(wm8903_mic_detect); 1636 1637 static irqreturn_t wm8903_irq(int irq, void *data) 1638 { 1639 struct snd_soc_codec *codec = data; 1640 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1641 int mic_report; 1642 int int_pol; 1643 int int_val = 0; 1644 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK); 1645 1646 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask; 1647 1648 if (int_val & WM8903_WSEQ_BUSY_EINT) { 1649 dev_warn(codec->dev, "Write sequencer done\n"); 1650 } 1651 1652 /* 1653 * The rest is microphone jack detection. We need to manually 1654 * invert the polarity of the interrupt after each event - to 1655 * simplify the code keep track of the last state we reported 1656 * and just invert the relevant bits in both the report and 1657 * the polarity register. 1658 */ 1659 mic_report = wm8903->mic_last_report; 1660 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1); 1661 1662 #ifndef CONFIG_SND_SOC_WM8903_MODULE 1663 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT)) 1664 trace_snd_soc_jack_irq(dev_name(codec->dev)); 1665 #endif 1666 1667 if (int_val & WM8903_MICSHRT_EINT) { 1668 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol); 1669 1670 mic_report ^= wm8903->mic_short; 1671 int_pol ^= WM8903_MICSHRT_INV; 1672 } 1673 1674 if (int_val & WM8903_MICDET_EINT) { 1675 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol); 1676 1677 mic_report ^= wm8903->mic_det; 1678 int_pol ^= WM8903_MICDET_INV; 1679 1680 msleep(wm8903->mic_delay); 1681 } 1682 1683 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1, 1684 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol); 1685 1686 snd_soc_jack_report(wm8903->mic_jack, mic_report, 1687 wm8903->mic_short | wm8903->mic_det); 1688 1689 wm8903->mic_last_report = mic_report; 1690 1691 return IRQ_HANDLED; 1692 } 1693 1694 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\ 1695 SNDRV_PCM_RATE_11025 | \ 1696 SNDRV_PCM_RATE_16000 | \ 1697 SNDRV_PCM_RATE_22050 | \ 1698 SNDRV_PCM_RATE_32000 | \ 1699 SNDRV_PCM_RATE_44100 | \ 1700 SNDRV_PCM_RATE_48000 | \ 1701 SNDRV_PCM_RATE_88200 | \ 1702 SNDRV_PCM_RATE_96000) 1703 1704 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 1705 SNDRV_PCM_RATE_11025 | \ 1706 SNDRV_PCM_RATE_16000 | \ 1707 SNDRV_PCM_RATE_22050 | \ 1708 SNDRV_PCM_RATE_32000 | \ 1709 SNDRV_PCM_RATE_44100 | \ 1710 SNDRV_PCM_RATE_48000) 1711 1712 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1713 SNDRV_PCM_FMTBIT_S20_3LE |\ 1714 SNDRV_PCM_FMTBIT_S24_LE) 1715 1716 static const struct snd_soc_dai_ops wm8903_dai_ops = { 1717 .hw_params = wm8903_hw_params, 1718 .digital_mute = wm8903_digital_mute, 1719 .set_fmt = wm8903_set_dai_fmt, 1720 .set_sysclk = wm8903_set_dai_sysclk, 1721 }; 1722 1723 static struct snd_soc_dai_driver wm8903_dai = { 1724 .name = "wm8903-hifi", 1725 .playback = { 1726 .stream_name = "Playback", 1727 .channels_min = 2, 1728 .channels_max = 2, 1729 .rates = WM8903_PLAYBACK_RATES, 1730 .formats = WM8903_FORMATS, 1731 }, 1732 .capture = { 1733 .stream_name = "Capture", 1734 .channels_min = 2, 1735 .channels_max = 2, 1736 .rates = WM8903_CAPTURE_RATES, 1737 .formats = WM8903_FORMATS, 1738 }, 1739 .ops = &wm8903_dai_ops, 1740 .symmetric_rates = 1, 1741 }; 1742 1743 static int wm8903_suspend(struct snd_soc_codec *codec) 1744 { 1745 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); 1746 1747 return 0; 1748 } 1749 1750 static int wm8903_resume(struct snd_soc_codec *codec) 1751 { 1752 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1753 1754 regcache_sync(wm8903->regmap); 1755 1756 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1757 1758 return 0; 1759 } 1760 1761 #ifdef CONFIG_GPIOLIB 1762 static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip) 1763 { 1764 return container_of(chip, struct wm8903_priv, gpio_chip); 1765 } 1766 1767 static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset) 1768 { 1769 if (offset >= WM8903_NUM_GPIO) 1770 return -EINVAL; 1771 1772 return 0; 1773 } 1774 1775 static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset) 1776 { 1777 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip); 1778 struct snd_soc_codec *codec = wm8903->codec; 1779 unsigned int mask, val; 1780 int ret; 1781 1782 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK; 1783 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) | 1784 WM8903_GP1_DIR; 1785 1786 ret = snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset, 1787 mask, val); 1788 if (ret < 0) 1789 return ret; 1790 1791 return 0; 1792 } 1793 1794 static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset) 1795 { 1796 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip); 1797 struct snd_soc_codec *codec = wm8903->codec; 1798 int reg; 1799 1800 reg = snd_soc_read(codec, WM8903_GPIO_CONTROL_1 + offset); 1801 1802 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT; 1803 } 1804 1805 static int wm8903_gpio_direction_out(struct gpio_chip *chip, 1806 unsigned offset, int value) 1807 { 1808 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip); 1809 struct snd_soc_codec *codec = wm8903->codec; 1810 unsigned int mask, val; 1811 int ret; 1812 1813 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK; 1814 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) | 1815 (value << WM8903_GP2_LVL_SHIFT); 1816 1817 ret = snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset, 1818 mask, val); 1819 if (ret < 0) 1820 return ret; 1821 1822 return 0; 1823 } 1824 1825 static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1826 { 1827 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip); 1828 struct snd_soc_codec *codec = wm8903->codec; 1829 1830 snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset, 1831 WM8903_GP1_LVL_MASK, 1832 !!value << WM8903_GP1_LVL_SHIFT); 1833 } 1834 1835 static struct gpio_chip wm8903_template_chip = { 1836 .label = "wm8903", 1837 .owner = THIS_MODULE, 1838 .request = wm8903_gpio_request, 1839 .direction_input = wm8903_gpio_direction_in, 1840 .get = wm8903_gpio_get, 1841 .direction_output = wm8903_gpio_direction_out, 1842 .set = wm8903_gpio_set, 1843 .can_sleep = 1, 1844 }; 1845 1846 static void wm8903_init_gpio(struct snd_soc_codec *codec) 1847 { 1848 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1849 struct wm8903_platform_data *pdata = wm8903->pdata; 1850 int ret; 1851 1852 wm8903->gpio_chip = wm8903_template_chip; 1853 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO; 1854 wm8903->gpio_chip.dev = codec->dev; 1855 1856 if (pdata->gpio_base) 1857 wm8903->gpio_chip.base = pdata->gpio_base; 1858 else 1859 wm8903->gpio_chip.base = -1; 1860 1861 ret = gpiochip_add(&wm8903->gpio_chip); 1862 if (ret != 0) 1863 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret); 1864 } 1865 1866 static void wm8903_free_gpio(struct snd_soc_codec *codec) 1867 { 1868 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1869 int ret; 1870 1871 ret = gpiochip_remove(&wm8903->gpio_chip); 1872 if (ret != 0) 1873 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret); 1874 } 1875 #else 1876 static void wm8903_init_gpio(struct snd_soc_codec *codec) 1877 { 1878 } 1879 1880 static void wm8903_free_gpio(struct snd_soc_codec *codec) 1881 { 1882 } 1883 #endif 1884 1885 static int wm8903_probe(struct snd_soc_codec *codec) 1886 { 1887 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1888 struct wm8903_platform_data *pdata = wm8903->pdata; 1889 int ret, i; 1890 int trigger, irq_pol; 1891 u16 val; 1892 bool mic_gpio = false; 1893 1894 wm8903->codec = codec; 1895 codec->control_data = wm8903->regmap; 1896 1897 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP); 1898 if (ret != 0) { 1899 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1900 return ret; 1901 } 1902 1903 /* Set up GPIOs, detect if any are MIC detect outputs */ 1904 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) { 1905 if ((!pdata->gpio_cfg[i]) || 1906 (pdata->gpio_cfg[i] > WM8903_GPIO_CONFIG_ZERO)) 1907 continue; 1908 1909 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i, 1910 pdata->gpio_cfg[i] & 0x7fff); 1911 1912 val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK) 1913 >> WM8903_GP1_FN_SHIFT; 1914 1915 switch (val) { 1916 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT: 1917 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT: 1918 mic_gpio = true; 1919 break; 1920 default: 1921 break; 1922 } 1923 } 1924 1925 /* Set up microphone detection */ 1926 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0, 1927 pdata->micdet_cfg); 1928 1929 /* Microphone detection needs the WSEQ clock */ 1930 if (pdata->micdet_cfg) 1931 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0, 1932 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA); 1933 1934 /* If microphone detection is enabled by pdata but 1935 * detected via IRQ then interrupts can be lost before 1936 * the machine driver has set up microphone detection 1937 * IRQs as the IRQs are clear on read. The detection 1938 * will be enabled when the machine driver configures. 1939 */ 1940 WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA)); 1941 1942 wm8903->mic_delay = pdata->micdet_delay; 1943 1944 if (wm8903->irq) { 1945 if (pdata->irq_active_low) { 1946 trigger = IRQF_TRIGGER_LOW; 1947 irq_pol = WM8903_IRQ_POL; 1948 } else { 1949 trigger = IRQF_TRIGGER_HIGH; 1950 irq_pol = 0; 1951 } 1952 1953 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL, 1954 WM8903_IRQ_POL, irq_pol); 1955 1956 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq, 1957 trigger | IRQF_ONESHOT, 1958 "wm8903", codec); 1959 if (ret != 0) { 1960 dev_err(codec->dev, "Failed to request IRQ: %d\n", 1961 ret); 1962 return ret; 1963 } 1964 1965 /* Enable write sequencer interrupts */ 1966 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK, 1967 WM8903_IM_WSEQ_BUSY_EINT, 0); 1968 } 1969 1970 /* power on device */ 1971 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1972 1973 /* Latch volume update bits */ 1974 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT); 1975 val |= WM8903_ADCVU; 1976 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val); 1977 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val); 1978 1979 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT); 1980 val |= WM8903_DACVU; 1981 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val); 1982 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val); 1983 1984 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT); 1985 val |= WM8903_HPOUTVU; 1986 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val); 1987 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val); 1988 1989 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT); 1990 val |= WM8903_LINEOUTVU; 1991 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val); 1992 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val); 1993 1994 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT); 1995 val |= WM8903_SPKVU; 1996 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val); 1997 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val); 1998 1999 /* Enable DAC soft mute by default */ 2000 snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1, 2001 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE, 2002 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE); 2003 2004 wm8903_init_gpio(codec); 2005 2006 return ret; 2007 } 2008 2009 /* power down chip */ 2010 static int wm8903_remove(struct snd_soc_codec *codec) 2011 { 2012 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 2013 2014 wm8903_free_gpio(codec); 2015 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); 2016 if (wm8903->irq) 2017 free_irq(wm8903->irq, codec); 2018 2019 return 0; 2020 } 2021 2022 static struct snd_soc_codec_driver soc_codec_dev_wm8903 = { 2023 .probe = wm8903_probe, 2024 .remove = wm8903_remove, 2025 .suspend = wm8903_suspend, 2026 .resume = wm8903_resume, 2027 .set_bias_level = wm8903_set_bias_level, 2028 .seq_notifier = wm8903_seq_notifier, 2029 .controls = wm8903_snd_controls, 2030 .num_controls = ARRAY_SIZE(wm8903_snd_controls), 2031 .dapm_widgets = wm8903_dapm_widgets, 2032 .num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets), 2033 .dapm_routes = wm8903_intercon, 2034 .num_dapm_routes = ARRAY_SIZE(wm8903_intercon), 2035 }; 2036 2037 static const struct regmap_config wm8903_regmap = { 2038 .reg_bits = 8, 2039 .val_bits = 16, 2040 2041 .max_register = WM8903_MAX_REGISTER, 2042 .volatile_reg = wm8903_volatile_register, 2043 .readable_reg = wm8903_readable_register, 2044 2045 .cache_type = REGCACHE_RBTREE, 2046 .reg_defaults = wm8903_reg_defaults, 2047 .num_reg_defaults = ARRAY_SIZE(wm8903_reg_defaults), 2048 }; 2049 2050 static int wm8903_set_pdata_irq_trigger(struct i2c_client *i2c, 2051 struct wm8903_platform_data *pdata) 2052 { 2053 struct irq_data *irq_data = irq_get_irq_data(i2c->irq); 2054 if (!irq_data) { 2055 dev_err(&i2c->dev, "Invalid IRQ: %d\n", 2056 i2c->irq); 2057 return -EINVAL; 2058 } 2059 2060 switch (irqd_get_trigger_type(irq_data)) { 2061 case IRQ_TYPE_NONE: 2062 default: 2063 /* 2064 * We assume the controller imposes no restrictions, 2065 * so we are able to select active-high 2066 */ 2067 /* Fall-through */ 2068 case IRQ_TYPE_LEVEL_HIGH: 2069 pdata->irq_active_low = false; 2070 break; 2071 case IRQ_TYPE_LEVEL_LOW: 2072 pdata->irq_active_low = true; 2073 break; 2074 } 2075 2076 return 0; 2077 } 2078 2079 static int wm8903_set_pdata_from_of(struct i2c_client *i2c, 2080 struct wm8903_platform_data *pdata) 2081 { 2082 const struct device_node *np = i2c->dev.of_node; 2083 u32 val32; 2084 int i; 2085 2086 if (of_property_read_u32(np, "micdet-cfg", &val32) >= 0) 2087 pdata->micdet_cfg = val32; 2088 2089 if (of_property_read_u32(np, "micdet-delay", &val32) >= 0) 2090 pdata->micdet_delay = val32; 2091 2092 if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_cfg, 2093 ARRAY_SIZE(pdata->gpio_cfg)) >= 0) { 2094 /* 2095 * In device tree: 0 means "write 0", 2096 * 0xffffffff means "don't touch". 2097 * 2098 * In platform data: 0 means "don't touch", 2099 * 0x8000 means "write 0". 2100 * 2101 * Note: WM8903_GPIO_CONFIG_ZERO == 0x8000. 2102 * 2103 * Convert from DT to pdata representation here, 2104 * so no other code needs to change. 2105 */ 2106 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) { 2107 if (pdata->gpio_cfg[i] == 0) { 2108 pdata->gpio_cfg[i] = WM8903_GPIO_CONFIG_ZERO; 2109 } else if (pdata->gpio_cfg[i] == 0xffffffff) { 2110 pdata->gpio_cfg[i] = 0; 2111 } else if (pdata->gpio_cfg[i] > 0x7fff) { 2112 dev_err(&i2c->dev, "Invalid gpio-cfg[%d] %x\n", 2113 i, pdata->gpio_cfg[i]); 2114 return -EINVAL; 2115 } 2116 } 2117 } 2118 2119 return 0; 2120 } 2121 2122 static __devinit int wm8903_i2c_probe(struct i2c_client *i2c, 2123 const struct i2c_device_id *id) 2124 { 2125 struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev); 2126 struct wm8903_priv *wm8903; 2127 unsigned int val; 2128 int ret; 2129 2130 wm8903 = devm_kzalloc(&i2c->dev, sizeof(struct wm8903_priv), 2131 GFP_KERNEL); 2132 if (wm8903 == NULL) 2133 return -ENOMEM; 2134 2135 wm8903->regmap = regmap_init_i2c(i2c, &wm8903_regmap); 2136 if (IS_ERR(wm8903->regmap)) { 2137 ret = PTR_ERR(wm8903->regmap); 2138 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 2139 ret); 2140 return ret; 2141 } 2142 2143 i2c_set_clientdata(i2c, wm8903); 2144 wm8903->irq = i2c->irq; 2145 2146 /* If no platform data was supplied, create storage for defaults */ 2147 if (pdata) { 2148 wm8903->pdata = pdata; 2149 } else { 2150 wm8903->pdata = devm_kzalloc(&i2c->dev, 2151 sizeof(struct wm8903_platform_data), 2152 GFP_KERNEL); 2153 if (wm8903->pdata == NULL) { 2154 dev_err(&i2c->dev, "Failed to allocate pdata\n"); 2155 return -ENOMEM; 2156 } 2157 2158 if (i2c->irq) { 2159 ret = wm8903_set_pdata_irq_trigger(i2c, wm8903->pdata); 2160 if (ret != 0) 2161 return ret; 2162 } 2163 2164 if (i2c->dev.of_node) { 2165 ret = wm8903_set_pdata_from_of(i2c, wm8903->pdata); 2166 if (ret != 0) 2167 return ret; 2168 } 2169 } 2170 2171 ret = regmap_read(wm8903->regmap, WM8903_SW_RESET_AND_ID, &val); 2172 if (ret != 0) { 2173 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret); 2174 goto err; 2175 } 2176 if (val != 0x8903) { 2177 dev_err(&i2c->dev, "Device with ID %x is not a WM8903\n", val); 2178 ret = -ENODEV; 2179 goto err; 2180 } 2181 2182 ret = regmap_read(wm8903->regmap, WM8903_REVISION_NUMBER, &val); 2183 if (ret != 0) { 2184 dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret); 2185 goto err; 2186 } 2187 dev_info(&i2c->dev, "WM8903 revision %c\n", 2188 (val & WM8903_CHIP_REV_MASK) + 'A'); 2189 2190 /* Reset the device */ 2191 regmap_write(wm8903->regmap, WM8903_SW_RESET_AND_ID, 0x8903); 2192 2193 ret = snd_soc_register_codec(&i2c->dev, 2194 &soc_codec_dev_wm8903, &wm8903_dai, 1); 2195 if (ret != 0) 2196 goto err; 2197 2198 return 0; 2199 err: 2200 regmap_exit(wm8903->regmap); 2201 return ret; 2202 } 2203 2204 static __devexit int wm8903_i2c_remove(struct i2c_client *client) 2205 { 2206 struct wm8903_priv *wm8903 = i2c_get_clientdata(client); 2207 2208 regmap_exit(wm8903->regmap); 2209 snd_soc_unregister_codec(&client->dev); 2210 2211 return 0; 2212 } 2213 2214 static const struct of_device_id wm8903_of_match[] = { 2215 { .compatible = "wlf,wm8903", }, 2216 {}, 2217 }; 2218 MODULE_DEVICE_TABLE(of, wm8903_of_match); 2219 2220 static const struct i2c_device_id wm8903_i2c_id[] = { 2221 { "wm8903", 0 }, 2222 { } 2223 }; 2224 MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id); 2225 2226 static struct i2c_driver wm8903_i2c_driver = { 2227 .driver = { 2228 .name = "wm8903", 2229 .owner = THIS_MODULE, 2230 .of_match_table = wm8903_of_match, 2231 }, 2232 .probe = wm8903_i2c_probe, 2233 .remove = __devexit_p(wm8903_i2c_remove), 2234 .id_table = wm8903_i2c_id, 2235 }; 2236 2237 static int __init wm8903_modinit(void) 2238 { 2239 int ret = 0; 2240 ret = i2c_add_driver(&wm8903_i2c_driver); 2241 if (ret != 0) { 2242 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n", 2243 ret); 2244 } 2245 return ret; 2246 } 2247 module_init(wm8903_modinit); 2248 2249 static void __exit wm8903_exit(void) 2250 { 2251 i2c_del_driver(&wm8903_i2c_driver); 2252 } 2253 module_exit(wm8903_exit); 2254 2255 MODULE_DESCRIPTION("ASoC WM8903 driver"); 2256 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>"); 2257 MODULE_LICENSE("GPL"); 2258