1 /* 2 * wm8903.c -- WM8903 ALSA SoC Audio driver 3 * 4 * Copyright 2008 Wolfson Microelectronics 5 * Copyright 2011 NVIDIA, Inc. 6 * 7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * TODO: 14 * - TDM mode configuration. 15 * - Digital microphone support. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/moduleparam.h> 20 #include <linux/init.h> 21 #include <linux/completion.h> 22 #include <linux/delay.h> 23 #include <linux/gpio.h> 24 #include <linux/pm.h> 25 #include <linux/i2c.h> 26 #include <linux/platform_device.h> 27 #include <linux/slab.h> 28 #include <sound/core.h> 29 #include <sound/jack.h> 30 #include <sound/pcm.h> 31 #include <sound/pcm_params.h> 32 #include <sound/tlv.h> 33 #include <sound/soc.h> 34 #include <sound/initval.h> 35 #include <sound/wm8903.h> 36 #include <trace/events/asoc.h> 37 38 #include "wm8903.h" 39 40 /* Register defaults at reset */ 41 static u16 wm8903_reg_defaults[] = { 42 0x8903, /* R0 - SW Reset and ID */ 43 0x0000, /* R1 - Revision Number */ 44 0x0000, /* R2 */ 45 0x0000, /* R3 */ 46 0x0018, /* R4 - Bias Control 0 */ 47 0x0000, /* R5 - VMID Control 0 */ 48 0x0000, /* R6 - Mic Bias Control 0 */ 49 0x0000, /* R7 */ 50 0x0001, /* R8 - Analogue DAC 0 */ 51 0x0000, /* R9 */ 52 0x0001, /* R10 - Analogue ADC 0 */ 53 0x0000, /* R11 */ 54 0x0000, /* R12 - Power Management 0 */ 55 0x0000, /* R13 - Power Management 1 */ 56 0x0000, /* R14 - Power Management 2 */ 57 0x0000, /* R15 - Power Management 3 */ 58 0x0000, /* R16 - Power Management 4 */ 59 0x0000, /* R17 - Power Management 5 */ 60 0x0000, /* R18 - Power Management 6 */ 61 0x0000, /* R19 */ 62 0x0400, /* R20 - Clock Rates 0 */ 63 0x0D07, /* R21 - Clock Rates 1 */ 64 0x0000, /* R22 - Clock Rates 2 */ 65 0x0000, /* R23 */ 66 0x0050, /* R24 - Audio Interface 0 */ 67 0x0242, /* R25 - Audio Interface 1 */ 68 0x0008, /* R26 - Audio Interface 2 */ 69 0x0022, /* R27 - Audio Interface 3 */ 70 0x0000, /* R28 */ 71 0x0000, /* R29 */ 72 0x00C0, /* R30 - DAC Digital Volume Left */ 73 0x00C0, /* R31 - DAC Digital Volume Right */ 74 0x0000, /* R32 - DAC Digital 0 */ 75 0x0000, /* R33 - DAC Digital 1 */ 76 0x0000, /* R34 */ 77 0x0000, /* R35 */ 78 0x00C0, /* R36 - ADC Digital Volume Left */ 79 0x00C0, /* R37 - ADC Digital Volume Right */ 80 0x0000, /* R38 - ADC Digital 0 */ 81 0x0073, /* R39 - Digital Microphone 0 */ 82 0x09BF, /* R40 - DRC 0 */ 83 0x3241, /* R41 - DRC 1 */ 84 0x0020, /* R42 - DRC 2 */ 85 0x0000, /* R43 - DRC 3 */ 86 0x0085, /* R44 - Analogue Left Input 0 */ 87 0x0085, /* R45 - Analogue Right Input 0 */ 88 0x0044, /* R46 - Analogue Left Input 1 */ 89 0x0044, /* R47 - Analogue Right Input 1 */ 90 0x0000, /* R48 */ 91 0x0000, /* R49 */ 92 0x0008, /* R50 - Analogue Left Mix 0 */ 93 0x0004, /* R51 - Analogue Right Mix 0 */ 94 0x0000, /* R52 - Analogue Spk Mix Left 0 */ 95 0x0000, /* R53 - Analogue Spk Mix Left 1 */ 96 0x0000, /* R54 - Analogue Spk Mix Right 0 */ 97 0x0000, /* R55 - Analogue Spk Mix Right 1 */ 98 0x0000, /* R56 */ 99 0x002D, /* R57 - Analogue OUT1 Left */ 100 0x002D, /* R58 - Analogue OUT1 Right */ 101 0x0039, /* R59 - Analogue OUT2 Left */ 102 0x0039, /* R60 - Analogue OUT2 Right */ 103 0x0100, /* R61 */ 104 0x0139, /* R62 - Analogue OUT3 Left */ 105 0x0139, /* R63 - Analogue OUT3 Right */ 106 0x0000, /* R64 */ 107 0x0000, /* R65 - Analogue SPK Output Control 0 */ 108 0x0000, /* R66 */ 109 0x0010, /* R67 - DC Servo 0 */ 110 0x0100, /* R68 */ 111 0x00A4, /* R69 - DC Servo 2 */ 112 0x0807, /* R70 */ 113 0x0000, /* R71 */ 114 0x0000, /* R72 */ 115 0x0000, /* R73 */ 116 0x0000, /* R74 */ 117 0x0000, /* R75 */ 118 0x0000, /* R76 */ 119 0x0000, /* R77 */ 120 0x0000, /* R78 */ 121 0x000E, /* R79 */ 122 0x0000, /* R80 */ 123 0x0000, /* R81 */ 124 0x0000, /* R82 */ 125 0x0000, /* R83 */ 126 0x0000, /* R84 */ 127 0x0000, /* R85 */ 128 0x0000, /* R86 */ 129 0x0006, /* R87 */ 130 0x0000, /* R88 */ 131 0x0000, /* R89 */ 132 0x0000, /* R90 - Analogue HP 0 */ 133 0x0060, /* R91 */ 134 0x0000, /* R92 */ 135 0x0000, /* R93 */ 136 0x0000, /* R94 - Analogue Lineout 0 */ 137 0x0060, /* R95 */ 138 0x0000, /* R96 */ 139 0x0000, /* R97 */ 140 0x0000, /* R98 - Charge Pump 0 */ 141 0x1F25, /* R99 */ 142 0x2B19, /* R100 */ 143 0x01C0, /* R101 */ 144 0x01EF, /* R102 */ 145 0x2B00, /* R103 */ 146 0x0000, /* R104 - Class W 0 */ 147 0x01C0, /* R105 */ 148 0x1C10, /* R106 */ 149 0x0000, /* R107 */ 150 0x0000, /* R108 - Write Sequencer 0 */ 151 0x0000, /* R109 - Write Sequencer 1 */ 152 0x0000, /* R110 - Write Sequencer 2 */ 153 0x0000, /* R111 - Write Sequencer 3 */ 154 0x0000, /* R112 - Write Sequencer 4 */ 155 0x0000, /* R113 */ 156 0x0000, /* R114 - Control Interface */ 157 0x0000, /* R115 */ 158 0x00A8, /* R116 - GPIO Control 1 */ 159 0x00A8, /* R117 - GPIO Control 2 */ 160 0x00A8, /* R118 - GPIO Control 3 */ 161 0x0220, /* R119 - GPIO Control 4 */ 162 0x01A0, /* R120 - GPIO Control 5 */ 163 0x0000, /* R121 - Interrupt Status 1 */ 164 0xFFFF, /* R122 - Interrupt Status 1 Mask */ 165 0x0000, /* R123 - Interrupt Polarity 1 */ 166 0x0000, /* R124 */ 167 0x0003, /* R125 */ 168 0x0000, /* R126 - Interrupt Control */ 169 0x0000, /* R127 */ 170 0x0005, /* R128 */ 171 0x0000, /* R129 - Control Interface Test 1 */ 172 0x0000, /* R130 */ 173 0x0000, /* R131 */ 174 0x0000, /* R132 */ 175 0x0000, /* R133 */ 176 0x0000, /* R134 */ 177 0x03FF, /* R135 */ 178 0x0007, /* R136 */ 179 0x0040, /* R137 */ 180 0x0000, /* R138 */ 181 0x0000, /* R139 */ 182 0x0000, /* R140 */ 183 0x0000, /* R141 */ 184 0x0000, /* R142 */ 185 0x0000, /* R143 */ 186 0x0000, /* R144 */ 187 0x0000, /* R145 */ 188 0x0000, /* R146 */ 189 0x0000, /* R147 */ 190 0x4000, /* R148 */ 191 0x6810, /* R149 - Charge Pump Test 1 */ 192 0x0004, /* R150 */ 193 0x0000, /* R151 */ 194 0x0000, /* R152 */ 195 0x0000, /* R153 */ 196 0x0000, /* R154 */ 197 0x0000, /* R155 */ 198 0x0000, /* R156 */ 199 0x0000, /* R157 */ 200 0x0000, /* R158 */ 201 0x0000, /* R159 */ 202 0x0000, /* R160 */ 203 0x0000, /* R161 */ 204 0x0000, /* R162 */ 205 0x0000, /* R163 */ 206 0x0028, /* R164 - Clock Rate Test 4 */ 207 0x0004, /* R165 */ 208 0x0000, /* R166 */ 209 0x0060, /* R167 */ 210 0x0000, /* R168 */ 211 0x0000, /* R169 */ 212 0x0000, /* R170 */ 213 0x0000, /* R171 */ 214 0x0000, /* R172 - Analogue Output Bias 0 */ 215 }; 216 217 struct wm8903_priv { 218 struct snd_soc_codec *codec; 219 220 int sysclk; 221 int irq; 222 223 int fs; 224 int deemph; 225 226 int dcs_pending; 227 int dcs_cache[4]; 228 229 /* Reference count */ 230 int class_w_users; 231 232 struct snd_soc_jack *mic_jack; 233 int mic_det; 234 int mic_short; 235 int mic_last_report; 236 int mic_delay; 237 238 #ifdef CONFIG_GPIOLIB 239 struct gpio_chip gpio_chip; 240 #endif 241 }; 242 243 static int wm8903_volatile_register(struct snd_soc_codec *codec, unsigned int reg) 244 { 245 switch (reg) { 246 case WM8903_SW_RESET_AND_ID: 247 case WM8903_REVISION_NUMBER: 248 case WM8903_INTERRUPT_STATUS_1: 249 case WM8903_WRITE_SEQUENCER_4: 250 case WM8903_POWER_MANAGEMENT_3: 251 case WM8903_POWER_MANAGEMENT_2: 252 case WM8903_DC_SERVO_READBACK_1: 253 case WM8903_DC_SERVO_READBACK_2: 254 case WM8903_DC_SERVO_READBACK_3: 255 case WM8903_DC_SERVO_READBACK_4: 256 return 1; 257 258 default: 259 return 0; 260 } 261 } 262 263 static void wm8903_reset(struct snd_soc_codec *codec) 264 { 265 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0); 266 memcpy(codec->reg_cache, wm8903_reg_defaults, 267 sizeof(wm8903_reg_defaults)); 268 } 269 270 static int wm8903_cp_event(struct snd_soc_dapm_widget *w, 271 struct snd_kcontrol *kcontrol, int event) 272 { 273 WARN_ON(event != SND_SOC_DAPM_POST_PMU); 274 mdelay(4); 275 276 return 0; 277 } 278 279 static int wm8903_dcs_event(struct snd_soc_dapm_widget *w, 280 struct snd_kcontrol *kcontrol, int event) 281 { 282 struct snd_soc_codec *codec = w->codec; 283 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 284 285 switch (event) { 286 case SND_SOC_DAPM_POST_PMU: 287 wm8903->dcs_pending |= 1 << w->shift; 288 break; 289 case SND_SOC_DAPM_PRE_PMD: 290 snd_soc_update_bits(codec, WM8903_DC_SERVO_0, 291 1 << w->shift, 0); 292 break; 293 } 294 295 return 0; 296 } 297 298 #define WM8903_DCS_MODE_WRITE_STOP 0 299 #define WM8903_DCS_MODE_START_STOP 2 300 301 static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm, 302 enum snd_soc_dapm_type event, int subseq) 303 { 304 struct snd_soc_codec *codec = container_of(dapm, 305 struct snd_soc_codec, dapm); 306 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 307 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP; 308 int i, val; 309 310 /* Complete any pending DC servo starts */ 311 if (wm8903->dcs_pending) { 312 dev_dbg(codec->dev, "Starting DC servo for %x\n", 313 wm8903->dcs_pending); 314 315 /* If we've no cached values then we need to do startup */ 316 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) { 317 if (!(wm8903->dcs_pending & (1 << i))) 318 continue; 319 320 if (wm8903->dcs_cache[i]) { 321 dev_dbg(codec->dev, 322 "Restore DC servo %d value %x\n", 323 3 - i, wm8903->dcs_cache[i]); 324 325 snd_soc_write(codec, WM8903_DC_SERVO_4 + i, 326 wm8903->dcs_cache[i] & 0xff); 327 } else { 328 dev_dbg(codec->dev, 329 "Calibrate DC servo %d\n", 3 - i); 330 dcs_mode = WM8903_DCS_MODE_START_STOP; 331 } 332 } 333 334 /* Don't trust the cache for analogue */ 335 if (wm8903->class_w_users) 336 dcs_mode = WM8903_DCS_MODE_START_STOP; 337 338 snd_soc_update_bits(codec, WM8903_DC_SERVO_2, 339 WM8903_DCS_MODE_MASK, dcs_mode); 340 341 snd_soc_update_bits(codec, WM8903_DC_SERVO_0, 342 WM8903_DCS_ENA_MASK, wm8903->dcs_pending); 343 344 switch (dcs_mode) { 345 case WM8903_DCS_MODE_WRITE_STOP: 346 break; 347 348 case WM8903_DCS_MODE_START_STOP: 349 msleep(270); 350 351 /* Cache the measured offsets for digital */ 352 if (wm8903->class_w_users) 353 break; 354 355 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) { 356 if (!(wm8903->dcs_pending & (1 << i))) 357 continue; 358 359 val = snd_soc_read(codec, 360 WM8903_DC_SERVO_READBACK_1 + i); 361 dev_dbg(codec->dev, "DC servo %d: %x\n", 362 3 - i, val); 363 wm8903->dcs_cache[i] = val; 364 } 365 break; 366 367 default: 368 pr_warn("DCS mode %d delay not set\n", dcs_mode); 369 break; 370 } 371 372 wm8903->dcs_pending = 0; 373 } 374 } 375 376 /* 377 * When used with DAC outputs only the WM8903 charge pump supports 378 * operation in class W mode, providing very low power consumption 379 * when used with digital sources. Enable and disable this mode 380 * automatically depending on the mixer configuration. 381 * 382 * All the relevant controls are simple switches. 383 */ 384 static int wm8903_class_w_put(struct snd_kcontrol *kcontrol, 385 struct snd_ctl_elem_value *ucontrol) 386 { 387 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); 388 struct snd_soc_codec *codec = widget->codec; 389 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 390 u16 reg; 391 int ret; 392 393 reg = snd_soc_read(codec, WM8903_CLASS_W_0); 394 395 /* Turn it off if we're about to enable bypass */ 396 if (ucontrol->value.integer.value[0]) { 397 if (wm8903->class_w_users == 0) { 398 dev_dbg(codec->dev, "Disabling Class W\n"); 399 snd_soc_write(codec, WM8903_CLASS_W_0, reg & 400 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V)); 401 } 402 wm8903->class_w_users++; 403 } 404 405 /* Implement the change */ 406 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 407 408 /* If we've just disabled the last bypass path turn Class W on */ 409 if (!ucontrol->value.integer.value[0]) { 410 if (wm8903->class_w_users == 1) { 411 dev_dbg(codec->dev, "Enabling Class W\n"); 412 snd_soc_write(codec, WM8903_CLASS_W_0, reg | 413 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); 414 } 415 wm8903->class_w_users--; 416 } 417 418 dev_dbg(codec->dev, "Bypass use count now %d\n", 419 wm8903->class_w_users); 420 421 return ret; 422 } 423 424 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \ 425 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 426 .info = snd_soc_info_volsw, \ 427 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \ 428 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 429 430 431 static int wm8903_deemph[] = { 0, 32000, 44100, 48000 }; 432 433 static int wm8903_set_deemph(struct snd_soc_codec *codec) 434 { 435 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 436 int val, i, best; 437 438 /* If we're using deemphasis select the nearest available sample 439 * rate. 440 */ 441 if (wm8903->deemph) { 442 best = 1; 443 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) { 444 if (abs(wm8903_deemph[i] - wm8903->fs) < 445 abs(wm8903_deemph[best] - wm8903->fs)) 446 best = i; 447 } 448 449 val = best << WM8903_DEEMPH_SHIFT; 450 } else { 451 best = 0; 452 val = 0; 453 } 454 455 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n", 456 best, wm8903_deemph[best]); 457 458 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1, 459 WM8903_DEEMPH_MASK, val); 460 } 461 462 static int wm8903_get_deemph(struct snd_kcontrol *kcontrol, 463 struct snd_ctl_elem_value *ucontrol) 464 { 465 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 466 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 467 468 ucontrol->value.enumerated.item[0] = wm8903->deemph; 469 470 return 0; 471 } 472 473 static int wm8903_put_deemph(struct snd_kcontrol *kcontrol, 474 struct snd_ctl_elem_value *ucontrol) 475 { 476 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 477 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 478 int deemph = ucontrol->value.enumerated.item[0]; 479 int ret = 0; 480 481 if (deemph > 1) 482 return -EINVAL; 483 484 mutex_lock(&codec->mutex); 485 if (wm8903->deemph != deemph) { 486 wm8903->deemph = deemph; 487 488 wm8903_set_deemph(codec); 489 490 ret = 1; 491 } 492 mutex_unlock(&codec->mutex); 493 494 return ret; 495 } 496 497 /* ALSA can only do steps of .01dB */ 498 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 499 500 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0); 501 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); 502 503 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0); 504 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0); 505 static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0); 506 static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0); 507 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0); 508 509 static const char *hpf_mode_text[] = { 510 "Hi-fi", "Voice 1", "Voice 2", "Voice 3" 511 }; 512 513 static const struct soc_enum hpf_mode = 514 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text); 515 516 static const char *osr_text[] = { 517 "Low power", "High performance" 518 }; 519 520 static const struct soc_enum adc_osr = 521 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text); 522 523 static const struct soc_enum dac_osr = 524 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text); 525 526 static const char *drc_slope_text[] = { 527 "1", "1/2", "1/4", "1/8", "1/16", "0" 528 }; 529 530 static const struct soc_enum drc_slope_r0 = 531 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text); 532 533 static const struct soc_enum drc_slope_r1 = 534 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text); 535 536 static const char *drc_attack_text[] = { 537 "instantaneous", 538 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms", 539 "46.4ms", "92.8ms", "185.6ms" 540 }; 541 542 static const struct soc_enum drc_attack = 543 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text); 544 545 static const char *drc_decay_text[] = { 546 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s", 547 "23.87s", "47.56s" 548 }; 549 550 static const struct soc_enum drc_decay = 551 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text); 552 553 static const char *drc_ff_delay_text[] = { 554 "5 samples", "9 samples" 555 }; 556 557 static const struct soc_enum drc_ff_delay = 558 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text); 559 560 static const char *drc_qr_decay_text[] = { 561 "0.725ms", "1.45ms", "5.8ms" 562 }; 563 564 static const struct soc_enum drc_qr_decay = 565 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text); 566 567 static const char *drc_smoothing_text[] = { 568 "Low", "Medium", "High" 569 }; 570 571 static const struct soc_enum drc_smoothing = 572 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text); 573 574 static const char *soft_mute_text[] = { 575 "Fast (fs/2)", "Slow (fs/32)" 576 }; 577 578 static const struct soc_enum soft_mute = 579 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text); 580 581 static const char *mute_mode_text[] = { 582 "Hard", "Soft" 583 }; 584 585 static const struct soc_enum mute_mode = 586 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text); 587 588 static const char *companding_text[] = { 589 "ulaw", "alaw" 590 }; 591 592 static const struct soc_enum dac_companding = 593 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text); 594 595 static const struct soc_enum adc_companding = 596 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text); 597 598 static const char *input_mode_text[] = { 599 "Single-Ended", "Differential Line", "Differential Mic" 600 }; 601 602 static const struct soc_enum linput_mode_enum = 603 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text); 604 605 static const struct soc_enum rinput_mode_enum = 606 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text); 607 608 static const char *linput_mux_text[] = { 609 "IN1L", "IN2L", "IN3L" 610 }; 611 612 static const struct soc_enum linput_enum = 613 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text); 614 615 static const struct soc_enum linput_inv_enum = 616 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text); 617 618 static const char *rinput_mux_text[] = { 619 "IN1R", "IN2R", "IN3R" 620 }; 621 622 static const struct soc_enum rinput_enum = 623 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text); 624 625 static const struct soc_enum rinput_inv_enum = 626 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text); 627 628 629 static const char *sidetone_text[] = { 630 "None", "Left", "Right" 631 }; 632 633 static const struct soc_enum lsidetone_enum = 634 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text); 635 636 static const struct soc_enum rsidetone_enum = 637 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text); 638 639 static const char *aif_text[] = { 640 "Left", "Right" 641 }; 642 643 static const struct soc_enum lcapture_enum = 644 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 7, 2, aif_text); 645 646 static const struct soc_enum rcapture_enum = 647 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 6, 2, aif_text); 648 649 static const struct soc_enum lplay_enum = 650 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 5, 2, aif_text); 651 652 static const struct soc_enum rplay_enum = 653 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 4, 2, aif_text); 654 655 static const struct snd_kcontrol_new wm8903_snd_controls[] = { 656 657 /* Input PGAs - No TLV since the scale depends on PGA mode */ 658 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0, 659 7, 1, 1), 660 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0, 661 0, 31, 0), 662 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1, 663 6, 1, 0), 664 665 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0, 666 7, 1, 1), 667 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0, 668 0, 31, 0), 669 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1, 670 6, 1, 0), 671 672 /* ADCs */ 673 SOC_ENUM("ADC OSR", adc_osr), 674 SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0), 675 SOC_ENUM("HPF Mode", hpf_mode), 676 SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0), 677 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0), 678 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1), 679 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1, 680 drc_tlv_thresh), 681 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp), 682 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min), 683 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max), 684 SOC_ENUM("DRC Attack Rate", drc_attack), 685 SOC_ENUM("DRC Decay Rate", drc_decay), 686 SOC_ENUM("DRC FF Delay", drc_ff_delay), 687 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0), 688 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0), 689 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max), 690 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay), 691 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0), 692 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0), 693 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing), 694 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup), 695 696 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT, 697 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv), 698 SOC_ENUM("ADC Companding Mode", adc_companding), 699 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0), 700 701 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8, 702 12, 0, digital_sidetone_tlv), 703 704 /* DAC */ 705 SOC_ENUM("DAC OSR", dac_osr), 706 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT, 707 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), 708 SOC_ENUM("DAC Soft Mute Rate", soft_mute), 709 SOC_ENUM("DAC Mute Mode", mute_mode), 710 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0), 711 SOC_ENUM("DAC Companding Mode", dac_companding), 712 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0), 713 SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0, 714 wm8903_get_deemph, wm8903_put_deemph), 715 716 /* Headphones */ 717 SOC_DOUBLE_R("Headphone Switch", 718 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 719 8, 1, 1), 720 SOC_DOUBLE_R("Headphone ZC Switch", 721 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 722 6, 1, 0), 723 SOC_DOUBLE_R_TLV("Headphone Volume", 724 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 725 0, 63, 0, out_tlv), 726 727 /* Line out */ 728 SOC_DOUBLE_R("Line Out Switch", 729 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 730 8, 1, 1), 731 SOC_DOUBLE_R("Line Out ZC Switch", 732 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 733 6, 1, 0), 734 SOC_DOUBLE_R_TLV("Line Out Volume", 735 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 736 0, 63, 0, out_tlv), 737 738 /* Speaker */ 739 SOC_DOUBLE_R("Speaker Switch", 740 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1), 741 SOC_DOUBLE_R("Speaker ZC Switch", 742 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0), 743 SOC_DOUBLE_R_TLV("Speaker Volume", 744 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 745 0, 63, 0, out_tlv), 746 }; 747 748 static const struct snd_kcontrol_new linput_mode_mux = 749 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum); 750 751 static const struct snd_kcontrol_new rinput_mode_mux = 752 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum); 753 754 static const struct snd_kcontrol_new linput_mux = 755 SOC_DAPM_ENUM("Left Input Mux", linput_enum); 756 757 static const struct snd_kcontrol_new linput_inv_mux = 758 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum); 759 760 static const struct snd_kcontrol_new rinput_mux = 761 SOC_DAPM_ENUM("Right Input Mux", rinput_enum); 762 763 static const struct snd_kcontrol_new rinput_inv_mux = 764 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum); 765 766 static const struct snd_kcontrol_new lsidetone_mux = 767 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum); 768 769 static const struct snd_kcontrol_new rsidetone_mux = 770 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum); 771 772 static const struct snd_kcontrol_new lcapture_mux = 773 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum); 774 775 static const struct snd_kcontrol_new rcapture_mux = 776 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum); 777 778 static const struct snd_kcontrol_new lplay_mux = 779 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum); 780 781 static const struct snd_kcontrol_new rplay_mux = 782 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum); 783 784 static const struct snd_kcontrol_new left_output_mixer[] = { 785 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0), 786 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0), 787 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0), 788 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0), 789 }; 790 791 static const struct snd_kcontrol_new right_output_mixer[] = { 792 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0), 793 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0), 794 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0), 795 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0), 796 }; 797 798 static const struct snd_kcontrol_new left_speaker_mixer[] = { 799 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0), 800 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0), 801 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0), 802 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 803 0, 1, 0), 804 }; 805 806 static const struct snd_kcontrol_new right_speaker_mixer[] = { 807 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0), 808 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0), 809 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 810 1, 1, 0), 811 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 812 0, 1, 0), 813 }; 814 815 static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = { 816 SND_SOC_DAPM_INPUT("IN1L"), 817 SND_SOC_DAPM_INPUT("IN1R"), 818 SND_SOC_DAPM_INPUT("IN2L"), 819 SND_SOC_DAPM_INPUT("IN2R"), 820 SND_SOC_DAPM_INPUT("IN3L"), 821 SND_SOC_DAPM_INPUT("IN3R"), 822 823 SND_SOC_DAPM_OUTPUT("HPOUTL"), 824 SND_SOC_DAPM_OUTPUT("HPOUTR"), 825 SND_SOC_DAPM_OUTPUT("LINEOUTL"), 826 SND_SOC_DAPM_OUTPUT("LINEOUTR"), 827 SND_SOC_DAPM_OUTPUT("LOP"), 828 SND_SOC_DAPM_OUTPUT("LON"), 829 SND_SOC_DAPM_OUTPUT("ROP"), 830 SND_SOC_DAPM_OUTPUT("RON"), 831 832 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0), 833 834 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux), 835 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0, 836 &linput_inv_mux), 837 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux), 838 839 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux), 840 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0, 841 &rinput_inv_mux), 842 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux), 843 844 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0), 845 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0), 846 847 SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0), 848 SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0), 849 850 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux), 851 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux), 852 853 SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0), 854 SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0), 855 856 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux), 857 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux), 858 859 SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0), 860 SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0), 861 862 SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux), 863 SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux), 864 865 SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0), 866 SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0), 867 868 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0, 869 left_output_mixer, ARRAY_SIZE(left_output_mixer)), 870 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0, 871 right_output_mixer, ARRAY_SIZE(right_output_mixer)), 872 873 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0, 874 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 875 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0, 876 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 877 878 SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_ANALOGUE_HP_0, 879 4, 0, NULL, 0), 880 SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_ANALOGUE_HP_0, 881 0, 0, NULL, 0), 882 883 SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_ANALOGUE_LINEOUT_0, 4, 0, 884 NULL, 0), 885 SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_ANALOGUE_LINEOUT_0, 0, 0, 886 NULL, 0), 887 888 SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0), 889 SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0), 890 SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 1, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0), 891 SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0), 892 SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0), 893 SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 1, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0), 894 895 SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0, 896 NULL, 0), 897 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0, 898 NULL, 0), 899 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 1, WM8903_ANALOGUE_LINEOUT_0, 5, 0, 900 NULL, 0), 901 SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0, 902 NULL, 0), 903 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0, 904 NULL, 0), 905 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 1, WM8903_ANALOGUE_LINEOUT_0, 1, 0, 906 NULL, 0), 907 908 SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0), 909 SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event, 910 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 911 SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event, 912 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 913 SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event, 914 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 915 SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event, 916 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 917 918 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0, 919 NULL, 0), 920 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0, 921 NULL, 0), 922 923 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0, 924 wm8903_cp_event, SND_SOC_DAPM_POST_PMU), 925 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0), 926 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0), 927 }; 928 929 static const struct snd_soc_dapm_route intercon[] = { 930 931 { "CLK_DSP", NULL, "CLK_SYS" }, 932 { "Mic Bias", NULL, "CLK_SYS" }, 933 { "HPL_DCS", NULL, "CLK_SYS" }, 934 { "HPR_DCS", NULL, "CLK_SYS" }, 935 { "LINEOUTL_DCS", NULL, "CLK_SYS" }, 936 { "LINEOUTR_DCS", NULL, "CLK_SYS" }, 937 938 { "Left Input Mux", "IN1L", "IN1L" }, 939 { "Left Input Mux", "IN2L", "IN2L" }, 940 { "Left Input Mux", "IN3L", "IN3L" }, 941 942 { "Left Input Inverting Mux", "IN1L", "IN1L" }, 943 { "Left Input Inverting Mux", "IN2L", "IN2L" }, 944 { "Left Input Inverting Mux", "IN3L", "IN3L" }, 945 946 { "Right Input Mux", "IN1R", "IN1R" }, 947 { "Right Input Mux", "IN2R", "IN2R" }, 948 { "Right Input Mux", "IN3R", "IN3R" }, 949 950 { "Right Input Inverting Mux", "IN1R", "IN1R" }, 951 { "Right Input Inverting Mux", "IN2R", "IN2R" }, 952 { "Right Input Inverting Mux", "IN3R", "IN3R" }, 953 954 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" }, 955 { "Left Input Mode Mux", "Differential Line", 956 "Left Input Mux" }, 957 { "Left Input Mode Mux", "Differential Line", 958 "Left Input Inverting Mux" }, 959 { "Left Input Mode Mux", "Differential Mic", 960 "Left Input Mux" }, 961 { "Left Input Mode Mux", "Differential Mic", 962 "Left Input Inverting Mux" }, 963 964 { "Right Input Mode Mux", "Single-Ended", 965 "Right Input Inverting Mux" }, 966 { "Right Input Mode Mux", "Differential Line", 967 "Right Input Mux" }, 968 { "Right Input Mode Mux", "Differential Line", 969 "Right Input Inverting Mux" }, 970 { "Right Input Mode Mux", "Differential Mic", 971 "Right Input Mux" }, 972 { "Right Input Mode Mux", "Differential Mic", 973 "Right Input Inverting Mux" }, 974 975 { "Left Input PGA", NULL, "Left Input Mode Mux" }, 976 { "Right Input PGA", NULL, "Right Input Mode Mux" }, 977 978 { "Left Capture Mux", "Left", "ADCL" }, 979 { "Left Capture Mux", "Right", "ADCR" }, 980 981 { "Right Capture Mux", "Left", "ADCL" }, 982 { "Right Capture Mux", "Right", "ADCR" }, 983 984 { "AIFTXL", NULL, "Left Capture Mux" }, 985 { "AIFTXR", NULL, "Right Capture Mux" }, 986 987 { "ADCL", NULL, "Left Input PGA" }, 988 { "ADCL", NULL, "CLK_DSP" }, 989 { "ADCR", NULL, "Right Input PGA" }, 990 { "ADCR", NULL, "CLK_DSP" }, 991 992 { "Left Playback Mux", "Left", "AIFRXL" }, 993 { "Left Playback Mux", "Right", "AIFRXR" }, 994 995 { "Right Playback Mux", "Left", "AIFRXL" }, 996 { "Right Playback Mux", "Right", "AIFRXR" }, 997 998 { "DACL Sidetone", "Left", "ADCL" }, 999 { "DACL Sidetone", "Right", "ADCR" }, 1000 { "DACR Sidetone", "Left", "ADCL" }, 1001 { "DACR Sidetone", "Right", "ADCR" }, 1002 1003 { "DACL", NULL, "Left Playback Mux" }, 1004 { "DACL", NULL, "DACL Sidetone" }, 1005 { "DACL", NULL, "CLK_DSP" }, 1006 1007 { "DACR", NULL, "Right Playback Mux" }, 1008 { "DACR", NULL, "DACR Sidetone" }, 1009 { "DACR", NULL, "CLK_DSP" }, 1010 1011 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" }, 1012 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" }, 1013 { "Left Output Mixer", "DACL Switch", "DACL" }, 1014 { "Left Output Mixer", "DACR Switch", "DACR" }, 1015 1016 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" }, 1017 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" }, 1018 { "Right Output Mixer", "DACL Switch", "DACL" }, 1019 { "Right Output Mixer", "DACR Switch", "DACR" }, 1020 1021 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, 1022 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, 1023 { "Left Speaker Mixer", "DACL Switch", "DACL" }, 1024 { "Left Speaker Mixer", "DACR Switch", "DACR" }, 1025 1026 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, 1027 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, 1028 { "Right Speaker Mixer", "DACL Switch", "DACL" }, 1029 { "Right Speaker Mixer", "DACR Switch", "DACR" }, 1030 1031 { "Left Line Output PGA", NULL, "Left Output Mixer" }, 1032 { "Right Line Output PGA", NULL, "Right Output Mixer" }, 1033 1034 { "Left Headphone Output PGA", NULL, "Left Output Mixer" }, 1035 { "Right Headphone Output PGA", NULL, "Right Output Mixer" }, 1036 1037 { "Left Speaker PGA", NULL, "Left Speaker Mixer" }, 1038 { "Right Speaker PGA", NULL, "Right Speaker Mixer" }, 1039 1040 { "HPL_ENA_DLY", NULL, "Left Headphone Output PGA" }, 1041 { "HPR_ENA_DLY", NULL, "Right Headphone Output PGA" }, 1042 { "LINEOUTL_ENA_DLY", NULL, "Left Line Output PGA" }, 1043 { "LINEOUTR_ENA_DLY", NULL, "Right Line Output PGA" }, 1044 1045 { "HPL_DCS", NULL, "DCS Master" }, 1046 { "HPR_DCS", NULL, "DCS Master" }, 1047 { "LINEOUTL_DCS", NULL, "DCS Master" }, 1048 { "LINEOUTR_DCS", NULL, "DCS Master" }, 1049 1050 { "HPL_DCS", NULL, "HPL_ENA_DLY" }, 1051 { "HPR_DCS", NULL, "HPR_ENA_DLY" }, 1052 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" }, 1053 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" }, 1054 1055 { "HPL_ENA_OUTP", NULL, "HPL_DCS" }, 1056 { "HPR_ENA_OUTP", NULL, "HPR_DCS" }, 1057 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" }, 1058 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" }, 1059 1060 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" }, 1061 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" }, 1062 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" }, 1063 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" }, 1064 1065 { "HPOUTL", NULL, "HPL_RMV_SHORT" }, 1066 { "HPOUTR", NULL, "HPR_RMV_SHORT" }, 1067 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" }, 1068 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" }, 1069 1070 { "LOP", NULL, "Left Speaker PGA" }, 1071 { "LON", NULL, "Left Speaker PGA" }, 1072 1073 { "ROP", NULL, "Right Speaker PGA" }, 1074 { "RON", NULL, "Right Speaker PGA" }, 1075 1076 { "Left Headphone Output PGA", NULL, "Charge Pump" }, 1077 { "Right Headphone Output PGA", NULL, "Charge Pump" }, 1078 { "Left Line Output PGA", NULL, "Charge Pump" }, 1079 { "Right Line Output PGA", NULL, "Charge Pump" }, 1080 }; 1081 1082 static int wm8903_add_widgets(struct snd_soc_codec *codec) 1083 { 1084 struct snd_soc_dapm_context *dapm = &codec->dapm; 1085 1086 snd_soc_dapm_new_controls(dapm, wm8903_dapm_widgets, 1087 ARRAY_SIZE(wm8903_dapm_widgets)); 1088 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); 1089 1090 return 0; 1091 } 1092 1093 static int wm8903_set_bias_level(struct snd_soc_codec *codec, 1094 enum snd_soc_bias_level level) 1095 { 1096 switch (level) { 1097 case SND_SOC_BIAS_ON: 1098 break; 1099 1100 case SND_SOC_BIAS_PREPARE: 1101 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1102 WM8903_VMID_RES_MASK, 1103 WM8903_VMID_RES_50K); 1104 break; 1105 1106 case SND_SOC_BIAS_STANDBY: 1107 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1108 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0, 1109 WM8903_POBCTRL | WM8903_ISEL_MASK | 1110 WM8903_STARTUP_BIAS_ENA | 1111 WM8903_BIAS_ENA, 1112 WM8903_POBCTRL | 1113 (2 << WM8903_ISEL_SHIFT) | 1114 WM8903_STARTUP_BIAS_ENA); 1115 1116 snd_soc_update_bits(codec, 1117 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0, 1118 WM8903_SPK_DISCHARGE, 1119 WM8903_SPK_DISCHARGE); 1120 1121 msleep(33); 1122 1123 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5, 1124 WM8903_SPKL_ENA | WM8903_SPKR_ENA, 1125 WM8903_SPKL_ENA | WM8903_SPKR_ENA); 1126 1127 snd_soc_update_bits(codec, 1128 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0, 1129 WM8903_SPK_DISCHARGE, 0); 1130 1131 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1132 WM8903_VMID_TIE_ENA | 1133 WM8903_BUFIO_ENA | 1134 WM8903_VMID_IO_ENA | 1135 WM8903_VMID_SOFT_MASK | 1136 WM8903_VMID_RES_MASK | 1137 WM8903_VMID_BUF_ENA, 1138 WM8903_VMID_TIE_ENA | 1139 WM8903_BUFIO_ENA | 1140 WM8903_VMID_IO_ENA | 1141 (2 << WM8903_VMID_SOFT_SHIFT) | 1142 WM8903_VMID_RES_250K | 1143 WM8903_VMID_BUF_ENA); 1144 1145 msleep(129); 1146 1147 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5, 1148 WM8903_SPKL_ENA | WM8903_SPKR_ENA, 1149 0); 1150 1151 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1152 WM8903_VMID_SOFT_MASK, 0); 1153 1154 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1155 WM8903_VMID_RES_MASK, 1156 WM8903_VMID_RES_50K); 1157 1158 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0, 1159 WM8903_BIAS_ENA | WM8903_POBCTRL, 1160 WM8903_BIAS_ENA); 1161 1162 /* By default no bypass paths are enabled so 1163 * enable Class W support. 1164 */ 1165 dev_dbg(codec->dev, "Enabling Class W\n"); 1166 snd_soc_update_bits(codec, WM8903_CLASS_W_0, 1167 WM8903_CP_DYN_FREQ | 1168 WM8903_CP_DYN_V, 1169 WM8903_CP_DYN_FREQ | 1170 WM8903_CP_DYN_V); 1171 } 1172 1173 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1174 WM8903_VMID_RES_MASK, 1175 WM8903_VMID_RES_250K); 1176 break; 1177 1178 case SND_SOC_BIAS_OFF: 1179 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0, 1180 WM8903_BIAS_ENA, 0); 1181 1182 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1183 WM8903_VMID_SOFT_MASK, 1184 2 << WM8903_VMID_SOFT_SHIFT); 1185 1186 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1187 WM8903_VMID_BUF_ENA, 0); 1188 1189 msleep(290); 1190 1191 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1192 WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA | 1193 WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK | 1194 WM8903_VMID_SOFT_MASK | 1195 WM8903_VMID_BUF_ENA, 0); 1196 1197 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0, 1198 WM8903_STARTUP_BIAS_ENA, 0); 1199 break; 1200 } 1201 1202 codec->dapm.bias_level = level; 1203 1204 return 0; 1205 } 1206 1207 static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1208 int clk_id, unsigned int freq, int dir) 1209 { 1210 struct snd_soc_codec *codec = codec_dai->codec; 1211 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1212 1213 wm8903->sysclk = freq; 1214 1215 return 0; 1216 } 1217 1218 static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai, 1219 unsigned int fmt) 1220 { 1221 struct snd_soc_codec *codec = codec_dai->codec; 1222 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1); 1223 1224 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK | 1225 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV); 1226 1227 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1228 case SND_SOC_DAIFMT_CBS_CFS: 1229 break; 1230 case SND_SOC_DAIFMT_CBS_CFM: 1231 aif1 |= WM8903_LRCLK_DIR; 1232 break; 1233 case SND_SOC_DAIFMT_CBM_CFM: 1234 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR; 1235 break; 1236 case SND_SOC_DAIFMT_CBM_CFS: 1237 aif1 |= WM8903_BCLK_DIR; 1238 break; 1239 default: 1240 return -EINVAL; 1241 } 1242 1243 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1244 case SND_SOC_DAIFMT_DSP_A: 1245 aif1 |= 0x3; 1246 break; 1247 case SND_SOC_DAIFMT_DSP_B: 1248 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV; 1249 break; 1250 case SND_SOC_DAIFMT_I2S: 1251 aif1 |= 0x2; 1252 break; 1253 case SND_SOC_DAIFMT_RIGHT_J: 1254 aif1 |= 0x1; 1255 break; 1256 case SND_SOC_DAIFMT_LEFT_J: 1257 break; 1258 default: 1259 return -EINVAL; 1260 } 1261 1262 /* Clock inversion */ 1263 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1264 case SND_SOC_DAIFMT_DSP_A: 1265 case SND_SOC_DAIFMT_DSP_B: 1266 /* frame inversion not valid for DSP modes */ 1267 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1268 case SND_SOC_DAIFMT_NB_NF: 1269 break; 1270 case SND_SOC_DAIFMT_IB_NF: 1271 aif1 |= WM8903_AIF_BCLK_INV; 1272 break; 1273 default: 1274 return -EINVAL; 1275 } 1276 break; 1277 case SND_SOC_DAIFMT_I2S: 1278 case SND_SOC_DAIFMT_RIGHT_J: 1279 case SND_SOC_DAIFMT_LEFT_J: 1280 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1281 case SND_SOC_DAIFMT_NB_NF: 1282 break; 1283 case SND_SOC_DAIFMT_IB_IF: 1284 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV; 1285 break; 1286 case SND_SOC_DAIFMT_IB_NF: 1287 aif1 |= WM8903_AIF_BCLK_INV; 1288 break; 1289 case SND_SOC_DAIFMT_NB_IF: 1290 aif1 |= WM8903_AIF_LRCLK_INV; 1291 break; 1292 default: 1293 return -EINVAL; 1294 } 1295 break; 1296 default: 1297 return -EINVAL; 1298 } 1299 1300 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); 1301 1302 return 0; 1303 } 1304 1305 static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1306 { 1307 struct snd_soc_codec *codec = codec_dai->codec; 1308 u16 reg; 1309 1310 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); 1311 1312 if (mute) 1313 reg |= WM8903_DAC_MUTE; 1314 else 1315 reg &= ~WM8903_DAC_MUTE; 1316 1317 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg); 1318 1319 return 0; 1320 } 1321 1322 /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended 1323 * for optimal performance so we list the lower rates first and match 1324 * on the last match we find. */ 1325 static struct { 1326 int div; 1327 int rate; 1328 int mode; 1329 int mclk_div; 1330 } clk_sys_ratios[] = { 1331 { 64, 0x0, 0x0, 1 }, 1332 { 68, 0x0, 0x1, 1 }, 1333 { 125, 0x0, 0x2, 1 }, 1334 { 128, 0x1, 0x0, 1 }, 1335 { 136, 0x1, 0x1, 1 }, 1336 { 192, 0x2, 0x0, 1 }, 1337 { 204, 0x2, 0x1, 1 }, 1338 1339 { 64, 0x0, 0x0, 2 }, 1340 { 68, 0x0, 0x1, 2 }, 1341 { 125, 0x0, 0x2, 2 }, 1342 { 128, 0x1, 0x0, 2 }, 1343 { 136, 0x1, 0x1, 2 }, 1344 { 192, 0x2, 0x0, 2 }, 1345 { 204, 0x2, 0x1, 2 }, 1346 1347 { 250, 0x2, 0x2, 1 }, 1348 { 256, 0x3, 0x0, 1 }, 1349 { 272, 0x3, 0x1, 1 }, 1350 { 384, 0x4, 0x0, 1 }, 1351 { 408, 0x4, 0x1, 1 }, 1352 { 375, 0x4, 0x2, 1 }, 1353 { 512, 0x5, 0x0, 1 }, 1354 { 544, 0x5, 0x1, 1 }, 1355 { 500, 0x5, 0x2, 1 }, 1356 { 768, 0x6, 0x0, 1 }, 1357 { 816, 0x6, 0x1, 1 }, 1358 { 750, 0x6, 0x2, 1 }, 1359 { 1024, 0x7, 0x0, 1 }, 1360 { 1088, 0x7, 0x1, 1 }, 1361 { 1000, 0x7, 0x2, 1 }, 1362 { 1408, 0x8, 0x0, 1 }, 1363 { 1496, 0x8, 0x1, 1 }, 1364 { 1536, 0x9, 0x0, 1 }, 1365 { 1632, 0x9, 0x1, 1 }, 1366 { 1500, 0x9, 0x2, 1 }, 1367 1368 { 250, 0x2, 0x2, 2 }, 1369 { 256, 0x3, 0x0, 2 }, 1370 { 272, 0x3, 0x1, 2 }, 1371 { 384, 0x4, 0x0, 2 }, 1372 { 408, 0x4, 0x1, 2 }, 1373 { 375, 0x4, 0x2, 2 }, 1374 { 512, 0x5, 0x0, 2 }, 1375 { 544, 0x5, 0x1, 2 }, 1376 { 500, 0x5, 0x2, 2 }, 1377 { 768, 0x6, 0x0, 2 }, 1378 { 816, 0x6, 0x1, 2 }, 1379 { 750, 0x6, 0x2, 2 }, 1380 { 1024, 0x7, 0x0, 2 }, 1381 { 1088, 0x7, 0x1, 2 }, 1382 { 1000, 0x7, 0x2, 2 }, 1383 { 1408, 0x8, 0x0, 2 }, 1384 { 1496, 0x8, 0x1, 2 }, 1385 { 1536, 0x9, 0x0, 2 }, 1386 { 1632, 0x9, 0x1, 2 }, 1387 { 1500, 0x9, 0x2, 2 }, 1388 }; 1389 1390 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */ 1391 static struct { 1392 int ratio; 1393 int div; 1394 } bclk_divs[] = { 1395 { 10, 0 }, 1396 { 20, 2 }, 1397 { 30, 3 }, 1398 { 40, 4 }, 1399 { 50, 5 }, 1400 { 60, 7 }, 1401 { 80, 8 }, 1402 { 100, 9 }, 1403 { 120, 11 }, 1404 { 160, 12 }, 1405 { 200, 13 }, 1406 { 220, 14 }, 1407 { 240, 15 }, 1408 { 300, 17 }, 1409 { 320, 18 }, 1410 { 440, 19 }, 1411 { 480, 20 }, 1412 }; 1413 1414 /* Sample rates for DSP */ 1415 static struct { 1416 int rate; 1417 int value; 1418 } sample_rates[] = { 1419 { 8000, 0 }, 1420 { 11025, 1 }, 1421 { 12000, 2 }, 1422 { 16000, 3 }, 1423 { 22050, 4 }, 1424 { 24000, 5 }, 1425 { 32000, 6 }, 1426 { 44100, 7 }, 1427 { 48000, 8 }, 1428 { 88200, 9 }, 1429 { 96000, 10 }, 1430 { 0, 0 }, 1431 }; 1432 1433 static int wm8903_hw_params(struct snd_pcm_substream *substream, 1434 struct snd_pcm_hw_params *params, 1435 struct snd_soc_dai *dai) 1436 { 1437 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1438 struct snd_soc_codec *codec =rtd->codec; 1439 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1440 int fs = params_rate(params); 1441 int bclk; 1442 int bclk_div; 1443 int i; 1444 int dsp_config; 1445 int clk_config; 1446 int best_val; 1447 int cur_val; 1448 int clk_sys; 1449 1450 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1); 1451 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2); 1452 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3); 1453 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0); 1454 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1); 1455 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); 1456 1457 /* Enable sloping stopband filter for low sample rates */ 1458 if (fs <= 24000) 1459 dac_digital1 |= WM8903_DAC_SB_FILT; 1460 else 1461 dac_digital1 &= ~WM8903_DAC_SB_FILT; 1462 1463 /* Configure sample rate logic for DSP - choose nearest rate */ 1464 dsp_config = 0; 1465 best_val = abs(sample_rates[dsp_config].rate - fs); 1466 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1467 cur_val = abs(sample_rates[i].rate - fs); 1468 if (cur_val <= best_val) { 1469 dsp_config = i; 1470 best_val = cur_val; 1471 } 1472 } 1473 1474 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate); 1475 clock1 &= ~WM8903_SAMPLE_RATE_MASK; 1476 clock1 |= sample_rates[dsp_config].value; 1477 1478 aif1 &= ~WM8903_AIF_WL_MASK; 1479 bclk = 2 * fs; 1480 switch (params_format(params)) { 1481 case SNDRV_PCM_FORMAT_S16_LE: 1482 bclk *= 16; 1483 break; 1484 case SNDRV_PCM_FORMAT_S20_3LE: 1485 bclk *= 20; 1486 aif1 |= 0x4; 1487 break; 1488 case SNDRV_PCM_FORMAT_S24_LE: 1489 bclk *= 24; 1490 aif1 |= 0x8; 1491 break; 1492 case SNDRV_PCM_FORMAT_S32_LE: 1493 bclk *= 32; 1494 aif1 |= 0xc; 1495 break; 1496 default: 1497 return -EINVAL; 1498 } 1499 1500 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n", 1501 wm8903->sysclk, fs); 1502 1503 /* We may not have an MCLK which allows us to generate exactly 1504 * the clock we want, particularly with USB derived inputs, so 1505 * approximate. 1506 */ 1507 clk_config = 0; 1508 best_val = abs((wm8903->sysclk / 1509 (clk_sys_ratios[0].mclk_div * 1510 clk_sys_ratios[0].div)) - fs); 1511 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) { 1512 cur_val = abs((wm8903->sysclk / 1513 (clk_sys_ratios[i].mclk_div * 1514 clk_sys_ratios[i].div)) - fs); 1515 1516 if (cur_val <= best_val) { 1517 clk_config = i; 1518 best_val = cur_val; 1519 } 1520 } 1521 1522 if (clk_sys_ratios[clk_config].mclk_div == 2) { 1523 clock0 |= WM8903_MCLKDIV2; 1524 clk_sys = wm8903->sysclk / 2; 1525 } else { 1526 clock0 &= ~WM8903_MCLKDIV2; 1527 clk_sys = wm8903->sysclk; 1528 } 1529 1530 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK | 1531 WM8903_CLK_SYS_MODE_MASK); 1532 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT; 1533 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT; 1534 1535 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n", 1536 clk_sys_ratios[clk_config].rate, 1537 clk_sys_ratios[clk_config].mode, 1538 clk_sys_ratios[clk_config].div); 1539 1540 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys); 1541 1542 /* We may not get quite the right frequency if using 1543 * approximate clocks so look for the closest match that is 1544 * higher than the target (we need to ensure that there enough 1545 * BCLKs to clock out the samples). 1546 */ 1547 bclk_div = 0; 1548 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk; 1549 i = 1; 1550 while (i < ARRAY_SIZE(bclk_divs)) { 1551 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk; 1552 if (cur_val < 0) /* BCLK table is sorted */ 1553 break; 1554 bclk_div = i; 1555 best_val = cur_val; 1556 i++; 1557 } 1558 1559 aif2 &= ~WM8903_BCLK_DIV_MASK; 1560 aif3 &= ~WM8903_LRCLK_RATE_MASK; 1561 1562 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n", 1563 bclk_divs[bclk_div].ratio / 10, bclk, 1564 (clk_sys * 10) / bclk_divs[bclk_div].ratio); 1565 1566 aif2 |= bclk_divs[bclk_div].div; 1567 aif3 |= bclk / fs; 1568 1569 wm8903->fs = params_rate(params); 1570 wm8903_set_deemph(codec); 1571 1572 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0); 1573 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1); 1574 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); 1575 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2); 1576 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3); 1577 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1); 1578 1579 return 0; 1580 } 1581 1582 /** 1583 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ 1584 * 1585 * @codec: WM8903 codec 1586 * @jack: jack to report detection events on 1587 * @det: value to report for presence detection 1588 * @shrt: value to report for short detection 1589 * 1590 * Enable microphone detection via IRQ on the WM8903. If GPIOs are 1591 * being used to bring out signals to the processor then only platform 1592 * data configuration is needed for WM8903 and processor GPIOs should 1593 * be configured using snd_soc_jack_add_gpios() instead. 1594 * 1595 * The current threasholds for detection should be configured using 1596 * micdet_cfg in the platform data. Using this function will force on 1597 * the microphone bias for the device. 1598 */ 1599 int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 1600 int det, int shrt) 1601 { 1602 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1603 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT; 1604 1605 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n", 1606 det, shrt); 1607 1608 /* Store the configuration */ 1609 wm8903->mic_jack = jack; 1610 wm8903->mic_det = det; 1611 wm8903->mic_short = shrt; 1612 1613 /* Enable interrupts we've got a report configured for */ 1614 if (det) 1615 irq_mask &= ~WM8903_MICDET_EINT; 1616 if (shrt) 1617 irq_mask &= ~WM8903_MICSHRT_EINT; 1618 1619 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK, 1620 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT, 1621 irq_mask); 1622 1623 if (det || shrt) { 1624 /* Enable mic detection, this may not have been set through 1625 * platform data (eg, if the defaults are OK). */ 1626 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0, 1627 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA); 1628 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0, 1629 WM8903_MICDET_ENA, WM8903_MICDET_ENA); 1630 } else { 1631 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0, 1632 WM8903_MICDET_ENA, 0); 1633 } 1634 1635 return 0; 1636 } 1637 EXPORT_SYMBOL_GPL(wm8903_mic_detect); 1638 1639 static irqreturn_t wm8903_irq(int irq, void *data) 1640 { 1641 struct snd_soc_codec *codec = data; 1642 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1643 int mic_report; 1644 int int_pol; 1645 int int_val = 0; 1646 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK); 1647 1648 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask; 1649 1650 if (int_val & WM8903_WSEQ_BUSY_EINT) { 1651 dev_warn(codec->dev, "Write sequencer done\n"); 1652 } 1653 1654 /* 1655 * The rest is microphone jack detection. We need to manually 1656 * invert the polarity of the interrupt after each event - to 1657 * simplify the code keep track of the last state we reported 1658 * and just invert the relevant bits in both the report and 1659 * the polarity register. 1660 */ 1661 mic_report = wm8903->mic_last_report; 1662 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1); 1663 1664 #ifndef CONFIG_SND_SOC_WM8903_MODULE 1665 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT)) 1666 trace_snd_soc_jack_irq(dev_name(codec->dev)); 1667 #endif 1668 1669 if (int_val & WM8903_MICSHRT_EINT) { 1670 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol); 1671 1672 mic_report ^= wm8903->mic_short; 1673 int_pol ^= WM8903_MICSHRT_INV; 1674 } 1675 1676 if (int_val & WM8903_MICDET_EINT) { 1677 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol); 1678 1679 mic_report ^= wm8903->mic_det; 1680 int_pol ^= WM8903_MICDET_INV; 1681 1682 msleep(wm8903->mic_delay); 1683 } 1684 1685 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1, 1686 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol); 1687 1688 snd_soc_jack_report(wm8903->mic_jack, mic_report, 1689 wm8903->mic_short | wm8903->mic_det); 1690 1691 wm8903->mic_last_report = mic_report; 1692 1693 return IRQ_HANDLED; 1694 } 1695 1696 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\ 1697 SNDRV_PCM_RATE_11025 | \ 1698 SNDRV_PCM_RATE_16000 | \ 1699 SNDRV_PCM_RATE_22050 | \ 1700 SNDRV_PCM_RATE_32000 | \ 1701 SNDRV_PCM_RATE_44100 | \ 1702 SNDRV_PCM_RATE_48000 | \ 1703 SNDRV_PCM_RATE_88200 | \ 1704 SNDRV_PCM_RATE_96000) 1705 1706 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 1707 SNDRV_PCM_RATE_11025 | \ 1708 SNDRV_PCM_RATE_16000 | \ 1709 SNDRV_PCM_RATE_22050 | \ 1710 SNDRV_PCM_RATE_32000 | \ 1711 SNDRV_PCM_RATE_44100 | \ 1712 SNDRV_PCM_RATE_48000) 1713 1714 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1715 SNDRV_PCM_FMTBIT_S20_3LE |\ 1716 SNDRV_PCM_FMTBIT_S24_LE) 1717 1718 static struct snd_soc_dai_ops wm8903_dai_ops = { 1719 .hw_params = wm8903_hw_params, 1720 .digital_mute = wm8903_digital_mute, 1721 .set_fmt = wm8903_set_dai_fmt, 1722 .set_sysclk = wm8903_set_dai_sysclk, 1723 }; 1724 1725 static struct snd_soc_dai_driver wm8903_dai = { 1726 .name = "wm8903-hifi", 1727 .playback = { 1728 .stream_name = "Playback", 1729 .channels_min = 2, 1730 .channels_max = 2, 1731 .rates = WM8903_PLAYBACK_RATES, 1732 .formats = WM8903_FORMATS, 1733 }, 1734 .capture = { 1735 .stream_name = "Capture", 1736 .channels_min = 2, 1737 .channels_max = 2, 1738 .rates = WM8903_CAPTURE_RATES, 1739 .formats = WM8903_FORMATS, 1740 }, 1741 .ops = &wm8903_dai_ops, 1742 .symmetric_rates = 1, 1743 }; 1744 1745 static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state) 1746 { 1747 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); 1748 1749 return 0; 1750 } 1751 1752 static int wm8903_resume(struct snd_soc_codec *codec) 1753 { 1754 int i; 1755 u16 *reg_cache = codec->reg_cache; 1756 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults), 1757 GFP_KERNEL); 1758 1759 /* Bring the codec back up to standby first to minimise pop/clicks */ 1760 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1761 1762 /* Sync back everything else */ 1763 if (tmp_cache) { 1764 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++) 1765 if (tmp_cache[i] != reg_cache[i]) 1766 snd_soc_write(codec, i, tmp_cache[i]); 1767 kfree(tmp_cache); 1768 } else { 1769 dev_err(codec->dev, "Failed to allocate temporary cache\n"); 1770 } 1771 1772 return 0; 1773 } 1774 1775 #ifdef CONFIG_GPIOLIB 1776 static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip) 1777 { 1778 return container_of(chip, struct wm8903_priv, gpio_chip); 1779 } 1780 1781 static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset) 1782 { 1783 if (offset >= WM8903_NUM_GPIO) 1784 return -EINVAL; 1785 1786 return 0; 1787 } 1788 1789 static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset) 1790 { 1791 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip); 1792 struct snd_soc_codec *codec = wm8903->codec; 1793 unsigned int mask, val; 1794 1795 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK; 1796 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) | 1797 WM8903_GP1_DIR; 1798 1799 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset, 1800 mask, val); 1801 } 1802 1803 static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset) 1804 { 1805 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip); 1806 struct snd_soc_codec *codec = wm8903->codec; 1807 int reg; 1808 1809 reg = snd_soc_read(codec, WM8903_GPIO_CONTROL_1 + offset); 1810 1811 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT; 1812 } 1813 1814 static int wm8903_gpio_direction_out(struct gpio_chip *chip, 1815 unsigned offset, int value) 1816 { 1817 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip); 1818 struct snd_soc_codec *codec = wm8903->codec; 1819 unsigned int mask, val; 1820 1821 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK; 1822 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) | 1823 (value << WM8903_GP2_LVL_SHIFT); 1824 1825 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset, 1826 mask, val); 1827 } 1828 1829 static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1830 { 1831 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip); 1832 struct snd_soc_codec *codec = wm8903->codec; 1833 1834 snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset, 1835 WM8903_GP1_LVL_MASK, 1836 !!value << WM8903_GP1_LVL_SHIFT); 1837 } 1838 1839 static struct gpio_chip wm8903_template_chip = { 1840 .label = "wm8903", 1841 .owner = THIS_MODULE, 1842 .request = wm8903_gpio_request, 1843 .direction_input = wm8903_gpio_direction_in, 1844 .get = wm8903_gpio_get, 1845 .direction_output = wm8903_gpio_direction_out, 1846 .set = wm8903_gpio_set, 1847 .can_sleep = 1, 1848 }; 1849 1850 static void wm8903_init_gpio(struct snd_soc_codec *codec) 1851 { 1852 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1853 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev); 1854 int ret; 1855 1856 wm8903->gpio_chip = wm8903_template_chip; 1857 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO; 1858 wm8903->gpio_chip.dev = codec->dev; 1859 1860 if (pdata && pdata->gpio_base) 1861 wm8903->gpio_chip.base = pdata->gpio_base; 1862 else 1863 wm8903->gpio_chip.base = -1; 1864 1865 ret = gpiochip_add(&wm8903->gpio_chip); 1866 if (ret != 0) 1867 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret); 1868 } 1869 1870 static void wm8903_free_gpio(struct snd_soc_codec *codec) 1871 { 1872 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1873 int ret; 1874 1875 ret = gpiochip_remove(&wm8903->gpio_chip); 1876 if (ret != 0) 1877 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret); 1878 } 1879 #else 1880 static void wm8903_init_gpio(struct snd_soc_codec *codec) 1881 { 1882 } 1883 1884 static void wm8903_free_gpio(struct snd_soc_codec *codec) 1885 { 1886 } 1887 #endif 1888 1889 static int wm8903_probe(struct snd_soc_codec *codec) 1890 { 1891 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev); 1892 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1893 int ret, i; 1894 int trigger, irq_pol; 1895 u16 val; 1896 1897 wm8903->codec = codec; 1898 1899 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C); 1900 if (ret != 0) { 1901 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1902 return ret; 1903 } 1904 1905 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID); 1906 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) { 1907 dev_err(codec->dev, 1908 "Device with ID register %x is not a WM8903\n", val); 1909 return -ENODEV; 1910 } 1911 1912 val = snd_soc_read(codec, WM8903_REVISION_NUMBER); 1913 dev_info(codec->dev, "WM8903 revision %c\n", 1914 (val & WM8903_CHIP_REV_MASK) + 'A'); 1915 1916 wm8903_reset(codec); 1917 1918 /* Set up GPIOs and microphone detection */ 1919 if (pdata) { 1920 bool mic_gpio = false; 1921 1922 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) { 1923 if (pdata->gpio_cfg[i] == WM8903_GPIO_NO_CONFIG) 1924 continue; 1925 1926 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i, 1927 pdata->gpio_cfg[i] & 0xffff); 1928 1929 val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK) 1930 >> WM8903_GP1_FN_SHIFT; 1931 1932 switch (val) { 1933 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT: 1934 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT: 1935 mic_gpio = true; 1936 break; 1937 default: 1938 break; 1939 } 1940 } 1941 1942 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0, 1943 pdata->micdet_cfg); 1944 1945 /* Microphone detection needs the WSEQ clock */ 1946 if (pdata->micdet_cfg) 1947 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0, 1948 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA); 1949 1950 /* If microphone detection is enabled by pdata but 1951 * detected via IRQ then interrupts can be lost before 1952 * the machine driver has set up microphone detection 1953 * IRQs as the IRQs are clear on read. The detection 1954 * will be enabled when the machine driver configures. 1955 */ 1956 WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA)); 1957 1958 wm8903->mic_delay = pdata->micdet_delay; 1959 } 1960 1961 if (wm8903->irq) { 1962 if (pdata && pdata->irq_active_low) { 1963 trigger = IRQF_TRIGGER_LOW; 1964 irq_pol = WM8903_IRQ_POL; 1965 } else { 1966 trigger = IRQF_TRIGGER_HIGH; 1967 irq_pol = 0; 1968 } 1969 1970 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL, 1971 WM8903_IRQ_POL, irq_pol); 1972 1973 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq, 1974 trigger | IRQF_ONESHOT, 1975 "wm8903", codec); 1976 if (ret != 0) { 1977 dev_err(codec->dev, "Failed to request IRQ: %d\n", 1978 ret); 1979 return ret; 1980 } 1981 1982 /* Enable write sequencer interrupts */ 1983 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK, 1984 WM8903_IM_WSEQ_BUSY_EINT, 0); 1985 } 1986 1987 /* power on device */ 1988 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1989 1990 /* Latch volume update bits */ 1991 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT); 1992 val |= WM8903_ADCVU; 1993 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val); 1994 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val); 1995 1996 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT); 1997 val |= WM8903_DACVU; 1998 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val); 1999 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val); 2000 2001 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT); 2002 val |= WM8903_HPOUTVU; 2003 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val); 2004 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val); 2005 2006 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT); 2007 val |= WM8903_LINEOUTVU; 2008 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val); 2009 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val); 2010 2011 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT); 2012 val |= WM8903_SPKVU; 2013 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val); 2014 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val); 2015 2016 /* Enable DAC soft mute by default */ 2017 snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1, 2018 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE, 2019 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE); 2020 2021 snd_soc_add_controls(codec, wm8903_snd_controls, 2022 ARRAY_SIZE(wm8903_snd_controls)); 2023 wm8903_add_widgets(codec); 2024 2025 wm8903_init_gpio(codec); 2026 2027 return ret; 2028 } 2029 2030 /* power down chip */ 2031 static int wm8903_remove(struct snd_soc_codec *codec) 2032 { 2033 wm8903_free_gpio(codec); 2034 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); 2035 return 0; 2036 } 2037 2038 static struct snd_soc_codec_driver soc_codec_dev_wm8903 = { 2039 .probe = wm8903_probe, 2040 .remove = wm8903_remove, 2041 .suspend = wm8903_suspend, 2042 .resume = wm8903_resume, 2043 .set_bias_level = wm8903_set_bias_level, 2044 .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults), 2045 .reg_word_size = sizeof(u16), 2046 .reg_cache_default = wm8903_reg_defaults, 2047 .volatile_register = wm8903_volatile_register, 2048 .seq_notifier = wm8903_seq_notifier, 2049 }; 2050 2051 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 2052 static __devinit int wm8903_i2c_probe(struct i2c_client *i2c, 2053 const struct i2c_device_id *id) 2054 { 2055 struct wm8903_priv *wm8903; 2056 int ret; 2057 2058 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL); 2059 if (wm8903 == NULL) 2060 return -ENOMEM; 2061 2062 i2c_set_clientdata(i2c, wm8903); 2063 wm8903->irq = i2c->irq; 2064 2065 ret = snd_soc_register_codec(&i2c->dev, 2066 &soc_codec_dev_wm8903, &wm8903_dai, 1); 2067 if (ret < 0) 2068 kfree(wm8903); 2069 return ret; 2070 } 2071 2072 static __devexit int wm8903_i2c_remove(struct i2c_client *client) 2073 { 2074 snd_soc_unregister_codec(&client->dev); 2075 kfree(i2c_get_clientdata(client)); 2076 return 0; 2077 } 2078 2079 static const struct i2c_device_id wm8903_i2c_id[] = { 2080 { "wm8903", 0 }, 2081 { } 2082 }; 2083 MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id); 2084 2085 static struct i2c_driver wm8903_i2c_driver = { 2086 .driver = { 2087 .name = "wm8903", 2088 .owner = THIS_MODULE, 2089 }, 2090 .probe = wm8903_i2c_probe, 2091 .remove = __devexit_p(wm8903_i2c_remove), 2092 .id_table = wm8903_i2c_id, 2093 }; 2094 #endif 2095 2096 static int __init wm8903_modinit(void) 2097 { 2098 int ret = 0; 2099 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 2100 ret = i2c_add_driver(&wm8903_i2c_driver); 2101 if (ret != 0) { 2102 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n", 2103 ret); 2104 } 2105 #endif 2106 return ret; 2107 } 2108 module_init(wm8903_modinit); 2109 2110 static void __exit wm8903_exit(void) 2111 { 2112 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 2113 i2c_del_driver(&wm8903_i2c_driver); 2114 #endif 2115 } 2116 module_exit(wm8903_exit); 2117 2118 MODULE_DESCRIPTION("ASoC WM8903 driver"); 2119 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>"); 2120 MODULE_LICENSE("GPL"); 2121