1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 4 #include <linux/component.h> 5 #include <linux/delay.h> 6 #include <linux/device.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of_gpio.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regmap.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/slab.h> 17 #include <sound/jack.h> 18 #include <sound/pcm_params.h> 19 #include <sound/pcm.h> 20 #include <sound/soc-dapm.h> 21 #include <sound/soc.h> 22 #include <sound/tlv.h> 23 24 #include "wcd-clsh-v2.h" 25 #include "wcd-mbhc-v2.h" 26 #include "wcd937x.h" 27 28 enum { 29 CHIPID_WCD9370 = 0, 30 CHIPID_WCD9375 = 5, 31 }; 32 33 /* Z value defined in milliohm */ 34 #define WCD937X_ZDET_VAL_32 (32000) 35 #define WCD937X_ZDET_VAL_400 (400000) 36 #define WCD937X_ZDET_VAL_1200 (1200000) 37 #define WCD937X_ZDET_VAL_100K (100000000) 38 /* Z floating defined in ohms */ 39 #define WCD937X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE) 40 #define WCD937X_ZDET_NUM_MEASUREMENTS (900) 41 #define WCD937X_MBHC_GET_C1(c) (((c) & 0xC000) >> 14) 42 #define WCD937X_MBHC_GET_X1(x) ((x) & 0x3FFF) 43 /* Z value compared in milliOhm */ 44 #define WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z) (((z) > 400000) || ((z) < 32000)) 45 #define WCD937X_MBHC_ZDET_CONST (86 * 16384) 46 #define WCD937X_MBHC_MOISTURE_RREF R_24_KOHM 47 #define WCD_MBHC_HS_V_MAX 1600 48 #define EAR_RX_PATH_AUX 1 49 #define WCD937X_MBHC_MAX_BUTTONS 8 50 51 #define WCD937X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 52 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 53 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\ 54 SNDRV_PCM_RATE_384000) 55 56 /* Fractional Rates */ 57 #define WCD937X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 58 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800) 59 60 #define WCD937X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |\ 61 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 62 63 enum { 64 ALLOW_BUCK_DISABLE, 65 HPH_COMP_DELAY, 66 HPH_PA_DELAY, 67 AMIC2_BCS_ENABLE, 68 }; 69 70 enum { 71 AIF1_PB = 0, 72 AIF1_CAP, 73 NUM_CODEC_DAIS, 74 }; 75 76 struct wcd937x_priv { 77 struct sdw_slave *tx_sdw_dev; 78 struct wcd937x_sdw_priv *sdw_priv[NUM_CODEC_DAIS]; 79 struct device *txdev; 80 struct device *rxdev; 81 struct device_node *rxnode; 82 struct device_node *txnode; 83 struct regmap *regmap; 84 /* micb setup lock */ 85 struct mutex micb_lock; 86 /* mbhc module */ 87 struct wcd_mbhc *wcd_mbhc; 88 struct wcd_mbhc_config mbhc_cfg; 89 struct wcd_mbhc_intr intr_ids; 90 struct wcd_clsh_ctrl *clsh_info; 91 struct irq_domain *virq; 92 struct regmap_irq_chip *wcd_regmap_irq_chip; 93 struct regmap_irq_chip_data *irq_chip; 94 struct regulator_bulk_data supplies[WCD937X_MAX_BULK_SUPPLY]; 95 struct regulator *buck_supply; 96 struct snd_soc_jack *jack; 97 unsigned long status_mask; 98 s32 micb_ref[WCD937X_MAX_MICBIAS]; 99 s32 pullup_ref[WCD937X_MAX_MICBIAS]; 100 u32 hph_mode; 101 int ear_rx_path; 102 u32 micb1_mv; 103 u32 micb2_mv; 104 u32 micb3_mv; 105 int hphr_pdm_wd_int; 106 int hphl_pdm_wd_int; 107 int aux_pdm_wd_int; 108 bool comp1_enable; 109 bool comp2_enable; 110 111 struct gpio_desc *us_euro_gpio; 112 struct gpio_desc *reset_gpio; 113 114 atomic_t rx_clk_cnt; 115 atomic_t ana_clk_count; 116 }; 117 118 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800); 119 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 120 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 121 122 struct wcd937x_mbhc_zdet_param { 123 u16 ldo_ctl; 124 u16 noff; 125 u16 nshift; 126 u16 btn5; 127 u16 btn6; 128 u16 btn7; 129 }; 130 131 static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 132 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD937X_ANA_MBHC_MECH, 0x80), 133 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD937X_ANA_MBHC_MECH, 0x40), 134 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD937X_ANA_MBHC_MECH, 0x20), 135 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD937X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 136 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD937X_ANA_MBHC_ELECT, 0x08), 137 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F), 138 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD937X_ANA_MBHC_MECH, 0x04), 139 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD937X_ANA_MBHC_MECH, 0x10), 140 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD937X_ANA_MBHC_MECH, 0x08), 141 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD937X_ANA_MBHC_MECH, 0x01), 142 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD937X_ANA_MBHC_ELECT, 0x06), 143 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD937X_ANA_MBHC_ELECT, 0x80), 144 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD937X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 145 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD937X_MBHC_NEW_CTL_1, 0x03), 146 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD937X_MBHC_NEW_CTL_2, 0x03), 147 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x08), 148 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD937X_ANA_MBHC_RESULT_3, 0x10), 149 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x20), 150 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x80), 151 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x40), 152 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD937X_HPH_OCP_CTL, 0x10), 153 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x07), 154 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD937X_ANA_MBHC_ELECT, 0x70), 155 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0xFF), 156 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD937X_ANA_MICB2, 0xC0), 157 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD937X_HPH_CNP_WG_TIME, 0xFF), 158 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD937X_ANA_HPH, 0x40), 159 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD937X_ANA_HPH, 0x80), 160 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD937X_ANA_HPH, 0xC0), 161 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD937X_ANA_MBHC_RESULT_3, 0x10), 162 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD937X_MBHC_CTL_BCS, 0x02), 163 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD937X_MBHC_NEW_FSM_STATUS, 0x01), 164 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD937X_MBHC_NEW_CTL_2, 0x70), 165 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD937X_MBHC_NEW_FSM_STATUS, 0x20), 166 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD937X_HPH_PA_CTL2, 0x40), 167 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD937X_HPH_PA_CTL2, 0x10), 168 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD937X_HPH_L_TEST, 0x01), 169 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD937X_HPH_R_TEST, 0x01), 170 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD937X_DIGITAL_INTR_STATUS_0, 0x80), 171 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD937X_DIGITAL_INTR_STATUS_0, 0x20), 172 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD937X_MBHC_NEW_CTL_1, 0x08), 173 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD937X_MBHC_NEW_FSM_STATUS, 0x40), 174 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD937X_MBHC_NEW_FSM_STATUS, 0x80), 175 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD937X_MBHC_NEW_ADC_RESULT, 0xFF), 176 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD937X_ANA_MICB2, 0x3F), 177 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD937X_MBHC_NEW_CTL_1, 0x10), 178 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD937X_MBHC_NEW_CTL_1, 0x04), 179 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD937X_ANA_MBHC_ZDET, 0x02), 180 }; 181 182 static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = { 183 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, BIT(0)), 184 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, BIT(1)), 185 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, BIT(2)), 186 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, BIT(3)), 187 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, BIT(4)), 188 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, BIT(5)), 189 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, BIT(6)), 190 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, BIT(7)), 191 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, BIT(0)), 192 REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, BIT(1)), 193 REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, BIT(2)), 194 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, BIT(3)), 195 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, BIT(4)), 196 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, BIT(5)), 197 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, BIT(6)), 198 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, BIT(7)), 199 REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, BIT(0)), 200 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, BIT(1)), 201 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, BIT(2)), 202 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, BIT(3)), 203 }; 204 205 static int wcd937x_handle_post_irq(void *data) 206 { 207 struct wcd937x_priv *wcd937x; 208 209 if (data) 210 wcd937x = (struct wcd937x_priv *)data; 211 else 212 return IRQ_HANDLED; 213 214 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_0, 0); 215 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_1, 0); 216 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_2, 0); 217 218 return IRQ_HANDLED; 219 } 220 221 static const u32 wcd937x_config_regs[] = { 222 WCD937X_DIGITAL_INTR_LEVEL_0, 223 }; 224 225 static const struct regmap_irq_chip wcd937x_regmap_irq_chip = { 226 .name = "wcd937x", 227 .irqs = wcd937x_irqs, 228 .num_irqs = ARRAY_SIZE(wcd937x_irqs), 229 .num_regs = 3, 230 .status_base = WCD937X_DIGITAL_INTR_STATUS_0, 231 .mask_base = WCD937X_DIGITAL_INTR_MASK_0, 232 .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0, 233 .use_ack = 1, 234 .clear_ack = 1, 235 .config_base = wcd937x_config_regs, 236 .num_config_bases = ARRAY_SIZE(wcd937x_config_regs), 237 .num_config_regs = 1, 238 .runtime_pm = true, 239 .handle_post_irq = wcd937x_handle_post_irq, 240 .irq_drv_data = NULL, 241 }; 242 243 static void wcd937x_reset(struct wcd937x_priv *wcd937x) 244 { 245 usleep_range(20, 30); 246 247 gpiod_set_value(wcd937x->reset_gpio, 1); 248 249 usleep_range(20, 30); 250 } 251 252 static void wcd937x_io_init(struct regmap *regmap) 253 { 254 u32 val = 0, temp = 0, temp1 = 0; 255 256 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_29, &val); 257 258 val = val & 0x0F; 259 260 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_16, &temp); 261 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_17, &temp1); 262 263 if (temp == 0x02 || temp1 > 0x09) 264 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x0E, val); 265 else 266 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x0e, 0x0e); 267 268 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x80, 0x80); 269 usleep_range(1000, 1010); 270 271 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x40, 0x40); 272 usleep_range(1000, 1010); 273 274 regmap_update_bits(regmap, WCD937X_LDORXTX_CONFIG, BIT(4), 0x00); 275 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xf0, BIT(7)); 276 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(7), BIT(7)); 277 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(6), BIT(6)); 278 usleep_range(10000, 10010); 279 280 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(6), 0x00); 281 regmap_update_bits(regmap, WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xff, 0xd9); 282 regmap_update_bits(regmap, WCD937X_MICB1_TEST_CTL_1, 0xff, 0xfa); 283 regmap_update_bits(regmap, WCD937X_MICB2_TEST_CTL_1, 0xff, 0xfa); 284 regmap_update_bits(regmap, WCD937X_MICB3_TEST_CTL_1, 0xff, 0xfa); 285 286 regmap_update_bits(regmap, WCD937X_MICB1_TEST_CTL_2, 0x38, 0x00); 287 regmap_update_bits(regmap, WCD937X_MICB2_TEST_CTL_2, 0x38, 0x00); 288 regmap_update_bits(regmap, WCD937X_MICB3_TEST_CTL_2, 0x38, 0x00); 289 290 /* Set Bandgap Fine Adjustment to +5mV for Tanggu SMIC part */ 291 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_16, &val); 292 if (val == 0x01) { 293 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0); 294 } else if (val == 0x02) { 295 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x1F, 0x04); 296 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x1F, 0x04); 297 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0); 298 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL, 0xF0, 0x50); 299 } 300 } 301 302 static int wcd937x_rx_clk_enable(struct snd_soc_component *component) 303 { 304 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 305 306 if (atomic_read(&wcd937x->rx_clk_cnt)) 307 return 0; 308 309 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(3), BIT(3)); 310 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(0), BIT(0)); 311 snd_soc_component_update_bits(component, WCD937X_ANA_RX_SUPPLIES, BIT(0), BIT(0)); 312 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX0_CTL, BIT(6), 0x00); 313 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX1_CTL, BIT(6), 0x00); 314 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX2_CTL, BIT(6), 0x00); 315 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(1), BIT(1)); 316 317 atomic_inc(&wcd937x->rx_clk_cnt); 318 319 return 0; 320 } 321 322 static int wcd937x_rx_clk_disable(struct snd_soc_component *component) 323 { 324 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 325 326 if (!atomic_read(&wcd937x->rx_clk_cnt)) { 327 dev_err(component->dev, "clk already disabled\n"); 328 return 0; 329 } 330 331 atomic_dec(&wcd937x->rx_clk_cnt); 332 333 snd_soc_component_update_bits(component, WCD937X_ANA_RX_SUPPLIES, BIT(0), 0x00); 334 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(1), 0x00); 335 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(0), 0x00); 336 337 return 0; 338 } 339 340 static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 341 struct snd_kcontrol *kcontrol, 342 int event) 343 { 344 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 345 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 346 int hph_mode = wcd937x->hph_mode; 347 348 switch (event) { 349 case SND_SOC_DAPM_PRE_PMU: 350 wcd937x_rx_clk_enable(component); 351 snd_soc_component_update_bits(component, 352 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 353 BIT(0), BIT(0)); 354 snd_soc_component_update_bits(component, 355 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 356 BIT(2), BIT(2)); 357 snd_soc_component_update_bits(component, 358 WCD937X_HPH_RDAC_CLK_CTL1, 359 BIT(7), 0x00); 360 set_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 361 break; 362 case SND_SOC_DAPM_POST_PMU: 363 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 364 snd_soc_component_update_bits(component, 365 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 366 0x0f, BIT(1)); 367 else if (hph_mode == CLS_H_LOHIFI) 368 snd_soc_component_update_bits(component, 369 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 370 0x0f, 0x06); 371 372 if (wcd937x->comp1_enable) { 373 snd_soc_component_update_bits(component, 374 WCD937X_DIGITAL_CDC_COMP_CTL_0, 375 BIT(1), BIT(1)); 376 snd_soc_component_update_bits(component, 377 WCD937X_HPH_L_EN, 378 BIT(5), 0x00); 379 380 if (wcd937x->comp2_enable) { 381 snd_soc_component_update_bits(component, 382 WCD937X_DIGITAL_CDC_COMP_CTL_0, 383 BIT(0), BIT(0)); 384 snd_soc_component_update_bits(component, 385 WCD937X_HPH_R_EN, BIT(5), 0x00); 386 } 387 388 if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) { 389 usleep_range(5000, 5110); 390 clear_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 391 } 392 } else { 393 snd_soc_component_update_bits(component, 394 WCD937X_DIGITAL_CDC_COMP_CTL_0, 395 BIT(1), 0x00); 396 snd_soc_component_update_bits(component, 397 WCD937X_HPH_L_EN, 398 BIT(5), BIT(5)); 399 } 400 401 snd_soc_component_update_bits(component, 402 WCD937X_HPH_NEW_INT_HPH_TIMER1, 403 BIT(1), 0x00); 404 break; 405 case SND_SOC_DAPM_POST_PMD: 406 snd_soc_component_update_bits(component, 407 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 408 0x0f, BIT(0)); 409 break; 410 } 411 412 return 0; 413 } 414 415 static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 416 struct snd_kcontrol *kcontrol, 417 int event) 418 { 419 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 420 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 421 int hph_mode = wcd937x->hph_mode; 422 423 switch (event) { 424 case SND_SOC_DAPM_PRE_PMU: 425 wcd937x_rx_clk_enable(component); 426 snd_soc_component_update_bits(component, 427 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(1), BIT(1)); 428 snd_soc_component_update_bits(component, 429 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, BIT(3), BIT(3)); 430 snd_soc_component_update_bits(component, 431 WCD937X_HPH_RDAC_CLK_CTL1, BIT(7), 0x00); 432 set_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 433 break; 434 case SND_SOC_DAPM_POST_PMU: 435 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 436 snd_soc_component_update_bits(component, 437 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 438 0x0f, BIT(1)); 439 else if (hph_mode == CLS_H_LOHIFI) 440 snd_soc_component_update_bits(component, 441 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 442 0x0f, 0x06); 443 if (wcd937x->comp2_enable) { 444 snd_soc_component_update_bits(component, 445 WCD937X_DIGITAL_CDC_COMP_CTL_0, 446 BIT(0), BIT(0)); 447 snd_soc_component_update_bits(component, 448 WCD937X_HPH_R_EN, BIT(5), 0x00); 449 if (wcd937x->comp1_enable) { 450 snd_soc_component_update_bits(component, 451 WCD937X_DIGITAL_CDC_COMP_CTL_0, 452 BIT(1), BIT(1)); 453 snd_soc_component_update_bits(component, 454 WCD937X_HPH_L_EN, 455 BIT(5), 0x00); 456 } 457 458 if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) { 459 usleep_range(5000, 5110); 460 clear_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 461 } 462 } else { 463 snd_soc_component_update_bits(component, 464 WCD937X_DIGITAL_CDC_COMP_CTL_0, 465 BIT(0), 0x00); 466 snd_soc_component_update_bits(component, 467 WCD937X_HPH_R_EN, 468 BIT(5), BIT(5)); 469 } 470 snd_soc_component_update_bits(component, 471 WCD937X_HPH_NEW_INT_HPH_TIMER1, 472 BIT(1), 0x00); 473 break; 474 case SND_SOC_DAPM_POST_PMD: 475 snd_soc_component_update_bits(component, 476 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 477 0x0f, BIT(0)); 478 break; 479 } 480 481 return 0; 482 } 483 484 static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 485 struct snd_kcontrol *kcontrol, 486 int event) 487 { 488 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 489 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 490 int hph_mode = wcd937x->hph_mode; 491 492 switch (event) { 493 case SND_SOC_DAPM_PRE_PMU: 494 wcd937x_rx_clk_enable(component); 495 snd_soc_component_update_bits(component, 496 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 497 BIT(2), BIT(2)); 498 snd_soc_component_update_bits(component, 499 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 500 BIT(0), BIT(0)); 501 502 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 503 snd_soc_component_update_bits(component, 504 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 505 0x0f, BIT(1)); 506 else if (hph_mode == CLS_H_LOHIFI) 507 snd_soc_component_update_bits(component, 508 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 509 0x0f, 0x06); 510 if (wcd937x->comp1_enable) 511 snd_soc_component_update_bits(component, 512 WCD937X_DIGITAL_CDC_COMP_CTL_0, 513 BIT(1), BIT(1)); 514 usleep_range(5000, 5010); 515 516 snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN, BIT(2), 0x00); 517 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 518 WCD_CLSH_EVENT_PRE_DAC, 519 WCD_CLSH_STATE_EAR, 520 hph_mode); 521 522 break; 523 case SND_SOC_DAPM_POST_PMD: 524 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI || 525 hph_mode == CLS_H_HIFI) 526 snd_soc_component_update_bits(component, 527 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 528 0x0f, BIT(0)); 529 if (wcd937x->comp1_enable) 530 snd_soc_component_update_bits(component, 531 WCD937X_DIGITAL_CDC_COMP_CTL_0, 532 BIT(1), 0x00); 533 break; 534 } 535 536 return 0; 537 } 538 539 static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w, 540 struct snd_kcontrol *kcontrol, 541 int event) 542 { 543 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 544 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 545 int hph_mode = wcd937x->hph_mode; 546 547 switch (event) { 548 case SND_SOC_DAPM_PRE_PMU: 549 wcd937x_rx_clk_enable(component); 550 snd_soc_component_update_bits(component, 551 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 552 BIT(2), BIT(2)); 553 snd_soc_component_update_bits(component, 554 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 555 BIT(2), BIT(2)); 556 snd_soc_component_update_bits(component, 557 WCD937X_DIGITAL_CDC_AUX_GAIN_CTL, 558 BIT(0), BIT(0)); 559 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 560 WCD_CLSH_EVENT_PRE_DAC, 561 WCD_CLSH_STATE_AUX, 562 hph_mode); 563 564 break; 565 case SND_SOC_DAPM_POST_PMD: 566 snd_soc_component_update_bits(component, 567 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 568 BIT(2), 0x00); 569 break; 570 } 571 572 return 0; 573 } 574 575 static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 576 struct snd_kcontrol *kcontrol, 577 int event) 578 { 579 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 580 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 581 int hph_mode = wcd937x->hph_mode; 582 583 switch (event) { 584 case SND_SOC_DAPM_PRE_PMU: 585 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 586 WCD_CLSH_EVENT_PRE_DAC, 587 WCD_CLSH_STATE_HPHR, 588 hph_mode); 589 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 590 BIT(4), BIT(4)); 591 usleep_range(100, 110); 592 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 593 snd_soc_component_update_bits(component, 594 WCD937X_DIGITAL_PDM_WD_CTL1, 595 0x07, 0x03); 596 break; 597 case SND_SOC_DAPM_POST_PMU: 598 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 599 if (wcd937x->comp2_enable) 600 usleep_range(7000, 7100); 601 else 602 usleep_range(20000, 20100); 603 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 604 } 605 606 snd_soc_component_update_bits(component, 607 WCD937X_HPH_NEW_INT_HPH_TIMER1, 608 BIT(1), BIT(1)); 609 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 610 snd_soc_component_update_bits(component, 611 WCD937X_ANA_RX_SUPPLIES, 612 BIT(1), BIT(1)); 613 enable_irq(wcd937x->hphr_pdm_wd_int); 614 break; 615 case SND_SOC_DAPM_PRE_PMD: 616 disable_irq_nosync(wcd937x->hphr_pdm_wd_int); 617 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 618 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_PRE_HPHR_PA_OFF); 619 break; 620 case SND_SOC_DAPM_POST_PMD: 621 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 622 if (wcd937x->comp2_enable) 623 usleep_range(7000, 7100); 624 else 625 usleep_range(20000, 20100); 626 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 627 } 628 629 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_POST_HPHR_PA_OFF); 630 snd_soc_component_update_bits(component, 631 WCD937X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00); 632 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 633 BIT(4), 0x00); 634 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 635 WCD_CLSH_EVENT_POST_PA, 636 WCD_CLSH_STATE_HPHR, 637 hph_mode); 638 break; 639 } 640 641 return 0; 642 } 643 644 static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 645 struct snd_kcontrol *kcontrol, 646 int event) 647 { 648 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 649 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 650 int hph_mode = wcd937x->hph_mode; 651 652 switch (event) { 653 case SND_SOC_DAPM_PRE_PMU: 654 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 655 WCD_CLSH_EVENT_PRE_DAC, 656 WCD_CLSH_STATE_HPHL, 657 hph_mode); 658 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 659 BIT(5), BIT(5)); 660 usleep_range(100, 110); 661 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 662 snd_soc_component_update_bits(component, 663 WCD937X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03); 664 break; 665 case SND_SOC_DAPM_POST_PMU: 666 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 667 if (!wcd937x->comp1_enable) 668 usleep_range(20000, 20100); 669 else 670 usleep_range(7000, 7100); 671 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 672 } 673 674 snd_soc_component_update_bits(component, 675 WCD937X_HPH_NEW_INT_HPH_TIMER1, 676 BIT(1), BIT(1)); 677 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 678 snd_soc_component_update_bits(component, 679 WCD937X_ANA_RX_SUPPLIES, 680 BIT(1), BIT(1)); 681 enable_irq(wcd937x->hphl_pdm_wd_int); 682 break; 683 case SND_SOC_DAPM_PRE_PMD: 684 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 685 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 686 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF); 687 break; 688 case SND_SOC_DAPM_POST_PMD: 689 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 690 if (!wcd937x->comp1_enable) 691 usleep_range(20000, 20100); 692 else 693 usleep_range(7000, 7100); 694 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 695 } 696 697 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 698 snd_soc_component_update_bits(component, 699 WCD937X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00); 700 snd_soc_component_update_bits(component, 701 WCD937X_ANA_HPH, BIT(5), 0x00); 702 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 703 WCD_CLSH_EVENT_POST_PA, 704 WCD_CLSH_STATE_HPHL, 705 hph_mode); 706 break; 707 } 708 709 return 0; 710 } 711 712 static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w, 713 struct snd_kcontrol *kcontrol, 714 int event) 715 { 716 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 717 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 718 int hph_mode = wcd937x->hph_mode; 719 720 switch (event) { 721 case SND_SOC_DAPM_PRE_PMU: 722 snd_soc_component_update_bits(component, 723 WCD937X_DIGITAL_PDM_WD_CTL2, 724 BIT(0), BIT(0)); 725 break; 726 case SND_SOC_DAPM_POST_PMU: 727 usleep_range(1000, 1010); 728 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 729 snd_soc_component_update_bits(component, 730 WCD937X_ANA_RX_SUPPLIES, 731 BIT(1), BIT(1)); 732 enable_irq(wcd937x->aux_pdm_wd_int); 733 break; 734 case SND_SOC_DAPM_PRE_PMD: 735 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 736 break; 737 case SND_SOC_DAPM_POST_PMD: 738 usleep_range(2000, 2010); 739 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 740 WCD_CLSH_EVENT_POST_PA, 741 WCD_CLSH_STATE_AUX, 742 hph_mode); 743 snd_soc_component_update_bits(component, 744 WCD937X_DIGITAL_PDM_WD_CTL2, 745 BIT(0), 0x00); 746 break; 747 } 748 749 return 0; 750 } 751 752 static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 753 struct snd_kcontrol *kcontrol, 754 int event) 755 { 756 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 757 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 758 int hph_mode = wcd937x->hph_mode; 759 760 switch (event) { 761 case SND_SOC_DAPM_PRE_PMU: 762 /* Enable watchdog interrupt for HPHL or AUX depending on mux value */ 763 wcd937x->ear_rx_path = snd_soc_component_read(component, 764 WCD937X_DIGITAL_CDC_EAR_PATH_CTL); 765 766 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 767 snd_soc_component_update_bits(component, 768 WCD937X_DIGITAL_PDM_WD_CTL2, 769 BIT(0), BIT(0)); 770 else 771 snd_soc_component_update_bits(component, 772 WCD937X_DIGITAL_PDM_WD_CTL0, 773 0x07, 0x03); 774 if (!wcd937x->comp1_enable) 775 snd_soc_component_update_bits(component, 776 WCD937X_ANA_EAR_COMPANDER_CTL, 777 BIT(7), BIT(7)); 778 break; 779 case SND_SOC_DAPM_POST_PMU: 780 usleep_range(6000, 6010); 781 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 782 snd_soc_component_update_bits(component, 783 WCD937X_ANA_RX_SUPPLIES, 784 BIT(1), BIT(1)); 785 786 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 787 enable_irq(wcd937x->aux_pdm_wd_int); 788 else 789 enable_irq(wcd937x->hphl_pdm_wd_int); 790 break; 791 case SND_SOC_DAPM_PRE_PMD: 792 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 793 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 794 else 795 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 796 break; 797 case SND_SOC_DAPM_POST_PMD: 798 if (!wcd937x->comp1_enable) 799 snd_soc_component_update_bits(component, 800 WCD937X_ANA_EAR_COMPANDER_CTL, 801 BIT(7), 0x00); 802 usleep_range(7000, 7010); 803 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 804 WCD_CLSH_EVENT_POST_PA, 805 WCD_CLSH_STATE_EAR, 806 hph_mode); 807 snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN, 808 BIT(2), BIT(2)); 809 810 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 811 snd_soc_component_update_bits(component, 812 WCD937X_DIGITAL_PDM_WD_CTL2, 813 BIT(0), 0x00); 814 else 815 snd_soc_component_update_bits(component, 816 WCD937X_DIGITAL_PDM_WD_CTL0, 817 0x07, 0x00); 818 break; 819 } 820 821 return 0; 822 } 823 824 static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w, 825 struct snd_kcontrol *kcontrol, 826 int event) 827 { 828 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 829 830 if (event == SND_SOC_DAPM_POST_PMD) { 831 wcd937x_rx_clk_disable(component); 832 snd_soc_component_update_bits(component, 833 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 834 BIT(0), 0x00); 835 } 836 837 return 0; 838 } 839 840 static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w, 841 struct snd_kcontrol *kcontrol, int event) 842 { 843 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 844 845 if (event == SND_SOC_DAPM_POST_PMD) { 846 wcd937x_rx_clk_disable(component); 847 snd_soc_component_update_bits(component, 848 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 849 BIT(1), 0x00); 850 } 851 852 return 0; 853 } 854 855 static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w, 856 struct snd_kcontrol *kcontrol, 857 int event) 858 { 859 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 860 861 if (event == SND_SOC_DAPM_POST_PMD) { 862 usleep_range(6000, 6010); 863 wcd937x_rx_clk_disable(component); 864 snd_soc_component_update_bits(component, 865 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 866 BIT(2), 0x00); 867 } 868 869 return 0; 870 } 871 872 static int wcd937x_get_micb_vout_ctl_val(u32 micb_mv) 873 { 874 if (micb_mv < 1000 || micb_mv > 2850) { 875 pr_err("Unsupported micbias voltage (%u mV)\n", micb_mv); 876 return -EINVAL; 877 } 878 879 return (micb_mv - 1000) / 50; 880 } 881 882 static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w, 883 struct snd_kcontrol *kcontrol, int event) 884 { 885 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 886 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 887 bool use_amic3 = snd_soc_component_read(component, WCD937X_TX_NEW_TX_CH2_SEL) & BIT(7); 888 889 /* Enable BCS for Headset mic */ 890 if (event == SND_SOC_DAPM_PRE_PMU && strnstr(w->name, "ADC", sizeof("ADC"))) 891 if (w->shift == 1 && !use_amic3) 892 set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask); 893 894 return 0; 895 } 896 897 static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w, 898 struct snd_kcontrol *kcontrol, int event) 899 { 900 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 901 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 902 903 switch (event) { 904 case SND_SOC_DAPM_PRE_PMU: 905 atomic_inc(&wcd937x->ana_clk_count); 906 snd_soc_component_update_bits(component, 907 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(7), BIT(7)); 908 snd_soc_component_update_bits(component, 909 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(3), BIT(3)); 910 snd_soc_component_update_bits(component, 911 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(4), BIT(4)); 912 break; 913 case SND_SOC_DAPM_POST_PMD: 914 if (w->shift == 1 && test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) 915 clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask); 916 917 snd_soc_component_update_bits(component, 918 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(3), 0x00); 919 break; 920 } 921 922 return 0; 923 } 924 925 static int wcd937x_enable_req(struct snd_soc_dapm_widget *w, 926 struct snd_kcontrol *kcontrol, int event) 927 { 928 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 929 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 930 931 switch (event) { 932 case SND_SOC_DAPM_PRE_PMU: 933 snd_soc_component_update_bits(component, 934 WCD937X_DIGITAL_CDC_REQ_CTL, BIT(1), BIT(1)); 935 snd_soc_component_update_bits(component, 936 WCD937X_DIGITAL_CDC_REQ_CTL, BIT(0), 0x00); 937 snd_soc_component_update_bits(component, 938 WCD937X_ANA_TX_CH2, BIT(6), BIT(6)); 939 snd_soc_component_update_bits(component, 940 WCD937X_ANA_TX_CH3_HPF, BIT(6), BIT(6)); 941 snd_soc_component_update_bits(component, 942 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70); 943 snd_soc_component_update_bits(component, 944 WCD937X_ANA_TX_CH1, BIT(7), BIT(7)); 945 snd_soc_component_update_bits(component, 946 WCD937X_ANA_TX_CH2, BIT(6), 0x00); 947 snd_soc_component_update_bits(component, 948 WCD937X_ANA_TX_CH2, BIT(7), BIT(7)); 949 snd_soc_component_update_bits(component, 950 WCD937X_ANA_TX_CH3, BIT(7), BIT(7)); 951 break; 952 case SND_SOC_DAPM_POST_PMD: 953 snd_soc_component_update_bits(component, 954 WCD937X_ANA_TX_CH1, BIT(7), 0x00); 955 snd_soc_component_update_bits(component, 956 WCD937X_ANA_TX_CH2, BIT(7), 0x00); 957 snd_soc_component_update_bits(component, 958 WCD937X_ANA_TX_CH3, BIT(7), 0x00); 959 snd_soc_component_update_bits(component, 960 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(4), 0x00); 961 962 atomic_dec(&wcd937x->ana_clk_count); 963 if (atomic_read(&wcd937x->ana_clk_count) <= 0) { 964 snd_soc_component_update_bits(component, 965 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 966 BIT(4), 0x00); 967 atomic_set(&wcd937x->ana_clk_count, 0); 968 } 969 970 snd_soc_component_update_bits(component, 971 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 972 BIT(7), 0x00); 973 break; 974 } 975 976 return 0; 977 } 978 979 static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 980 struct snd_kcontrol *kcontrol, 981 int event) 982 { 983 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 984 u16 dmic_clk_reg; 985 986 switch (w->shift) { 987 case 0: 988 case 1: 989 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL; 990 break; 991 case 2: 992 case 3: 993 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL; 994 break; 995 case 4: 996 case 5: 997 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL; 998 break; 999 default: 1000 dev_err(component->dev, "Invalid DMIC Selection\n"); 1001 return -EINVAL; 1002 } 1003 1004 switch (event) { 1005 case SND_SOC_DAPM_PRE_PMU: 1006 snd_soc_component_update_bits(component, 1007 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 1008 BIT(7), BIT(7)); 1009 snd_soc_component_update_bits(component, 1010 dmic_clk_reg, 0x07, BIT(1)); 1011 snd_soc_component_update_bits(component, 1012 dmic_clk_reg, BIT(3), BIT(3)); 1013 snd_soc_component_update_bits(component, 1014 dmic_clk_reg, 0x70, BIT(5)); 1015 break; 1016 } 1017 1018 return 0; 1019 } 1020 1021 static int wcd937x_micbias_control(struct snd_soc_component *component, 1022 int micb_num, int req, bool is_dapm) 1023 { 1024 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1025 int micb_index = micb_num - 1; 1026 u16 micb_reg; 1027 1028 if (micb_index < 0 || (micb_index > WCD937X_MAX_MICBIAS - 1)) { 1029 dev_err(component->dev, "Invalid micbias index, micb_ind:%d\n", micb_index); 1030 return -EINVAL; 1031 } 1032 switch (micb_num) { 1033 case MIC_BIAS_1: 1034 micb_reg = WCD937X_ANA_MICB1; 1035 break; 1036 case MIC_BIAS_2: 1037 micb_reg = WCD937X_ANA_MICB2; 1038 break; 1039 case MIC_BIAS_3: 1040 micb_reg = WCD937X_ANA_MICB3; 1041 break; 1042 default: 1043 dev_err(component->dev, "Invalid micbias number: %d\n", micb_num); 1044 return -EINVAL; 1045 } 1046 1047 mutex_lock(&wcd937x->micb_lock); 1048 switch (req) { 1049 case MICB_PULLUP_ENABLE: 1050 wcd937x->pullup_ref[micb_index]++; 1051 if (wcd937x->pullup_ref[micb_index] == 1 && 1052 wcd937x->micb_ref[micb_index] == 0) 1053 snd_soc_component_update_bits(component, micb_reg, 1054 0xc0, BIT(7)); 1055 break; 1056 case MICB_PULLUP_DISABLE: 1057 if (wcd937x->pullup_ref[micb_index] > 0) 1058 wcd937x->pullup_ref[micb_index]++; 1059 if (wcd937x->pullup_ref[micb_index] == 0 && 1060 wcd937x->micb_ref[micb_index] == 0) 1061 snd_soc_component_update_bits(component, micb_reg, 1062 0xc0, 0x00); 1063 break; 1064 case MICB_ENABLE: 1065 wcd937x->micb_ref[micb_index]++; 1066 atomic_inc(&wcd937x->ana_clk_count); 1067 if (wcd937x->micb_ref[micb_index] == 1) { 1068 snd_soc_component_update_bits(component, 1069 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 1070 0xf0, 0xf0); 1071 snd_soc_component_update_bits(component, 1072 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 1073 BIT(4), BIT(4)); 1074 snd_soc_component_update_bits(component, 1075 WCD937X_MICB1_TEST_CTL_2, 1076 BIT(0), BIT(0)); 1077 snd_soc_component_update_bits(component, 1078 WCD937X_MICB2_TEST_CTL_2, 1079 BIT(0), BIT(0)); 1080 snd_soc_component_update_bits(component, 1081 WCD937X_MICB3_TEST_CTL_2, 1082 BIT(0), BIT(0)); 1083 snd_soc_component_update_bits(component, 1084 micb_reg, 0xc0, BIT(6)); 1085 1086 if (micb_num == MIC_BIAS_2) 1087 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1088 WCD_EVENT_POST_MICBIAS_2_ON); 1089 1090 if (micb_num == MIC_BIAS_2 && is_dapm) 1091 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1092 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 1093 } 1094 break; 1095 case MICB_DISABLE: 1096 atomic_dec(&wcd937x->ana_clk_count); 1097 if (wcd937x->micb_ref[micb_index] > 0) 1098 wcd937x->micb_ref[micb_index]--; 1099 if (wcd937x->micb_ref[micb_index] == 0 && 1100 wcd937x->pullup_ref[micb_index] > 0) 1101 snd_soc_component_update_bits(component, micb_reg, 1102 0xc0, BIT(7)); 1103 else if (wcd937x->micb_ref[micb_index] == 0 && 1104 wcd937x->pullup_ref[micb_index] == 0) { 1105 if (micb_num == MIC_BIAS_2) 1106 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1107 WCD_EVENT_PRE_MICBIAS_2_OFF); 1108 1109 snd_soc_component_update_bits(component, micb_reg, 1110 0xc0, 0x00); 1111 if (micb_num == MIC_BIAS_2) 1112 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1113 WCD_EVENT_POST_MICBIAS_2_OFF); 1114 } 1115 1116 if (is_dapm && micb_num == MIC_BIAS_2) 1117 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1118 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 1119 if (atomic_read(&wcd937x->ana_clk_count) <= 0) { 1120 snd_soc_component_update_bits(component, 1121 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 1122 BIT(4), 0x00); 1123 atomic_set(&wcd937x->ana_clk_count, 0); 1124 } 1125 break; 1126 } 1127 mutex_unlock(&wcd937x->micb_lock); 1128 1129 return 0; 1130 } 1131 1132 static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1133 int event) 1134 { 1135 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1136 int micb_num = w->shift; 1137 1138 switch (event) { 1139 case SND_SOC_DAPM_PRE_PMU: 1140 wcd937x_micbias_control(component, micb_num, 1141 MICB_ENABLE, true); 1142 break; 1143 case SND_SOC_DAPM_POST_PMU: 1144 usleep_range(1000, 1100); 1145 break; 1146 case SND_SOC_DAPM_POST_PMD: 1147 wcd937x_micbias_control(component, micb_num, 1148 MICB_DISABLE, true); 1149 break; 1150 } 1151 1152 return 0; 1153 } 1154 1155 static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1156 struct snd_kcontrol *kcontrol, 1157 int event) 1158 { 1159 return __wcd937x_codec_enable_micbias(w, event); 1160 } 1161 1162 static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1163 int event) 1164 { 1165 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1166 int micb_num = w->shift; 1167 1168 switch (event) { 1169 case SND_SOC_DAPM_PRE_PMU: 1170 wcd937x_micbias_control(component, micb_num, MICB_PULLUP_ENABLE, true); 1171 break; 1172 case SND_SOC_DAPM_POST_PMU: 1173 usleep_range(1000, 1100); 1174 break; 1175 case SND_SOC_DAPM_POST_PMD: 1176 wcd937x_micbias_control(component, micb_num, MICB_PULLUP_DISABLE, true); 1177 break; 1178 } 1179 1180 return 0; 1181 } 1182 1183 static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1184 struct snd_kcontrol *kcontrol, 1185 int event) 1186 { 1187 return __wcd937x_codec_enable_micbias_pullup(w, event); 1188 } 1189 1190 static int wcd937x_connect_port(struct wcd937x_sdw_priv *wcd, u8 port_idx, u8 ch_id, bool enable) 1191 { 1192 struct sdw_port_config *port_config = &wcd->port_config[port_idx - 1]; 1193 const struct wcd937x_sdw_ch_info *ch_info = &wcd->ch_info[ch_id]; 1194 u8 port_num = ch_info->port_num; 1195 u8 ch_mask = ch_info->ch_mask; 1196 1197 port_config->num = port_num; 1198 1199 if (enable) 1200 port_config->ch_mask |= ch_mask; 1201 else 1202 port_config->ch_mask &= ~ch_mask; 1203 1204 return 0; 1205 } 1206 1207 static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol, 1208 struct snd_ctl_elem_value *ucontrol) 1209 { 1210 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1211 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1212 1213 ucontrol->value.integer.value[0] = wcd937x->hph_mode; 1214 return 0; 1215 } 1216 1217 static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol, 1218 struct snd_ctl_elem_value *ucontrol) 1219 { 1220 struct snd_soc_component *component = 1221 snd_soc_kcontrol_component(kcontrol); 1222 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1223 u32 mode_val; 1224 1225 mode_val = ucontrol->value.enumerated.item[0]; 1226 1227 if (!mode_val) 1228 mode_val = CLS_AB; 1229 1230 if (mode_val == wcd937x->hph_mode) 1231 return 0; 1232 1233 switch (mode_val) { 1234 case CLS_H_NORMAL: 1235 case CLS_H_HIFI: 1236 case CLS_H_LP: 1237 case CLS_AB: 1238 case CLS_H_LOHIFI: 1239 case CLS_H_ULP: 1240 case CLS_AB_LP: 1241 case CLS_AB_HIFI: 1242 wcd937x->hph_mode = mode_val; 1243 return 1; 1244 } 1245 1246 dev_dbg(component->dev, "%s: Invalid HPH Mode\n", __func__); 1247 return -EINVAL; 1248 } 1249 1250 static int wcd937x_get_compander(struct snd_kcontrol *kcontrol, 1251 struct snd_ctl_elem_value *ucontrol) 1252 { 1253 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1254 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1255 struct soc_mixer_control *mc; 1256 bool hphr; 1257 1258 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1259 hphr = mc->shift; 1260 1261 ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable : 1262 wcd937x->comp1_enable; 1263 return 0; 1264 } 1265 1266 static int wcd937x_set_compander(struct snd_kcontrol *kcontrol, 1267 struct snd_ctl_elem_value *ucontrol) 1268 { 1269 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1270 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1271 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[AIF1_PB]; 1272 int value = ucontrol->value.integer.value[0]; 1273 struct soc_mixer_control *mc; 1274 int portidx; 1275 bool hphr; 1276 1277 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1278 hphr = mc->shift; 1279 1280 if (hphr) { 1281 if (value == wcd937x->comp2_enable) 1282 return 0; 1283 1284 wcd937x->comp2_enable = value; 1285 } else { 1286 if (value == wcd937x->comp1_enable) 1287 return 0; 1288 1289 wcd937x->comp1_enable = value; 1290 } 1291 1292 portidx = wcd->ch_info[mc->reg].port_num; 1293 1294 if (value) 1295 wcd937x_connect_port(wcd, portidx, mc->reg, true); 1296 else 1297 wcd937x_connect_port(wcd, portidx, mc->reg, false); 1298 1299 return 1; 1300 } 1301 1302 static int wcd937x_get_swr_port(struct snd_kcontrol *kcontrol, 1303 struct snd_ctl_elem_value *ucontrol) 1304 { 1305 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1306 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 1307 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(comp); 1308 struct wcd937x_sdw_priv *wcd; 1309 int dai_id = mixer->shift; 1310 int ch_idx = mixer->reg; 1311 int portidx; 1312 1313 wcd = wcd937x->sdw_priv[dai_id]; 1314 portidx = wcd->ch_info[ch_idx].port_num; 1315 1316 ucontrol->value.integer.value[0] = wcd->port_enable[portidx]; 1317 1318 return 0; 1319 } 1320 1321 static int wcd937x_set_swr_port(struct snd_kcontrol *kcontrol, 1322 struct snd_ctl_elem_value *ucontrol) 1323 { 1324 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1325 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 1326 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(comp); 1327 struct wcd937x_sdw_priv *wcd; 1328 int dai_id = mixer->shift; 1329 int ch_idx = mixer->reg; 1330 int portidx; 1331 bool enable; 1332 1333 wcd = wcd937x->sdw_priv[dai_id]; 1334 1335 portidx = wcd->ch_info[ch_idx].port_num; 1336 1337 enable = ucontrol->value.integer.value[0]; 1338 1339 if (enable == wcd->port_enable[portidx]) { 1340 wcd937x_connect_port(wcd, portidx, ch_idx, enable); 1341 return 0; 1342 } 1343 1344 wcd->port_enable[portidx] = enable; 1345 wcd937x_connect_port(wcd, portidx, ch_idx, enable); 1346 1347 return 1; 1348 } 1349 1350 static const char * const rx_hph_mode_mux_text[] = { 1351 "CLS_H_NORMAL", "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", 1352 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_AB_LP", "CLS_AB_HIFI", 1353 }; 1354 1355 static const struct soc_enum rx_hph_mode_mux_enum = 1356 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), rx_hph_mode_mux_text); 1357 1358 /* MBHC related */ 1359 static void wcd937x_mbhc_clk_setup(struct snd_soc_component *component, 1360 bool enable) 1361 { 1362 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_1, 1363 WCD937X_MBHC_CTL_RCO_EN_MASK, enable); 1364 } 1365 1366 static void wcd937x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 1367 bool enable) 1368 { 1369 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_ELECT, 1370 WCD937X_ANA_MBHC_BIAS_EN, enable); 1371 } 1372 1373 static void wcd937x_mbhc_program_btn_thr(struct snd_soc_component *component, 1374 int *btn_low, int *btn_high, 1375 int num_btn, bool is_micbias) 1376 { 1377 int i, vth; 1378 1379 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 1380 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 1381 __func__, num_btn); 1382 return; 1383 } 1384 1385 for (i = 0; i < num_btn; i++) { 1386 vth = ((btn_high[i] * 2) / 25) & 0x3F; 1387 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_BTN0 + i, 1388 WCD937X_MBHC_BTN_VTH_MASK, vth); 1389 } 1390 } 1391 1392 static bool wcd937x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 1393 { 1394 u8 val; 1395 1396 if (micb_num == MIC_BIAS_2) { 1397 val = snd_soc_component_read_field(component, 1398 WCD937X_ANA_MICB2, 1399 WCD937X_ANA_MICB2_ENABLE_MASK); 1400 if (val == WCD937X_MICB_ENABLE) 1401 return true; 1402 } 1403 return false; 1404 } 1405 1406 static void wcd937x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 1407 int pull_up_cur) 1408 { 1409 /* Default pull up current to 2uA */ 1410 if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA) 1411 pull_up_cur = HS_PULLUP_I_2P0_UA; 1412 1413 snd_soc_component_write_field(component, 1414 WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT, 1415 WCD937X_HSDET_PULLUP_C_MASK, pull_up_cur); 1416 } 1417 1418 static int wcd937x_mbhc_request_micbias(struct snd_soc_component *component, 1419 int micb_num, int req) 1420 { 1421 return wcd937x_micbias_control(component, micb_num, req, false); 1422 } 1423 1424 static void wcd937x_mbhc_micb_ramp_control(struct snd_soc_component *component, 1425 bool enable) 1426 { 1427 if (enable) { 1428 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1429 WCD937X_RAMP_SHIFT_CTRL_MASK, 0x0C); 1430 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1431 WCD937X_RAMP_EN_MASK, 1); 1432 } else { 1433 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1434 WCD937X_RAMP_EN_MASK, 0); 1435 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1436 WCD937X_RAMP_SHIFT_CTRL_MASK, 0); 1437 } 1438 } 1439 1440 static int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 1441 int req_volt, int micb_num) 1442 { 1443 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1444 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0; 1445 1446 switch (micb_num) { 1447 case MIC_BIAS_1: 1448 micb_reg = WCD937X_ANA_MICB1; 1449 break; 1450 case MIC_BIAS_2: 1451 micb_reg = WCD937X_ANA_MICB2; 1452 break; 1453 case MIC_BIAS_3: 1454 micb_reg = WCD937X_ANA_MICB3; 1455 break; 1456 default: 1457 return -EINVAL; 1458 } 1459 mutex_lock(&wcd937x->micb_lock); 1460 /* 1461 * If requested micbias voltage is same as current micbias 1462 * voltage, then just return. Otherwise, adjust voltage as 1463 * per requested value. If micbias is already enabled, then 1464 * to avoid slow micbias ramp-up or down enable pull-up 1465 * momentarily, change the micbias value and then re-enable 1466 * micbias. 1467 */ 1468 micb_en = snd_soc_component_read_field(component, micb_reg, 1469 WCD937X_MICB_EN_MASK); 1470 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 1471 WCD937X_MICB_VOUT_MASK); 1472 1473 req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt); 1474 if (req_vout_ctl < 0) { 1475 ret = -EINVAL; 1476 goto exit; 1477 } 1478 1479 if (cur_vout_ctl == req_vout_ctl) { 1480 ret = 0; 1481 goto exit; 1482 } 1483 1484 if (micb_en == WCD937X_MICB_ENABLE) 1485 snd_soc_component_write_field(component, micb_reg, 1486 WCD937X_MICB_EN_MASK, 1487 WCD937X_MICB_PULL_UP); 1488 1489 snd_soc_component_write_field(component, micb_reg, 1490 WCD937X_MICB_VOUT_MASK, 1491 req_vout_ctl); 1492 1493 if (micb_en == WCD937X_MICB_ENABLE) { 1494 snd_soc_component_write_field(component, micb_reg, 1495 WCD937X_MICB_EN_MASK, 1496 WCD937X_MICB_ENABLE); 1497 /* 1498 * Add 2ms delay as per HW requirement after enabling 1499 * micbias 1500 */ 1501 usleep_range(2000, 2100); 1502 } 1503 exit: 1504 mutex_unlock(&wcd937x->micb_lock); 1505 return ret; 1506 } 1507 1508 static int wcd937x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 1509 int micb_num, bool req_en) 1510 { 1511 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1512 int micb_mv; 1513 1514 if (micb_num != MIC_BIAS_2) 1515 return -EINVAL; 1516 /* 1517 * If device tree micbias level is already above the minimum 1518 * voltage needed to detect threshold microphone, then do 1519 * not change the micbias, just return. 1520 */ 1521 if (wcd937x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV) 1522 return 0; 1523 1524 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd937x->micb2_mv; 1525 1526 return wcd937x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 1527 } 1528 1529 static void wcd937x_mbhc_get_result_params(struct snd_soc_component *component, 1530 s16 *d1_a, u16 noff, 1531 int32_t *zdet) 1532 { 1533 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1534 int i; 1535 int val, val1; 1536 s16 c1; 1537 s32 x1, d1; 1538 s32 denom; 1539 static const int minCode_param[] = { 1540 3277, 1639, 820, 410, 205, 103, 52, 26 1541 }; 1542 1543 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MBHC_ZDET, 0x20, 0x20); 1544 for (i = 0; i < WCD937X_ZDET_NUM_MEASUREMENTS; i++) { 1545 regmap_read(wcd937x->regmap, WCD937X_ANA_MBHC_RESULT_2, &val); 1546 if (val & 0x80) 1547 break; 1548 } 1549 val = val << 0x8; 1550 regmap_read(wcd937x->regmap, WCD937X_ANA_MBHC_RESULT_1, &val1); 1551 val |= val1; 1552 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MBHC_ZDET, 0x20, 0x00); 1553 x1 = WCD937X_MBHC_GET_X1(val); 1554 c1 = WCD937X_MBHC_GET_C1(val); 1555 /* If ramp is not complete, give additional 5ms */ 1556 if (c1 < 2 && x1) 1557 usleep_range(5000, 5050); 1558 1559 if (!c1 || !x1) { 1560 dev_err(component->dev, "Impedance detect ramp error, c1=%d, x1=0x%x\n", 1561 c1, x1); 1562 goto ramp_down; 1563 } 1564 d1 = d1_a[c1]; 1565 denom = (x1 * d1) - (1 << (14 - noff)); 1566 if (denom > 0) 1567 *zdet = (WCD937X_MBHC_ZDET_CONST * 1000) / denom; 1568 else if (x1 < minCode_param[noff]) 1569 *zdet = WCD937X_ZDET_FLOATING_IMPEDANCE; 1570 1571 dev_err(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d (milliohm)\n", 1572 __func__, d1, c1, x1, *zdet); 1573 ramp_down: 1574 i = 0; 1575 while (x1) { 1576 regmap_read(wcd937x->regmap, 1577 WCD937X_ANA_MBHC_RESULT_1, &val); 1578 regmap_read(wcd937x->regmap, 1579 WCD937X_ANA_MBHC_RESULT_2, &val1); 1580 val = val << 0x08; 1581 val |= val1; 1582 x1 = WCD937X_MBHC_GET_X1(val); 1583 i++; 1584 if (i == WCD937X_ZDET_NUM_MEASUREMENTS) 1585 break; 1586 } 1587 } 1588 1589 static void wcd937x_mbhc_zdet_ramp(struct snd_soc_component *component, 1590 struct wcd937x_mbhc_zdet_param *zdet_param, 1591 s32 *zl, s32 *zr, s16 *d1_a) 1592 { 1593 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1594 s32 zdet = 0; 1595 1596 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, 1597 WCD937X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 1598 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN5, 1599 WCD937X_VTH_MASK, zdet_param->btn5); 1600 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN6, 1601 WCD937X_VTH_MASK, zdet_param->btn6); 1602 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN7, 1603 WCD937X_VTH_MASK, zdet_param->btn7); 1604 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, 1605 WCD937X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 1606 snd_soc_component_update_bits(component, WCD937X_MBHC_NEW_ZDET_RAMP_CTL, 1607 0x0F, zdet_param->nshift); 1608 1609 if (!zl) 1610 goto z_right; 1611 /* Start impedance measurement for HPH_L */ 1612 regmap_update_bits(wcd937x->regmap, 1613 WCD937X_ANA_MBHC_ZDET, 0x80, 0x80); 1614 wcd937x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 1615 regmap_update_bits(wcd937x->regmap, 1616 WCD937X_ANA_MBHC_ZDET, 0x80, 0x00); 1617 1618 *zl = zdet; 1619 1620 z_right: 1621 if (!zr) 1622 return; 1623 /* Start impedance measurement for HPH_R */ 1624 regmap_update_bits(wcd937x->regmap, 1625 WCD937X_ANA_MBHC_ZDET, 0x40, 0x40); 1626 wcd937x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 1627 regmap_update_bits(wcd937x->regmap, 1628 WCD937X_ANA_MBHC_ZDET, 0x40, 0x00); 1629 1630 *zr = zdet; 1631 } 1632 1633 static void wcd937x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 1634 s32 *z_val, int flag_l_r) 1635 { 1636 s16 q1; 1637 int q1_cal; 1638 1639 if (*z_val < (WCD937X_ZDET_VAL_400 / 1000)) 1640 q1 = snd_soc_component_read(component, 1641 WCD937X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r)); 1642 else 1643 q1 = snd_soc_component_read(component, 1644 WCD937X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r)); 1645 if (q1 & 0x80) 1646 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 1647 else 1648 q1_cal = (10000 + (q1 * 25)); 1649 if (q1_cal > 0) 1650 *z_val = ((*z_val) * 10000) / q1_cal; 1651 } 1652 1653 static void wcd937x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 1654 u32 *zl, u32 *zr) 1655 { 1656 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1657 s16 reg0, reg1, reg2, reg3, reg4; 1658 s32 z1l, z1r, z1ls; 1659 int zMono, z_diff1, z_diff2; 1660 bool is_fsm_disable = false; 1661 struct wcd937x_mbhc_zdet_param zdet_param[] = { 1662 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 1663 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 1664 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 1665 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 1666 }; 1667 struct wcd937x_mbhc_zdet_param *zdet_param_ptr = NULL; 1668 s16 d1_a[][4] = { 1669 {0, 30, 90, 30}, 1670 {0, 30, 30, 5}, 1671 {0, 30, 30, 5}, 1672 {0, 30, 30, 5}, 1673 }; 1674 s16 *d1 = NULL; 1675 1676 reg0 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN5); 1677 reg1 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN6); 1678 reg2 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN7); 1679 reg3 = snd_soc_component_read(component, WCD937X_MBHC_CTL_CLK); 1680 reg4 = snd_soc_component_read(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL); 1681 1682 if (snd_soc_component_read(component, WCD937X_ANA_MBHC_ELECT) & 0x80) { 1683 is_fsm_disable = true; 1684 regmap_update_bits(wcd937x->regmap, 1685 WCD937X_ANA_MBHC_ELECT, 0x80, 0x00); 1686 } 1687 1688 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 1689 if (wcd937x->mbhc_cfg.hphl_swh) 1690 regmap_update_bits(wcd937x->regmap, 1691 WCD937X_ANA_MBHC_MECH, 0x80, 0x00); 1692 1693 /* Turn off 100k pull down on HPHL */ 1694 regmap_update_bits(wcd937x->regmap, 1695 WCD937X_ANA_MBHC_MECH, 0x01, 0x00); 1696 1697 /* Disable surge protection before impedance detection. 1698 * This is done to give correct value for high impedance. 1699 */ 1700 regmap_update_bits(wcd937x->regmap, 1701 WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00); 1702 /* 1ms delay needed after disable surge protection */ 1703 usleep_range(1000, 1010); 1704 1705 /* First get impedance on Left */ 1706 d1 = d1_a[1]; 1707 zdet_param_ptr = &zdet_param[1]; 1708 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1l, NULL, d1); 1709 1710 if (!WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z1l)) 1711 goto left_ch_impedance; 1712 1713 /* Second ramp for left ch */ 1714 if (z1l < WCD937X_ZDET_VAL_32) { 1715 zdet_param_ptr = &zdet_param[0]; 1716 d1 = d1_a[0]; 1717 } else if ((z1l > WCD937X_ZDET_VAL_400) && 1718 (z1l <= WCD937X_ZDET_VAL_1200)) { 1719 zdet_param_ptr = &zdet_param[2]; 1720 d1 = d1_a[2]; 1721 } else if (z1l > WCD937X_ZDET_VAL_1200) { 1722 zdet_param_ptr = &zdet_param[3]; 1723 d1 = d1_a[3]; 1724 } 1725 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1l, NULL, d1); 1726 1727 left_ch_impedance: 1728 if (z1l == WCD937X_ZDET_FLOATING_IMPEDANCE || 1729 z1l > WCD937X_ZDET_VAL_100K) { 1730 *zl = WCD937X_ZDET_FLOATING_IMPEDANCE; 1731 zdet_param_ptr = &zdet_param[1]; 1732 d1 = d1_a[1]; 1733 } else { 1734 *zl = z1l / 1000; 1735 wcd937x_wcd_mbhc_qfuse_cal(component, zl, 0); 1736 } 1737 1738 /* Start of right impedance ramp and calculation */ 1739 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1r, d1); 1740 if (WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z1r)) { 1741 if ((z1r > WCD937X_ZDET_VAL_1200 && 1742 zdet_param_ptr->noff == 0x6) || 1743 ((*zl) != WCD937X_ZDET_FLOATING_IMPEDANCE)) 1744 goto right_ch_impedance; 1745 /* Second ramp for right ch */ 1746 if (z1r < WCD937X_ZDET_VAL_32) { 1747 zdet_param_ptr = &zdet_param[0]; 1748 d1 = d1_a[0]; 1749 } else if ((z1r > WCD937X_ZDET_VAL_400) && 1750 (z1r <= WCD937X_ZDET_VAL_1200)) { 1751 zdet_param_ptr = &zdet_param[2]; 1752 d1 = d1_a[2]; 1753 } else if (z1r > WCD937X_ZDET_VAL_1200) { 1754 zdet_param_ptr = &zdet_param[3]; 1755 d1 = d1_a[3]; 1756 } 1757 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1r, d1); 1758 } 1759 right_ch_impedance: 1760 if (z1r == WCD937X_ZDET_FLOATING_IMPEDANCE || 1761 z1r > WCD937X_ZDET_VAL_100K) { 1762 *zr = WCD937X_ZDET_FLOATING_IMPEDANCE; 1763 } else { 1764 *zr = z1r / 1000; 1765 wcd937x_wcd_mbhc_qfuse_cal(component, zr, 1); 1766 } 1767 1768 /* Mono/stereo detection */ 1769 if ((*zl == WCD937X_ZDET_FLOATING_IMPEDANCE) && 1770 (*zr == WCD937X_ZDET_FLOATING_IMPEDANCE)) { 1771 dev_err(component->dev, 1772 "%s: plug type is invalid or extension cable\n", 1773 __func__); 1774 goto zdet_complete; 1775 } 1776 if ((*zl == WCD937X_ZDET_FLOATING_IMPEDANCE) || 1777 (*zr == WCD937X_ZDET_FLOATING_IMPEDANCE) || 1778 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 1779 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 1780 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_MONO); 1781 goto zdet_complete; 1782 } 1783 snd_soc_component_write_field(component, WCD937X_HPH_R_ATEST, 1784 WCD937X_HPHPA_GND_OVR_MASK, 1); 1785 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1786 WCD937X_HPHPA_GND_R_MASK, 1); 1787 if (*zl < (WCD937X_ZDET_VAL_32 / 1000)) 1788 wcd937x_mbhc_zdet_ramp(component, &zdet_param[0], &z1ls, NULL, d1); 1789 else 1790 wcd937x_mbhc_zdet_ramp(component, &zdet_param[1], &z1ls, NULL, d1); 1791 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1792 WCD937X_HPHPA_GND_R_MASK, 0); 1793 snd_soc_component_write_field(component, WCD937X_HPH_R_ATEST, 1794 WCD937X_HPHPA_GND_OVR_MASK, 0); 1795 z1ls /= 1000; 1796 wcd937x_wcd_mbhc_qfuse_cal(component, &z1ls, 0); 1797 /* Parallel of left Z and 9 ohm pull down resistor */ 1798 zMono = ((*zl) * 9) / ((*zl) + 9); 1799 z_diff1 = (z1ls > zMono) ? (z1ls - zMono) : (zMono - z1ls); 1800 z_diff2 = ((*zl) > z1ls) ? ((*zl) - z1ls) : (z1ls - (*zl)); 1801 if ((z_diff1 * (*zl + z1ls)) > (z_diff2 * (z1ls + zMono))) 1802 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_STEREO); 1803 else 1804 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_MONO); 1805 1806 /* Enable surge protection again after impedance detection */ 1807 regmap_update_bits(wcd937x->regmap, 1808 WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 1809 zdet_complete: 1810 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN5, reg0); 1811 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN6, reg1); 1812 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN7, reg2); 1813 /* Turn on 100k pull down on HPHL */ 1814 regmap_update_bits(wcd937x->regmap, 1815 WCD937X_ANA_MBHC_MECH, 0x01, 0x01); 1816 1817 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 1818 if (wcd937x->mbhc_cfg.hphl_swh) 1819 regmap_update_bits(wcd937x->regmap, 1820 WCD937X_ANA_MBHC_MECH, 0x80, 0x80); 1821 1822 snd_soc_component_write(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, reg4); 1823 snd_soc_component_write(component, WCD937X_MBHC_CTL_CLK, reg3); 1824 if (is_fsm_disable) 1825 regmap_update_bits(wcd937x->regmap, 1826 WCD937X_ANA_MBHC_ELECT, 0x80, 0x80); 1827 } 1828 1829 static void wcd937x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 1830 bool enable) 1831 { 1832 if (enable) { 1833 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1834 WCD937X_MBHC_HSG_PULLUP_COMP_EN, 1); 1835 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1836 WCD937X_MBHC_GND_DET_EN_MASK, 1); 1837 } else { 1838 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1839 WCD937X_MBHC_GND_DET_EN_MASK, 0); 1840 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1841 WCD937X_MBHC_HSG_PULLUP_COMP_EN, 0); 1842 } 1843 } 1844 1845 static void wcd937x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 1846 bool enable) 1847 { 1848 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1849 WCD937X_HPHPA_GND_R_MASK, enable); 1850 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1851 WCD937X_HPHPA_GND_L_MASK, enable); 1852 } 1853 1854 static void wcd937x_mbhc_moisture_config(struct snd_soc_component *component) 1855 { 1856 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1857 1858 if (wcd937x->mbhc_cfg.moist_rref == R_OFF) { 1859 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1860 WCD937X_M_RTH_CTL_MASK, R_OFF); 1861 return; 1862 } 1863 1864 /* Do not enable moisture detection if jack type is NC */ 1865 if (!wcd937x->mbhc_cfg.hphl_swh) { 1866 dev_err(component->dev, "%s: disable moisture detection for NC\n", 1867 __func__); 1868 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1869 WCD937X_M_RTH_CTL_MASK, R_OFF); 1870 return; 1871 } 1872 1873 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1874 WCD937X_M_RTH_CTL_MASK, wcd937x->mbhc_cfg.moist_rref); 1875 } 1876 1877 static void wcd937x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable) 1878 { 1879 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1880 1881 if (enable) 1882 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1883 WCD937X_M_RTH_CTL_MASK, wcd937x->mbhc_cfg.moist_rref); 1884 else 1885 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1886 WCD937X_M_RTH_CTL_MASK, R_OFF); 1887 } 1888 1889 static bool wcd937x_mbhc_get_moisture_status(struct snd_soc_component *component) 1890 { 1891 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1892 bool ret = false; 1893 1894 if (wcd937x->mbhc_cfg.moist_rref == R_OFF) { 1895 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1896 WCD937X_M_RTH_CTL_MASK, R_OFF); 1897 goto done; 1898 } 1899 1900 /* Do not enable moisture detection if jack type is NC */ 1901 if (!wcd937x->mbhc_cfg.hphl_swh) { 1902 dev_err(component->dev, "%s: disable moisture detection for NC\n", 1903 __func__); 1904 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1905 WCD937X_M_RTH_CTL_MASK, R_OFF); 1906 goto done; 1907 } 1908 1909 /* 1910 * If moisture_en is already enabled, then skip to plug type 1911 * detection. 1912 */ 1913 if (snd_soc_component_read_field(component, WCD937X_MBHC_NEW_CTL_2, WCD937X_M_RTH_CTL_MASK)) 1914 goto done; 1915 1916 wcd937x_mbhc_moisture_detect_en(component, true); 1917 /* Read moisture comparator status */ 1918 ret = ((snd_soc_component_read(component, WCD937X_MBHC_NEW_FSM_STATUS) 1919 & 0x20) ? 0 : 1); 1920 done: 1921 return ret; 1922 } 1923 1924 static void wcd937x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component, 1925 bool enable) 1926 { 1927 snd_soc_component_write_field(component, 1928 WCD937X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 1929 WCD937X_MOISTURE_EN_POLLING_MASK, enable); 1930 } 1931 1932 static const struct wcd_mbhc_cb mbhc_cb = { 1933 .clk_setup = wcd937x_mbhc_clk_setup, 1934 .mbhc_bias = wcd937x_mbhc_mbhc_bias_control, 1935 .set_btn_thr = wcd937x_mbhc_program_btn_thr, 1936 .micbias_enable_status = wcd937x_mbhc_micb_en_status, 1937 .hph_pull_up_control_v2 = wcd937x_mbhc_hph_l_pull_up_control, 1938 .mbhc_micbias_control = wcd937x_mbhc_request_micbias, 1939 .mbhc_micb_ramp_control = wcd937x_mbhc_micb_ramp_control, 1940 .mbhc_micb_ctrl_thr_mic = wcd937x_mbhc_micb_ctrl_threshold_mic, 1941 .compute_impedance = wcd937x_wcd_mbhc_calc_impedance, 1942 .mbhc_gnd_det_ctrl = wcd937x_mbhc_gnd_det_ctrl, 1943 .hph_pull_down_ctrl = wcd937x_mbhc_hph_pull_down_ctrl, 1944 .mbhc_moisture_config = wcd937x_mbhc_moisture_config, 1945 .mbhc_get_moisture_status = wcd937x_mbhc_get_moisture_status, 1946 .mbhc_moisture_polling_ctrl = wcd937x_mbhc_moisture_polling_ctrl, 1947 .mbhc_moisture_detect_en = wcd937x_mbhc_moisture_detect_en, 1948 }; 1949 1950 static int wcd937x_get_hph_type(struct snd_kcontrol *kcontrol, 1951 struct snd_ctl_elem_value *ucontrol) 1952 { 1953 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1954 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1955 1956 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd937x->wcd_mbhc); 1957 1958 return 0; 1959 } 1960 1961 static int wcd937x_hph_impedance_get(struct snd_kcontrol *kcontrol, 1962 struct snd_ctl_elem_value *ucontrol) 1963 { 1964 u32 zl, zr; 1965 bool hphr; 1966 struct soc_mixer_control *mc; 1967 struct snd_soc_component *component = 1968 snd_soc_kcontrol_component(kcontrol); 1969 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1970 1971 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1972 hphr = mc->shift; 1973 wcd_mbhc_get_impedance(wcd937x->wcd_mbhc, &zl, &zr); 1974 ucontrol->value.integer.value[0] = hphr ? zr : zl; 1975 1976 return 0; 1977 } 1978 1979 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 1980 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0, 1981 wcd937x_get_hph_type, NULL), 1982 }; 1983 1984 static const struct snd_kcontrol_new impedance_detect_controls[] = { 1985 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0, 1986 wcd937x_hph_impedance_get, NULL), 1987 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0, 1988 wcd937x_hph_impedance_get, NULL), 1989 }; 1990 1991 static int wcd937x_mbhc_init(struct snd_soc_component *component) 1992 { 1993 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1994 struct wcd_mbhc_intr *intr_ids = &wcd937x->intr_ids; 1995 1996 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd937x->irq_chip, 1997 WCD937X_IRQ_MBHC_SW_DET); 1998 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd937x->irq_chip, 1999 WCD937X_IRQ_MBHC_BUTTON_PRESS_DET); 2000 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2001 WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET); 2002 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2003 WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 2004 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2005 WCD937X_IRQ_MBHC_ELECT_INS_REM_DET); 2006 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd937x->irq_chip, 2007 WCD937X_IRQ_HPHL_OCP_INT); 2008 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd937x->irq_chip, 2009 WCD937X_IRQ_HPHR_OCP_INT); 2010 2011 wcd937x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 2012 if (IS_ERR(wcd937x->wcd_mbhc)) 2013 return PTR_ERR(wcd937x->wcd_mbhc); 2014 2015 snd_soc_add_component_controls(component, impedance_detect_controls, 2016 ARRAY_SIZE(impedance_detect_controls)); 2017 snd_soc_add_component_controls(component, hph_type_detect_controls, 2018 ARRAY_SIZE(hph_type_detect_controls)); 2019 2020 return 0; 2021 } 2022 2023 static void wcd937x_mbhc_deinit(struct snd_soc_component *component) 2024 { 2025 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2026 2027 wcd_mbhc_deinit(wcd937x->wcd_mbhc); 2028 } 2029 2030 /* END MBHC */ 2031 2032 static const struct snd_kcontrol_new wcd937x_snd_controls[] = { 2033 SOC_SINGLE_TLV("EAR_PA Volume", WCD937X_ANA_EAR_COMPANDER_CTL, 2034 2, 0x10, 0, ear_pa_gain), 2035 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 2036 wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put), 2037 2038 SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0, 2039 wcd937x_get_compander, wcd937x_set_compander), 2040 SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0, 2041 wcd937x_get_compander, wcd937x_set_compander), 2042 2043 SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain), 2044 SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain), 2045 SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0, analog_gain), 2046 SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0, analog_gain), 2047 SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0, analog_gain), 2048 2049 SOC_SINGLE_EXT("HPHL Switch", WCD937X_HPH_L, 0, 1, 0, 2050 wcd937x_get_swr_port, wcd937x_set_swr_port), 2051 SOC_SINGLE_EXT("HPHR Switch", WCD937X_HPH_R, 0, 1, 0, 2052 wcd937x_get_swr_port, wcd937x_set_swr_port), 2053 2054 SOC_SINGLE_EXT("ADC1 Switch", WCD937X_ADC1, 1, 1, 0, 2055 wcd937x_get_swr_port, wcd937x_set_swr_port), 2056 SOC_SINGLE_EXT("ADC2 Switch", WCD937X_ADC2, 1, 1, 0, 2057 wcd937x_get_swr_port, wcd937x_set_swr_port), 2058 SOC_SINGLE_EXT("ADC3 Switch", WCD937X_ADC3, 1, 1, 0, 2059 wcd937x_get_swr_port, wcd937x_set_swr_port), 2060 SOC_SINGLE_EXT("DMIC0 Switch", WCD937X_DMIC0, 1, 1, 0, 2061 wcd937x_get_swr_port, wcd937x_set_swr_port), 2062 SOC_SINGLE_EXT("DMIC1 Switch", WCD937X_DMIC1, 1, 1, 0, 2063 wcd937x_get_swr_port, wcd937x_set_swr_port), 2064 SOC_SINGLE_EXT("MBHC Switch", WCD937X_MBHC, 1, 1, 0, 2065 wcd937x_get_swr_port, wcd937x_set_swr_port), 2066 SOC_SINGLE_EXT("DMIC2 Switch", WCD937X_DMIC2, 1, 1, 0, 2067 wcd937x_get_swr_port, wcd937x_set_swr_port), 2068 SOC_SINGLE_EXT("DMIC3 Switch", WCD937X_DMIC3, 1, 1, 0, 2069 wcd937x_get_swr_port, wcd937x_set_swr_port), 2070 SOC_SINGLE_EXT("DMIC4 Switch", WCD937X_DMIC4, 1, 1, 0, 2071 wcd937x_get_swr_port, wcd937x_set_swr_port), 2072 SOC_SINGLE_EXT("DMIC5 Switch", WCD937X_DMIC5, 1, 1, 0, 2073 wcd937x_get_swr_port, wcd937x_set_swr_port), 2074 }; 2075 2076 static const struct snd_kcontrol_new adc1_switch[] = { 2077 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2078 }; 2079 2080 static const struct snd_kcontrol_new adc2_switch[] = { 2081 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2082 }; 2083 2084 static const struct snd_kcontrol_new adc3_switch[] = { 2085 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2086 }; 2087 2088 static const struct snd_kcontrol_new dmic1_switch[] = { 2089 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2090 }; 2091 2092 static const struct snd_kcontrol_new dmic2_switch[] = { 2093 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2094 }; 2095 2096 static const struct snd_kcontrol_new dmic3_switch[] = { 2097 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2098 }; 2099 2100 static const struct snd_kcontrol_new dmic4_switch[] = { 2101 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2102 }; 2103 2104 static const struct snd_kcontrol_new dmic5_switch[] = { 2105 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2106 }; 2107 2108 static const struct snd_kcontrol_new dmic6_switch[] = { 2109 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2110 }; 2111 2112 static const struct snd_kcontrol_new ear_rdac_switch[] = { 2113 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2114 }; 2115 2116 static const struct snd_kcontrol_new aux_rdac_switch[] = { 2117 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2118 }; 2119 2120 static const struct snd_kcontrol_new hphl_rdac_switch[] = { 2121 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2122 }; 2123 2124 static const struct snd_kcontrol_new hphr_rdac_switch[] = { 2125 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2126 }; 2127 2128 static const char * const adc2_mux_text[] = { 2129 "INP2", "INP3" 2130 }; 2131 2132 static const char * const rdac3_mux_text[] = { 2133 "RX1", "RX3" 2134 }; 2135 2136 static const struct soc_enum adc2_enum = 2137 SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7, 2138 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 2139 2140 static const struct soc_enum rdac3_enum = 2141 SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0, 2142 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text); 2143 2144 static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum); 2145 2146 static const struct snd_kcontrol_new rx_rdac3_mux = SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum); 2147 2148 static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = { 2149 /* Input widgets */ 2150 SND_SOC_DAPM_INPUT("AMIC1"), 2151 SND_SOC_DAPM_INPUT("AMIC2"), 2152 SND_SOC_DAPM_INPUT("AMIC3"), 2153 SND_SOC_DAPM_INPUT("IN1_HPHL"), 2154 SND_SOC_DAPM_INPUT("IN2_HPHR"), 2155 SND_SOC_DAPM_INPUT("IN3_AUX"), 2156 2157 /* TX widgets */ 2158 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0, 2159 wcd937x_codec_enable_adc, 2160 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2161 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0, 2162 wcd937x_codec_enable_adc, 2163 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2164 2165 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, 2166 NULL, 0, wcd937x_enable_req, 2167 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2168 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0, 2169 NULL, 0, wcd937x_enable_req, 2170 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2171 2172 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 2173 2174 /* TX mixers */ 2175 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, 2176 adc1_switch, ARRAY_SIZE(adc1_switch), 2177 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2178 SND_SOC_DAPM_POST_PMD), 2179 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 1, 0, 2180 adc2_switch, ARRAY_SIZE(adc2_switch), 2181 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2182 SND_SOC_DAPM_POST_PMD), 2183 2184 /* MIC_BIAS widgets */ 2185 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2186 wcd937x_codec_enable_micbias, 2187 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2188 SND_SOC_DAPM_POST_PMD), 2189 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2190 wcd937x_codec_enable_micbias, 2191 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2192 SND_SOC_DAPM_POST_PMD), 2193 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2194 wcd937x_codec_enable_micbias, 2195 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2196 SND_SOC_DAPM_POST_PMD), 2197 2198 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0), 2199 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0), 2200 2201 /* RX widgets */ 2202 SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0, 2203 wcd937x_codec_enable_ear_pa, 2204 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2205 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2206 SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0, 2207 wcd937x_codec_enable_aux_pa, 2208 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2209 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2210 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0, 2211 wcd937x_codec_enable_hphl_pa, 2212 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2213 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2214 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0, 2215 wcd937x_codec_enable_hphr_pa, 2216 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2217 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2218 2219 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0, 2220 wcd937x_codec_hphl_dac_event, 2221 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2222 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2223 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0, 2224 wcd937x_codec_hphr_dac_event, 2225 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2226 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2227 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0, 2228 wcd937x_codec_ear_dac_event, 2229 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2230 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2231 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0, 2232 wcd937x_codec_aux_dac_event, 2233 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2234 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2235 2236 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux), 2237 2238 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, 2239 wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU | 2240 SND_SOC_DAPM_POST_PMD), 2241 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, 2242 wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU | 2243 SND_SOC_DAPM_POST_PMD), 2244 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, 2245 wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU | 2246 SND_SOC_DAPM_POST_PMD), 2247 2248 /* RX mixer widgets*/ 2249 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0, 2250 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)), 2251 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0, 2252 aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)), 2253 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0, 2254 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)), 2255 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0, 2256 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)), 2257 2258 /* TX output widgets */ 2259 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"), 2260 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"), 2261 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"), 2262 SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"), 2263 2264 /* RX output widgets */ 2265 SND_SOC_DAPM_OUTPUT("EAR"), 2266 SND_SOC_DAPM_OUTPUT("AUX"), 2267 SND_SOC_DAPM_OUTPUT("HPHL"), 2268 SND_SOC_DAPM_OUTPUT("HPHR"), 2269 2270 /* MIC_BIAS pull up widgets */ 2271 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2272 wcd937x_codec_enable_micbias_pullup, 2273 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2274 SND_SOC_DAPM_POST_PMD), 2275 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2276 wcd937x_codec_enable_micbias_pullup, 2277 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2278 SND_SOC_DAPM_POST_PMD), 2279 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2280 wcd937x_codec_enable_micbias_pullup, 2281 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2282 SND_SOC_DAPM_POST_PMD), 2283 }; 2284 2285 static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = { 2286 /* Input widgets */ 2287 SND_SOC_DAPM_INPUT("AMIC4"), 2288 2289 /* TX widgets */ 2290 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0, 2291 wcd937x_codec_enable_adc, 2292 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2293 2294 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0, 2295 NULL, 0, wcd937x_enable_req, 2296 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2297 2298 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 2299 wcd937x_codec_enable_dmic, 2300 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2301 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0, 2302 wcd937x_codec_enable_dmic, 2303 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2304 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0, 2305 wcd937x_codec_enable_dmic, 2306 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2307 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0, 2308 wcd937x_codec_enable_dmic, 2309 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2310 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0, 2311 wcd937x_codec_enable_dmic, 2312 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2313 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0, 2314 wcd937x_codec_enable_dmic, 2315 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2316 2317 /* TX mixer widgets */ 2318 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 2319 0, dmic1_switch, ARRAY_SIZE(dmic1_switch), 2320 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2321 SND_SOC_DAPM_POST_PMD), 2322 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 1, 2323 0, dmic2_switch, ARRAY_SIZE(dmic2_switch), 2324 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2325 SND_SOC_DAPM_POST_PMD), 2326 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 2, 2327 0, dmic3_switch, ARRAY_SIZE(dmic3_switch), 2328 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2329 SND_SOC_DAPM_POST_PMD), 2330 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 3, 2331 0, dmic4_switch, ARRAY_SIZE(dmic4_switch), 2332 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2333 SND_SOC_DAPM_POST_PMD), 2334 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 4, 2335 0, dmic5_switch, ARRAY_SIZE(dmic5_switch), 2336 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2337 SND_SOC_DAPM_POST_PMD), 2338 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 5, 2339 0, dmic6_switch, ARRAY_SIZE(dmic6_switch), 2340 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2341 SND_SOC_DAPM_POST_PMD), 2342 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 2, 0, adc3_switch, 2343 ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl, 2344 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2345 2346 /* Output widgets */ 2347 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"), 2348 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"), 2349 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"), 2350 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"), 2351 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"), 2352 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"), 2353 }; 2354 2355 static const struct snd_soc_dapm_route wcd937x_audio_map[] = { 2356 { "ADC1_OUTPUT", NULL, "ADC1_MIXER" }, 2357 { "ADC1_MIXER", "Switch", "ADC1 REQ" }, 2358 { "ADC1 REQ", NULL, "ADC1" }, 2359 { "ADC1", NULL, "AMIC1" }, 2360 2361 { "ADC2_OUTPUT", NULL, "ADC2_MIXER" }, 2362 { "ADC2_MIXER", "Switch", "ADC2 REQ" }, 2363 { "ADC2 REQ", NULL, "ADC2" }, 2364 { "ADC2", NULL, "ADC2 MUX" }, 2365 { "ADC2 MUX", "INP3", "AMIC3" }, 2366 { "ADC2 MUX", "INP2", "AMIC2" }, 2367 2368 { "IN1_HPHL", NULL, "VDD_BUCK" }, 2369 { "IN1_HPHL", NULL, "CLS_H_PORT" }, 2370 { "RX1", NULL, "IN1_HPHL" }, 2371 { "RDAC1", NULL, "RX1" }, 2372 { "HPHL_RDAC", "Switch", "RDAC1" }, 2373 { "HPHL PGA", NULL, "HPHL_RDAC" }, 2374 { "HPHL", NULL, "HPHL PGA" }, 2375 2376 { "IN2_HPHR", NULL, "VDD_BUCK" }, 2377 { "IN2_HPHR", NULL, "CLS_H_PORT" }, 2378 { "RX2", NULL, "IN2_HPHR" }, 2379 { "RDAC2", NULL, "RX2" }, 2380 { "HPHR_RDAC", "Switch", "RDAC2" }, 2381 { "HPHR PGA", NULL, "HPHR_RDAC" }, 2382 { "HPHR", NULL, "HPHR PGA" }, 2383 2384 { "IN3_AUX", NULL, "VDD_BUCK" }, 2385 { "IN3_AUX", NULL, "CLS_H_PORT" }, 2386 { "RX3", NULL, "IN3_AUX" }, 2387 { "RDAC4", NULL, "RX3" }, 2388 { "AUX_RDAC", "Switch", "RDAC4" }, 2389 { "AUX PGA", NULL, "AUX_RDAC" }, 2390 { "AUX", NULL, "AUX PGA" }, 2391 2392 { "RDAC3_MUX", "RX3", "RX3" }, 2393 { "RDAC3_MUX", "RX1", "RX1" }, 2394 { "RDAC3", NULL, "RDAC3_MUX" }, 2395 { "EAR_RDAC", "Switch", "RDAC3" }, 2396 { "EAR PGA", NULL, "EAR_RDAC" }, 2397 { "EAR", NULL, "EAR PGA" }, 2398 }; 2399 2400 static const struct snd_soc_dapm_route wcd9375_audio_map[] = { 2401 { "ADC3_OUTPUT", NULL, "ADC3_MIXER" }, 2402 { "ADC3_OUTPUT", NULL, "ADC3_MIXER" }, 2403 { "ADC3_MIXER", "Switch", "ADC3 REQ" }, 2404 { "ADC3 REQ", NULL, "ADC3" }, 2405 { "ADC3", NULL, "AMIC4" }, 2406 2407 { "DMIC1_OUTPUT", NULL, "DMIC1_MIXER" }, 2408 { "DMIC1_MIXER", "Switch", "DMIC1" }, 2409 2410 { "DMIC2_OUTPUT", NULL, "DMIC2_MIXER" }, 2411 { "DMIC2_MIXER", "Switch", "DMIC2" }, 2412 2413 { "DMIC3_OUTPUT", NULL, "DMIC3_MIXER" }, 2414 { "DMIC3_MIXER", "Switch", "DMIC3" }, 2415 2416 { "DMIC4_OUTPUT", NULL, "DMIC4_MIXER" }, 2417 { "DMIC4_MIXER", "Switch", "DMIC4" }, 2418 2419 { "DMIC5_OUTPUT", NULL, "DMIC5_MIXER" }, 2420 { "DMIC5_MIXER", "Switch", "DMIC5" }, 2421 2422 { "DMIC6_OUTPUT", NULL, "DMIC6_MIXER" }, 2423 { "DMIC6_MIXER", "Switch", "DMIC6" }, 2424 }; 2425 2426 static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x) 2427 { 2428 int vout_ctl[3]; 2429 2430 /* Set micbias voltage */ 2431 vout_ctl[0] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb1_mv); 2432 vout_ctl[1] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb2_mv); 2433 vout_ctl[2] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb3_mv); 2434 if ((vout_ctl[0] | vout_ctl[1] | vout_ctl[2]) < 0) 2435 return -EINVAL; 2436 2437 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, WCD937X_ANA_MICB_VOUT, vout_ctl[0]); 2438 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, WCD937X_ANA_MICB_VOUT, vout_ctl[1]); 2439 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, WCD937X_ANA_MICB_VOUT, vout_ctl[2]); 2440 2441 return 0; 2442 } 2443 2444 static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data) 2445 { 2446 return IRQ_HANDLED; 2447 } 2448 2449 static const struct irq_chip wcd_irq_chip = { 2450 .name = "WCD937x", 2451 }; 2452 2453 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq, 2454 irq_hw_number_t hw) 2455 { 2456 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq); 2457 irq_set_nested_thread(virq, 1); 2458 irq_set_noprobe(virq); 2459 2460 return 0; 2461 } 2462 2463 static const struct irq_domain_ops wcd_domain_ops = { 2464 .map = wcd_irq_chip_map, 2465 }; 2466 2467 static int wcd937x_irq_init(struct wcd937x_priv *wcd, struct device *dev) 2468 { 2469 wcd->virq = irq_domain_add_linear(NULL, 1, &wcd_domain_ops, NULL); 2470 if (!(wcd->virq)) { 2471 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__); 2472 return -EINVAL; 2473 } 2474 2475 return devm_regmap_add_irq_chip(dev, wcd->regmap, 2476 irq_create_mapping(wcd->virq, 0), 2477 IRQF_ONESHOT, 0, &wcd937x_regmap_irq_chip, 2478 &wcd->irq_chip); 2479 } 2480 2481 static int wcd937x_soc_codec_probe(struct snd_soc_component *component) 2482 { 2483 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 2484 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2485 struct sdw_slave *tx_sdw_dev = wcd937x->tx_sdw_dev; 2486 struct device *dev = component->dev; 2487 unsigned long time_left; 2488 int i, ret; 2489 u32 chipid; 2490 2491 time_left = wait_for_completion_timeout(&tx_sdw_dev->initialization_complete, 2492 msecs_to_jiffies(5000)); 2493 if (!time_left) { 2494 dev_err(dev, "soundwire device init timeout\n"); 2495 return -ETIMEDOUT; 2496 } 2497 2498 snd_soc_component_init_regmap(component, wcd937x->regmap); 2499 ret = pm_runtime_resume_and_get(dev); 2500 if (ret < 0) 2501 return ret; 2502 2503 chipid = (snd_soc_component_read(component, 2504 WCD937X_DIGITAL_EFUSE_REG_0) & 0x1e) >> 1; 2505 if (chipid != CHIPID_WCD9370 && chipid != CHIPID_WCD9375) { 2506 dev_err(dev, "Got unknown chip id: 0x%x\n", chipid); 2507 pm_runtime_put(dev); 2508 return -EINVAL; 2509 } 2510 2511 wcd937x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD937X); 2512 if (IS_ERR(wcd937x->clsh_info)) { 2513 pm_runtime_put(dev); 2514 return PTR_ERR(wcd937x->clsh_info); 2515 } 2516 2517 wcd937x_io_init(wcd937x->regmap); 2518 /* Set all interrupts as edge triggered */ 2519 for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++) 2520 regmap_write(wcd937x->regmap, (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0); 2521 2522 pm_runtime_put(dev); 2523 2524 wcd937x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2525 WCD937X_IRQ_HPHR_PDM_WD_INT); 2526 wcd937x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2527 WCD937X_IRQ_HPHL_PDM_WD_INT); 2528 wcd937x->aux_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2529 WCD937X_IRQ_AUX_PDM_WD_INT); 2530 2531 /* Request for watchdog interrupt */ 2532 ret = devm_request_threaded_irq(dev, wcd937x->hphr_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2533 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2534 "HPHR PDM WDOG INT", wcd937x); 2535 if (ret) 2536 dev_err(dev, "Failed to request HPHR watchdog interrupt (%d)\n", ret); 2537 2538 ret = devm_request_threaded_irq(dev, wcd937x->hphl_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2539 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2540 "HPHL PDM WDOG INT", wcd937x); 2541 if (ret) 2542 dev_err(dev, "Failed to request HPHL watchdog interrupt (%d)\n", ret); 2543 2544 ret = devm_request_threaded_irq(dev, wcd937x->aux_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2545 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2546 "AUX PDM WDOG INT", wcd937x); 2547 if (ret) 2548 dev_err(dev, "Failed to request Aux watchdog interrupt (%d)\n", ret); 2549 2550 /* Disable watchdog interrupt for HPH and AUX */ 2551 disable_irq_nosync(wcd937x->hphr_pdm_wd_int); 2552 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 2553 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 2554 2555 if (chipid == CHIPID_WCD9375) { 2556 ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets, 2557 ARRAY_SIZE(wcd9375_dapm_widgets)); 2558 if (ret < 0) { 2559 dev_err(component->dev, "Failed to add snd_ctls\n"); 2560 return ret; 2561 } 2562 2563 ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map, 2564 ARRAY_SIZE(wcd9375_audio_map)); 2565 if (ret < 0) { 2566 dev_err(component->dev, "Failed to add routes\n"); 2567 return ret; 2568 } 2569 } 2570 2571 ret = wcd937x_mbhc_init(component); 2572 if (ret) 2573 dev_err(component->dev, "mbhc initialization failed\n"); 2574 2575 return ret; 2576 } 2577 2578 static void wcd937x_soc_codec_remove(struct snd_soc_component *component) 2579 { 2580 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2581 2582 wcd937x_mbhc_deinit(component); 2583 free_irq(wcd937x->aux_pdm_wd_int, wcd937x); 2584 free_irq(wcd937x->hphl_pdm_wd_int, wcd937x); 2585 free_irq(wcd937x->hphr_pdm_wd_int, wcd937x); 2586 2587 wcd_clsh_ctrl_free(wcd937x->clsh_info); 2588 } 2589 2590 static int wcd937x_codec_set_jack(struct snd_soc_component *comp, 2591 struct snd_soc_jack *jack, void *data) 2592 { 2593 struct wcd937x_priv *wcd = dev_get_drvdata(comp->dev); 2594 int ret = 0; 2595 2596 if (jack) 2597 ret = wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack); 2598 else 2599 wcd_mbhc_stop(wcd->wcd_mbhc); 2600 2601 return ret; 2602 } 2603 2604 static const struct snd_soc_component_driver soc_codec_dev_wcd937x = { 2605 .name = "wcd937x_codec", 2606 .probe = wcd937x_soc_codec_probe, 2607 .remove = wcd937x_soc_codec_remove, 2608 .controls = wcd937x_snd_controls, 2609 .num_controls = ARRAY_SIZE(wcd937x_snd_controls), 2610 .dapm_widgets = wcd937x_dapm_widgets, 2611 .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets), 2612 .dapm_routes = wcd937x_audio_map, 2613 .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map), 2614 .set_jack = wcd937x_codec_set_jack, 2615 .endianness = 1, 2616 }; 2617 2618 static void wcd937x_dt_parse_micbias_info(struct device *dev, struct wcd937x_priv *wcd) 2619 { 2620 struct device_node *np = dev->of_node; 2621 u32 prop_val = 0; 2622 int ret = 0; 2623 2624 ret = of_property_read_u32(np, "qcom,micbias1-microvolt", &prop_val); 2625 if (!ret) 2626 wcd->micb1_mv = prop_val / 1000; 2627 else 2628 dev_warn(dev, "Micbias1 DT property not found\n"); 2629 2630 ret = of_property_read_u32(np, "qcom,micbias2-microvolt", &prop_val); 2631 if (!ret) 2632 wcd->micb2_mv = prop_val / 1000; 2633 else 2634 dev_warn(dev, "Micbias2 DT property not found\n"); 2635 2636 ret = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val); 2637 if (!ret) 2638 wcd->micb3_mv = prop_val / 1000; 2639 else 2640 dev_warn(dev, "Micbias3 DT property not found\n"); 2641 } 2642 2643 static bool wcd937x_swap_gnd_mic(struct snd_soc_component *component, bool active) 2644 { 2645 int value; 2646 struct wcd937x_priv *wcd937x; 2647 2648 wcd937x = snd_soc_component_get_drvdata(component); 2649 2650 value = gpiod_get_value(wcd937x->us_euro_gpio); 2651 gpiod_set_value(wcd937x->us_euro_gpio, !value); 2652 2653 return true; 2654 } 2655 2656 static int wcd937x_codec_hw_params(struct snd_pcm_substream *substream, 2657 struct snd_pcm_hw_params *params, 2658 struct snd_soc_dai *dai) 2659 { 2660 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2661 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2662 2663 return wcd937x_sdw_hw_params(wcd, substream, params, dai); 2664 } 2665 2666 static int wcd937x_codec_free(struct snd_pcm_substream *substream, 2667 struct snd_soc_dai *dai) 2668 { 2669 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2670 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2671 2672 return sdw_stream_remove_slave(wcd->sdev, wcd->sruntime); 2673 } 2674 2675 static int wcd937x_codec_set_sdw_stream(struct snd_soc_dai *dai, 2676 void *stream, int direction) 2677 { 2678 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2679 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2680 2681 wcd->sruntime = stream; 2682 2683 return 0; 2684 } 2685 2686 static const struct snd_soc_dai_ops wcd937x_sdw_dai_ops = { 2687 .hw_params = wcd937x_codec_hw_params, 2688 .hw_free = wcd937x_codec_free, 2689 .set_stream = wcd937x_codec_set_sdw_stream, 2690 }; 2691 2692 static struct snd_soc_dai_driver wcd937x_dais[] = { 2693 [0] = { 2694 .name = "wcd937x-sdw-rx", 2695 .playback = { 2696 .stream_name = "WCD AIF Playback", 2697 .rates = WCD937X_RATES | WCD937X_FRAC_RATES, 2698 .formats = WCD937X_FORMATS, 2699 .rate_min = 8000, 2700 .rate_max = 384000, 2701 .channels_min = 1, 2702 .channels_max = 4, 2703 }, 2704 .ops = &wcd937x_sdw_dai_ops, 2705 }, 2706 [1] = { 2707 .name = "wcd937x-sdw-tx", 2708 .capture = { 2709 .stream_name = "WCD AIF Capture", 2710 .rates = WCD937X_RATES, 2711 .formats = WCD937X_FORMATS, 2712 .rate_min = 8000, 2713 .rate_max = 192000, 2714 .channels_min = 1, 2715 .channels_max = 4, 2716 }, 2717 .ops = &wcd937x_sdw_dai_ops, 2718 }, 2719 }; 2720 2721 static int wcd937x_bind(struct device *dev) 2722 { 2723 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev); 2724 int ret; 2725 2726 /* Give the SDW subdevices some more time to settle */ 2727 usleep_range(5000, 5010); 2728 2729 ret = component_bind_all(dev, wcd937x); 2730 if (ret) { 2731 dev_err(dev, "Slave bind failed, ret = %d\n", ret); 2732 return ret; 2733 } 2734 2735 wcd937x->rxdev = wcd937x_sdw_device_get(wcd937x->rxnode); 2736 if (!wcd937x->rxdev) { 2737 dev_err(dev, "could not find slave with matching of node\n"); 2738 return -EINVAL; 2739 } 2740 2741 wcd937x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd937x->rxdev); 2742 wcd937x->sdw_priv[AIF1_PB]->wcd937x = wcd937x; 2743 2744 wcd937x->txdev = wcd937x_sdw_device_get(wcd937x->txnode); 2745 if (!wcd937x->txdev) { 2746 dev_err(dev, "could not find txslave with matching of node\n"); 2747 return -EINVAL; 2748 } 2749 2750 wcd937x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd937x->txdev); 2751 wcd937x->sdw_priv[AIF1_CAP]->wcd937x = wcd937x; 2752 wcd937x->tx_sdw_dev = dev_to_sdw_dev(wcd937x->txdev); 2753 if (!wcd937x->tx_sdw_dev) { 2754 dev_err(dev, "could not get txslave with matching of dev\n"); 2755 return -EINVAL; 2756 } 2757 2758 /* 2759 * As TX is the main CSR reg interface, which should not be suspended first. 2760 * expicilty add the dependency link 2761 */ 2762 if (!device_link_add(wcd937x->rxdev, wcd937x->txdev, 2763 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2764 dev_err(dev, "Could not devlink TX and RX\n"); 2765 return -EINVAL; 2766 } 2767 2768 if (!device_link_add(dev, wcd937x->txdev, 2769 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2770 dev_err(dev, "Could not devlink WCD and TX\n"); 2771 return -EINVAL; 2772 } 2773 2774 if (!device_link_add(dev, wcd937x->rxdev, 2775 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2776 dev_err(dev, "Could not devlink WCD and RX\n"); 2777 return -EINVAL; 2778 } 2779 2780 wcd937x->regmap = dev_get_regmap(&wcd937x->tx_sdw_dev->dev, NULL); 2781 if (!wcd937x->regmap) { 2782 dev_err(dev, "could not get TX device regmap\n"); 2783 return -EINVAL; 2784 } 2785 2786 ret = wcd937x_irq_init(wcd937x, dev); 2787 if (ret) { 2788 dev_err(dev, "IRQ init failed: %d\n", ret); 2789 return ret; 2790 } 2791 2792 wcd937x->sdw_priv[AIF1_PB]->slave_irq = wcd937x->virq; 2793 wcd937x->sdw_priv[AIF1_CAP]->slave_irq = wcd937x->virq; 2794 2795 ret = wcd937x_set_micbias_data(wcd937x); 2796 if (ret < 0) { 2797 dev_err(dev, "Bad micbias pdata\n"); 2798 return ret; 2799 } 2800 2801 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x, 2802 wcd937x_dais, ARRAY_SIZE(wcd937x_dais)); 2803 if (ret) 2804 dev_err(dev, "Codec registration failed\n"); 2805 2806 return ret; 2807 } 2808 2809 static void wcd937x_unbind(struct device *dev) 2810 { 2811 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev); 2812 2813 snd_soc_unregister_component(dev); 2814 device_link_remove(dev, wcd937x->txdev); 2815 device_link_remove(dev, wcd937x->rxdev); 2816 device_link_remove(wcd937x->rxdev, wcd937x->txdev); 2817 component_unbind_all(dev, wcd937x); 2818 mutex_destroy(&wcd937x->micb_lock); 2819 } 2820 2821 static const struct component_master_ops wcd937x_comp_ops = { 2822 .bind = wcd937x_bind, 2823 .unbind = wcd937x_unbind, 2824 }; 2825 2826 static int wcd937x_add_slave_components(struct wcd937x_priv *wcd937x, 2827 struct device *dev, 2828 struct component_match **matchptr) 2829 { 2830 struct device_node *np = dev->of_node; 2831 2832 wcd937x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0); 2833 if (!wcd937x->rxnode) { 2834 dev_err(dev, "Couldn't parse phandle to qcom,rx-device!\n"); 2835 return -ENODEV; 2836 } 2837 of_node_get(wcd937x->rxnode); 2838 component_match_add_release(dev, matchptr, component_release_of, 2839 component_compare_of, wcd937x->rxnode); 2840 2841 wcd937x->txnode = of_parse_phandle(np, "qcom,tx-device", 0); 2842 if (!wcd937x->txnode) { 2843 dev_err(dev, "Couldn't parse phandle to qcom,tx-device\n"); 2844 return -ENODEV; 2845 } 2846 of_node_get(wcd937x->txnode); 2847 component_match_add_release(dev, matchptr, component_release_of, 2848 component_compare_of, wcd937x->txnode); 2849 2850 return 0; 2851 } 2852 2853 static int wcd937x_probe(struct platform_device *pdev) 2854 { 2855 struct component_match *match = NULL; 2856 struct device *dev = &pdev->dev; 2857 struct wcd937x_priv *wcd937x; 2858 struct wcd_mbhc_config *cfg; 2859 int ret; 2860 2861 wcd937x = devm_kzalloc(dev, sizeof(*wcd937x), GFP_KERNEL); 2862 if (!wcd937x) 2863 return -ENOMEM; 2864 2865 dev_set_drvdata(dev, wcd937x); 2866 mutex_init(&wcd937x->micb_lock); 2867 2868 wcd937x->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 2869 if (IS_ERR(wcd937x->reset_gpio)) 2870 return dev_err_probe(dev, PTR_ERR(wcd937x->reset_gpio), 2871 "failed to reset wcd gpio\n"); 2872 2873 wcd937x->us_euro_gpio = devm_gpiod_get_optional(dev, "us-euro", GPIOD_OUT_LOW); 2874 if (IS_ERR(wcd937x->us_euro_gpio)) 2875 return dev_err_probe(dev, PTR_ERR(wcd937x->us_euro_gpio), 2876 "us-euro swap Control GPIO not found\n"); 2877 2878 cfg = &wcd937x->mbhc_cfg; 2879 cfg->swap_gnd_mic = wcd937x_swap_gnd_mic; 2880 2881 wcd937x->supplies[0].supply = "vdd-rxtx"; 2882 wcd937x->supplies[1].supply = "vdd-px"; 2883 wcd937x->supplies[2].supply = "vdd-mic-bias"; 2884 wcd937x->supplies[3].supply = "vdd-buck"; 2885 2886 ret = devm_regulator_bulk_get(dev, WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2887 if (ret) 2888 return dev_err_probe(dev, ret, "Failed to get supplies\n"); 2889 2890 ret = regulator_bulk_enable(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2891 if (ret) { 2892 regulator_bulk_free(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2893 return dev_err_probe(dev, ret, "Failed to enable supplies\n"); 2894 } 2895 2896 wcd937x_dt_parse_micbias_info(dev, wcd937x); 2897 2898 cfg->mbhc_micbias = MIC_BIAS_2; 2899 cfg->anc_micbias = MIC_BIAS_2; 2900 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 2901 cfg->num_btn = WCD937X_MBHC_MAX_BUTTONS; 2902 cfg->micb_mv = wcd937x->micb2_mv; 2903 cfg->linein_th = 5000; 2904 cfg->hs_thr = 1700; 2905 cfg->hph_thr = 50; 2906 2907 wcd_dt_parse_mbhc_data(dev, &wcd937x->mbhc_cfg); 2908 2909 ret = wcd937x_add_slave_components(wcd937x, dev, &match); 2910 if (ret) 2911 goto err_disable_regulators; 2912 2913 wcd937x_reset(wcd937x); 2914 2915 ret = component_master_add_with_match(dev, &wcd937x_comp_ops, match); 2916 if (ret) 2917 goto err_disable_regulators; 2918 2919 pm_runtime_set_autosuspend_delay(dev, 1000); 2920 pm_runtime_use_autosuspend(dev); 2921 pm_runtime_mark_last_busy(dev); 2922 pm_runtime_set_active(dev); 2923 pm_runtime_enable(dev); 2924 pm_runtime_idle(dev); 2925 2926 return 0; 2927 2928 err_disable_regulators: 2929 regulator_bulk_disable(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2930 regulator_bulk_free(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2931 2932 return ret; 2933 } 2934 2935 static void wcd937x_remove(struct platform_device *pdev) 2936 { 2937 struct device *dev = &pdev->dev; 2938 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev); 2939 2940 component_master_del(&pdev->dev, &wcd937x_comp_ops); 2941 2942 pm_runtime_disable(dev); 2943 pm_runtime_set_suspended(dev); 2944 pm_runtime_dont_use_autosuspend(dev); 2945 2946 regulator_bulk_disable(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2947 regulator_bulk_free(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2948 } 2949 2950 #if defined(CONFIG_OF) 2951 static const struct of_device_id wcd937x_of_match[] = { 2952 { .compatible = "qcom,wcd9370-codec" }, 2953 { .compatible = "qcom,wcd9375-codec" }, 2954 { } 2955 }; 2956 MODULE_DEVICE_TABLE(of, wcd937x_of_match); 2957 #endif 2958 2959 static struct platform_driver wcd937x_codec_driver = { 2960 .probe = wcd937x_probe, 2961 .remove_new = wcd937x_remove, 2962 .driver = { 2963 .name = "wcd937x_codec", 2964 .of_match_table = of_match_ptr(wcd937x_of_match), 2965 .suppress_bind_attrs = true, 2966 }, 2967 }; 2968 2969 module_platform_driver(wcd937x_codec_driver); 2970 MODULE_DESCRIPTION("WCD937X Codec driver"); 2971 MODULE_LICENSE("GPL"); 2972