xref: /linux/sound/soc/codecs/wcd937x.c (revision 15cb732c16edd39ce00ce655710e34cc82bbcf2c)
1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
3 
4 #include <linux/component.h>
5 #include <linux/delay.h>
6 #include <linux/device.h>
7 #include <linux/gpio/consumer.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/of_gpio.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/regmap.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/slab.h>
17 #include <sound/jack.h>
18 #include <sound/pcm_params.h>
19 #include <sound/pcm.h>
20 #include <sound/soc-dapm.h>
21 #include <sound/soc.h>
22 #include <sound/tlv.h>
23 
24 #include "wcd-clsh-v2.h"
25 #include "wcd-mbhc-v2.h"
26 #include "wcd937x.h"
27 
28 enum {
29 	CHIPID_WCD9370 = 0,
30 	CHIPID_WCD9375 = 5,
31 };
32 
33 /* Z value defined in milliohm */
34 #define WCD937X_ZDET_VAL_32		(32000)
35 #define WCD937X_ZDET_VAL_400		(400000)
36 #define WCD937X_ZDET_VAL_1200		(1200000)
37 #define WCD937X_ZDET_VAL_100K		(100000000)
38 /* Z floating defined in ohms */
39 #define WCD937X_ZDET_FLOATING_IMPEDANCE	(0x0FFFFFFE)
40 #define WCD937X_ZDET_NUM_MEASUREMENTS	(900)
41 #define WCD937X_MBHC_GET_C1(c)		(((c) & 0xC000) >> 14)
42 #define WCD937X_MBHC_GET_X1(x)		((x) & 0x3FFF)
43 /* Z value compared in milliOhm */
44 #define WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z)	(((z) > 400000) || ((z) < 32000))
45 #define WCD937X_MBHC_ZDET_CONST		(86 * 16384)
46 #define WCD937X_MBHC_MOISTURE_RREF	R_24_KOHM
47 #define WCD_MBHC_HS_V_MAX		1600
48 #define EAR_RX_PATH_AUX			1
49 #define WCD937X_MBHC_MAX_BUTTONS	8
50 
51 #define WCD937X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
52 		       SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
53 		       SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
54 		       SNDRV_PCM_RATE_384000)
55 
56 /* Fractional Rates */
57 #define WCD937X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
58 			    SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
59 
60 #define WCD937X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |\
61 			 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
62 
63 enum {
64 	ALLOW_BUCK_DISABLE,
65 	HPH_COMP_DELAY,
66 	HPH_PA_DELAY,
67 	AMIC2_BCS_ENABLE,
68 };
69 
70 enum {
71 	AIF1_PB = 0,
72 	AIF1_CAP,
73 	NUM_CODEC_DAIS,
74 };
75 
76 struct wcd937x_priv {
77 	struct sdw_slave *tx_sdw_dev;
78 	struct wcd937x_sdw_priv *sdw_priv[NUM_CODEC_DAIS];
79 	struct device *txdev;
80 	struct device *rxdev;
81 	struct device_node *rxnode;
82 	struct device_node *txnode;
83 	struct regmap *regmap;
84 	/* micb setup lock */
85 	struct mutex micb_lock;
86 	/* mbhc module */
87 	struct wcd_mbhc *wcd_mbhc;
88 	struct wcd_mbhc_config mbhc_cfg;
89 	struct wcd_mbhc_intr intr_ids;
90 	struct wcd_clsh_ctrl *clsh_info;
91 	struct irq_domain *virq;
92 	struct regmap_irq_chip *wcd_regmap_irq_chip;
93 	struct regmap_irq_chip_data *irq_chip;
94 	struct regulator_bulk_data supplies[WCD937X_MAX_BULK_SUPPLY];
95 	struct regulator *buck_supply;
96 	struct snd_soc_jack *jack;
97 	unsigned long status_mask;
98 	s32 micb_ref[WCD937X_MAX_MICBIAS];
99 	s32 pullup_ref[WCD937X_MAX_MICBIAS];
100 	u32 hph_mode;
101 	int ear_rx_path;
102 	u32 micb1_mv;
103 	u32 micb2_mv;
104 	u32 micb3_mv;
105 	int hphr_pdm_wd_int;
106 	int hphl_pdm_wd_int;
107 	int aux_pdm_wd_int;
108 	bool comp1_enable;
109 	bool comp2_enable;
110 
111 	struct gpio_desc *us_euro_gpio;
112 	struct gpio_desc *reset_gpio;
113 
114 	atomic_t rx_clk_cnt;
115 	atomic_t ana_clk_count;
116 };
117 
118 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
119 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
120 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
121 
122 struct wcd937x_mbhc_zdet_param {
123 	u16 ldo_ctl;
124 	u16 noff;
125 	u16 nshift;
126 	u16 btn5;
127 	u16 btn6;
128 	u16 btn7;
129 };
130 
131 static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = {
132 	WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD937X_ANA_MBHC_MECH, 0x80),
133 	WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD937X_ANA_MBHC_MECH, 0x40),
134 	WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD937X_ANA_MBHC_MECH, 0x20),
135 	WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD937X_MBHC_NEW_PLUG_DETECT_CTL, 0x30),
136 	WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD937X_ANA_MBHC_ELECT, 0x08),
137 	WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F),
138 	WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD937X_ANA_MBHC_MECH, 0x04),
139 	WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD937X_ANA_MBHC_MECH, 0x10),
140 	WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD937X_ANA_MBHC_MECH, 0x08),
141 	WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD937X_ANA_MBHC_MECH, 0x01),
142 	WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD937X_ANA_MBHC_ELECT, 0x06),
143 	WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD937X_ANA_MBHC_ELECT, 0x80),
144 	WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD937X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F),
145 	WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD937X_MBHC_NEW_CTL_1, 0x03),
146 	WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD937X_MBHC_NEW_CTL_2, 0x03),
147 	WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x08),
148 	WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD937X_ANA_MBHC_RESULT_3, 0x10),
149 	WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x20),
150 	WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x80),
151 	WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x40),
152 	WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD937X_HPH_OCP_CTL, 0x10),
153 	WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x07),
154 	WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD937X_ANA_MBHC_ELECT, 0x70),
155 	WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0xFF),
156 	WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD937X_ANA_MICB2, 0xC0),
157 	WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD937X_HPH_CNP_WG_TIME, 0xFF),
158 	WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD937X_ANA_HPH, 0x40),
159 	WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD937X_ANA_HPH, 0x80),
160 	WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD937X_ANA_HPH, 0xC0),
161 	WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD937X_ANA_MBHC_RESULT_3, 0x10),
162 	WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD937X_MBHC_CTL_BCS, 0x02),
163 	WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD937X_MBHC_NEW_FSM_STATUS, 0x01),
164 	WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD937X_MBHC_NEW_CTL_2, 0x70),
165 	WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD937X_MBHC_NEW_FSM_STATUS, 0x20),
166 	WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD937X_HPH_PA_CTL2, 0x40),
167 	WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD937X_HPH_PA_CTL2, 0x10),
168 	WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD937X_HPH_L_TEST, 0x01),
169 	WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD937X_HPH_R_TEST, 0x01),
170 	WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD937X_DIGITAL_INTR_STATUS_0, 0x80),
171 	WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD937X_DIGITAL_INTR_STATUS_0, 0x20),
172 	WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD937X_MBHC_NEW_CTL_1, 0x08),
173 	WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD937X_MBHC_NEW_FSM_STATUS, 0x40),
174 	WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD937X_MBHC_NEW_FSM_STATUS, 0x80),
175 	WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD937X_MBHC_NEW_ADC_RESULT, 0xFF),
176 	WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD937X_ANA_MICB2, 0x3F),
177 	WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD937X_MBHC_NEW_CTL_1, 0x10),
178 	WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD937X_MBHC_NEW_CTL_1, 0x04),
179 	WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD937X_ANA_MBHC_ZDET, 0x02),
180 };
181 
182 static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
183 	REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, BIT(0)),
184 	REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, BIT(1)),
185 	REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, BIT(2)),
186 	REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, BIT(3)),
187 	REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, BIT(4)),
188 	REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, BIT(5)),
189 	REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, BIT(6)),
190 	REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, BIT(7)),
191 	REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, BIT(0)),
192 	REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, BIT(1)),
193 	REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, BIT(2)),
194 	REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, BIT(3)),
195 	REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, BIT(4)),
196 	REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, BIT(5)),
197 	REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, BIT(6)),
198 	REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, BIT(7)),
199 	REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, BIT(0)),
200 	REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, BIT(1)),
201 	REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, BIT(2)),
202 	REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, BIT(3)),
203 };
204 
wcd937x_handle_post_irq(void * data)205 static int wcd937x_handle_post_irq(void *data)
206 {
207 	struct wcd937x_priv *wcd937x;
208 
209 	if (data)
210 		wcd937x = (struct wcd937x_priv *)data;
211 	else
212 		return IRQ_HANDLED;
213 
214 	regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_0, 0);
215 	regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_1, 0);
216 	regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_2, 0);
217 
218 	return IRQ_HANDLED;
219 }
220 
221 static const u32 wcd937x_config_regs[] = {
222 	WCD937X_DIGITAL_INTR_LEVEL_0,
223 };
224 
225 static const struct regmap_irq_chip wcd937x_regmap_irq_chip = {
226 	.name = "wcd937x",
227 	.irqs = wcd937x_irqs,
228 	.num_irqs = ARRAY_SIZE(wcd937x_irqs),
229 	.num_regs = 3,
230 	.status_base = WCD937X_DIGITAL_INTR_STATUS_0,
231 	.mask_base = WCD937X_DIGITAL_INTR_MASK_0,
232 	.ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
233 	.use_ack = 1,
234 	.clear_ack = 1,
235 	.config_base = wcd937x_config_regs,
236 	.num_config_bases = ARRAY_SIZE(wcd937x_config_regs),
237 	.num_config_regs = 1,
238 	.runtime_pm = true,
239 	.handle_post_irq = wcd937x_handle_post_irq,
240 	.irq_drv_data = NULL,
241 };
242 
wcd937x_reset(struct wcd937x_priv * wcd937x)243 static void wcd937x_reset(struct wcd937x_priv *wcd937x)
244 {
245 	gpiod_set_value(wcd937x->reset_gpio, 1);
246 	usleep_range(20, 30);
247 	gpiod_set_value(wcd937x->reset_gpio, 0);
248 	usleep_range(20, 30);
249 }
250 
wcd937x_io_init(struct regmap * regmap)251 static void wcd937x_io_init(struct regmap *regmap)
252 {
253 	u32 val = 0, temp = 0, temp1 = 0;
254 
255 	regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_29, &val);
256 
257 	val = val & 0x0F;
258 
259 	regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_16, &temp);
260 	regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_17, &temp1);
261 
262 	if (temp == 0x02 || temp1 > 0x09)
263 		regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x0E, val);
264 	else
265 		regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x0e, 0x0e);
266 
267 	regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x80, 0x80);
268 	usleep_range(1000, 1010);
269 
270 	regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x40, 0x40);
271 	usleep_range(1000, 1010);
272 
273 	regmap_update_bits(regmap, WCD937X_LDORXTX_CONFIG, BIT(4), 0x00);
274 	regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xf0, BIT(7));
275 	regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(7), BIT(7));
276 	regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(6), BIT(6));
277 	usleep_range(10000, 10010);
278 
279 	regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(6), 0x00);
280 	regmap_update_bits(regmap, WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xff, 0xd9);
281 	regmap_update_bits(regmap, WCD937X_MICB1_TEST_CTL_1, 0xff, 0xfa);
282 	regmap_update_bits(regmap, WCD937X_MICB2_TEST_CTL_1, 0xff, 0xfa);
283 	regmap_update_bits(regmap, WCD937X_MICB3_TEST_CTL_1, 0xff, 0xfa);
284 
285 	regmap_update_bits(regmap, WCD937X_MICB1_TEST_CTL_2, 0x38, 0x00);
286 	regmap_update_bits(regmap, WCD937X_MICB2_TEST_CTL_2, 0x38, 0x00);
287 	regmap_update_bits(regmap, WCD937X_MICB3_TEST_CTL_2, 0x38, 0x00);
288 
289 	/* Set Bandgap Fine Adjustment to +5mV for Tanggu SMIC part */
290 	regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_16, &val);
291 	if (val == 0x01) {
292 		regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0);
293 	} else if (val == 0x02) {
294 		regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x1F, 0x04);
295 		regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x1F, 0x04);
296 		regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0);
297 		regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL, 0xF0, 0x50);
298 	}
299 }
300 
wcd937x_rx_clk_enable(struct snd_soc_component * component)301 static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
302 {
303 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
304 
305 	if (atomic_read(&wcd937x->rx_clk_cnt))
306 		return 0;
307 
308 	snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(3), BIT(3));
309 	snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(0), BIT(0));
310 	snd_soc_component_update_bits(component, WCD937X_ANA_RX_SUPPLIES, BIT(0), BIT(0));
311 	snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX0_CTL, BIT(6), 0x00);
312 	snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX1_CTL, BIT(6), 0x00);
313 	snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX2_CTL, BIT(6), 0x00);
314 	snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(1), BIT(1));
315 
316 	atomic_inc(&wcd937x->rx_clk_cnt);
317 
318 	return 0;
319 }
320 
wcd937x_rx_clk_disable(struct snd_soc_component * component)321 static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
322 {
323 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
324 
325 	if (!atomic_read(&wcd937x->rx_clk_cnt)) {
326 		dev_err(component->dev, "clk already disabled\n");
327 		return 0;
328 	}
329 
330 	atomic_dec(&wcd937x->rx_clk_cnt);
331 
332 	snd_soc_component_update_bits(component, WCD937X_ANA_RX_SUPPLIES, BIT(0), 0x00);
333 	snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(1), 0x00);
334 	snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(0), 0x00);
335 
336 	return 0;
337 }
338 
wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)339 static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
340 					struct snd_kcontrol *kcontrol,
341 					int event)
342 {
343 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
344 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
345 	int hph_mode = wcd937x->hph_mode;
346 
347 	switch (event) {
348 	case SND_SOC_DAPM_PRE_PMU:
349 		wcd937x_rx_clk_enable(component);
350 		snd_soc_component_update_bits(component,
351 					      WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
352 					      BIT(0), BIT(0));
353 		snd_soc_component_update_bits(component,
354 					      WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
355 					      BIT(2), BIT(2));
356 		snd_soc_component_update_bits(component,
357 					      WCD937X_HPH_RDAC_CLK_CTL1,
358 					      BIT(7), 0x00);
359 		set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
360 		break;
361 	case SND_SOC_DAPM_POST_PMU:
362 		if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
363 			snd_soc_component_update_bits(component,
364 						      WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
365 						      0x0f, BIT(1));
366 		else if (hph_mode == CLS_H_LOHIFI)
367 			snd_soc_component_update_bits(component,
368 						      WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
369 						      0x0f, 0x06);
370 
371 		if (wcd937x->comp1_enable) {
372 			snd_soc_component_update_bits(component,
373 						      WCD937X_DIGITAL_CDC_COMP_CTL_0,
374 						      BIT(1), BIT(1));
375 			snd_soc_component_update_bits(component,
376 						      WCD937X_HPH_L_EN,
377 						      BIT(5), 0x00);
378 
379 			if (wcd937x->comp2_enable) {
380 				snd_soc_component_update_bits(component,
381 							      WCD937X_DIGITAL_CDC_COMP_CTL_0,
382 							      BIT(0), BIT(0));
383 				snd_soc_component_update_bits(component,
384 							      WCD937X_HPH_R_EN, BIT(5), 0x00);
385 			}
386 
387 			if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
388 				usleep_range(5000, 5110);
389 				clear_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
390 			}
391 		} else {
392 			snd_soc_component_update_bits(component,
393 						      WCD937X_DIGITAL_CDC_COMP_CTL_0,
394 						      BIT(1), 0x00);
395 			snd_soc_component_update_bits(component,
396 						      WCD937X_HPH_L_EN,
397 						      BIT(5), BIT(5));
398 		}
399 
400 		snd_soc_component_update_bits(component,
401 					      WCD937X_HPH_NEW_INT_HPH_TIMER1,
402 					      BIT(1), 0x00);
403 		break;
404 	case SND_SOC_DAPM_POST_PMD:
405 		snd_soc_component_update_bits(component,
406 					      WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
407 					      0x0f, BIT(0));
408 		break;
409 	}
410 
411 	return 0;
412 }
413 
wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)414 static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
415 					struct snd_kcontrol *kcontrol,
416 					int event)
417 {
418 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
419 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
420 	int hph_mode = wcd937x->hph_mode;
421 
422 	switch (event) {
423 	case SND_SOC_DAPM_PRE_PMU:
424 		wcd937x_rx_clk_enable(component);
425 		snd_soc_component_update_bits(component,
426 					      WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(1), BIT(1));
427 		snd_soc_component_update_bits(component,
428 					      WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, BIT(3), BIT(3));
429 		snd_soc_component_update_bits(component,
430 					      WCD937X_HPH_RDAC_CLK_CTL1, BIT(7), 0x00);
431 		set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
432 		break;
433 	case SND_SOC_DAPM_POST_PMU:
434 		if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
435 			snd_soc_component_update_bits(component,
436 						      WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
437 						      0x0f, BIT(1));
438 		else if (hph_mode == CLS_H_LOHIFI)
439 			snd_soc_component_update_bits(component,
440 						      WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
441 						      0x0f, 0x06);
442 		if (wcd937x->comp2_enable) {
443 			snd_soc_component_update_bits(component,
444 						      WCD937X_DIGITAL_CDC_COMP_CTL_0,
445 						      BIT(0), BIT(0));
446 			snd_soc_component_update_bits(component,
447 						      WCD937X_HPH_R_EN, BIT(5), 0x00);
448 			if (wcd937x->comp1_enable) {
449 				snd_soc_component_update_bits(component,
450 							      WCD937X_DIGITAL_CDC_COMP_CTL_0,
451 							      BIT(1), BIT(1));
452 				snd_soc_component_update_bits(component,
453 							      WCD937X_HPH_L_EN,
454 							      BIT(5), 0x00);
455 			}
456 
457 			if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
458 				usleep_range(5000, 5110);
459 				clear_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
460 			}
461 		} else {
462 			snd_soc_component_update_bits(component,
463 						      WCD937X_DIGITAL_CDC_COMP_CTL_0,
464 						      BIT(0), 0x00);
465 			snd_soc_component_update_bits(component,
466 						      WCD937X_HPH_R_EN,
467 						      BIT(5), BIT(5));
468 		}
469 		snd_soc_component_update_bits(component,
470 					      WCD937X_HPH_NEW_INT_HPH_TIMER1,
471 					      BIT(1), 0x00);
472 		break;
473 	case SND_SOC_DAPM_POST_PMD:
474 		snd_soc_component_update_bits(component,
475 					      WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
476 					      0x0f, BIT(0));
477 		break;
478 	}
479 
480 	return 0;
481 }
482 
wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)483 static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
484 				       struct snd_kcontrol *kcontrol,
485 				       int event)
486 {
487 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
488 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
489 	int hph_mode = wcd937x->hph_mode;
490 
491 	switch (event) {
492 	case SND_SOC_DAPM_PRE_PMU:
493 		wcd937x_rx_clk_enable(component);
494 		snd_soc_component_update_bits(component,
495 					      WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
496 					      BIT(2), BIT(2));
497 		snd_soc_component_update_bits(component,
498 					      WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
499 					      BIT(0), BIT(0));
500 
501 		if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
502 			snd_soc_component_update_bits(component,
503 						      WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
504 						      0x0f, BIT(1));
505 		else if (hph_mode == CLS_H_LOHIFI)
506 			snd_soc_component_update_bits(component,
507 						      WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
508 						      0x0f, 0x06);
509 		if (wcd937x->comp1_enable)
510 			snd_soc_component_update_bits(component,
511 						      WCD937X_DIGITAL_CDC_COMP_CTL_0,
512 						      BIT(1), BIT(1));
513 		usleep_range(5000, 5010);
514 
515 		snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN, BIT(2), 0x00);
516 		wcd_clsh_ctrl_set_state(wcd937x->clsh_info,
517 					WCD_CLSH_EVENT_PRE_DAC,
518 					WCD_CLSH_STATE_EAR,
519 					hph_mode);
520 
521 		break;
522 	case SND_SOC_DAPM_POST_PMD:
523 		if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
524 		    hph_mode == CLS_H_HIFI)
525 			snd_soc_component_update_bits(component,
526 						      WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
527 						      0x0f, BIT(0));
528 		if (wcd937x->comp1_enable)
529 			snd_soc_component_update_bits(component,
530 						      WCD937X_DIGITAL_CDC_COMP_CTL_0,
531 						      BIT(1), 0x00);
532 		break;
533 	}
534 
535 	return 0;
536 }
537 
wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)538 static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
539 				       struct snd_kcontrol *kcontrol,
540 				       int event)
541 {
542 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
543 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
544 	int hph_mode = wcd937x->hph_mode;
545 
546 	switch (event) {
547 	case SND_SOC_DAPM_PRE_PMU:
548 		wcd937x_rx_clk_enable(component);
549 		snd_soc_component_update_bits(component,
550 					      WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
551 					      BIT(2), BIT(2));
552 		snd_soc_component_update_bits(component,
553 					      WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
554 					      BIT(2), BIT(2));
555 		snd_soc_component_update_bits(component,
556 					      WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
557 					      BIT(0), BIT(0));
558 		wcd_clsh_ctrl_set_state(wcd937x->clsh_info,
559 					WCD_CLSH_EVENT_PRE_DAC,
560 					WCD_CLSH_STATE_AUX,
561 					hph_mode);
562 
563 		break;
564 	case SND_SOC_DAPM_POST_PMD:
565 		snd_soc_component_update_bits(component,
566 					      WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
567 					      BIT(2), 0x00);
568 		break;
569 	}
570 
571 	return 0;
572 }
573 
wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)574 static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
575 					struct snd_kcontrol *kcontrol,
576 					int event)
577 {
578 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
579 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
580 	int hph_mode = wcd937x->hph_mode;
581 
582 	switch (event) {
583 	case SND_SOC_DAPM_PRE_PMU:
584 		wcd_clsh_ctrl_set_state(wcd937x->clsh_info,
585 					WCD_CLSH_EVENT_PRE_DAC,
586 					WCD_CLSH_STATE_HPHR,
587 					hph_mode);
588 		snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
589 					      BIT(4), BIT(4));
590 		usleep_range(100, 110);
591 		set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
592 		snd_soc_component_update_bits(component,
593 					      WCD937X_DIGITAL_PDM_WD_CTL1,
594 					      0x07, 0x03);
595 		break;
596 	case SND_SOC_DAPM_POST_PMU:
597 		if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
598 			if (wcd937x->comp2_enable)
599 				usleep_range(7000, 7100);
600 			else
601 				usleep_range(20000, 20100);
602 			clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
603 		}
604 
605 		snd_soc_component_update_bits(component,
606 					      WCD937X_HPH_NEW_INT_HPH_TIMER1,
607 					      BIT(1), BIT(1));
608 		if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
609 			snd_soc_component_update_bits(component,
610 						      WCD937X_ANA_RX_SUPPLIES,
611 						      BIT(1), BIT(1));
612 		enable_irq(wcd937x->hphr_pdm_wd_int);
613 		break;
614 	case SND_SOC_DAPM_PRE_PMD:
615 		disable_irq_nosync(wcd937x->hphr_pdm_wd_int);
616 		set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
617 		wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_PRE_HPHR_PA_OFF);
618 		break;
619 	case SND_SOC_DAPM_POST_PMD:
620 		if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
621 			if (wcd937x->comp2_enable)
622 				usleep_range(7000, 7100);
623 			else
624 				usleep_range(20000, 20100);
625 			clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
626 		}
627 
628 		wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_POST_HPHR_PA_OFF);
629 		snd_soc_component_update_bits(component,
630 					      WCD937X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00);
631 		snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
632 					      BIT(4), 0x00);
633 		wcd_clsh_ctrl_set_state(wcd937x->clsh_info,
634 					WCD_CLSH_EVENT_POST_PA,
635 					WCD_CLSH_STATE_HPHR,
636 					hph_mode);
637 		break;
638 	}
639 
640 	return 0;
641 }
642 
wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)643 static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
644 					struct snd_kcontrol *kcontrol,
645 					int event)
646 {
647 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
648 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
649 	int hph_mode = wcd937x->hph_mode;
650 
651 	switch (event) {
652 	case SND_SOC_DAPM_PRE_PMU:
653 		wcd_clsh_ctrl_set_state(wcd937x->clsh_info,
654 					WCD_CLSH_EVENT_PRE_DAC,
655 					WCD_CLSH_STATE_HPHL,
656 					hph_mode);
657 		snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
658 					      BIT(5), BIT(5));
659 		usleep_range(100, 110);
660 		set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
661 		snd_soc_component_update_bits(component,
662 					      WCD937X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03);
663 		break;
664 	case SND_SOC_DAPM_POST_PMU:
665 		if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
666 			if (!wcd937x->comp1_enable)
667 				usleep_range(20000, 20100);
668 			else
669 				usleep_range(7000, 7100);
670 			clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
671 		}
672 
673 		snd_soc_component_update_bits(component,
674 					      WCD937X_HPH_NEW_INT_HPH_TIMER1,
675 					      BIT(1), BIT(1));
676 		if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
677 			snd_soc_component_update_bits(component,
678 						      WCD937X_ANA_RX_SUPPLIES,
679 						      BIT(1), BIT(1));
680 		enable_irq(wcd937x->hphl_pdm_wd_int);
681 		break;
682 	case SND_SOC_DAPM_PRE_PMD:
683 		disable_irq_nosync(wcd937x->hphl_pdm_wd_int);
684 		set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
685 		wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF);
686 		break;
687 	case SND_SOC_DAPM_POST_PMD:
688 		if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
689 			if (!wcd937x->comp1_enable)
690 				usleep_range(20000, 20100);
691 			else
692 				usleep_range(7000, 7100);
693 			clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
694 		}
695 
696 		wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_POST_HPHL_PA_OFF);
697 		snd_soc_component_update_bits(component,
698 					      WCD937X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00);
699 		snd_soc_component_update_bits(component,
700 					      WCD937X_ANA_HPH, BIT(5), 0x00);
701 		wcd_clsh_ctrl_set_state(wcd937x->clsh_info,
702 					WCD_CLSH_EVENT_POST_PA,
703 					WCD_CLSH_STATE_HPHL,
704 					hph_mode);
705 		break;
706 	}
707 
708 	return 0;
709 }
710 
wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)711 static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
712 				       struct snd_kcontrol *kcontrol,
713 				       int event)
714 {
715 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
716 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
717 	int hph_mode = wcd937x->hph_mode;
718 	u8 val;
719 
720 	switch (event) {
721 	case SND_SOC_DAPM_PRE_PMU:
722 		val = WCD937X_DIGITAL_PDM_WD_CTL2_EN |
723 		      WCD937X_DIGITAL_PDM_WD_CTL2_TIMEOUT_SEL |
724 		      WCD937X_DIGITAL_PDM_WD_CTL2_HOLD_OFF;
725 		snd_soc_component_update_bits(component,
726 					      WCD937X_DIGITAL_PDM_WD_CTL2,
727 					      WCD937X_DIGITAL_PDM_WD_CTL2_MASK,
728 					      val);
729 		break;
730 	case SND_SOC_DAPM_POST_PMU:
731 		usleep_range(1000, 1010);
732 		if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
733 			snd_soc_component_update_bits(component,
734 						      WCD937X_ANA_RX_SUPPLIES,
735 						      BIT(1), BIT(1));
736 		enable_irq(wcd937x->aux_pdm_wd_int);
737 		break;
738 	case SND_SOC_DAPM_PRE_PMD:
739 		disable_irq_nosync(wcd937x->aux_pdm_wd_int);
740 		break;
741 	case SND_SOC_DAPM_POST_PMD:
742 		usleep_range(2000, 2010);
743 		wcd_clsh_ctrl_set_state(wcd937x->clsh_info,
744 					WCD_CLSH_EVENT_POST_PA,
745 					WCD_CLSH_STATE_AUX,
746 					hph_mode);
747 		snd_soc_component_update_bits(component,
748 					      WCD937X_DIGITAL_PDM_WD_CTL2,
749 					      WCD937X_DIGITAL_PDM_WD_CTL2_MASK,
750 					      0x00);
751 		break;
752 	}
753 
754 	return 0;
755 }
756 
wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)757 static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
758 				       struct snd_kcontrol *kcontrol,
759 				       int event)
760 {
761 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
762 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
763 	int hph_mode = wcd937x->hph_mode;
764 
765 	switch (event) {
766 	case SND_SOC_DAPM_PRE_PMU:
767 		/* Enable watchdog interrupt for HPHL or AUX depending on mux value */
768 		wcd937x->ear_rx_path = snd_soc_component_read(component,
769 							      WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
770 
771 		if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
772 			snd_soc_component_update_bits(component,
773 						      WCD937X_DIGITAL_PDM_WD_CTL2,
774 						      BIT(0), BIT(0));
775 		else
776 			snd_soc_component_update_bits(component,
777 						      WCD937X_DIGITAL_PDM_WD_CTL0,
778 						      0x07, 0x03);
779 		if (!wcd937x->comp1_enable)
780 			snd_soc_component_update_bits(component,
781 						      WCD937X_ANA_EAR_COMPANDER_CTL,
782 						      BIT(7), BIT(7));
783 		break;
784 	case SND_SOC_DAPM_POST_PMU:
785 		usleep_range(6000, 6010);
786 		if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
787 			snd_soc_component_update_bits(component,
788 						      WCD937X_ANA_RX_SUPPLIES,
789 						      BIT(1), BIT(1));
790 
791 		if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
792 			enable_irq(wcd937x->aux_pdm_wd_int);
793 		else
794 			enable_irq(wcd937x->hphl_pdm_wd_int);
795 		break;
796 	case SND_SOC_DAPM_PRE_PMD:
797 		if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
798 			disable_irq_nosync(wcd937x->aux_pdm_wd_int);
799 		else
800 			disable_irq_nosync(wcd937x->hphl_pdm_wd_int);
801 		break;
802 	case SND_SOC_DAPM_POST_PMD:
803 		if (!wcd937x->comp1_enable)
804 			snd_soc_component_update_bits(component,
805 						      WCD937X_ANA_EAR_COMPANDER_CTL,
806 						      BIT(7), 0x00);
807 		usleep_range(7000, 7010);
808 		wcd_clsh_ctrl_set_state(wcd937x->clsh_info,
809 					WCD_CLSH_EVENT_POST_PA,
810 					WCD_CLSH_STATE_EAR,
811 					hph_mode);
812 		snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
813 					      BIT(2), BIT(2));
814 
815 		if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
816 			snd_soc_component_update_bits(component,
817 						      WCD937X_DIGITAL_PDM_WD_CTL2,
818 						      BIT(0), 0x00);
819 		else
820 			snd_soc_component_update_bits(component,
821 						      WCD937X_DIGITAL_PDM_WD_CTL0,
822 						      0x07, 0x00);
823 		break;
824 	}
825 
826 	return 0;
827 }
828 
wcd937x_enable_rx1(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)829 static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
830 			      struct snd_kcontrol *kcontrol,
831 			      int event)
832 {
833 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
834 
835 	if (event == SND_SOC_DAPM_POST_PMD) {
836 		wcd937x_rx_clk_disable(component);
837 		snd_soc_component_update_bits(component,
838 					      WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
839 					      BIT(0), 0x00);
840 	}
841 
842 	return 0;
843 }
844 
wcd937x_enable_rx2(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)845 static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
846 			      struct snd_kcontrol *kcontrol, int event)
847 {
848 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
849 
850 	if (event == SND_SOC_DAPM_POST_PMD) {
851 		wcd937x_rx_clk_disable(component);
852 		snd_soc_component_update_bits(component,
853 					      WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
854 					      BIT(1), 0x00);
855 	}
856 
857 	return 0;
858 }
859 
wcd937x_enable_rx3(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)860 static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
861 			      struct snd_kcontrol *kcontrol,
862 			      int event)
863 {
864 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
865 
866 	if (event == SND_SOC_DAPM_POST_PMD) {
867 		usleep_range(6000, 6010);
868 		wcd937x_rx_clk_disable(component);
869 		snd_soc_component_update_bits(component,
870 					      WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
871 					      BIT(2), 0x00);
872 	}
873 
874 	return 0;
875 }
876 
wcd937x_get_micb_vout_ctl_val(u32 micb_mv)877 static int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
878 {
879 	if (micb_mv < 1000 || micb_mv > 2850) {
880 		pr_err("Unsupported micbias voltage (%u mV)\n", micb_mv);
881 		return -EINVAL;
882 	}
883 
884 	return (micb_mv - 1000) / 50;
885 }
886 
wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)887 static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
888 			       struct snd_kcontrol *kcontrol, int event)
889 {
890 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
891 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
892 	bool use_amic3 = snd_soc_component_read(component, WCD937X_TX_NEW_TX_CH2_SEL) & BIT(7);
893 
894 	/* Enable BCS for Headset mic */
895 	if (event == SND_SOC_DAPM_PRE_PMU && strnstr(w->name, "ADC", sizeof("ADC")))
896 		if (w->shift == 1 && !use_amic3)
897 			set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
898 
899 	return 0;
900 }
901 
wcd937x_codec_enable_adc(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)902 static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
903 				    struct snd_kcontrol *kcontrol, int event)
904 {
905 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
906 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
907 
908 	switch (event) {
909 	case SND_SOC_DAPM_PRE_PMU:
910 		atomic_inc(&wcd937x->ana_clk_count);
911 		snd_soc_component_update_bits(component,
912 					      WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(7), BIT(7));
913 		snd_soc_component_update_bits(component,
914 					      WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(3), BIT(3));
915 		snd_soc_component_update_bits(component,
916 					      WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(4), BIT(4));
917 		break;
918 	case SND_SOC_DAPM_POST_PMD:
919 		if (w->shift == 1 && test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask))
920 			clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
921 
922 		snd_soc_component_update_bits(component,
923 					      WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(3), 0x00);
924 		break;
925 	}
926 
927 	return 0;
928 }
929 
wcd937x_enable_req(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)930 static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
931 			      struct snd_kcontrol *kcontrol, int event)
932 {
933 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
934 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
935 
936 	switch (event) {
937 	case SND_SOC_DAPM_PRE_PMU:
938 		snd_soc_component_update_bits(component,
939 					      WCD937X_DIGITAL_CDC_REQ_CTL, BIT(1), BIT(1));
940 		snd_soc_component_update_bits(component,
941 					      WCD937X_DIGITAL_CDC_REQ_CTL, BIT(0), 0x00);
942 		snd_soc_component_update_bits(component,
943 					      WCD937X_ANA_TX_CH2, BIT(6), BIT(6));
944 		snd_soc_component_update_bits(component,
945 					      WCD937X_ANA_TX_CH3_HPF, BIT(6), BIT(6));
946 		snd_soc_component_update_bits(component,
947 					      WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70);
948 		snd_soc_component_update_bits(component,
949 					      WCD937X_ANA_TX_CH1, BIT(7), BIT(7));
950 		snd_soc_component_update_bits(component,
951 					      WCD937X_ANA_TX_CH2, BIT(6), 0x00);
952 		snd_soc_component_update_bits(component,
953 					      WCD937X_ANA_TX_CH2, BIT(7), BIT(7));
954 		snd_soc_component_update_bits(component,
955 					      WCD937X_ANA_TX_CH3, BIT(7), BIT(7));
956 		break;
957 	case SND_SOC_DAPM_POST_PMD:
958 		snd_soc_component_update_bits(component,
959 					      WCD937X_ANA_TX_CH1, BIT(7), 0x00);
960 		snd_soc_component_update_bits(component,
961 					      WCD937X_ANA_TX_CH2, BIT(7), 0x00);
962 		snd_soc_component_update_bits(component,
963 					      WCD937X_ANA_TX_CH3, BIT(7), 0x00);
964 		snd_soc_component_update_bits(component,
965 					      WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(4), 0x00);
966 
967 		atomic_dec(&wcd937x->ana_clk_count);
968 		if (atomic_read(&wcd937x->ana_clk_count) <= 0) {
969 			snd_soc_component_update_bits(component,
970 						      WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
971 						      BIT(4), 0x00);
972 			atomic_set(&wcd937x->ana_clk_count, 0);
973 		}
974 
975 		snd_soc_component_update_bits(component,
976 					      WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
977 					      BIT(7), 0x00);
978 		break;
979 	}
980 
981 	return 0;
982 }
983 
wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)984 static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
985 				     struct snd_kcontrol *kcontrol,
986 				     int event)
987 {
988 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
989 	u16 dmic_clk_reg;
990 
991 	switch (w->shift) {
992 	case 0:
993 	case 1:
994 		dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
995 		break;
996 	case 2:
997 	case 3:
998 		dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
999 		break;
1000 	case 4:
1001 	case 5:
1002 		dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL;
1003 		break;
1004 	default:
1005 		dev_err(component->dev, "Invalid DMIC Selection\n");
1006 		return -EINVAL;
1007 	}
1008 
1009 	switch (event) {
1010 	case SND_SOC_DAPM_PRE_PMU:
1011 		snd_soc_component_update_bits(component,
1012 					      WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
1013 					      BIT(7), BIT(7));
1014 		snd_soc_component_update_bits(component,
1015 					      dmic_clk_reg, 0x07, BIT(1));
1016 		snd_soc_component_update_bits(component,
1017 					      dmic_clk_reg, BIT(3), BIT(3));
1018 		snd_soc_component_update_bits(component,
1019 					      dmic_clk_reg, 0x70, BIT(5));
1020 		break;
1021 	}
1022 
1023 	return 0;
1024 }
1025 
wcd937x_micbias_control(struct snd_soc_component * component,int micb_num,int req,bool is_dapm)1026 static int wcd937x_micbias_control(struct snd_soc_component *component,
1027 				   int micb_num, int req, bool is_dapm)
1028 {
1029 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1030 	int micb_index = micb_num - 1;
1031 	u16 micb_reg;
1032 
1033 	if (micb_index < 0 || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
1034 		dev_err(component->dev, "Invalid micbias index, micb_ind:%d\n", micb_index);
1035 		return -EINVAL;
1036 	}
1037 	switch (micb_num) {
1038 	case MIC_BIAS_1:
1039 		micb_reg = WCD937X_ANA_MICB1;
1040 		break;
1041 	case MIC_BIAS_2:
1042 		micb_reg = WCD937X_ANA_MICB2;
1043 		break;
1044 	case MIC_BIAS_3:
1045 		micb_reg = WCD937X_ANA_MICB3;
1046 		break;
1047 	default:
1048 		dev_err(component->dev, "Invalid micbias number: %d\n", micb_num);
1049 		return -EINVAL;
1050 	}
1051 
1052 	mutex_lock(&wcd937x->micb_lock);
1053 	switch (req) {
1054 	case MICB_PULLUP_ENABLE:
1055 		wcd937x->pullup_ref[micb_index]++;
1056 		if (wcd937x->pullup_ref[micb_index] == 1 &&
1057 		    wcd937x->micb_ref[micb_index] == 0)
1058 			snd_soc_component_update_bits(component, micb_reg,
1059 						      0xc0, BIT(7));
1060 		break;
1061 	case MICB_PULLUP_DISABLE:
1062 		if (wcd937x->pullup_ref[micb_index] > 0)
1063 			wcd937x->pullup_ref[micb_index]++;
1064 		if (wcd937x->pullup_ref[micb_index] == 0 &&
1065 		    wcd937x->micb_ref[micb_index] == 0)
1066 			snd_soc_component_update_bits(component, micb_reg,
1067 						      0xc0, 0x00);
1068 		break;
1069 	case MICB_ENABLE:
1070 		wcd937x->micb_ref[micb_index]++;
1071 		atomic_inc(&wcd937x->ana_clk_count);
1072 		if (wcd937x->micb_ref[micb_index] == 1) {
1073 			snd_soc_component_update_bits(component,
1074 						      WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
1075 						      0xf0, 0xf0);
1076 			snd_soc_component_update_bits(component,
1077 						      WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
1078 						      BIT(4), BIT(4));
1079 			snd_soc_component_update_bits(component,
1080 						      WCD937X_MICB1_TEST_CTL_2,
1081 						      BIT(0), BIT(0));
1082 			snd_soc_component_update_bits(component,
1083 						      WCD937X_MICB2_TEST_CTL_2,
1084 						      BIT(0), BIT(0));
1085 			snd_soc_component_update_bits(component,
1086 						      WCD937X_MICB3_TEST_CTL_2,
1087 						      BIT(0), BIT(0));
1088 			snd_soc_component_update_bits(component,
1089 						      micb_reg, 0xc0, BIT(6));
1090 
1091 			if (micb_num == MIC_BIAS_2)
1092 				wcd_mbhc_event_notify(wcd937x->wcd_mbhc,
1093 						      WCD_EVENT_POST_MICBIAS_2_ON);
1094 
1095 			if (micb_num == MIC_BIAS_2 && is_dapm)
1096 				wcd_mbhc_event_notify(wcd937x->wcd_mbhc,
1097 						      WCD_EVENT_POST_DAPM_MICBIAS_2_ON);
1098 		}
1099 		break;
1100 	case MICB_DISABLE:
1101 		atomic_dec(&wcd937x->ana_clk_count);
1102 		if (wcd937x->micb_ref[micb_index] > 0)
1103 			wcd937x->micb_ref[micb_index]--;
1104 		if (wcd937x->micb_ref[micb_index] == 0 &&
1105 		    wcd937x->pullup_ref[micb_index] > 0)
1106 			snd_soc_component_update_bits(component, micb_reg,
1107 						      0xc0, BIT(7));
1108 		else if (wcd937x->micb_ref[micb_index] == 0 &&
1109 			 wcd937x->pullup_ref[micb_index] == 0) {
1110 			if (micb_num == MIC_BIAS_2)
1111 				wcd_mbhc_event_notify(wcd937x->wcd_mbhc,
1112 						      WCD_EVENT_PRE_MICBIAS_2_OFF);
1113 
1114 			snd_soc_component_update_bits(component, micb_reg,
1115 						      0xc0, 0x00);
1116 			if (micb_num == MIC_BIAS_2)
1117 				wcd_mbhc_event_notify(wcd937x->wcd_mbhc,
1118 						      WCD_EVENT_POST_MICBIAS_2_OFF);
1119 		}
1120 
1121 		if (is_dapm && micb_num == MIC_BIAS_2)
1122 			wcd_mbhc_event_notify(wcd937x->wcd_mbhc,
1123 					      WCD_EVENT_POST_DAPM_MICBIAS_2_OFF);
1124 		if (atomic_read(&wcd937x->ana_clk_count) <= 0) {
1125 			snd_soc_component_update_bits(component,
1126 						      WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
1127 						      BIT(4), 0x00);
1128 			atomic_set(&wcd937x->ana_clk_count, 0);
1129 		}
1130 		break;
1131 	}
1132 	mutex_unlock(&wcd937x->micb_lock);
1133 
1134 	return 0;
1135 }
1136 
__wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget * w,int event)1137 static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
1138 					  int event)
1139 {
1140 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1141 	int micb_num = w->shift;
1142 
1143 	switch (event) {
1144 	case SND_SOC_DAPM_PRE_PMU:
1145 		wcd937x_micbias_control(component, micb_num,
1146 					MICB_ENABLE, true);
1147 		break;
1148 	case SND_SOC_DAPM_POST_PMU:
1149 		usleep_range(1000, 1100);
1150 		break;
1151 	case SND_SOC_DAPM_POST_PMD:
1152 		wcd937x_micbias_control(component, micb_num,
1153 					MICB_DISABLE, true);
1154 		break;
1155 	}
1156 
1157 	return 0;
1158 }
1159 
wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1160 static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
1161 					struct snd_kcontrol *kcontrol,
1162 					int event)
1163 {
1164 	return __wcd937x_codec_enable_micbias(w, event);
1165 }
1166 
__wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget * w,int event)1167 static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
1168 						 int event)
1169 {
1170 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1171 	int micb_num = w->shift;
1172 
1173 	switch (event) {
1174 	case SND_SOC_DAPM_PRE_PMU:
1175 		wcd937x_micbias_control(component, micb_num, MICB_PULLUP_ENABLE, true);
1176 		break;
1177 	case SND_SOC_DAPM_POST_PMU:
1178 		usleep_range(1000, 1100);
1179 		break;
1180 	case SND_SOC_DAPM_POST_PMD:
1181 		wcd937x_micbias_control(component, micb_num, MICB_PULLUP_DISABLE, true);
1182 		break;
1183 	}
1184 
1185 	return 0;
1186 }
1187 
wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1188 static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
1189 					       struct snd_kcontrol *kcontrol,
1190 					       int event)
1191 {
1192 	return __wcd937x_codec_enable_micbias_pullup(w, event);
1193 }
1194 
wcd937x_connect_port(struct wcd937x_sdw_priv * wcd,u8 port_idx,u8 ch_id,bool enable)1195 static int wcd937x_connect_port(struct wcd937x_sdw_priv *wcd, u8 port_idx, u8 ch_id, bool enable)
1196 {
1197 	struct sdw_port_config *port_config = &wcd->port_config[port_idx - 1];
1198 	const struct wcd937x_sdw_ch_info *ch_info = &wcd->ch_info[ch_id];
1199 	u8 port_num = ch_info->port_num;
1200 	u8 ch_mask = ch_info->ch_mask;
1201 
1202 	port_config->num = port_num;
1203 
1204 	if (enable)
1205 		port_config->ch_mask |= ch_mask;
1206 	else
1207 		port_config->ch_mask &= ~ch_mask;
1208 
1209 	return 0;
1210 }
1211 
wcd937x_rx_hph_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1212 static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
1213 				   struct snd_ctl_elem_value *ucontrol)
1214 {
1215 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1216 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1217 
1218 	ucontrol->value.integer.value[0] = wcd937x->hph_mode;
1219 	return 0;
1220 }
1221 
wcd937x_rx_hph_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1222 static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
1223 				   struct snd_ctl_elem_value *ucontrol)
1224 {
1225 	struct snd_soc_component *component =
1226 				snd_soc_kcontrol_component(kcontrol);
1227 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1228 	u32 mode_val;
1229 
1230 	mode_val = ucontrol->value.enumerated.item[0];
1231 
1232 	if (!mode_val)
1233 		mode_val = CLS_AB;
1234 
1235 	if (mode_val == wcd937x->hph_mode)
1236 		return 0;
1237 
1238 	switch (mode_val) {
1239 	case CLS_H_NORMAL:
1240 	case CLS_H_HIFI:
1241 	case CLS_H_LP:
1242 	case CLS_AB:
1243 	case CLS_H_LOHIFI:
1244 	case CLS_H_ULP:
1245 	case CLS_AB_LP:
1246 	case CLS_AB_HIFI:
1247 		wcd937x->hph_mode = mode_val;
1248 		return 1;
1249 	}
1250 
1251 	dev_dbg(component->dev, "%s: Invalid HPH Mode\n", __func__);
1252 	return -EINVAL;
1253 }
1254 
wcd937x_get_compander(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1255 static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
1256 				 struct snd_ctl_elem_value *ucontrol)
1257 {
1258 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1259 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1260 	struct soc_mixer_control *mc;
1261 	bool hphr;
1262 
1263 	mc = (struct soc_mixer_control *)(kcontrol->private_value);
1264 	hphr = mc->shift;
1265 
1266 	ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
1267 						  wcd937x->comp1_enable;
1268 	return 0;
1269 }
1270 
wcd937x_set_compander(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1271 static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
1272 				 struct snd_ctl_elem_value *ucontrol)
1273 {
1274 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1275 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1276 	struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[AIF1_PB];
1277 	int value = ucontrol->value.integer.value[0];
1278 	struct soc_mixer_control *mc;
1279 	int portidx;
1280 	bool hphr;
1281 
1282 	mc = (struct soc_mixer_control *)(kcontrol->private_value);
1283 	hphr = mc->shift;
1284 
1285 	if (hphr) {
1286 		if (value == wcd937x->comp2_enable)
1287 			return 0;
1288 
1289 		wcd937x->comp2_enable = value;
1290 	} else {
1291 		if (value == wcd937x->comp1_enable)
1292 			return 0;
1293 
1294 		wcd937x->comp1_enable = value;
1295 	}
1296 
1297 	portidx = wcd->ch_info[mc->reg].port_num;
1298 
1299 	if (value)
1300 		wcd937x_connect_port(wcd, portidx, mc->reg, true);
1301 	else
1302 		wcd937x_connect_port(wcd, portidx, mc->reg, false);
1303 
1304 	return 1;
1305 }
1306 
wcd937x_get_swr_port(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1307 static int wcd937x_get_swr_port(struct snd_kcontrol *kcontrol,
1308 				struct snd_ctl_elem_value *ucontrol)
1309 {
1310 	struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1311 	struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1312 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(comp);
1313 	struct wcd937x_sdw_priv *wcd;
1314 	int dai_id = mixer->shift;
1315 	int ch_idx = mixer->reg;
1316 	int portidx;
1317 
1318 	wcd = wcd937x->sdw_priv[dai_id];
1319 	portidx = wcd->ch_info[ch_idx].port_num;
1320 
1321 	ucontrol->value.integer.value[0] = wcd->port_enable[portidx];
1322 
1323 	return 0;
1324 }
1325 
wcd937x_set_swr_port(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1326 static int wcd937x_set_swr_port(struct snd_kcontrol *kcontrol,
1327 				struct snd_ctl_elem_value *ucontrol)
1328 {
1329 	struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1330 	struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1331 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(comp);
1332 	struct wcd937x_sdw_priv *wcd;
1333 	int dai_id = mixer->shift;
1334 	int ch_idx = mixer->reg;
1335 	int portidx;
1336 	bool enable;
1337 
1338 	wcd = wcd937x->sdw_priv[dai_id];
1339 
1340 	portidx = wcd->ch_info[ch_idx].port_num;
1341 
1342 	enable = ucontrol->value.integer.value[0];
1343 
1344 	if (enable == wcd->port_enable[portidx]) {
1345 		wcd937x_connect_port(wcd, portidx, ch_idx, enable);
1346 		return 0;
1347 	}
1348 
1349 	wcd->port_enable[portidx] = enable;
1350 	wcd937x_connect_port(wcd, portidx, ch_idx, enable);
1351 
1352 	return 1;
1353 }
1354 
1355 static const char * const rx_hph_mode_mux_text[] = {
1356 	"CLS_H_NORMAL", "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB",
1357 	"CLS_H_LOHIFI", "CLS_H_ULP", "CLS_AB_LP", "CLS_AB_HIFI",
1358 };
1359 
1360 static const struct soc_enum rx_hph_mode_mux_enum =
1361 	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), rx_hph_mode_mux_text);
1362 
1363 /* MBHC related */
wcd937x_mbhc_clk_setup(struct snd_soc_component * component,bool enable)1364 static void wcd937x_mbhc_clk_setup(struct snd_soc_component *component,
1365 				   bool enable)
1366 {
1367 	snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_1,
1368 				      WCD937X_MBHC_CTL_RCO_EN_MASK, enable);
1369 }
1370 
wcd937x_mbhc_mbhc_bias_control(struct snd_soc_component * component,bool enable)1371 static void wcd937x_mbhc_mbhc_bias_control(struct snd_soc_component *component,
1372 					   bool enable)
1373 {
1374 	snd_soc_component_write_field(component, WCD937X_ANA_MBHC_ELECT,
1375 				      WCD937X_ANA_MBHC_BIAS_EN, enable);
1376 }
1377 
wcd937x_mbhc_program_btn_thr(struct snd_soc_component * component,int * btn_low,int * btn_high,int num_btn,bool is_micbias)1378 static void wcd937x_mbhc_program_btn_thr(struct snd_soc_component *component,
1379 					 int *btn_low, int *btn_high,
1380 					 int num_btn, bool is_micbias)
1381 {
1382 	int i, vth;
1383 
1384 	if (num_btn > WCD_MBHC_DEF_BUTTONS) {
1385 		dev_err(component->dev, "%s: invalid number of buttons: %d\n",
1386 			__func__, num_btn);
1387 		return;
1388 	}
1389 
1390 	for (i = 0; i < num_btn; i++) {
1391 		vth = ((btn_high[i] * 2) / 25) & 0x3F;
1392 		snd_soc_component_write_field(component, WCD937X_ANA_MBHC_BTN0 + i,
1393 					      WCD937X_MBHC_BTN_VTH_MASK, vth);
1394 	}
1395 }
1396 
wcd937x_mbhc_micb_en_status(struct snd_soc_component * component,int micb_num)1397 static bool wcd937x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num)
1398 {
1399 	u8 val;
1400 
1401 	if (micb_num == MIC_BIAS_2) {
1402 		val = snd_soc_component_read_field(component,
1403 						   WCD937X_ANA_MICB2,
1404 						   WCD937X_ANA_MICB2_ENABLE_MASK);
1405 		if (val == WCD937X_MICB_ENABLE)
1406 			return true;
1407 	}
1408 	return false;
1409 }
1410 
wcd937x_mbhc_hph_l_pull_up_control(struct snd_soc_component * component,int pull_up_cur)1411 static void wcd937x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component,
1412 					       int pull_up_cur)
1413 {
1414 	/* Default pull up current to 2uA */
1415 	if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA)
1416 		pull_up_cur = HS_PULLUP_I_2P0_UA;
1417 
1418 	snd_soc_component_write_field(component,
1419 				      WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT,
1420 				      WCD937X_HSDET_PULLUP_C_MASK, pull_up_cur);
1421 }
1422 
wcd937x_mbhc_request_micbias(struct snd_soc_component * component,int micb_num,int req)1423 static int wcd937x_mbhc_request_micbias(struct snd_soc_component *component,
1424 					int micb_num, int req)
1425 {
1426 	return wcd937x_micbias_control(component, micb_num, req, false);
1427 }
1428 
wcd937x_mbhc_micb_ramp_control(struct snd_soc_component * component,bool enable)1429 static void wcd937x_mbhc_micb_ramp_control(struct snd_soc_component *component,
1430 					   bool enable)
1431 {
1432 	if (enable) {
1433 		snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP,
1434 					      WCD937X_RAMP_SHIFT_CTRL_MASK, 0x0C);
1435 		snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP,
1436 					      WCD937X_RAMP_EN_MASK, 1);
1437 	} else {
1438 		snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP,
1439 					      WCD937X_RAMP_EN_MASK, 0);
1440 		snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP,
1441 					      WCD937X_RAMP_SHIFT_CTRL_MASK, 0);
1442 	}
1443 }
1444 
wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component * component,int req_volt,int micb_num)1445 static int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
1446 					    int req_volt, int micb_num)
1447 {
1448 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1449 	int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0;
1450 
1451 	switch (micb_num) {
1452 	case MIC_BIAS_1:
1453 		micb_reg = WCD937X_ANA_MICB1;
1454 		break;
1455 	case MIC_BIAS_2:
1456 		micb_reg = WCD937X_ANA_MICB2;
1457 		break;
1458 	case MIC_BIAS_3:
1459 		micb_reg = WCD937X_ANA_MICB3;
1460 		break;
1461 	default:
1462 		return -EINVAL;
1463 	}
1464 	mutex_lock(&wcd937x->micb_lock);
1465 	/*
1466 	 * If requested micbias voltage is same as current micbias
1467 	 * voltage, then just return. Otherwise, adjust voltage as
1468 	 * per requested value. If micbias is already enabled, then
1469 	 * to avoid slow micbias ramp-up or down enable pull-up
1470 	 * momentarily, change the micbias value and then re-enable
1471 	 * micbias.
1472 	 */
1473 	micb_en = snd_soc_component_read_field(component, micb_reg,
1474 					       WCD937X_MICB_EN_MASK);
1475 	cur_vout_ctl = snd_soc_component_read_field(component, micb_reg,
1476 						    WCD937X_MICB_VOUT_MASK);
1477 
1478 	req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
1479 	if (req_vout_ctl < 0) {
1480 		ret = -EINVAL;
1481 		goto exit;
1482 	}
1483 
1484 	if (cur_vout_ctl == req_vout_ctl) {
1485 		ret = 0;
1486 		goto exit;
1487 	}
1488 
1489 	if (micb_en == WCD937X_MICB_ENABLE)
1490 		snd_soc_component_write_field(component, micb_reg,
1491 					      WCD937X_MICB_EN_MASK,
1492 					      WCD937X_MICB_PULL_UP);
1493 
1494 	snd_soc_component_write_field(component, micb_reg,
1495 				      WCD937X_MICB_VOUT_MASK,
1496 				      req_vout_ctl);
1497 
1498 	if (micb_en == WCD937X_MICB_ENABLE) {
1499 		snd_soc_component_write_field(component, micb_reg,
1500 					      WCD937X_MICB_EN_MASK,
1501 					      WCD937X_MICB_ENABLE);
1502 		/*
1503 		 * Add 2ms delay as per HW requirement after enabling
1504 		 * micbias
1505 		 */
1506 		usleep_range(2000, 2100);
1507 	}
1508 exit:
1509 	mutex_unlock(&wcd937x->micb_lock);
1510 	return ret;
1511 }
1512 
wcd937x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component * component,int micb_num,bool req_en)1513 static int wcd937x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component,
1514 						int micb_num, bool req_en)
1515 {
1516 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1517 	int micb_mv;
1518 
1519 	if (micb_num != MIC_BIAS_2)
1520 		return -EINVAL;
1521 	/*
1522 	 * If device tree micbias level is already above the minimum
1523 	 * voltage needed to detect threshold microphone, then do
1524 	 * not change the micbias, just return.
1525 	 */
1526 	if (wcd937x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
1527 		return 0;
1528 
1529 	micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd937x->micb2_mv;
1530 
1531 	return wcd937x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
1532 }
1533 
wcd937x_mbhc_get_result_params(struct snd_soc_component * component,s16 * d1_a,u16 noff,int32_t * zdet)1534 static void wcd937x_mbhc_get_result_params(struct snd_soc_component *component,
1535 					   s16 *d1_a, u16 noff,
1536 					   int32_t *zdet)
1537 {
1538 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1539 	int i;
1540 	int val, val1;
1541 	s16 c1;
1542 	s32 x1, d1;
1543 	s32 denom;
1544 	static const int minCode_param[] = {
1545 		3277, 1639, 820, 410, 205, 103, 52, 26
1546 	};
1547 
1548 	regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MBHC_ZDET, 0x20, 0x20);
1549 	for (i = 0; i < WCD937X_ZDET_NUM_MEASUREMENTS; i++) {
1550 		regmap_read(wcd937x->regmap, WCD937X_ANA_MBHC_RESULT_2, &val);
1551 		if (val & 0x80)
1552 			break;
1553 	}
1554 	val = val << 0x8;
1555 	regmap_read(wcd937x->regmap, WCD937X_ANA_MBHC_RESULT_1, &val1);
1556 	val |= val1;
1557 	regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MBHC_ZDET, 0x20, 0x00);
1558 	x1 = WCD937X_MBHC_GET_X1(val);
1559 	c1 = WCD937X_MBHC_GET_C1(val);
1560 	/* If ramp is not complete, give additional 5ms */
1561 	if (c1 < 2 && x1)
1562 		usleep_range(5000, 5050);
1563 
1564 	if (!c1 || !x1) {
1565 		dev_err(component->dev, "Impedance detect ramp error, c1=%d, x1=0x%x\n",
1566 			c1, x1);
1567 		goto ramp_down;
1568 	}
1569 	d1 = d1_a[c1];
1570 	denom = (x1 * d1) - (1 << (14 - noff));
1571 	if (denom > 0)
1572 		*zdet = (WCD937X_MBHC_ZDET_CONST * 1000) / denom;
1573 	else if (x1 < minCode_param[noff])
1574 		*zdet = WCD937X_ZDET_FLOATING_IMPEDANCE;
1575 
1576 	dev_err(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d (milliohm)\n",
1577 		__func__, d1, c1, x1, *zdet);
1578 ramp_down:
1579 	i = 0;
1580 	while (x1) {
1581 		regmap_read(wcd937x->regmap,
1582 			    WCD937X_ANA_MBHC_RESULT_1, &val);
1583 		regmap_read(wcd937x->regmap,
1584 			    WCD937X_ANA_MBHC_RESULT_2, &val1);
1585 		val = val << 0x08;
1586 		val |= val1;
1587 		x1 = WCD937X_MBHC_GET_X1(val);
1588 		i++;
1589 		if (i == WCD937X_ZDET_NUM_MEASUREMENTS)
1590 			break;
1591 	}
1592 }
1593 
wcd937x_mbhc_zdet_ramp(struct snd_soc_component * component,struct wcd937x_mbhc_zdet_param * zdet_param,s32 * zl,s32 * zr,s16 * d1_a)1594 static void wcd937x_mbhc_zdet_ramp(struct snd_soc_component *component,
1595 				   struct wcd937x_mbhc_zdet_param *zdet_param,
1596 				   s32 *zl, s32 *zr, s16 *d1_a)
1597 {
1598 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1599 	s32 zdet = 0;
1600 
1601 	snd_soc_component_write_field(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL,
1602 				      WCD937X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl);
1603 	snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN5,
1604 				      WCD937X_VTH_MASK, zdet_param->btn5);
1605 	snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN6,
1606 				      WCD937X_VTH_MASK, zdet_param->btn6);
1607 	snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN7,
1608 				      WCD937X_VTH_MASK, zdet_param->btn7);
1609 	snd_soc_component_write_field(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL,
1610 				      WCD937X_ZDET_RANGE_CTL_MASK, zdet_param->noff);
1611 	snd_soc_component_update_bits(component, WCD937X_MBHC_NEW_ZDET_RAMP_CTL,
1612 				      0x0F, zdet_param->nshift);
1613 
1614 	if (!zl)
1615 		goto z_right;
1616 	/* Start impedance measurement for HPH_L */
1617 	regmap_update_bits(wcd937x->regmap,
1618 			   WCD937X_ANA_MBHC_ZDET, 0x80, 0x80);
1619 	wcd937x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet);
1620 	regmap_update_bits(wcd937x->regmap,
1621 			   WCD937X_ANA_MBHC_ZDET, 0x80, 0x00);
1622 
1623 	*zl = zdet;
1624 
1625 z_right:
1626 	if (!zr)
1627 		return;
1628 	/* Start impedance measurement for HPH_R */
1629 	regmap_update_bits(wcd937x->regmap,
1630 			   WCD937X_ANA_MBHC_ZDET, 0x40, 0x40);
1631 	wcd937x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet);
1632 	regmap_update_bits(wcd937x->regmap,
1633 			   WCD937X_ANA_MBHC_ZDET, 0x40, 0x00);
1634 
1635 	*zr = zdet;
1636 }
1637 
wcd937x_wcd_mbhc_qfuse_cal(struct snd_soc_component * component,s32 * z_val,int flag_l_r)1638 static void wcd937x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component,
1639 				       s32 *z_val, int flag_l_r)
1640 {
1641 	s16 q1;
1642 	int q1_cal;
1643 
1644 	if (*z_val < (WCD937X_ZDET_VAL_400 / 1000))
1645 		q1 = snd_soc_component_read(component,
1646 					    WCD937X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r));
1647 	else
1648 		q1 = snd_soc_component_read(component,
1649 					    WCD937X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r));
1650 	if (q1 & 0x80)
1651 		q1_cal = (10000 - ((q1 & 0x7F) * 25));
1652 	else
1653 		q1_cal = (10000 + (q1 * 25));
1654 	if (q1_cal > 0)
1655 		*z_val = ((*z_val) * 10000) / q1_cal;
1656 }
1657 
wcd937x_wcd_mbhc_calc_impedance(struct snd_soc_component * component,u32 * zl,u32 * zr)1658 static void wcd937x_wcd_mbhc_calc_impedance(struct snd_soc_component *component,
1659 					    u32 *zl, u32 *zr)
1660 {
1661 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1662 	s16 reg0, reg1, reg2, reg3, reg4;
1663 	s32 z1l, z1r, z1ls;
1664 	int zMono, z_diff1, z_diff2;
1665 	bool is_fsm_disable = false;
1666 	struct wcd937x_mbhc_zdet_param zdet_param[] = {
1667 		{4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */
1668 		{2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */
1669 		{1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */
1670 		{1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */
1671 	};
1672 	struct wcd937x_mbhc_zdet_param *zdet_param_ptr = NULL;
1673 	s16 d1_a[][4] = {
1674 		{0, 30, 90, 30},
1675 		{0, 30, 30, 5},
1676 		{0, 30, 30, 5},
1677 		{0, 30, 30, 5},
1678 	};
1679 	s16 *d1 = NULL;
1680 
1681 	reg0 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN5);
1682 	reg1 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN6);
1683 	reg2 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN7);
1684 	reg3 = snd_soc_component_read(component, WCD937X_MBHC_CTL_CLK);
1685 	reg4 = snd_soc_component_read(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL);
1686 
1687 	if (snd_soc_component_read(component, WCD937X_ANA_MBHC_ELECT) & 0x80) {
1688 		is_fsm_disable = true;
1689 		regmap_update_bits(wcd937x->regmap,
1690 				   WCD937X_ANA_MBHC_ELECT, 0x80, 0x00);
1691 	}
1692 
1693 	/* For NO-jack, disable L_DET_EN before Z-det measurements */
1694 	if (wcd937x->mbhc_cfg.hphl_swh)
1695 		regmap_update_bits(wcd937x->regmap,
1696 				   WCD937X_ANA_MBHC_MECH, 0x80, 0x00);
1697 
1698 	/* Turn off 100k pull down on HPHL */
1699 	regmap_update_bits(wcd937x->regmap,
1700 			   WCD937X_ANA_MBHC_MECH, 0x01, 0x00);
1701 
1702 	/* Disable surge protection before impedance detection.
1703 	 * This is done to give correct value for high impedance.
1704 	 */
1705 	regmap_update_bits(wcd937x->regmap,
1706 			   WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00);
1707 	/* 1ms delay needed after disable surge protection */
1708 	usleep_range(1000, 1010);
1709 
1710 	/* First get impedance on Left */
1711 	d1 = d1_a[1];
1712 	zdet_param_ptr = &zdet_param[1];
1713 	wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1l, NULL, d1);
1714 
1715 	if (!WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z1l))
1716 		goto left_ch_impedance;
1717 
1718 	/* Second ramp for left ch */
1719 	if (z1l < WCD937X_ZDET_VAL_32) {
1720 		zdet_param_ptr = &zdet_param[0];
1721 		d1 = d1_a[0];
1722 	} else if ((z1l > WCD937X_ZDET_VAL_400) &&
1723 		  (z1l <= WCD937X_ZDET_VAL_1200)) {
1724 		zdet_param_ptr = &zdet_param[2];
1725 		d1 = d1_a[2];
1726 	} else if (z1l > WCD937X_ZDET_VAL_1200) {
1727 		zdet_param_ptr = &zdet_param[3];
1728 		d1 = d1_a[3];
1729 	}
1730 	wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1l, NULL, d1);
1731 
1732 left_ch_impedance:
1733 	if (z1l == WCD937X_ZDET_FLOATING_IMPEDANCE ||
1734 	    z1l > WCD937X_ZDET_VAL_100K) {
1735 		*zl = WCD937X_ZDET_FLOATING_IMPEDANCE;
1736 		zdet_param_ptr = &zdet_param[1];
1737 		d1 = d1_a[1];
1738 	} else {
1739 		*zl = z1l / 1000;
1740 		wcd937x_wcd_mbhc_qfuse_cal(component, zl, 0);
1741 	}
1742 
1743 	/* Start of right impedance ramp and calculation */
1744 	wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1r, d1);
1745 	if (WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z1r)) {
1746 		if ((z1r > WCD937X_ZDET_VAL_1200 &&
1747 		     zdet_param_ptr->noff == 0x6) ||
1748 		     ((*zl) != WCD937X_ZDET_FLOATING_IMPEDANCE))
1749 			goto right_ch_impedance;
1750 		/* Second ramp for right ch */
1751 		if (z1r < WCD937X_ZDET_VAL_32) {
1752 			zdet_param_ptr = &zdet_param[0];
1753 			d1 = d1_a[0];
1754 		} else if ((z1r > WCD937X_ZDET_VAL_400) &&
1755 			(z1r <= WCD937X_ZDET_VAL_1200)) {
1756 			zdet_param_ptr = &zdet_param[2];
1757 			d1 = d1_a[2];
1758 		} else if (z1r > WCD937X_ZDET_VAL_1200) {
1759 			zdet_param_ptr = &zdet_param[3];
1760 			d1 = d1_a[3];
1761 		}
1762 		wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1r, d1);
1763 	}
1764 right_ch_impedance:
1765 	if (z1r == WCD937X_ZDET_FLOATING_IMPEDANCE ||
1766 	    z1r > WCD937X_ZDET_VAL_100K) {
1767 		*zr = WCD937X_ZDET_FLOATING_IMPEDANCE;
1768 	} else {
1769 		*zr = z1r / 1000;
1770 		wcd937x_wcd_mbhc_qfuse_cal(component, zr, 1);
1771 	}
1772 
1773 	/* Mono/stereo detection */
1774 	if ((*zl == WCD937X_ZDET_FLOATING_IMPEDANCE) &&
1775 	    (*zr == WCD937X_ZDET_FLOATING_IMPEDANCE)) {
1776 		dev_err(component->dev,
1777 			"%s: plug type is invalid or extension cable\n",
1778 			__func__);
1779 		goto zdet_complete;
1780 	}
1781 	if ((*zl == WCD937X_ZDET_FLOATING_IMPEDANCE) ||
1782 	    (*zr == WCD937X_ZDET_FLOATING_IMPEDANCE) ||
1783 	    ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) ||
1784 	    ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) {
1785 		wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_MONO);
1786 		goto zdet_complete;
1787 	}
1788 	snd_soc_component_write_field(component, WCD937X_HPH_R_ATEST,
1789 				      WCD937X_HPHPA_GND_OVR_MASK, 1);
1790 	snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2,
1791 				      WCD937X_HPHPA_GND_R_MASK, 1);
1792 	if (*zl < (WCD937X_ZDET_VAL_32 / 1000))
1793 		wcd937x_mbhc_zdet_ramp(component, &zdet_param[0], &z1ls, NULL, d1);
1794 	else
1795 		wcd937x_mbhc_zdet_ramp(component, &zdet_param[1], &z1ls, NULL, d1);
1796 	snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2,
1797 				      WCD937X_HPHPA_GND_R_MASK, 0);
1798 	snd_soc_component_write_field(component, WCD937X_HPH_R_ATEST,
1799 				      WCD937X_HPHPA_GND_OVR_MASK, 0);
1800 	z1ls /= 1000;
1801 	wcd937x_wcd_mbhc_qfuse_cal(component, &z1ls, 0);
1802 	/* Parallel of left Z and 9 ohm pull down resistor */
1803 	zMono = ((*zl) * 9) / ((*zl) + 9);
1804 	z_diff1 = (z1ls > zMono) ? (z1ls - zMono) : (zMono - z1ls);
1805 	z_diff2 = ((*zl) > z1ls) ? ((*zl) - z1ls) : (z1ls - (*zl));
1806 	if ((z_diff1 * (*zl + z1ls)) > (z_diff2 * (z1ls + zMono)))
1807 		wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_STEREO);
1808 	else
1809 		wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_MONO);
1810 
1811 	/* Enable surge protection again after impedance detection */
1812 	regmap_update_bits(wcd937x->regmap,
1813 			   WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
1814 zdet_complete:
1815 	snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN5, reg0);
1816 	snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN6, reg1);
1817 	snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN7, reg2);
1818 	/* Turn on 100k pull down on HPHL */
1819 	regmap_update_bits(wcd937x->regmap,
1820 			   WCD937X_ANA_MBHC_MECH, 0x01, 0x01);
1821 
1822 	/* For NO-jack, re-enable L_DET_EN after Z-det measurements */
1823 	if (wcd937x->mbhc_cfg.hphl_swh)
1824 		regmap_update_bits(wcd937x->regmap,
1825 				   WCD937X_ANA_MBHC_MECH, 0x80, 0x80);
1826 
1827 	snd_soc_component_write(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, reg4);
1828 	snd_soc_component_write(component, WCD937X_MBHC_CTL_CLK, reg3);
1829 	if (is_fsm_disable)
1830 		regmap_update_bits(wcd937x->regmap,
1831 				   WCD937X_ANA_MBHC_ELECT, 0x80, 0x80);
1832 }
1833 
wcd937x_mbhc_gnd_det_ctrl(struct snd_soc_component * component,bool enable)1834 static void wcd937x_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
1835 				      bool enable)
1836 {
1837 	if (enable) {
1838 		snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH,
1839 					      WCD937X_MBHC_HSG_PULLUP_COMP_EN, 1);
1840 		snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH,
1841 					      WCD937X_MBHC_GND_DET_EN_MASK, 1);
1842 	} else {
1843 		snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH,
1844 					      WCD937X_MBHC_GND_DET_EN_MASK, 0);
1845 		snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH,
1846 					      WCD937X_MBHC_HSG_PULLUP_COMP_EN, 0);
1847 	}
1848 }
1849 
wcd937x_mbhc_hph_pull_down_ctrl(struct snd_soc_component * component,bool enable)1850 static void wcd937x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
1851 					    bool enable)
1852 {
1853 	snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2,
1854 				      WCD937X_HPHPA_GND_R_MASK, enable);
1855 	snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2,
1856 				      WCD937X_HPHPA_GND_L_MASK, enable);
1857 }
1858 
wcd937x_mbhc_moisture_config(struct snd_soc_component * component)1859 static void wcd937x_mbhc_moisture_config(struct snd_soc_component *component)
1860 {
1861 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1862 
1863 	if (wcd937x->mbhc_cfg.moist_rref == R_OFF) {
1864 		snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2,
1865 					      WCD937X_M_RTH_CTL_MASK, R_OFF);
1866 		return;
1867 	}
1868 
1869 	/* Do not enable moisture detection if jack type is NC */
1870 	if (!wcd937x->mbhc_cfg.hphl_swh) {
1871 		dev_err(component->dev, "%s: disable moisture detection for NC\n",
1872 			__func__);
1873 		snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2,
1874 					      WCD937X_M_RTH_CTL_MASK, R_OFF);
1875 		return;
1876 	}
1877 
1878 	snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2,
1879 				      WCD937X_M_RTH_CTL_MASK, wcd937x->mbhc_cfg.moist_rref);
1880 }
1881 
wcd937x_mbhc_moisture_detect_en(struct snd_soc_component * component,bool enable)1882 static void wcd937x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable)
1883 {
1884 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1885 
1886 	if (enable)
1887 		snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2,
1888 					      WCD937X_M_RTH_CTL_MASK, wcd937x->mbhc_cfg.moist_rref);
1889 	else
1890 		snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2,
1891 					      WCD937X_M_RTH_CTL_MASK, R_OFF);
1892 }
1893 
wcd937x_mbhc_get_moisture_status(struct snd_soc_component * component)1894 static bool wcd937x_mbhc_get_moisture_status(struct snd_soc_component *component)
1895 {
1896 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1897 	bool ret = false;
1898 
1899 	if (wcd937x->mbhc_cfg.moist_rref == R_OFF) {
1900 		snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2,
1901 					      WCD937X_M_RTH_CTL_MASK, R_OFF);
1902 		goto done;
1903 	}
1904 
1905 	/* Do not enable moisture detection if jack type is NC */
1906 	if (!wcd937x->mbhc_cfg.hphl_swh) {
1907 		dev_err(component->dev, "%s: disable moisture detection for NC\n",
1908 			__func__);
1909 		snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2,
1910 					      WCD937X_M_RTH_CTL_MASK, R_OFF);
1911 		goto done;
1912 	}
1913 
1914 	/*
1915 	 * If moisture_en is already enabled, then skip to plug type
1916 	 * detection.
1917 	 */
1918 	if (snd_soc_component_read_field(component, WCD937X_MBHC_NEW_CTL_2, WCD937X_M_RTH_CTL_MASK))
1919 		goto done;
1920 
1921 	wcd937x_mbhc_moisture_detect_en(component, true);
1922 	/* Read moisture comparator status */
1923 	ret = ((snd_soc_component_read(component, WCD937X_MBHC_NEW_FSM_STATUS)
1924 				       & 0x20) ? 0 : 1);
1925 done:
1926 	return ret;
1927 }
1928 
wcd937x_mbhc_moisture_polling_ctrl(struct snd_soc_component * component,bool enable)1929 static void wcd937x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component,
1930 					       bool enable)
1931 {
1932 	snd_soc_component_write_field(component,
1933 				      WCD937X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL,
1934 				      WCD937X_MOISTURE_EN_POLLING_MASK, enable);
1935 }
1936 
1937 static const struct wcd_mbhc_cb mbhc_cb = {
1938 	.clk_setup = wcd937x_mbhc_clk_setup,
1939 	.mbhc_bias = wcd937x_mbhc_mbhc_bias_control,
1940 	.set_btn_thr = wcd937x_mbhc_program_btn_thr,
1941 	.micbias_enable_status = wcd937x_mbhc_micb_en_status,
1942 	.hph_pull_up_control_v2 = wcd937x_mbhc_hph_l_pull_up_control,
1943 	.mbhc_micbias_control = wcd937x_mbhc_request_micbias,
1944 	.mbhc_micb_ramp_control = wcd937x_mbhc_micb_ramp_control,
1945 	.mbhc_micb_ctrl_thr_mic = wcd937x_mbhc_micb_ctrl_threshold_mic,
1946 	.compute_impedance = wcd937x_wcd_mbhc_calc_impedance,
1947 	.mbhc_gnd_det_ctrl = wcd937x_mbhc_gnd_det_ctrl,
1948 	.hph_pull_down_ctrl = wcd937x_mbhc_hph_pull_down_ctrl,
1949 	.mbhc_moisture_config = wcd937x_mbhc_moisture_config,
1950 	.mbhc_get_moisture_status = wcd937x_mbhc_get_moisture_status,
1951 	.mbhc_moisture_polling_ctrl = wcd937x_mbhc_moisture_polling_ctrl,
1952 	.mbhc_moisture_detect_en = wcd937x_mbhc_moisture_detect_en,
1953 };
1954 
wcd937x_get_hph_type(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1955 static int wcd937x_get_hph_type(struct snd_kcontrol *kcontrol,
1956 				struct snd_ctl_elem_value *ucontrol)
1957 {
1958 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1959 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1960 
1961 	ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd937x->wcd_mbhc);
1962 
1963 	return 0;
1964 }
1965 
wcd937x_hph_impedance_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1966 static int wcd937x_hph_impedance_get(struct snd_kcontrol *kcontrol,
1967 				     struct snd_ctl_elem_value *ucontrol)
1968 {
1969 	u32 zl, zr;
1970 	bool hphr;
1971 	struct soc_mixer_control *mc;
1972 	struct snd_soc_component *component =
1973 					snd_soc_kcontrol_component(kcontrol);
1974 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1975 
1976 	mc = (struct soc_mixer_control *)(kcontrol->private_value);
1977 	hphr = mc->shift;
1978 	wcd_mbhc_get_impedance(wcd937x->wcd_mbhc, &zl, &zr);
1979 	ucontrol->value.integer.value[0] = hphr ? zr : zl;
1980 
1981 	return 0;
1982 }
1983 
1984 static const struct snd_kcontrol_new hph_type_detect_controls[] = {
1985 	SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0,
1986 		       wcd937x_get_hph_type, NULL),
1987 };
1988 
1989 static const struct snd_kcontrol_new impedance_detect_controls[] = {
1990 	SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0,
1991 		       wcd937x_hph_impedance_get, NULL),
1992 	SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0,
1993 		       wcd937x_hph_impedance_get, NULL),
1994 };
1995 
wcd937x_mbhc_init(struct snd_soc_component * component)1996 static int wcd937x_mbhc_init(struct snd_soc_component *component)
1997 {
1998 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1999 	struct wcd_mbhc_intr *intr_ids = &wcd937x->intr_ids;
2000 
2001 	intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd937x->irq_chip,
2002 						     WCD937X_IRQ_MBHC_SW_DET);
2003 	intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd937x->irq_chip,
2004 							    WCD937X_IRQ_MBHC_BUTTON_PRESS_DET);
2005 	intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd937x->irq_chip,
2006 							      WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET);
2007 	intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd937x->irq_chip,
2008 							 WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET);
2009 	intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd937x->irq_chip,
2010 							 WCD937X_IRQ_MBHC_ELECT_INS_REM_DET);
2011 	intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd937x->irq_chip,
2012 						     WCD937X_IRQ_HPHL_OCP_INT);
2013 	intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd937x->irq_chip,
2014 						      WCD937X_IRQ_HPHR_OCP_INT);
2015 
2016 	wcd937x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true);
2017 	if (IS_ERR(wcd937x->wcd_mbhc))
2018 		return PTR_ERR(wcd937x->wcd_mbhc);
2019 
2020 	snd_soc_add_component_controls(component, impedance_detect_controls,
2021 				       ARRAY_SIZE(impedance_detect_controls));
2022 	snd_soc_add_component_controls(component, hph_type_detect_controls,
2023 				       ARRAY_SIZE(hph_type_detect_controls));
2024 
2025 	return 0;
2026 }
2027 
wcd937x_mbhc_deinit(struct snd_soc_component * component)2028 static void wcd937x_mbhc_deinit(struct snd_soc_component *component)
2029 {
2030 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
2031 
2032 	wcd_mbhc_deinit(wcd937x->wcd_mbhc);
2033 }
2034 
2035 /* END MBHC */
2036 
2037 static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
2038 	SOC_SINGLE_TLV("EAR_PA Volume", WCD937X_ANA_EAR_COMPANDER_CTL,
2039 		       2, 0x10, 0, ear_pa_gain),
2040 	SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
2041 		     wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
2042 
2043 	SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
2044 		       wcd937x_get_compander, wcd937x_set_compander),
2045 	SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
2046 		       wcd937x_get_compander, wcd937x_set_compander),
2047 
2048 	SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
2049 	SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
2050 	SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0, analog_gain),
2051 	SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0, analog_gain),
2052 	SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0, analog_gain),
2053 
2054 	SOC_SINGLE_EXT("HPHL Switch", WCD937X_HPH_L, 0, 1, 0,
2055 		       wcd937x_get_swr_port, wcd937x_set_swr_port),
2056 	SOC_SINGLE_EXT("HPHR Switch", WCD937X_HPH_R, 0, 1, 0,
2057 		       wcd937x_get_swr_port, wcd937x_set_swr_port),
2058 	SOC_SINGLE_EXT("LO Switch", WCD937X_LO, 0, 1, 0,
2059 		       wcd937x_get_swr_port, wcd937x_set_swr_port),
2060 
2061 	SOC_SINGLE_EXT("ADC1 Switch", WCD937X_ADC1, 1, 1, 0,
2062 		       wcd937x_get_swr_port, wcd937x_set_swr_port),
2063 	SOC_SINGLE_EXT("ADC2 Switch", WCD937X_ADC2, 1, 1, 0,
2064 		       wcd937x_get_swr_port, wcd937x_set_swr_port),
2065 	SOC_SINGLE_EXT("ADC3 Switch", WCD937X_ADC3, 1, 1, 0,
2066 		       wcd937x_get_swr_port, wcd937x_set_swr_port),
2067 	SOC_SINGLE_EXT("DMIC0 Switch", WCD937X_DMIC0, 1, 1, 0,
2068 		       wcd937x_get_swr_port, wcd937x_set_swr_port),
2069 	SOC_SINGLE_EXT("DMIC1 Switch", WCD937X_DMIC1, 1, 1, 0,
2070 		       wcd937x_get_swr_port, wcd937x_set_swr_port),
2071 	SOC_SINGLE_EXT("MBHC Switch", WCD937X_MBHC, 1, 1, 0,
2072 		       wcd937x_get_swr_port, wcd937x_set_swr_port),
2073 	SOC_SINGLE_EXT("DMIC2 Switch", WCD937X_DMIC2, 1, 1, 0,
2074 		       wcd937x_get_swr_port, wcd937x_set_swr_port),
2075 	SOC_SINGLE_EXT("DMIC3 Switch", WCD937X_DMIC3, 1, 1, 0,
2076 		       wcd937x_get_swr_port, wcd937x_set_swr_port),
2077 	SOC_SINGLE_EXT("DMIC4 Switch", WCD937X_DMIC4, 1, 1, 0,
2078 		       wcd937x_get_swr_port, wcd937x_set_swr_port),
2079 	SOC_SINGLE_EXT("DMIC5 Switch", WCD937X_DMIC5, 1, 1, 0,
2080 		       wcd937x_get_swr_port, wcd937x_set_swr_port),
2081 };
2082 
2083 static const struct snd_kcontrol_new adc1_switch[] = {
2084 	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2085 };
2086 
2087 static const struct snd_kcontrol_new adc2_switch[] = {
2088 	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2089 };
2090 
2091 static const struct snd_kcontrol_new adc3_switch[] = {
2092 	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2093 };
2094 
2095 static const struct snd_kcontrol_new dmic1_switch[] = {
2096 	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2097 };
2098 
2099 static const struct snd_kcontrol_new dmic2_switch[] = {
2100 	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2101 };
2102 
2103 static const struct snd_kcontrol_new dmic3_switch[] = {
2104 	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2105 };
2106 
2107 static const struct snd_kcontrol_new dmic4_switch[] = {
2108 	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2109 };
2110 
2111 static const struct snd_kcontrol_new dmic5_switch[] = {
2112 	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2113 };
2114 
2115 static const struct snd_kcontrol_new dmic6_switch[] = {
2116 	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2117 };
2118 
2119 static const struct snd_kcontrol_new ear_rdac_switch[] = {
2120 	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2121 };
2122 
2123 static const struct snd_kcontrol_new aux_rdac_switch[] = {
2124 	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2125 };
2126 
2127 static const struct snd_kcontrol_new hphl_rdac_switch[] = {
2128 	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2129 };
2130 
2131 static const struct snd_kcontrol_new hphr_rdac_switch[] = {
2132 	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2133 };
2134 
2135 static const char * const adc2_mux_text[] = {
2136 	"INP2", "INP3"
2137 };
2138 
2139 static const char * const rdac3_mux_text[] = {
2140 	"RX1", "RX3"
2141 };
2142 
2143 static const struct soc_enum adc2_enum =
2144 	SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
2145 			ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
2146 
2147 static const struct soc_enum rdac3_enum =
2148 	SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
2149 			ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
2150 
2151 static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
2152 
2153 static const struct snd_kcontrol_new rx_rdac3_mux = SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
2154 
2155 static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
2156 	/* Input widgets */
2157 	SND_SOC_DAPM_INPUT("AMIC1"),
2158 	SND_SOC_DAPM_INPUT("AMIC2"),
2159 	SND_SOC_DAPM_INPUT("AMIC3"),
2160 	SND_SOC_DAPM_INPUT("IN1_HPHL"),
2161 	SND_SOC_DAPM_INPUT("IN2_HPHR"),
2162 	SND_SOC_DAPM_INPUT("IN3_AUX"),
2163 
2164 	/* TX widgets */
2165 	SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
2166 			   wcd937x_codec_enable_adc,
2167 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2168 	SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
2169 			   wcd937x_codec_enable_adc,
2170 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2171 
2172 	SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
2173 			     NULL, 0, wcd937x_enable_req,
2174 			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2175 	SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
2176 			     NULL, 0, wcd937x_enable_req,
2177 			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2178 
2179 	SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
2180 
2181 	/* TX mixers */
2182 	SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
2183 			     adc1_switch, ARRAY_SIZE(adc1_switch),
2184 			     wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
2185 			     SND_SOC_DAPM_POST_PMD),
2186 	SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 1, 0,
2187 			     adc2_switch, ARRAY_SIZE(adc2_switch),
2188 			     wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
2189 			     SND_SOC_DAPM_POST_PMD),
2190 
2191 	/* MIC_BIAS widgets */
2192 	SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
2193 			    wcd937x_codec_enable_micbias,
2194 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2195 			    SND_SOC_DAPM_POST_PMD),
2196 	SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
2197 			    wcd937x_codec_enable_micbias,
2198 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2199 			    SND_SOC_DAPM_POST_PMD),
2200 	SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
2201 			    wcd937x_codec_enable_micbias,
2202 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2203 			    SND_SOC_DAPM_POST_PMD),
2204 
2205 	SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0),
2206 	SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0),
2207 
2208 	/* RX widgets */
2209 	SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
2210 			   wcd937x_codec_enable_ear_pa,
2211 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2212 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2213 	SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
2214 			   wcd937x_codec_enable_aux_pa,
2215 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2216 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2217 	SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
2218 			   wcd937x_codec_enable_hphl_pa,
2219 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2220 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2221 	SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
2222 			   wcd937x_codec_enable_hphr_pa,
2223 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2224 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2225 
2226 	SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
2227 			   wcd937x_codec_hphl_dac_event,
2228 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2229 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2230 	SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
2231 			   wcd937x_codec_hphr_dac_event,
2232 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2233 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2234 	SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
2235 			   wcd937x_codec_ear_dac_event,
2236 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2237 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2238 	SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
2239 			   wcd937x_codec_aux_dac_event,
2240 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2241 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2242 
2243 	SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
2244 
2245 	SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
2246 			     wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
2247 			     SND_SOC_DAPM_POST_PMD),
2248 	SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
2249 			     wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
2250 			     SND_SOC_DAPM_POST_PMD),
2251 	SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
2252 			     wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
2253 			     SND_SOC_DAPM_POST_PMD),
2254 
2255 	/* RX mixer widgets*/
2256 	SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
2257 			   ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
2258 	SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
2259 			   aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
2260 	SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
2261 			   hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
2262 	SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
2263 			   hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
2264 
2265 	/* TX output widgets */
2266 	SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
2267 	SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
2268 	SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
2269 	SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
2270 
2271 	/* RX output widgets */
2272 	SND_SOC_DAPM_OUTPUT("EAR"),
2273 	SND_SOC_DAPM_OUTPUT("AUX"),
2274 	SND_SOC_DAPM_OUTPUT("HPHL"),
2275 	SND_SOC_DAPM_OUTPUT("HPHR"),
2276 
2277 	/* MIC_BIAS pull up widgets */
2278 	SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
2279 			    wcd937x_codec_enable_micbias_pullup,
2280 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2281 			    SND_SOC_DAPM_POST_PMD),
2282 	SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
2283 			    wcd937x_codec_enable_micbias_pullup,
2284 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2285 			    SND_SOC_DAPM_POST_PMD),
2286 	SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
2287 			    wcd937x_codec_enable_micbias_pullup,
2288 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2289 			    SND_SOC_DAPM_POST_PMD),
2290 };
2291 
2292 static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
2293 	/* Input widgets */
2294 	SND_SOC_DAPM_INPUT("AMIC4"),
2295 
2296 	/* TX widgets */
2297 	SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
2298 			   wcd937x_codec_enable_adc,
2299 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2300 
2301 	SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
2302 			     NULL, 0, wcd937x_enable_req,
2303 			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2304 
2305 	SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
2306 			   wcd937x_codec_enable_dmic,
2307 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2308 	SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
2309 			   wcd937x_codec_enable_dmic,
2310 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2311 	SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
2312 			   wcd937x_codec_enable_dmic,
2313 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2314 	SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
2315 			   wcd937x_codec_enable_dmic,
2316 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2317 	SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
2318 			   wcd937x_codec_enable_dmic,
2319 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2320 	SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
2321 			   wcd937x_codec_enable_dmic,
2322 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2323 
2324 	/* TX mixer widgets */
2325 	SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
2326 			     0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
2327 			     wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
2328 			     SND_SOC_DAPM_POST_PMD),
2329 	SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 1,
2330 			     0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
2331 			     wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
2332 			     SND_SOC_DAPM_POST_PMD),
2333 	SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 2,
2334 			     0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
2335 			     wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
2336 			     SND_SOC_DAPM_POST_PMD),
2337 	SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 3,
2338 			     0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
2339 			     wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
2340 			     SND_SOC_DAPM_POST_PMD),
2341 	SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 4,
2342 			     0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
2343 			     wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
2344 			     SND_SOC_DAPM_POST_PMD),
2345 	SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 5,
2346 			     0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
2347 			     wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
2348 			     SND_SOC_DAPM_POST_PMD),
2349 	SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 2, 0, adc3_switch,
2350 			     ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
2351 			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2352 
2353 	/* Output widgets */
2354 	SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
2355 	SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
2356 	SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
2357 	SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
2358 	SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
2359 	SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
2360 };
2361 
2362 static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
2363 	{ "ADC1_OUTPUT", NULL, "ADC1_MIXER" },
2364 	{ "ADC1_MIXER", "Switch", "ADC1 REQ" },
2365 	{ "ADC1 REQ", NULL, "ADC1" },
2366 	{ "ADC1", NULL, "AMIC1" },
2367 
2368 	{ "ADC2_OUTPUT", NULL, "ADC2_MIXER" },
2369 	{ "ADC2_MIXER", "Switch", "ADC2 REQ" },
2370 	{ "ADC2 REQ", NULL, "ADC2" },
2371 	{ "ADC2", NULL, "ADC2 MUX" },
2372 	{ "ADC2 MUX", "INP3", "AMIC3" },
2373 	{ "ADC2 MUX", "INP2", "AMIC2" },
2374 
2375 	{ "IN1_HPHL", NULL, "VDD_BUCK" },
2376 	{ "IN1_HPHL", NULL, "CLS_H_PORT" },
2377 	{ "RX1", NULL, "IN1_HPHL" },
2378 	{ "RDAC1", NULL, "RX1" },
2379 	{ "HPHL_RDAC", "Switch", "RDAC1" },
2380 	{ "HPHL PGA", NULL, "HPHL_RDAC" },
2381 	{ "HPHL", NULL, "HPHL PGA" },
2382 
2383 	{ "IN2_HPHR", NULL, "VDD_BUCK" },
2384 	{ "IN2_HPHR", NULL, "CLS_H_PORT" },
2385 	{ "RX2", NULL, "IN2_HPHR" },
2386 	{ "RDAC2", NULL, "RX2" },
2387 	{ "HPHR_RDAC", "Switch", "RDAC2" },
2388 	{ "HPHR PGA", NULL, "HPHR_RDAC" },
2389 	{ "HPHR", NULL, "HPHR PGA" },
2390 
2391 	{ "IN3_AUX", NULL, "VDD_BUCK" },
2392 	{ "IN3_AUX", NULL, "CLS_H_PORT" },
2393 	{ "RX3", NULL, "IN3_AUX" },
2394 	{ "RDAC4", NULL, "RX3" },
2395 	{ "AUX_RDAC", "Switch", "RDAC4" },
2396 	{ "AUX PGA", NULL, "AUX_RDAC" },
2397 	{ "AUX", NULL, "AUX PGA" },
2398 
2399 	{ "RDAC3_MUX", "RX3", "RX3" },
2400 	{ "RDAC3_MUX", "RX1", "RX1" },
2401 	{ "RDAC3", NULL, "RDAC3_MUX" },
2402 	{ "EAR_RDAC", "Switch", "RDAC3" },
2403 	{ "EAR PGA", NULL, "EAR_RDAC" },
2404 	{ "EAR", NULL, "EAR PGA" },
2405 };
2406 
2407 static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
2408 	{ "ADC3_OUTPUT", NULL, "ADC3_MIXER" },
2409 	{ "ADC3_OUTPUT", NULL, "ADC3_MIXER" },
2410 	{ "ADC3_MIXER", "Switch", "ADC3 REQ" },
2411 	{ "ADC3 REQ", NULL, "ADC3" },
2412 	{ "ADC3", NULL, "AMIC4" },
2413 
2414 	{ "DMIC1_OUTPUT", NULL, "DMIC1_MIXER" },
2415 	{ "DMIC1_MIXER", "Switch", "DMIC1" },
2416 
2417 	{ "DMIC2_OUTPUT", NULL, "DMIC2_MIXER" },
2418 	{ "DMIC2_MIXER", "Switch", "DMIC2" },
2419 
2420 	{ "DMIC3_OUTPUT", NULL, "DMIC3_MIXER" },
2421 	{ "DMIC3_MIXER", "Switch", "DMIC3" },
2422 
2423 	{ "DMIC4_OUTPUT", NULL, "DMIC4_MIXER" },
2424 	{ "DMIC4_MIXER", "Switch", "DMIC4" },
2425 
2426 	{ "DMIC5_OUTPUT", NULL, "DMIC5_MIXER" },
2427 	{ "DMIC5_MIXER", "Switch", "DMIC5" },
2428 
2429 	{ "DMIC6_OUTPUT", NULL, "DMIC6_MIXER" },
2430 	{ "DMIC6_MIXER", "Switch", "DMIC6" },
2431 };
2432 
wcd937x_set_micbias_data(struct wcd937x_priv * wcd937x)2433 static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x)
2434 {
2435 	int vout_ctl[3];
2436 
2437 	/* Set micbias voltage */
2438 	vout_ctl[0] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb1_mv);
2439 	vout_ctl[1] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb2_mv);
2440 	vout_ctl[2] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb3_mv);
2441 	if ((vout_ctl[0] | vout_ctl[1] | vout_ctl[2]) < 0)
2442 		return -EINVAL;
2443 
2444 	regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, WCD937X_ANA_MICB_VOUT, vout_ctl[0]);
2445 	regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, WCD937X_ANA_MICB_VOUT, vout_ctl[1]);
2446 	regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, WCD937X_ANA_MICB_VOUT, vout_ctl[2]);
2447 
2448 	return 0;
2449 }
2450 
wcd937x_wd_handle_irq(int irq,void * data)2451 static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
2452 {
2453 	return IRQ_HANDLED;
2454 }
2455 
2456 static const struct irq_chip wcd_irq_chip = {
2457 	.name = "WCD937x",
2458 };
2459 
wcd_irq_chip_map(struct irq_domain * irqd,unsigned int virq,irq_hw_number_t hw)2460 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq,
2461 			    irq_hw_number_t hw)
2462 {
2463 	irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq);
2464 	irq_set_nested_thread(virq, 1);
2465 	irq_set_noprobe(virq);
2466 
2467 	return 0;
2468 }
2469 
2470 static const struct irq_domain_ops wcd_domain_ops = {
2471 	.map = wcd_irq_chip_map,
2472 };
2473 
wcd937x_irq_init(struct wcd937x_priv * wcd,struct device * dev)2474 static int wcd937x_irq_init(struct wcd937x_priv *wcd, struct device *dev)
2475 {
2476 	wcd->virq = irq_domain_add_linear(NULL, 1, &wcd_domain_ops, NULL);
2477 	if (!(wcd->virq)) {
2478 		dev_err(dev, "%s: Failed to add IRQ domain\n", __func__);
2479 		return -EINVAL;
2480 	}
2481 
2482 	return devm_regmap_add_irq_chip(dev, wcd->regmap,
2483 					irq_create_mapping(wcd->virq, 0),
2484 					IRQF_ONESHOT, 0, &wcd937x_regmap_irq_chip,
2485 					&wcd->irq_chip);
2486 }
2487 
wcd937x_soc_codec_probe(struct snd_soc_component * component)2488 static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
2489 {
2490 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2491 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
2492 	struct sdw_slave *tx_sdw_dev = wcd937x->tx_sdw_dev;
2493 	struct device *dev = component->dev;
2494 	unsigned long time_left;
2495 	int i, ret;
2496 	u32 chipid;
2497 
2498 	time_left = wait_for_completion_timeout(&tx_sdw_dev->initialization_complete,
2499 						msecs_to_jiffies(5000));
2500 	if (!time_left) {
2501 		dev_err(dev, "soundwire device init timeout\n");
2502 		return -ETIMEDOUT;
2503 	}
2504 
2505 	snd_soc_component_init_regmap(component, wcd937x->regmap);
2506 	ret = pm_runtime_resume_and_get(dev);
2507 	if (ret < 0)
2508 		return ret;
2509 
2510 	chipid = (snd_soc_component_read(component,
2511 					 WCD937X_DIGITAL_EFUSE_REG_0) & 0x1e) >> 1;
2512 	if (chipid != CHIPID_WCD9370 && chipid != CHIPID_WCD9375) {
2513 		dev_err(dev, "Got unknown chip id: 0x%x\n", chipid);
2514 		pm_runtime_put(dev);
2515 		return -EINVAL;
2516 	}
2517 
2518 	wcd937x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD937X);
2519 	if (IS_ERR(wcd937x->clsh_info)) {
2520 		pm_runtime_put(dev);
2521 		return PTR_ERR(wcd937x->clsh_info);
2522 	}
2523 
2524 	wcd937x_io_init(wcd937x->regmap);
2525 	/* Set all interrupts as edge triggered */
2526 	for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
2527 		regmap_write(wcd937x->regmap, (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
2528 
2529 	pm_runtime_put(dev);
2530 
2531 	wcd937x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip,
2532 						       WCD937X_IRQ_HPHR_PDM_WD_INT);
2533 	wcd937x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip,
2534 						       WCD937X_IRQ_HPHL_PDM_WD_INT);
2535 	wcd937x->aux_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip,
2536 						      WCD937X_IRQ_AUX_PDM_WD_INT);
2537 
2538 	/* Request for watchdog interrupt */
2539 	ret = devm_request_threaded_irq(dev, wcd937x->hphr_pdm_wd_int, NULL, wcd937x_wd_handle_irq,
2540 					IRQF_ONESHOT | IRQF_TRIGGER_RISING,
2541 					"HPHR PDM WDOG INT", wcd937x);
2542 	if (ret)
2543 		dev_err(dev, "Failed to request HPHR watchdog interrupt (%d)\n", ret);
2544 
2545 	ret = devm_request_threaded_irq(dev, wcd937x->hphl_pdm_wd_int, NULL, wcd937x_wd_handle_irq,
2546 					IRQF_ONESHOT | IRQF_TRIGGER_RISING,
2547 					"HPHL PDM WDOG INT", wcd937x);
2548 	if (ret)
2549 		dev_err(dev, "Failed to request HPHL watchdog interrupt (%d)\n", ret);
2550 
2551 	ret = devm_request_threaded_irq(dev, wcd937x->aux_pdm_wd_int, NULL, wcd937x_wd_handle_irq,
2552 					IRQF_ONESHOT | IRQF_TRIGGER_RISING,
2553 					"AUX PDM WDOG INT", wcd937x);
2554 	if (ret)
2555 		dev_err(dev, "Failed to request Aux watchdog interrupt (%d)\n", ret);
2556 
2557 	/* Disable watchdog interrupt for HPH and AUX */
2558 	disable_irq_nosync(wcd937x->hphr_pdm_wd_int);
2559 	disable_irq_nosync(wcd937x->hphl_pdm_wd_int);
2560 	disable_irq_nosync(wcd937x->aux_pdm_wd_int);
2561 
2562 	if (chipid == CHIPID_WCD9375) {
2563 		ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
2564 						ARRAY_SIZE(wcd9375_dapm_widgets));
2565 		if (ret < 0) {
2566 			dev_err(component->dev, "Failed to add snd_ctls\n");
2567 			return ret;
2568 		}
2569 
2570 		ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
2571 					      ARRAY_SIZE(wcd9375_audio_map));
2572 		if (ret < 0) {
2573 			dev_err(component->dev, "Failed to add routes\n");
2574 			return ret;
2575 		}
2576 	}
2577 
2578 	ret = wcd937x_mbhc_init(component);
2579 	if (ret)
2580 		dev_err(component->dev, "mbhc initialization failed\n");
2581 
2582 	return ret;
2583 }
2584 
wcd937x_soc_codec_remove(struct snd_soc_component * component)2585 static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
2586 {
2587 	struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
2588 
2589 	wcd937x_mbhc_deinit(component);
2590 	free_irq(wcd937x->aux_pdm_wd_int, wcd937x);
2591 	free_irq(wcd937x->hphl_pdm_wd_int, wcd937x);
2592 	free_irq(wcd937x->hphr_pdm_wd_int, wcd937x);
2593 
2594 	wcd_clsh_ctrl_free(wcd937x->clsh_info);
2595 }
2596 
wcd937x_codec_set_jack(struct snd_soc_component * comp,struct snd_soc_jack * jack,void * data)2597 static int wcd937x_codec_set_jack(struct snd_soc_component *comp,
2598 				  struct snd_soc_jack *jack, void *data)
2599 {
2600 	struct wcd937x_priv *wcd = dev_get_drvdata(comp->dev);
2601 	int ret = 0;
2602 
2603 	if (jack)
2604 		ret = wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack);
2605 	else
2606 		wcd_mbhc_stop(wcd->wcd_mbhc);
2607 
2608 	return ret;
2609 }
2610 
2611 static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
2612 	.name = "wcd937x_codec",
2613 	.probe = wcd937x_soc_codec_probe,
2614 	.remove = wcd937x_soc_codec_remove,
2615 	.controls = wcd937x_snd_controls,
2616 	.num_controls = ARRAY_SIZE(wcd937x_snd_controls),
2617 	.dapm_widgets = wcd937x_dapm_widgets,
2618 	.num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
2619 	.dapm_routes = wcd937x_audio_map,
2620 	.num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
2621 	.set_jack = wcd937x_codec_set_jack,
2622 	.endianness = 1,
2623 };
2624 
wcd937x_dt_parse_micbias_info(struct device * dev,struct wcd937x_priv * wcd)2625 static void wcd937x_dt_parse_micbias_info(struct device *dev, struct wcd937x_priv *wcd)
2626 {
2627 	struct device_node *np = dev->of_node;
2628 	u32 prop_val = 0;
2629 	int ret = 0;
2630 
2631 	ret = of_property_read_u32(np, "qcom,micbias1-microvolt", &prop_val);
2632 	if (!ret)
2633 		wcd->micb1_mv = prop_val / 1000;
2634 	else
2635 		dev_warn(dev, "Micbias1 DT property not found\n");
2636 
2637 	ret = of_property_read_u32(np, "qcom,micbias2-microvolt", &prop_val);
2638 	if (!ret)
2639 		wcd->micb2_mv = prop_val / 1000;
2640 	else
2641 		dev_warn(dev, "Micbias2 DT property not found\n");
2642 
2643 	ret = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val);
2644 	if (!ret)
2645 		wcd->micb3_mv = prop_val / 1000;
2646 	else
2647 		dev_warn(dev, "Micbias3 DT property not found\n");
2648 }
2649 
wcd937x_swap_gnd_mic(struct snd_soc_component * component,bool active)2650 static bool wcd937x_swap_gnd_mic(struct snd_soc_component *component, bool active)
2651 {
2652 	int value;
2653 	struct wcd937x_priv *wcd937x;
2654 
2655 	wcd937x = snd_soc_component_get_drvdata(component);
2656 
2657 	value = gpiod_get_value(wcd937x->us_euro_gpio);
2658 	gpiod_set_value(wcd937x->us_euro_gpio, !value);
2659 
2660 	return true;
2661 }
2662 
wcd937x_codec_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)2663 static int wcd937x_codec_hw_params(struct snd_pcm_substream *substream,
2664 				   struct snd_pcm_hw_params *params,
2665 				   struct snd_soc_dai *dai)
2666 {
2667 	struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev);
2668 	struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id];
2669 
2670 	return wcd937x_sdw_hw_params(wcd, substream, params, dai);
2671 }
2672 
wcd937x_codec_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)2673 static int wcd937x_codec_free(struct snd_pcm_substream *substream,
2674 			      struct snd_soc_dai *dai)
2675 {
2676 	struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev);
2677 	struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id];
2678 
2679 	return sdw_stream_remove_slave(wcd->sdev, wcd->sruntime);
2680 }
2681 
wcd937x_codec_set_sdw_stream(struct snd_soc_dai * dai,void * stream,int direction)2682 static int wcd937x_codec_set_sdw_stream(struct snd_soc_dai *dai,
2683 					void *stream, int direction)
2684 {
2685 	struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev);
2686 	struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id];
2687 
2688 	wcd->sruntime = stream;
2689 
2690 	return 0;
2691 }
2692 
2693 static const struct snd_soc_dai_ops wcd937x_sdw_dai_ops = {
2694 	.hw_params = wcd937x_codec_hw_params,
2695 	.hw_free = wcd937x_codec_free,
2696 	.set_stream = wcd937x_codec_set_sdw_stream,
2697 };
2698 
2699 static struct snd_soc_dai_driver wcd937x_dais[] = {
2700 	[0] = {
2701 		.name = "wcd937x-sdw-rx",
2702 		.playback = {
2703 			.stream_name = "WCD AIF Playback",
2704 			.rates = WCD937X_RATES | WCD937X_FRAC_RATES,
2705 			.formats = WCD937X_FORMATS,
2706 			.rate_min = 8000,
2707 			.rate_max = 384000,
2708 			.channels_min = 1,
2709 			.channels_max = 4,
2710 		},
2711 		.ops = &wcd937x_sdw_dai_ops,
2712 	},
2713 	[1] = {
2714 		.name = "wcd937x-sdw-tx",
2715 		.capture = {
2716 			.stream_name = "WCD AIF Capture",
2717 			.rates = WCD937X_RATES,
2718 			.formats = WCD937X_FORMATS,
2719 			.rate_min = 8000,
2720 			.rate_max = 192000,
2721 			.channels_min = 1,
2722 			.channels_max = 4,
2723 		},
2724 		.ops = &wcd937x_sdw_dai_ops,
2725 	},
2726 };
2727 
wcd937x_bind(struct device * dev)2728 static int wcd937x_bind(struct device *dev)
2729 {
2730 	struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
2731 	int ret;
2732 
2733 	/* Give the SDW subdevices some more time to settle */
2734 	usleep_range(5000, 5010);
2735 
2736 	ret = component_bind_all(dev, wcd937x);
2737 	if (ret) {
2738 		dev_err(dev, "Slave bind failed, ret = %d\n", ret);
2739 		return ret;
2740 	}
2741 
2742 	wcd937x->rxdev = wcd937x_sdw_device_get(wcd937x->rxnode);
2743 	if (!wcd937x->rxdev) {
2744 		dev_err(dev, "could not find slave with matching of node\n");
2745 		return -EINVAL;
2746 	}
2747 
2748 	wcd937x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd937x->rxdev);
2749 	wcd937x->sdw_priv[AIF1_PB]->wcd937x = wcd937x;
2750 
2751 	wcd937x->txdev = wcd937x_sdw_device_get(wcd937x->txnode);
2752 	if (!wcd937x->txdev) {
2753 		dev_err(dev, "could not find txslave with matching of node\n");
2754 		return -EINVAL;
2755 	}
2756 
2757 	wcd937x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd937x->txdev);
2758 	wcd937x->sdw_priv[AIF1_CAP]->wcd937x = wcd937x;
2759 	wcd937x->tx_sdw_dev = dev_to_sdw_dev(wcd937x->txdev);
2760 	if (!wcd937x->tx_sdw_dev) {
2761 		dev_err(dev, "could not get txslave with matching of dev\n");
2762 		return -EINVAL;
2763 	}
2764 
2765 	/*
2766 	 * As TX is the main CSR reg interface, which should not be suspended first.
2767 	 * expicilty add the dependency link
2768 	 */
2769 	if (!device_link_add(wcd937x->rxdev, wcd937x->txdev,
2770 			     DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) {
2771 		dev_err(dev, "Could not devlink TX and RX\n");
2772 		return -EINVAL;
2773 	}
2774 
2775 	if (!device_link_add(dev, wcd937x->txdev,
2776 			     DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) {
2777 		dev_err(dev, "Could not devlink WCD and TX\n");
2778 		return -EINVAL;
2779 	}
2780 
2781 	if (!device_link_add(dev, wcd937x->rxdev,
2782 			     DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) {
2783 		dev_err(dev, "Could not devlink WCD and RX\n");
2784 		return -EINVAL;
2785 	}
2786 
2787 	wcd937x->regmap = dev_get_regmap(&wcd937x->tx_sdw_dev->dev, NULL);
2788 	if (!wcd937x->regmap) {
2789 		dev_err(dev, "could not get TX device regmap\n");
2790 		return -EINVAL;
2791 	}
2792 
2793 	ret = wcd937x_irq_init(wcd937x, dev);
2794 	if (ret) {
2795 		dev_err(dev, "IRQ init failed: %d\n", ret);
2796 		return ret;
2797 	}
2798 
2799 	wcd937x->sdw_priv[AIF1_PB]->slave_irq = wcd937x->virq;
2800 	wcd937x->sdw_priv[AIF1_CAP]->slave_irq = wcd937x->virq;
2801 
2802 	ret = wcd937x_set_micbias_data(wcd937x);
2803 	if (ret < 0) {
2804 		dev_err(dev, "Bad micbias pdata\n");
2805 		return ret;
2806 	}
2807 
2808 	ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
2809 					 wcd937x_dais, ARRAY_SIZE(wcd937x_dais));
2810 	if (ret)
2811 		dev_err(dev, "Codec registration failed\n");
2812 
2813 	return ret;
2814 }
2815 
wcd937x_unbind(struct device * dev)2816 static void wcd937x_unbind(struct device *dev)
2817 {
2818 	struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
2819 
2820 	snd_soc_unregister_component(dev);
2821 	device_link_remove(dev, wcd937x->txdev);
2822 	device_link_remove(dev, wcd937x->rxdev);
2823 	device_link_remove(wcd937x->rxdev, wcd937x->txdev);
2824 	component_unbind_all(dev, wcd937x);
2825 	mutex_destroy(&wcd937x->micb_lock);
2826 }
2827 
2828 static const struct component_master_ops wcd937x_comp_ops = {
2829 	.bind = wcd937x_bind,
2830 	.unbind = wcd937x_unbind,
2831 };
2832 
wcd937x_add_slave_components(struct wcd937x_priv * wcd937x,struct device * dev,struct component_match ** matchptr)2833 static int wcd937x_add_slave_components(struct wcd937x_priv *wcd937x,
2834 					struct device *dev,
2835 					struct component_match **matchptr)
2836 {
2837 	struct device_node *np = dev->of_node;
2838 
2839 	wcd937x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0);
2840 	if (!wcd937x->rxnode) {
2841 		dev_err(dev, "Couldn't parse phandle to qcom,rx-device!\n");
2842 		return -ENODEV;
2843 	}
2844 	of_node_get(wcd937x->rxnode);
2845 	component_match_add_release(dev, matchptr, component_release_of,
2846 				    component_compare_of, wcd937x->rxnode);
2847 
2848 	wcd937x->txnode = of_parse_phandle(np, "qcom,tx-device", 0);
2849 	if (!wcd937x->txnode) {
2850 		dev_err(dev, "Couldn't parse phandle to qcom,tx-device\n");
2851 			return -ENODEV;
2852 	}
2853 	of_node_get(wcd937x->txnode);
2854 	component_match_add_release(dev, matchptr, component_release_of,
2855 				    component_compare_of, wcd937x->txnode);
2856 
2857 	return 0;
2858 }
2859 
wcd937x_probe(struct platform_device * pdev)2860 static int wcd937x_probe(struct platform_device *pdev)
2861 {
2862 	struct component_match *match = NULL;
2863 	struct device *dev = &pdev->dev;
2864 	struct wcd937x_priv *wcd937x;
2865 	struct wcd_mbhc_config *cfg;
2866 	int ret;
2867 
2868 	wcd937x = devm_kzalloc(dev, sizeof(*wcd937x), GFP_KERNEL);
2869 	if (!wcd937x)
2870 		return -ENOMEM;
2871 
2872 	dev_set_drvdata(dev, wcd937x);
2873 	mutex_init(&wcd937x->micb_lock);
2874 
2875 	wcd937x->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
2876 	if (IS_ERR(wcd937x->reset_gpio))
2877 		return dev_err_probe(dev, PTR_ERR(wcd937x->reset_gpio),
2878 				     "failed to reset wcd gpio\n");
2879 
2880 	wcd937x->us_euro_gpio = devm_gpiod_get_optional(dev, "us-euro", GPIOD_OUT_LOW);
2881 	if (IS_ERR(wcd937x->us_euro_gpio))
2882 		return dev_err_probe(dev, PTR_ERR(wcd937x->us_euro_gpio),
2883 				"us-euro swap Control GPIO not found\n");
2884 
2885 	cfg = &wcd937x->mbhc_cfg;
2886 	cfg->swap_gnd_mic = wcd937x_swap_gnd_mic;
2887 
2888 	wcd937x->supplies[0].supply = "vdd-rxtx";
2889 	wcd937x->supplies[1].supply = "vdd-px";
2890 	wcd937x->supplies[2].supply = "vdd-mic-bias";
2891 	wcd937x->supplies[3].supply = "vdd-buck";
2892 
2893 	ret = devm_regulator_bulk_get(dev, WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies);
2894 	if (ret)
2895 		return dev_err_probe(dev, ret, "Failed to get supplies\n");
2896 
2897 	ret = regulator_bulk_enable(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies);
2898 	if (ret) {
2899 		regulator_bulk_free(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies);
2900 		return dev_err_probe(dev, ret, "Failed to enable supplies\n");
2901 	}
2902 
2903 	wcd937x_dt_parse_micbias_info(dev, wcd937x);
2904 
2905 	cfg->mbhc_micbias = MIC_BIAS_2;
2906 	cfg->anc_micbias = MIC_BIAS_2;
2907 	cfg->v_hs_max = WCD_MBHC_HS_V_MAX;
2908 	cfg->num_btn = WCD937X_MBHC_MAX_BUTTONS;
2909 	cfg->micb_mv = wcd937x->micb2_mv;
2910 	cfg->linein_th = 5000;
2911 	cfg->hs_thr = 1700;
2912 	cfg->hph_thr = 50;
2913 
2914 	wcd_dt_parse_mbhc_data(dev, &wcd937x->mbhc_cfg);
2915 
2916 	ret = wcd937x_add_slave_components(wcd937x, dev, &match);
2917 	if (ret)
2918 		goto err_disable_regulators;
2919 
2920 	wcd937x_reset(wcd937x);
2921 
2922 	ret = component_master_add_with_match(dev, &wcd937x_comp_ops, match);
2923 	if (ret)
2924 		goto err_disable_regulators;
2925 
2926 	pm_runtime_set_autosuspend_delay(dev, 1000);
2927 	pm_runtime_use_autosuspend(dev);
2928 	pm_runtime_mark_last_busy(dev);
2929 	pm_runtime_set_active(dev);
2930 	pm_runtime_enable(dev);
2931 	pm_runtime_idle(dev);
2932 
2933 	return 0;
2934 
2935 err_disable_regulators:
2936 	regulator_bulk_disable(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies);
2937 	regulator_bulk_free(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies);
2938 
2939 	return ret;
2940 }
2941 
wcd937x_remove(struct platform_device * pdev)2942 static void wcd937x_remove(struct platform_device *pdev)
2943 {
2944 	struct device *dev = &pdev->dev;
2945 	struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
2946 
2947 	component_master_del(&pdev->dev, &wcd937x_comp_ops);
2948 
2949 	pm_runtime_disable(dev);
2950 	pm_runtime_set_suspended(dev);
2951 	pm_runtime_dont_use_autosuspend(dev);
2952 
2953 	regulator_bulk_disable(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies);
2954 	regulator_bulk_free(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies);
2955 }
2956 
2957 #if defined(CONFIG_OF)
2958 static const struct of_device_id wcd937x_of_match[] = {
2959 	{ .compatible = "qcom,wcd9370-codec" },
2960 	{ .compatible = "qcom,wcd9375-codec" },
2961 	{ }
2962 };
2963 MODULE_DEVICE_TABLE(of, wcd937x_of_match);
2964 #endif
2965 
2966 static struct platform_driver wcd937x_codec_driver = {
2967 	.probe = wcd937x_probe,
2968 	.remove = wcd937x_remove,
2969 	.driver = {
2970 		.name = "wcd937x_codec",
2971 		.of_match_table = of_match_ptr(wcd937x_of_match),
2972 		.suppress_bind_attrs = true,
2973 	},
2974 };
2975 
2976 module_platform_driver(wcd937x_codec_driver);
2977 MODULE_DESCRIPTION("WCD937X Codec driver");
2978 MODULE_LICENSE("GPL");
2979