1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 4 #include <linux/component.h> 5 #include <linux/delay.h> 6 #include <linux/device.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/slab.h> 16 #include <sound/jack.h> 17 #include <sound/pcm_params.h> 18 #include <sound/pcm.h> 19 #include <sound/soc-dapm.h> 20 #include <sound/soc.h> 21 #include <sound/tlv.h> 22 23 #include "wcd-clsh-v2.h" 24 #include "wcd-mbhc-v2.h" 25 #include "wcd937x.h" 26 27 enum { 28 CHIPID_WCD9370 = 0, 29 CHIPID_WCD9375 = 5, 30 }; 31 32 /* Z value defined in milliohm */ 33 #define WCD937X_ZDET_VAL_32 (32000) 34 #define WCD937X_ZDET_VAL_400 (400000) 35 #define WCD937X_ZDET_VAL_1200 (1200000) 36 #define WCD937X_ZDET_VAL_100K (100000000) 37 /* Z floating defined in ohms */ 38 #define WCD937X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE) 39 #define WCD937X_ZDET_NUM_MEASUREMENTS (900) 40 #define WCD937X_MBHC_GET_C1(c) (((c) & 0xC000) >> 14) 41 #define WCD937X_MBHC_GET_X1(x) ((x) & 0x3FFF) 42 /* Z value compared in milliOhm */ 43 #define WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z) (((z) > 400000) || ((z) < 32000)) 44 #define WCD937X_MBHC_ZDET_CONST (86 * 16384) 45 #define WCD937X_MBHC_MOISTURE_RREF R_24_KOHM 46 #define WCD_MBHC_HS_V_MAX 1600 47 #define EAR_RX_PATH_AUX 1 48 #define WCD937X_MBHC_MAX_BUTTONS 8 49 50 #define WCD937X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 51 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 52 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\ 53 SNDRV_PCM_RATE_384000) 54 55 /* Fractional Rates */ 56 #define WCD937X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 57 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800) 58 59 #define WCD937X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |\ 60 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 61 62 enum { 63 ALLOW_BUCK_DISABLE, 64 HPH_COMP_DELAY, 65 HPH_PA_DELAY, 66 AMIC2_BCS_ENABLE, 67 }; 68 69 enum { 70 AIF1_PB = 0, 71 AIF1_CAP, 72 NUM_CODEC_DAIS, 73 }; 74 75 struct wcd937x_priv { 76 struct sdw_slave *tx_sdw_dev; 77 struct wcd937x_sdw_priv *sdw_priv[NUM_CODEC_DAIS]; 78 struct device *txdev; 79 struct device *rxdev; 80 struct device_node *rxnode; 81 struct device_node *txnode; 82 struct regmap *regmap; 83 /* micb setup lock */ 84 struct mutex micb_lock; 85 /* mbhc module */ 86 struct wcd_mbhc *wcd_mbhc; 87 struct wcd_mbhc_config mbhc_cfg; 88 struct wcd_mbhc_intr intr_ids; 89 struct wcd_clsh_ctrl *clsh_info; 90 struct irq_domain *virq; 91 struct regmap_irq_chip *wcd_regmap_irq_chip; 92 struct regmap_irq_chip_data *irq_chip; 93 struct regulator_bulk_data supplies[WCD937X_MAX_BULK_SUPPLY]; 94 struct regulator *buck_supply; 95 struct snd_soc_jack *jack; 96 unsigned long status_mask; 97 s32 micb_ref[WCD937X_MAX_MICBIAS]; 98 s32 pullup_ref[WCD937X_MAX_MICBIAS]; 99 u32 hph_mode; 100 int ear_rx_path; 101 u32 micb1_mv; 102 u32 micb2_mv; 103 u32 micb3_mv; 104 int hphr_pdm_wd_int; 105 int hphl_pdm_wd_int; 106 int aux_pdm_wd_int; 107 bool comp1_enable; 108 bool comp2_enable; 109 110 struct gpio_desc *us_euro_gpio; 111 struct gpio_desc *reset_gpio; 112 113 atomic_t rx_clk_cnt; 114 atomic_t ana_clk_count; 115 }; 116 117 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800); 118 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 119 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 120 121 struct wcd937x_mbhc_zdet_param { 122 u16 ldo_ctl; 123 u16 noff; 124 u16 nshift; 125 u16 btn5; 126 u16 btn6; 127 u16 btn7; 128 }; 129 130 static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 131 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD937X_ANA_MBHC_MECH, 0x80), 132 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD937X_ANA_MBHC_MECH, 0x40), 133 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD937X_ANA_MBHC_MECH, 0x20), 134 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD937X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 135 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD937X_ANA_MBHC_ELECT, 0x08), 136 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F), 137 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD937X_ANA_MBHC_MECH, 0x04), 138 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD937X_ANA_MBHC_MECH, 0x10), 139 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD937X_ANA_MBHC_MECH, 0x08), 140 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD937X_ANA_MBHC_MECH, 0x01), 141 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD937X_ANA_MBHC_ELECT, 0x06), 142 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD937X_ANA_MBHC_ELECT, 0x80), 143 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD937X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 144 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD937X_MBHC_NEW_CTL_1, 0x03), 145 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD937X_MBHC_NEW_CTL_2, 0x03), 146 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x08), 147 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD937X_ANA_MBHC_RESULT_3, 0x10), 148 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x20), 149 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x80), 150 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x40), 151 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD937X_HPH_OCP_CTL, 0x10), 152 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x07), 153 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD937X_ANA_MBHC_ELECT, 0x70), 154 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0xFF), 155 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD937X_ANA_MICB2, 0xC0), 156 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD937X_HPH_CNP_WG_TIME, 0xFF), 157 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD937X_ANA_HPH, 0x40), 158 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD937X_ANA_HPH, 0x80), 159 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD937X_ANA_HPH, 0xC0), 160 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD937X_ANA_MBHC_RESULT_3, 0x10), 161 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD937X_MBHC_CTL_BCS, 0x02), 162 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD937X_MBHC_NEW_FSM_STATUS, 0x01), 163 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD937X_MBHC_NEW_CTL_2, 0x70), 164 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD937X_MBHC_NEW_FSM_STATUS, 0x20), 165 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD937X_HPH_PA_CTL2, 0x40), 166 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD937X_HPH_PA_CTL2, 0x10), 167 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD937X_HPH_L_TEST, 0x01), 168 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD937X_HPH_R_TEST, 0x01), 169 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD937X_DIGITAL_INTR_STATUS_0, 0x80), 170 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD937X_DIGITAL_INTR_STATUS_0, 0x20), 171 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD937X_MBHC_NEW_CTL_1, 0x08), 172 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD937X_MBHC_NEW_FSM_STATUS, 0x40), 173 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD937X_MBHC_NEW_FSM_STATUS, 0x80), 174 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD937X_MBHC_NEW_ADC_RESULT, 0xFF), 175 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD937X_ANA_MICB2, 0x3F), 176 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD937X_MBHC_NEW_CTL_1, 0x10), 177 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD937X_MBHC_NEW_CTL_1, 0x04), 178 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD937X_ANA_MBHC_ZDET, 0x02), 179 }; 180 181 static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = { 182 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, BIT(0)), 183 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, BIT(1)), 184 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, BIT(2)), 185 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, BIT(3)), 186 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, BIT(4)), 187 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, BIT(5)), 188 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, BIT(6)), 189 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, BIT(7)), 190 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, BIT(0)), 191 REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, BIT(1)), 192 REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, BIT(2)), 193 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, BIT(3)), 194 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, BIT(4)), 195 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, BIT(5)), 196 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, BIT(6)), 197 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, BIT(7)), 198 REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, BIT(0)), 199 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, BIT(1)), 200 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, BIT(2)), 201 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, BIT(3)), 202 }; 203 204 static int wcd937x_handle_post_irq(void *data) 205 { 206 struct wcd937x_priv *wcd937x; 207 208 if (data) 209 wcd937x = (struct wcd937x_priv *)data; 210 else 211 return IRQ_HANDLED; 212 213 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_0, 0); 214 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_1, 0); 215 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_2, 0); 216 217 return IRQ_HANDLED; 218 } 219 220 static const u32 wcd937x_config_regs[] = { 221 WCD937X_DIGITAL_INTR_LEVEL_0, 222 }; 223 224 static const struct regmap_irq_chip wcd937x_regmap_irq_chip = { 225 .name = "wcd937x", 226 .irqs = wcd937x_irqs, 227 .num_irqs = ARRAY_SIZE(wcd937x_irqs), 228 .num_regs = 3, 229 .status_base = WCD937X_DIGITAL_INTR_STATUS_0, 230 .mask_base = WCD937X_DIGITAL_INTR_MASK_0, 231 .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0, 232 .use_ack = 1, 233 .clear_ack = 1, 234 .config_base = wcd937x_config_regs, 235 .num_config_bases = ARRAY_SIZE(wcd937x_config_regs), 236 .num_config_regs = 1, 237 .runtime_pm = true, 238 .handle_post_irq = wcd937x_handle_post_irq, 239 .irq_drv_data = NULL, 240 }; 241 242 static void wcd937x_reset(struct wcd937x_priv *wcd937x) 243 { 244 gpiod_set_value(wcd937x->reset_gpio, 1); 245 usleep_range(20, 30); 246 gpiod_set_value(wcd937x->reset_gpio, 0); 247 usleep_range(20, 30); 248 } 249 250 static void wcd937x_io_init(struct regmap *regmap) 251 { 252 u32 val = 0, temp = 0, temp1 = 0; 253 254 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_29, &val); 255 256 val = val & 0x0F; 257 258 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_16, &temp); 259 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_17, &temp1); 260 261 if (temp == 0x02 || temp1 > 0x09) 262 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x0E, val); 263 else 264 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x0e, 0x0e); 265 266 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x80, 0x80); 267 usleep_range(1000, 1010); 268 269 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x40, 0x40); 270 usleep_range(1000, 1010); 271 272 regmap_update_bits(regmap, WCD937X_LDORXTX_CONFIG, BIT(4), 0x00); 273 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xf0, BIT(7)); 274 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(7), BIT(7)); 275 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(6), BIT(6)); 276 usleep_range(10000, 10010); 277 278 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(6), 0x00); 279 regmap_update_bits(regmap, WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xff, 0xd9); 280 regmap_update_bits(regmap, WCD937X_MICB1_TEST_CTL_1, 0xff, 0xfa); 281 regmap_update_bits(regmap, WCD937X_MICB2_TEST_CTL_1, 0xff, 0xfa); 282 regmap_update_bits(regmap, WCD937X_MICB3_TEST_CTL_1, 0xff, 0xfa); 283 284 regmap_update_bits(regmap, WCD937X_MICB1_TEST_CTL_2, 0x38, 0x00); 285 regmap_update_bits(regmap, WCD937X_MICB2_TEST_CTL_2, 0x38, 0x00); 286 regmap_update_bits(regmap, WCD937X_MICB3_TEST_CTL_2, 0x38, 0x00); 287 288 /* Set Bandgap Fine Adjustment to +5mV for Tanggu SMIC part */ 289 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_16, &val); 290 if (val == 0x01) { 291 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0); 292 } else if (val == 0x02) { 293 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x1F, 0x04); 294 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x1F, 0x04); 295 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0); 296 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL, 0xF0, 0x50); 297 } 298 } 299 300 static int wcd937x_rx_clk_enable(struct snd_soc_component *component) 301 { 302 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 303 304 if (atomic_read(&wcd937x->rx_clk_cnt)) 305 return 0; 306 307 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(3), BIT(3)); 308 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(0), BIT(0)); 309 snd_soc_component_update_bits(component, WCD937X_ANA_RX_SUPPLIES, BIT(0), BIT(0)); 310 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX0_CTL, BIT(6), 0x00); 311 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX1_CTL, BIT(6), 0x00); 312 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX2_CTL, BIT(6), 0x00); 313 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(1), BIT(1)); 314 315 atomic_inc(&wcd937x->rx_clk_cnt); 316 317 return 0; 318 } 319 320 static int wcd937x_rx_clk_disable(struct snd_soc_component *component) 321 { 322 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 323 324 if (!atomic_read(&wcd937x->rx_clk_cnt)) { 325 dev_err(component->dev, "clk already disabled\n"); 326 return 0; 327 } 328 329 atomic_dec(&wcd937x->rx_clk_cnt); 330 331 snd_soc_component_update_bits(component, WCD937X_ANA_RX_SUPPLIES, BIT(0), 0x00); 332 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(1), 0x00); 333 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(0), 0x00); 334 335 return 0; 336 } 337 338 static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 339 struct snd_kcontrol *kcontrol, 340 int event) 341 { 342 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 343 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 344 int hph_mode = wcd937x->hph_mode; 345 346 switch (event) { 347 case SND_SOC_DAPM_PRE_PMU: 348 wcd937x_rx_clk_enable(component); 349 snd_soc_component_update_bits(component, 350 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 351 BIT(0), BIT(0)); 352 snd_soc_component_update_bits(component, 353 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 354 BIT(2), BIT(2)); 355 snd_soc_component_update_bits(component, 356 WCD937X_HPH_RDAC_CLK_CTL1, 357 BIT(7), 0x00); 358 set_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 359 break; 360 case SND_SOC_DAPM_POST_PMU: 361 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 362 snd_soc_component_update_bits(component, 363 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 364 0x0f, BIT(1)); 365 else if (hph_mode == CLS_H_LOHIFI) 366 snd_soc_component_update_bits(component, 367 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 368 0x0f, 0x06); 369 370 if (wcd937x->comp1_enable) { 371 snd_soc_component_update_bits(component, 372 WCD937X_DIGITAL_CDC_COMP_CTL_0, 373 BIT(1), BIT(1)); 374 snd_soc_component_update_bits(component, 375 WCD937X_HPH_L_EN, 376 BIT(5), 0x00); 377 378 if (wcd937x->comp2_enable) { 379 snd_soc_component_update_bits(component, 380 WCD937X_DIGITAL_CDC_COMP_CTL_0, 381 BIT(0), BIT(0)); 382 snd_soc_component_update_bits(component, 383 WCD937X_HPH_R_EN, BIT(5), 0x00); 384 } 385 386 if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) { 387 usleep_range(5000, 5110); 388 clear_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 389 } 390 } else { 391 snd_soc_component_update_bits(component, 392 WCD937X_DIGITAL_CDC_COMP_CTL_0, 393 BIT(1), 0x00); 394 snd_soc_component_update_bits(component, 395 WCD937X_HPH_L_EN, 396 BIT(5), BIT(5)); 397 } 398 399 snd_soc_component_update_bits(component, 400 WCD937X_HPH_NEW_INT_HPH_TIMER1, 401 BIT(1), 0x00); 402 break; 403 case SND_SOC_DAPM_POST_PMD: 404 snd_soc_component_update_bits(component, 405 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 406 0x0f, BIT(0)); 407 break; 408 } 409 410 return 0; 411 } 412 413 static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 414 struct snd_kcontrol *kcontrol, 415 int event) 416 { 417 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 418 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 419 int hph_mode = wcd937x->hph_mode; 420 421 switch (event) { 422 case SND_SOC_DAPM_PRE_PMU: 423 wcd937x_rx_clk_enable(component); 424 snd_soc_component_update_bits(component, 425 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(1), BIT(1)); 426 snd_soc_component_update_bits(component, 427 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, BIT(3), BIT(3)); 428 snd_soc_component_update_bits(component, 429 WCD937X_HPH_RDAC_CLK_CTL1, BIT(7), 0x00); 430 set_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 431 break; 432 case SND_SOC_DAPM_POST_PMU: 433 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 434 snd_soc_component_update_bits(component, 435 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 436 0x0f, BIT(1)); 437 else if (hph_mode == CLS_H_LOHIFI) 438 snd_soc_component_update_bits(component, 439 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 440 0x0f, 0x06); 441 if (wcd937x->comp2_enable) { 442 snd_soc_component_update_bits(component, 443 WCD937X_DIGITAL_CDC_COMP_CTL_0, 444 BIT(0), BIT(0)); 445 snd_soc_component_update_bits(component, 446 WCD937X_HPH_R_EN, BIT(5), 0x00); 447 if (wcd937x->comp1_enable) { 448 snd_soc_component_update_bits(component, 449 WCD937X_DIGITAL_CDC_COMP_CTL_0, 450 BIT(1), BIT(1)); 451 snd_soc_component_update_bits(component, 452 WCD937X_HPH_L_EN, 453 BIT(5), 0x00); 454 } 455 456 if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) { 457 usleep_range(5000, 5110); 458 clear_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 459 } 460 } else { 461 snd_soc_component_update_bits(component, 462 WCD937X_DIGITAL_CDC_COMP_CTL_0, 463 BIT(0), 0x00); 464 snd_soc_component_update_bits(component, 465 WCD937X_HPH_R_EN, 466 BIT(5), BIT(5)); 467 } 468 snd_soc_component_update_bits(component, 469 WCD937X_HPH_NEW_INT_HPH_TIMER1, 470 BIT(1), 0x00); 471 break; 472 case SND_SOC_DAPM_POST_PMD: 473 snd_soc_component_update_bits(component, 474 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 475 0x0f, BIT(0)); 476 break; 477 } 478 479 return 0; 480 } 481 482 static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 483 struct snd_kcontrol *kcontrol, 484 int event) 485 { 486 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 487 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 488 int hph_mode = wcd937x->hph_mode; 489 490 switch (event) { 491 case SND_SOC_DAPM_PRE_PMU: 492 wcd937x_rx_clk_enable(component); 493 snd_soc_component_update_bits(component, 494 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 495 BIT(2), BIT(2)); 496 snd_soc_component_update_bits(component, 497 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 498 BIT(0), BIT(0)); 499 500 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 501 snd_soc_component_update_bits(component, 502 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 503 0x0f, BIT(1)); 504 else if (hph_mode == CLS_H_LOHIFI) 505 snd_soc_component_update_bits(component, 506 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 507 0x0f, 0x06); 508 if (wcd937x->comp1_enable) 509 snd_soc_component_update_bits(component, 510 WCD937X_DIGITAL_CDC_COMP_CTL_0, 511 BIT(1), BIT(1)); 512 usleep_range(5000, 5010); 513 514 snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN, BIT(2), 0x00); 515 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 516 WCD_CLSH_EVENT_PRE_DAC, 517 WCD_CLSH_STATE_EAR, 518 hph_mode); 519 520 break; 521 case SND_SOC_DAPM_POST_PMD: 522 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI || 523 hph_mode == CLS_H_HIFI) 524 snd_soc_component_update_bits(component, 525 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 526 0x0f, BIT(0)); 527 if (wcd937x->comp1_enable) 528 snd_soc_component_update_bits(component, 529 WCD937X_DIGITAL_CDC_COMP_CTL_0, 530 BIT(1), 0x00); 531 break; 532 } 533 534 return 0; 535 } 536 537 static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w, 538 struct snd_kcontrol *kcontrol, 539 int event) 540 { 541 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 542 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 543 int hph_mode = wcd937x->hph_mode; 544 545 switch (event) { 546 case SND_SOC_DAPM_PRE_PMU: 547 wcd937x_rx_clk_enable(component); 548 snd_soc_component_update_bits(component, 549 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 550 BIT(2), BIT(2)); 551 snd_soc_component_update_bits(component, 552 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 553 BIT(2), BIT(2)); 554 snd_soc_component_update_bits(component, 555 WCD937X_DIGITAL_CDC_AUX_GAIN_CTL, 556 BIT(0), BIT(0)); 557 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 558 WCD_CLSH_EVENT_PRE_DAC, 559 WCD_CLSH_STATE_AUX, 560 hph_mode); 561 562 break; 563 case SND_SOC_DAPM_POST_PMD: 564 snd_soc_component_update_bits(component, 565 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 566 BIT(2), 0x00); 567 break; 568 } 569 570 return 0; 571 } 572 573 static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 574 struct snd_kcontrol *kcontrol, 575 int event) 576 { 577 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 578 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 579 int hph_mode = wcd937x->hph_mode; 580 581 switch (event) { 582 case SND_SOC_DAPM_PRE_PMU: 583 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 584 WCD_CLSH_EVENT_PRE_DAC, 585 WCD_CLSH_STATE_HPHR, 586 hph_mode); 587 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 588 BIT(4), BIT(4)); 589 usleep_range(100, 110); 590 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 591 snd_soc_component_update_bits(component, 592 WCD937X_DIGITAL_PDM_WD_CTL1, 593 0x07, 0x03); 594 break; 595 case SND_SOC_DAPM_POST_PMU: 596 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 597 if (wcd937x->comp2_enable) 598 usleep_range(7000, 7100); 599 else 600 usleep_range(20000, 20100); 601 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 602 } 603 604 snd_soc_component_update_bits(component, 605 WCD937X_HPH_NEW_INT_HPH_TIMER1, 606 BIT(1), BIT(1)); 607 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 608 snd_soc_component_update_bits(component, 609 WCD937X_ANA_RX_SUPPLIES, 610 BIT(1), BIT(1)); 611 enable_irq(wcd937x->hphr_pdm_wd_int); 612 break; 613 case SND_SOC_DAPM_PRE_PMD: 614 disable_irq_nosync(wcd937x->hphr_pdm_wd_int); 615 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 616 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_PRE_HPHR_PA_OFF); 617 break; 618 case SND_SOC_DAPM_POST_PMD: 619 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 620 if (wcd937x->comp2_enable) 621 usleep_range(7000, 7100); 622 else 623 usleep_range(20000, 20100); 624 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 625 } 626 627 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_POST_HPHR_PA_OFF); 628 snd_soc_component_update_bits(component, 629 WCD937X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00); 630 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 631 BIT(4), 0x00); 632 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 633 WCD_CLSH_EVENT_POST_PA, 634 WCD_CLSH_STATE_HPHR, 635 hph_mode); 636 break; 637 } 638 639 return 0; 640 } 641 642 static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 643 struct snd_kcontrol *kcontrol, 644 int event) 645 { 646 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 647 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 648 int hph_mode = wcd937x->hph_mode; 649 650 switch (event) { 651 case SND_SOC_DAPM_PRE_PMU: 652 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 653 WCD_CLSH_EVENT_PRE_DAC, 654 WCD_CLSH_STATE_HPHL, 655 hph_mode); 656 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 657 BIT(5), BIT(5)); 658 usleep_range(100, 110); 659 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 660 snd_soc_component_update_bits(component, 661 WCD937X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03); 662 break; 663 case SND_SOC_DAPM_POST_PMU: 664 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 665 if (!wcd937x->comp1_enable) 666 usleep_range(20000, 20100); 667 else 668 usleep_range(7000, 7100); 669 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 670 } 671 672 snd_soc_component_update_bits(component, 673 WCD937X_HPH_NEW_INT_HPH_TIMER1, 674 BIT(1), BIT(1)); 675 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 676 snd_soc_component_update_bits(component, 677 WCD937X_ANA_RX_SUPPLIES, 678 BIT(1), BIT(1)); 679 enable_irq(wcd937x->hphl_pdm_wd_int); 680 break; 681 case SND_SOC_DAPM_PRE_PMD: 682 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 683 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 684 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF); 685 break; 686 case SND_SOC_DAPM_POST_PMD: 687 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 688 if (!wcd937x->comp1_enable) 689 usleep_range(20000, 20100); 690 else 691 usleep_range(7000, 7100); 692 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 693 } 694 695 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 696 snd_soc_component_update_bits(component, 697 WCD937X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00); 698 snd_soc_component_update_bits(component, 699 WCD937X_ANA_HPH, BIT(5), 0x00); 700 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 701 WCD_CLSH_EVENT_POST_PA, 702 WCD_CLSH_STATE_HPHL, 703 hph_mode); 704 break; 705 } 706 707 return 0; 708 } 709 710 static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w, 711 struct snd_kcontrol *kcontrol, 712 int event) 713 { 714 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 715 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 716 int hph_mode = wcd937x->hph_mode; 717 u8 val; 718 719 switch (event) { 720 case SND_SOC_DAPM_PRE_PMU: 721 val = WCD937X_DIGITAL_PDM_WD_CTL2_EN | 722 WCD937X_DIGITAL_PDM_WD_CTL2_TIMEOUT_SEL | 723 WCD937X_DIGITAL_PDM_WD_CTL2_HOLD_OFF; 724 snd_soc_component_update_bits(component, 725 WCD937X_DIGITAL_PDM_WD_CTL2, 726 WCD937X_DIGITAL_PDM_WD_CTL2_MASK, 727 val); 728 break; 729 case SND_SOC_DAPM_POST_PMU: 730 usleep_range(1000, 1010); 731 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 732 snd_soc_component_update_bits(component, 733 WCD937X_ANA_RX_SUPPLIES, 734 BIT(1), BIT(1)); 735 enable_irq(wcd937x->aux_pdm_wd_int); 736 break; 737 case SND_SOC_DAPM_PRE_PMD: 738 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 739 break; 740 case SND_SOC_DAPM_POST_PMD: 741 usleep_range(2000, 2010); 742 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 743 WCD_CLSH_EVENT_POST_PA, 744 WCD_CLSH_STATE_AUX, 745 hph_mode); 746 snd_soc_component_update_bits(component, 747 WCD937X_DIGITAL_PDM_WD_CTL2, 748 WCD937X_DIGITAL_PDM_WD_CTL2_MASK, 749 0x00); 750 break; 751 } 752 753 return 0; 754 } 755 756 static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 757 struct snd_kcontrol *kcontrol, 758 int event) 759 { 760 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 761 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 762 int hph_mode = wcd937x->hph_mode; 763 764 switch (event) { 765 case SND_SOC_DAPM_PRE_PMU: 766 /* Enable watchdog interrupt for HPHL or AUX depending on mux value */ 767 wcd937x->ear_rx_path = snd_soc_component_read(component, 768 WCD937X_DIGITAL_CDC_EAR_PATH_CTL); 769 770 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 771 snd_soc_component_update_bits(component, 772 WCD937X_DIGITAL_PDM_WD_CTL2, 773 BIT(0), BIT(0)); 774 else 775 snd_soc_component_update_bits(component, 776 WCD937X_DIGITAL_PDM_WD_CTL0, 777 0x07, 0x03); 778 if (!wcd937x->comp1_enable) 779 snd_soc_component_update_bits(component, 780 WCD937X_ANA_EAR_COMPANDER_CTL, 781 BIT(7), BIT(7)); 782 break; 783 case SND_SOC_DAPM_POST_PMU: 784 usleep_range(6000, 6010); 785 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 786 snd_soc_component_update_bits(component, 787 WCD937X_ANA_RX_SUPPLIES, 788 BIT(1), BIT(1)); 789 790 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 791 enable_irq(wcd937x->aux_pdm_wd_int); 792 else 793 enable_irq(wcd937x->hphl_pdm_wd_int); 794 break; 795 case SND_SOC_DAPM_PRE_PMD: 796 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 797 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 798 else 799 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 800 break; 801 case SND_SOC_DAPM_POST_PMD: 802 if (!wcd937x->comp1_enable) 803 snd_soc_component_update_bits(component, 804 WCD937X_ANA_EAR_COMPANDER_CTL, 805 BIT(7), 0x00); 806 usleep_range(7000, 7010); 807 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 808 WCD_CLSH_EVENT_POST_PA, 809 WCD_CLSH_STATE_EAR, 810 hph_mode); 811 snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN, 812 BIT(2), BIT(2)); 813 814 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 815 snd_soc_component_update_bits(component, 816 WCD937X_DIGITAL_PDM_WD_CTL2, 817 BIT(0), 0x00); 818 else 819 snd_soc_component_update_bits(component, 820 WCD937X_DIGITAL_PDM_WD_CTL0, 821 0x07, 0x00); 822 break; 823 } 824 825 return 0; 826 } 827 828 static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w, 829 struct snd_kcontrol *kcontrol, 830 int event) 831 { 832 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 833 834 if (event == SND_SOC_DAPM_POST_PMD) { 835 wcd937x_rx_clk_disable(component); 836 snd_soc_component_update_bits(component, 837 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 838 BIT(0), 0x00); 839 } 840 841 return 0; 842 } 843 844 static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w, 845 struct snd_kcontrol *kcontrol, int event) 846 { 847 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 848 849 if (event == SND_SOC_DAPM_POST_PMD) { 850 wcd937x_rx_clk_disable(component); 851 snd_soc_component_update_bits(component, 852 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 853 BIT(1), 0x00); 854 } 855 856 return 0; 857 } 858 859 static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w, 860 struct snd_kcontrol *kcontrol, 861 int event) 862 { 863 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 864 865 if (event == SND_SOC_DAPM_POST_PMD) { 866 usleep_range(6000, 6010); 867 wcd937x_rx_clk_disable(component); 868 snd_soc_component_update_bits(component, 869 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 870 BIT(2), 0x00); 871 } 872 873 return 0; 874 } 875 876 static int wcd937x_get_micb_vout_ctl_val(u32 micb_mv) 877 { 878 if (micb_mv < 1000 || micb_mv > 2850) { 879 pr_err("Unsupported micbias voltage (%u mV)\n", micb_mv); 880 return -EINVAL; 881 } 882 883 return (micb_mv - 1000) / 50; 884 } 885 886 static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w, 887 struct snd_kcontrol *kcontrol, int event) 888 { 889 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 890 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 891 bool use_amic3 = snd_soc_component_read(component, WCD937X_TX_NEW_TX_CH2_SEL) & BIT(7); 892 893 /* Enable BCS for Headset mic */ 894 if (event == SND_SOC_DAPM_PRE_PMU && strnstr(w->name, "ADC", sizeof("ADC"))) 895 if (w->shift == 1 && !use_amic3) 896 set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask); 897 898 return 0; 899 } 900 901 static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w, 902 struct snd_kcontrol *kcontrol, int event) 903 { 904 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 905 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 906 907 switch (event) { 908 case SND_SOC_DAPM_PRE_PMU: 909 atomic_inc(&wcd937x->ana_clk_count); 910 snd_soc_component_update_bits(component, 911 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(7), BIT(7)); 912 snd_soc_component_update_bits(component, 913 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(3), BIT(3)); 914 snd_soc_component_update_bits(component, 915 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(4), BIT(4)); 916 break; 917 case SND_SOC_DAPM_POST_PMD: 918 if (w->shift == 1 && test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) 919 clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask); 920 921 snd_soc_component_update_bits(component, 922 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(3), 0x00); 923 break; 924 } 925 926 return 0; 927 } 928 929 static int wcd937x_enable_req(struct snd_soc_dapm_widget *w, 930 struct snd_kcontrol *kcontrol, int event) 931 { 932 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 933 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 934 935 switch (event) { 936 case SND_SOC_DAPM_PRE_PMU: 937 snd_soc_component_update_bits(component, 938 WCD937X_DIGITAL_CDC_REQ_CTL, BIT(1), BIT(1)); 939 snd_soc_component_update_bits(component, 940 WCD937X_DIGITAL_CDC_REQ_CTL, BIT(0), 0x00); 941 snd_soc_component_update_bits(component, 942 WCD937X_ANA_TX_CH2, BIT(6), BIT(6)); 943 snd_soc_component_update_bits(component, 944 WCD937X_ANA_TX_CH3_HPF, BIT(6), BIT(6)); 945 snd_soc_component_update_bits(component, 946 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70); 947 snd_soc_component_update_bits(component, 948 WCD937X_ANA_TX_CH1, BIT(7), BIT(7)); 949 snd_soc_component_update_bits(component, 950 WCD937X_ANA_TX_CH2, BIT(6), 0x00); 951 snd_soc_component_update_bits(component, 952 WCD937X_ANA_TX_CH2, BIT(7), BIT(7)); 953 snd_soc_component_update_bits(component, 954 WCD937X_ANA_TX_CH3, BIT(7), BIT(7)); 955 break; 956 case SND_SOC_DAPM_POST_PMD: 957 snd_soc_component_update_bits(component, 958 WCD937X_ANA_TX_CH1, BIT(7), 0x00); 959 snd_soc_component_update_bits(component, 960 WCD937X_ANA_TX_CH2, BIT(7), 0x00); 961 snd_soc_component_update_bits(component, 962 WCD937X_ANA_TX_CH3, BIT(7), 0x00); 963 snd_soc_component_update_bits(component, 964 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(4), 0x00); 965 966 atomic_dec(&wcd937x->ana_clk_count); 967 if (atomic_read(&wcd937x->ana_clk_count) <= 0) { 968 snd_soc_component_update_bits(component, 969 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 970 BIT(4), 0x00); 971 atomic_set(&wcd937x->ana_clk_count, 0); 972 } 973 974 snd_soc_component_update_bits(component, 975 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 976 BIT(7), 0x00); 977 break; 978 } 979 980 return 0; 981 } 982 983 static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 984 struct snd_kcontrol *kcontrol, 985 int event) 986 { 987 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 988 u16 dmic_clk_reg; 989 990 switch (w->shift) { 991 case 0: 992 case 1: 993 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL; 994 break; 995 case 2: 996 case 3: 997 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL; 998 break; 999 case 4: 1000 case 5: 1001 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL; 1002 break; 1003 default: 1004 dev_err(component->dev, "Invalid DMIC Selection\n"); 1005 return -EINVAL; 1006 } 1007 1008 switch (event) { 1009 case SND_SOC_DAPM_PRE_PMU: 1010 snd_soc_component_update_bits(component, 1011 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 1012 BIT(7), BIT(7)); 1013 snd_soc_component_update_bits(component, 1014 dmic_clk_reg, 0x07, BIT(1)); 1015 snd_soc_component_update_bits(component, 1016 dmic_clk_reg, BIT(3), BIT(3)); 1017 snd_soc_component_update_bits(component, 1018 dmic_clk_reg, 0x70, BIT(5)); 1019 break; 1020 } 1021 1022 return 0; 1023 } 1024 1025 static int wcd937x_micbias_control(struct snd_soc_component *component, 1026 int micb_num, int req, bool is_dapm) 1027 { 1028 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1029 int micb_index = micb_num - 1; 1030 u16 micb_reg; 1031 1032 if (micb_index < 0 || (micb_index > WCD937X_MAX_MICBIAS - 1)) { 1033 dev_err(component->dev, "Invalid micbias index, micb_ind:%d\n", micb_index); 1034 return -EINVAL; 1035 } 1036 switch (micb_num) { 1037 case MIC_BIAS_1: 1038 micb_reg = WCD937X_ANA_MICB1; 1039 break; 1040 case MIC_BIAS_2: 1041 micb_reg = WCD937X_ANA_MICB2; 1042 break; 1043 case MIC_BIAS_3: 1044 micb_reg = WCD937X_ANA_MICB3; 1045 break; 1046 default: 1047 dev_err(component->dev, "Invalid micbias number: %d\n", micb_num); 1048 return -EINVAL; 1049 } 1050 1051 mutex_lock(&wcd937x->micb_lock); 1052 switch (req) { 1053 case MICB_PULLUP_ENABLE: 1054 wcd937x->pullup_ref[micb_index]++; 1055 if (wcd937x->pullup_ref[micb_index] == 1 && 1056 wcd937x->micb_ref[micb_index] == 0) 1057 snd_soc_component_update_bits(component, micb_reg, 1058 0xc0, BIT(7)); 1059 break; 1060 case MICB_PULLUP_DISABLE: 1061 if (wcd937x->pullup_ref[micb_index] > 0) 1062 wcd937x->pullup_ref[micb_index]++; 1063 if (wcd937x->pullup_ref[micb_index] == 0 && 1064 wcd937x->micb_ref[micb_index] == 0) 1065 snd_soc_component_update_bits(component, micb_reg, 1066 0xc0, 0x00); 1067 break; 1068 case MICB_ENABLE: 1069 wcd937x->micb_ref[micb_index]++; 1070 atomic_inc(&wcd937x->ana_clk_count); 1071 if (wcd937x->micb_ref[micb_index] == 1) { 1072 snd_soc_component_update_bits(component, 1073 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 1074 0xf0, 0xf0); 1075 snd_soc_component_update_bits(component, 1076 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 1077 BIT(4), BIT(4)); 1078 snd_soc_component_update_bits(component, 1079 WCD937X_MICB1_TEST_CTL_2, 1080 BIT(0), BIT(0)); 1081 snd_soc_component_update_bits(component, 1082 WCD937X_MICB2_TEST_CTL_2, 1083 BIT(0), BIT(0)); 1084 snd_soc_component_update_bits(component, 1085 WCD937X_MICB3_TEST_CTL_2, 1086 BIT(0), BIT(0)); 1087 snd_soc_component_update_bits(component, 1088 micb_reg, 0xc0, BIT(6)); 1089 1090 if (micb_num == MIC_BIAS_2) 1091 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1092 WCD_EVENT_POST_MICBIAS_2_ON); 1093 1094 if (micb_num == MIC_BIAS_2 && is_dapm) 1095 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1096 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 1097 } 1098 break; 1099 case MICB_DISABLE: 1100 atomic_dec(&wcd937x->ana_clk_count); 1101 if (wcd937x->micb_ref[micb_index] > 0) 1102 wcd937x->micb_ref[micb_index]--; 1103 if (wcd937x->micb_ref[micb_index] == 0 && 1104 wcd937x->pullup_ref[micb_index] > 0) 1105 snd_soc_component_update_bits(component, micb_reg, 1106 0xc0, BIT(7)); 1107 else if (wcd937x->micb_ref[micb_index] == 0 && 1108 wcd937x->pullup_ref[micb_index] == 0) { 1109 if (micb_num == MIC_BIAS_2) 1110 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1111 WCD_EVENT_PRE_MICBIAS_2_OFF); 1112 1113 snd_soc_component_update_bits(component, micb_reg, 1114 0xc0, 0x00); 1115 if (micb_num == MIC_BIAS_2) 1116 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1117 WCD_EVENT_POST_MICBIAS_2_OFF); 1118 } 1119 1120 if (is_dapm && micb_num == MIC_BIAS_2) 1121 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1122 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 1123 if (atomic_read(&wcd937x->ana_clk_count) <= 0) { 1124 snd_soc_component_update_bits(component, 1125 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 1126 BIT(4), 0x00); 1127 atomic_set(&wcd937x->ana_clk_count, 0); 1128 } 1129 break; 1130 } 1131 mutex_unlock(&wcd937x->micb_lock); 1132 1133 return 0; 1134 } 1135 1136 static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1137 int event) 1138 { 1139 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1140 int micb_num = w->shift; 1141 1142 switch (event) { 1143 case SND_SOC_DAPM_PRE_PMU: 1144 wcd937x_micbias_control(component, micb_num, 1145 MICB_ENABLE, true); 1146 break; 1147 case SND_SOC_DAPM_POST_PMU: 1148 usleep_range(1000, 1100); 1149 break; 1150 case SND_SOC_DAPM_POST_PMD: 1151 wcd937x_micbias_control(component, micb_num, 1152 MICB_DISABLE, true); 1153 break; 1154 } 1155 1156 return 0; 1157 } 1158 1159 static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1160 struct snd_kcontrol *kcontrol, 1161 int event) 1162 { 1163 return __wcd937x_codec_enable_micbias(w, event); 1164 } 1165 1166 static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1167 int event) 1168 { 1169 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1170 int micb_num = w->shift; 1171 1172 switch (event) { 1173 case SND_SOC_DAPM_PRE_PMU: 1174 wcd937x_micbias_control(component, micb_num, MICB_PULLUP_ENABLE, true); 1175 break; 1176 case SND_SOC_DAPM_POST_PMU: 1177 usleep_range(1000, 1100); 1178 break; 1179 case SND_SOC_DAPM_POST_PMD: 1180 wcd937x_micbias_control(component, micb_num, MICB_PULLUP_DISABLE, true); 1181 break; 1182 } 1183 1184 return 0; 1185 } 1186 1187 static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1188 struct snd_kcontrol *kcontrol, 1189 int event) 1190 { 1191 return __wcd937x_codec_enable_micbias_pullup(w, event); 1192 } 1193 1194 static int wcd937x_connect_port(struct wcd937x_sdw_priv *wcd, u8 port_idx, u8 ch_id, bool enable) 1195 { 1196 struct sdw_port_config *port_config = &wcd->port_config[port_idx - 1]; 1197 const struct wcd937x_sdw_ch_info *ch_info = &wcd->ch_info[ch_id]; 1198 u8 port_num = ch_info->port_num; 1199 u8 ch_mask = ch_info->ch_mask; 1200 u8 mstr_port_num, mstr_ch_mask; 1201 struct sdw_slave *sdev = wcd->sdev; 1202 1203 port_config->num = port_num; 1204 1205 mstr_port_num = sdev->m_port_map[port_num]; 1206 mstr_ch_mask = ch_info->master_ch_mask; 1207 1208 if (enable) { 1209 port_config->ch_mask |= ch_mask; 1210 wcd->master_channel_map[mstr_port_num] |= mstr_ch_mask; 1211 } else { 1212 port_config->ch_mask &= ~ch_mask; 1213 wcd->master_channel_map[mstr_port_num] &= ~mstr_ch_mask; 1214 } 1215 1216 return 0; 1217 } 1218 1219 static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol, 1220 struct snd_ctl_elem_value *ucontrol) 1221 { 1222 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1223 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1224 1225 ucontrol->value.integer.value[0] = wcd937x->hph_mode; 1226 return 0; 1227 } 1228 1229 static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol, 1230 struct snd_ctl_elem_value *ucontrol) 1231 { 1232 struct snd_soc_component *component = 1233 snd_soc_kcontrol_component(kcontrol); 1234 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1235 u32 mode_val; 1236 1237 mode_val = ucontrol->value.enumerated.item[0]; 1238 1239 if (!mode_val) 1240 mode_val = CLS_AB; 1241 1242 if (mode_val == wcd937x->hph_mode) 1243 return 0; 1244 1245 switch (mode_val) { 1246 case CLS_H_NORMAL: 1247 case CLS_H_HIFI: 1248 case CLS_H_LP: 1249 case CLS_AB: 1250 case CLS_H_LOHIFI: 1251 case CLS_H_ULP: 1252 case CLS_AB_LP: 1253 case CLS_AB_HIFI: 1254 wcd937x->hph_mode = mode_val; 1255 return 1; 1256 } 1257 1258 dev_dbg(component->dev, "%s: Invalid HPH Mode\n", __func__); 1259 return -EINVAL; 1260 } 1261 1262 static int wcd937x_get_compander(struct snd_kcontrol *kcontrol, 1263 struct snd_ctl_elem_value *ucontrol) 1264 { 1265 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1266 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1267 struct soc_mixer_control *mc; 1268 bool hphr; 1269 1270 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1271 hphr = mc->shift; 1272 1273 ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable : 1274 wcd937x->comp1_enable; 1275 return 0; 1276 } 1277 1278 static int wcd937x_set_compander(struct snd_kcontrol *kcontrol, 1279 struct snd_ctl_elem_value *ucontrol) 1280 { 1281 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1282 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1283 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[AIF1_PB]; 1284 int value = ucontrol->value.integer.value[0]; 1285 struct soc_mixer_control *mc; 1286 int portidx; 1287 bool hphr; 1288 1289 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1290 hphr = mc->shift; 1291 1292 if (hphr) { 1293 if (value == wcd937x->comp2_enable) 1294 return 0; 1295 1296 wcd937x->comp2_enable = value; 1297 } else { 1298 if (value == wcd937x->comp1_enable) 1299 return 0; 1300 1301 wcd937x->comp1_enable = value; 1302 } 1303 1304 portidx = wcd->ch_info[mc->reg].port_num; 1305 1306 if (value) 1307 wcd937x_connect_port(wcd, portidx, mc->reg, true); 1308 else 1309 wcd937x_connect_port(wcd, portidx, mc->reg, false); 1310 1311 return 1; 1312 } 1313 1314 static int wcd937x_get_swr_port(struct snd_kcontrol *kcontrol, 1315 struct snd_ctl_elem_value *ucontrol) 1316 { 1317 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1318 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 1319 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(comp); 1320 struct wcd937x_sdw_priv *wcd; 1321 int dai_id = mixer->shift; 1322 int ch_idx = mixer->reg; 1323 int portidx; 1324 1325 wcd = wcd937x->sdw_priv[dai_id]; 1326 portidx = wcd->ch_info[ch_idx].port_num; 1327 1328 ucontrol->value.integer.value[0] = wcd->port_enable[portidx]; 1329 1330 return 0; 1331 } 1332 1333 static int wcd937x_set_swr_port(struct snd_kcontrol *kcontrol, 1334 struct snd_ctl_elem_value *ucontrol) 1335 { 1336 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1337 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 1338 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(comp); 1339 struct wcd937x_sdw_priv *wcd; 1340 int dai_id = mixer->shift; 1341 int ch_idx = mixer->reg; 1342 int portidx; 1343 bool enable; 1344 1345 wcd = wcd937x->sdw_priv[dai_id]; 1346 1347 portidx = wcd->ch_info[ch_idx].port_num; 1348 1349 enable = ucontrol->value.integer.value[0]; 1350 1351 if (enable == wcd->port_enable[portidx]) { 1352 wcd937x_connect_port(wcd, portidx, ch_idx, enable); 1353 return 0; 1354 } 1355 1356 wcd->port_enable[portidx] = enable; 1357 wcd937x_connect_port(wcd, portidx, ch_idx, enable); 1358 1359 return 1; 1360 } 1361 1362 static const char * const rx_hph_mode_mux_text[] = { 1363 "CLS_H_NORMAL", "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", 1364 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_AB_LP", "CLS_AB_HIFI", 1365 }; 1366 1367 static const struct soc_enum rx_hph_mode_mux_enum = 1368 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), rx_hph_mode_mux_text); 1369 1370 /* MBHC related */ 1371 static void wcd937x_mbhc_clk_setup(struct snd_soc_component *component, 1372 bool enable) 1373 { 1374 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_1, 1375 WCD937X_MBHC_CTL_RCO_EN_MASK, enable); 1376 } 1377 1378 static void wcd937x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 1379 bool enable) 1380 { 1381 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_ELECT, 1382 WCD937X_ANA_MBHC_BIAS_EN, enable); 1383 } 1384 1385 static void wcd937x_mbhc_program_btn_thr(struct snd_soc_component *component, 1386 int *btn_low, int *btn_high, 1387 int num_btn, bool is_micbias) 1388 { 1389 int i, vth; 1390 1391 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 1392 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 1393 __func__, num_btn); 1394 return; 1395 } 1396 1397 for (i = 0; i < num_btn; i++) { 1398 vth = ((btn_high[i] * 2) / 25) & 0x3F; 1399 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_BTN0 + i, 1400 WCD937X_MBHC_BTN_VTH_MASK, vth); 1401 } 1402 } 1403 1404 static bool wcd937x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 1405 { 1406 u8 val; 1407 1408 if (micb_num == MIC_BIAS_2) { 1409 val = snd_soc_component_read_field(component, 1410 WCD937X_ANA_MICB2, 1411 WCD937X_ANA_MICB2_ENABLE_MASK); 1412 if (val == WCD937X_MICB_ENABLE) 1413 return true; 1414 } 1415 return false; 1416 } 1417 1418 static void wcd937x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 1419 int pull_up_cur) 1420 { 1421 /* Default pull up current to 2uA */ 1422 if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA) 1423 pull_up_cur = HS_PULLUP_I_2P0_UA; 1424 1425 snd_soc_component_write_field(component, 1426 WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT, 1427 WCD937X_HSDET_PULLUP_C_MASK, pull_up_cur); 1428 } 1429 1430 static int wcd937x_mbhc_request_micbias(struct snd_soc_component *component, 1431 int micb_num, int req) 1432 { 1433 return wcd937x_micbias_control(component, micb_num, req, false); 1434 } 1435 1436 static void wcd937x_mbhc_micb_ramp_control(struct snd_soc_component *component, 1437 bool enable) 1438 { 1439 if (enable) { 1440 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1441 WCD937X_RAMP_SHIFT_CTRL_MASK, 0x0C); 1442 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1443 WCD937X_RAMP_EN_MASK, 1); 1444 } else { 1445 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1446 WCD937X_RAMP_EN_MASK, 0); 1447 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1448 WCD937X_RAMP_SHIFT_CTRL_MASK, 0); 1449 } 1450 } 1451 1452 static int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 1453 int req_volt, int micb_num) 1454 { 1455 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1456 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0; 1457 1458 switch (micb_num) { 1459 case MIC_BIAS_1: 1460 micb_reg = WCD937X_ANA_MICB1; 1461 break; 1462 case MIC_BIAS_2: 1463 micb_reg = WCD937X_ANA_MICB2; 1464 break; 1465 case MIC_BIAS_3: 1466 micb_reg = WCD937X_ANA_MICB3; 1467 break; 1468 default: 1469 return -EINVAL; 1470 } 1471 mutex_lock(&wcd937x->micb_lock); 1472 /* 1473 * If requested micbias voltage is same as current micbias 1474 * voltage, then just return. Otherwise, adjust voltage as 1475 * per requested value. If micbias is already enabled, then 1476 * to avoid slow micbias ramp-up or down enable pull-up 1477 * momentarily, change the micbias value and then re-enable 1478 * micbias. 1479 */ 1480 micb_en = snd_soc_component_read_field(component, micb_reg, 1481 WCD937X_MICB_EN_MASK); 1482 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 1483 WCD937X_MICB_VOUT_MASK); 1484 1485 req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt); 1486 if (req_vout_ctl < 0) { 1487 ret = -EINVAL; 1488 goto exit; 1489 } 1490 1491 if (cur_vout_ctl == req_vout_ctl) { 1492 ret = 0; 1493 goto exit; 1494 } 1495 1496 if (micb_en == WCD937X_MICB_ENABLE) 1497 snd_soc_component_write_field(component, micb_reg, 1498 WCD937X_MICB_EN_MASK, 1499 WCD937X_MICB_PULL_UP); 1500 1501 snd_soc_component_write_field(component, micb_reg, 1502 WCD937X_MICB_VOUT_MASK, 1503 req_vout_ctl); 1504 1505 if (micb_en == WCD937X_MICB_ENABLE) { 1506 snd_soc_component_write_field(component, micb_reg, 1507 WCD937X_MICB_EN_MASK, 1508 WCD937X_MICB_ENABLE); 1509 /* 1510 * Add 2ms delay as per HW requirement after enabling 1511 * micbias 1512 */ 1513 usleep_range(2000, 2100); 1514 } 1515 exit: 1516 mutex_unlock(&wcd937x->micb_lock); 1517 return ret; 1518 } 1519 1520 static int wcd937x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 1521 int micb_num, bool req_en) 1522 { 1523 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1524 int micb_mv; 1525 1526 if (micb_num != MIC_BIAS_2) 1527 return -EINVAL; 1528 /* 1529 * If device tree micbias level is already above the minimum 1530 * voltage needed to detect threshold microphone, then do 1531 * not change the micbias, just return. 1532 */ 1533 if (wcd937x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV) 1534 return 0; 1535 1536 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd937x->micb2_mv; 1537 1538 return wcd937x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 1539 } 1540 1541 static void wcd937x_mbhc_get_result_params(struct snd_soc_component *component, 1542 s16 *d1_a, u16 noff, 1543 int32_t *zdet) 1544 { 1545 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1546 int i; 1547 int val, val1; 1548 s16 c1; 1549 s32 x1, d1; 1550 s32 denom; 1551 static const int minCode_param[] = { 1552 3277, 1639, 820, 410, 205, 103, 52, 26 1553 }; 1554 1555 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MBHC_ZDET, 0x20, 0x20); 1556 for (i = 0; i < WCD937X_ZDET_NUM_MEASUREMENTS; i++) { 1557 regmap_read(wcd937x->regmap, WCD937X_ANA_MBHC_RESULT_2, &val); 1558 if (val & 0x80) 1559 break; 1560 } 1561 val = val << 0x8; 1562 regmap_read(wcd937x->regmap, WCD937X_ANA_MBHC_RESULT_1, &val1); 1563 val |= val1; 1564 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MBHC_ZDET, 0x20, 0x00); 1565 x1 = WCD937X_MBHC_GET_X1(val); 1566 c1 = WCD937X_MBHC_GET_C1(val); 1567 /* If ramp is not complete, give additional 5ms */ 1568 if (c1 < 2 && x1) 1569 usleep_range(5000, 5050); 1570 1571 if (!c1 || !x1) { 1572 dev_err(component->dev, "Impedance detect ramp error, c1=%d, x1=0x%x\n", 1573 c1, x1); 1574 goto ramp_down; 1575 } 1576 d1 = d1_a[c1]; 1577 denom = (x1 * d1) - (1 << (14 - noff)); 1578 if (denom > 0) 1579 *zdet = (WCD937X_MBHC_ZDET_CONST * 1000) / denom; 1580 else if (x1 < minCode_param[noff]) 1581 *zdet = WCD937X_ZDET_FLOATING_IMPEDANCE; 1582 1583 dev_err(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d (milliohm)\n", 1584 __func__, d1, c1, x1, *zdet); 1585 ramp_down: 1586 i = 0; 1587 while (x1) { 1588 regmap_read(wcd937x->regmap, 1589 WCD937X_ANA_MBHC_RESULT_1, &val); 1590 regmap_read(wcd937x->regmap, 1591 WCD937X_ANA_MBHC_RESULT_2, &val1); 1592 val = val << 0x08; 1593 val |= val1; 1594 x1 = WCD937X_MBHC_GET_X1(val); 1595 i++; 1596 if (i == WCD937X_ZDET_NUM_MEASUREMENTS) 1597 break; 1598 } 1599 } 1600 1601 static void wcd937x_mbhc_zdet_ramp(struct snd_soc_component *component, 1602 struct wcd937x_mbhc_zdet_param *zdet_param, 1603 s32 *zl, s32 *zr, s16 *d1_a) 1604 { 1605 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1606 s32 zdet = 0; 1607 1608 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, 1609 WCD937X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 1610 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN5, 1611 WCD937X_VTH_MASK, zdet_param->btn5); 1612 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN6, 1613 WCD937X_VTH_MASK, zdet_param->btn6); 1614 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN7, 1615 WCD937X_VTH_MASK, zdet_param->btn7); 1616 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, 1617 WCD937X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 1618 snd_soc_component_update_bits(component, WCD937X_MBHC_NEW_ZDET_RAMP_CTL, 1619 0x0F, zdet_param->nshift); 1620 1621 if (!zl) 1622 goto z_right; 1623 /* Start impedance measurement for HPH_L */ 1624 regmap_update_bits(wcd937x->regmap, 1625 WCD937X_ANA_MBHC_ZDET, 0x80, 0x80); 1626 wcd937x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 1627 regmap_update_bits(wcd937x->regmap, 1628 WCD937X_ANA_MBHC_ZDET, 0x80, 0x00); 1629 1630 *zl = zdet; 1631 1632 z_right: 1633 if (!zr) 1634 return; 1635 /* Start impedance measurement for HPH_R */ 1636 regmap_update_bits(wcd937x->regmap, 1637 WCD937X_ANA_MBHC_ZDET, 0x40, 0x40); 1638 wcd937x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 1639 regmap_update_bits(wcd937x->regmap, 1640 WCD937X_ANA_MBHC_ZDET, 0x40, 0x00); 1641 1642 *zr = zdet; 1643 } 1644 1645 static void wcd937x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 1646 s32 *z_val, int flag_l_r) 1647 { 1648 s16 q1; 1649 int q1_cal; 1650 1651 if (*z_val < (WCD937X_ZDET_VAL_400 / 1000)) 1652 q1 = snd_soc_component_read(component, 1653 WCD937X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r)); 1654 else 1655 q1 = snd_soc_component_read(component, 1656 WCD937X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r)); 1657 if (q1 & 0x80) 1658 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 1659 else 1660 q1_cal = (10000 + (q1 * 25)); 1661 if (q1_cal > 0) 1662 *z_val = ((*z_val) * 10000) / q1_cal; 1663 } 1664 1665 static void wcd937x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 1666 u32 *zl, u32 *zr) 1667 { 1668 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1669 s16 reg0, reg1, reg2, reg3, reg4; 1670 s32 z1l, z1r, z1ls; 1671 int zMono, z_diff1, z_diff2; 1672 bool is_fsm_disable = false; 1673 struct wcd937x_mbhc_zdet_param zdet_param[] = { 1674 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 1675 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 1676 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 1677 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 1678 }; 1679 struct wcd937x_mbhc_zdet_param *zdet_param_ptr = NULL; 1680 s16 d1_a[][4] = { 1681 {0, 30, 90, 30}, 1682 {0, 30, 30, 5}, 1683 {0, 30, 30, 5}, 1684 {0, 30, 30, 5}, 1685 }; 1686 s16 *d1 = NULL; 1687 1688 reg0 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN5); 1689 reg1 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN6); 1690 reg2 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN7); 1691 reg3 = snd_soc_component_read(component, WCD937X_MBHC_CTL_CLK); 1692 reg4 = snd_soc_component_read(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL); 1693 1694 if (snd_soc_component_read(component, WCD937X_ANA_MBHC_ELECT) & 0x80) { 1695 is_fsm_disable = true; 1696 regmap_update_bits(wcd937x->regmap, 1697 WCD937X_ANA_MBHC_ELECT, 0x80, 0x00); 1698 } 1699 1700 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 1701 if (wcd937x->mbhc_cfg.hphl_swh) 1702 regmap_update_bits(wcd937x->regmap, 1703 WCD937X_ANA_MBHC_MECH, 0x80, 0x00); 1704 1705 /* Turn off 100k pull down on HPHL */ 1706 regmap_update_bits(wcd937x->regmap, 1707 WCD937X_ANA_MBHC_MECH, 0x01, 0x00); 1708 1709 /* Disable surge protection before impedance detection. 1710 * This is done to give correct value for high impedance. 1711 */ 1712 regmap_update_bits(wcd937x->regmap, 1713 WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00); 1714 /* 1ms delay needed after disable surge protection */ 1715 usleep_range(1000, 1010); 1716 1717 /* First get impedance on Left */ 1718 d1 = d1_a[1]; 1719 zdet_param_ptr = &zdet_param[1]; 1720 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1l, NULL, d1); 1721 1722 if (!WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z1l)) 1723 goto left_ch_impedance; 1724 1725 /* Second ramp for left ch */ 1726 if (z1l < WCD937X_ZDET_VAL_32) { 1727 zdet_param_ptr = &zdet_param[0]; 1728 d1 = d1_a[0]; 1729 } else if ((z1l > WCD937X_ZDET_VAL_400) && 1730 (z1l <= WCD937X_ZDET_VAL_1200)) { 1731 zdet_param_ptr = &zdet_param[2]; 1732 d1 = d1_a[2]; 1733 } else if (z1l > WCD937X_ZDET_VAL_1200) { 1734 zdet_param_ptr = &zdet_param[3]; 1735 d1 = d1_a[3]; 1736 } 1737 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1l, NULL, d1); 1738 1739 left_ch_impedance: 1740 if (z1l == WCD937X_ZDET_FLOATING_IMPEDANCE || 1741 z1l > WCD937X_ZDET_VAL_100K) { 1742 *zl = WCD937X_ZDET_FLOATING_IMPEDANCE; 1743 zdet_param_ptr = &zdet_param[1]; 1744 d1 = d1_a[1]; 1745 } else { 1746 *zl = z1l / 1000; 1747 wcd937x_wcd_mbhc_qfuse_cal(component, zl, 0); 1748 } 1749 1750 /* Start of right impedance ramp and calculation */ 1751 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1r, d1); 1752 if (WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z1r)) { 1753 if ((z1r > WCD937X_ZDET_VAL_1200 && 1754 zdet_param_ptr->noff == 0x6) || 1755 ((*zl) != WCD937X_ZDET_FLOATING_IMPEDANCE)) 1756 goto right_ch_impedance; 1757 /* Second ramp for right ch */ 1758 if (z1r < WCD937X_ZDET_VAL_32) { 1759 zdet_param_ptr = &zdet_param[0]; 1760 d1 = d1_a[0]; 1761 } else if ((z1r > WCD937X_ZDET_VAL_400) && 1762 (z1r <= WCD937X_ZDET_VAL_1200)) { 1763 zdet_param_ptr = &zdet_param[2]; 1764 d1 = d1_a[2]; 1765 } else if (z1r > WCD937X_ZDET_VAL_1200) { 1766 zdet_param_ptr = &zdet_param[3]; 1767 d1 = d1_a[3]; 1768 } 1769 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1r, d1); 1770 } 1771 right_ch_impedance: 1772 if (z1r == WCD937X_ZDET_FLOATING_IMPEDANCE || 1773 z1r > WCD937X_ZDET_VAL_100K) { 1774 *zr = WCD937X_ZDET_FLOATING_IMPEDANCE; 1775 } else { 1776 *zr = z1r / 1000; 1777 wcd937x_wcd_mbhc_qfuse_cal(component, zr, 1); 1778 } 1779 1780 /* Mono/stereo detection */ 1781 if ((*zl == WCD937X_ZDET_FLOATING_IMPEDANCE) && 1782 (*zr == WCD937X_ZDET_FLOATING_IMPEDANCE)) { 1783 dev_err(component->dev, 1784 "%s: plug type is invalid or extension cable\n", 1785 __func__); 1786 goto zdet_complete; 1787 } 1788 if ((*zl == WCD937X_ZDET_FLOATING_IMPEDANCE) || 1789 (*zr == WCD937X_ZDET_FLOATING_IMPEDANCE) || 1790 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 1791 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 1792 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_MONO); 1793 goto zdet_complete; 1794 } 1795 snd_soc_component_write_field(component, WCD937X_HPH_R_ATEST, 1796 WCD937X_HPHPA_GND_OVR_MASK, 1); 1797 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1798 WCD937X_HPHPA_GND_R_MASK, 1); 1799 if (*zl < (WCD937X_ZDET_VAL_32 / 1000)) 1800 wcd937x_mbhc_zdet_ramp(component, &zdet_param[0], &z1ls, NULL, d1); 1801 else 1802 wcd937x_mbhc_zdet_ramp(component, &zdet_param[1], &z1ls, NULL, d1); 1803 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1804 WCD937X_HPHPA_GND_R_MASK, 0); 1805 snd_soc_component_write_field(component, WCD937X_HPH_R_ATEST, 1806 WCD937X_HPHPA_GND_OVR_MASK, 0); 1807 z1ls /= 1000; 1808 wcd937x_wcd_mbhc_qfuse_cal(component, &z1ls, 0); 1809 /* Parallel of left Z and 9 ohm pull down resistor */ 1810 zMono = ((*zl) * 9) / ((*zl) + 9); 1811 z_diff1 = (z1ls > zMono) ? (z1ls - zMono) : (zMono - z1ls); 1812 z_diff2 = ((*zl) > z1ls) ? ((*zl) - z1ls) : (z1ls - (*zl)); 1813 if ((z_diff1 * (*zl + z1ls)) > (z_diff2 * (z1ls + zMono))) 1814 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_STEREO); 1815 else 1816 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_MONO); 1817 1818 /* Enable surge protection again after impedance detection */ 1819 regmap_update_bits(wcd937x->regmap, 1820 WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 1821 zdet_complete: 1822 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN5, reg0); 1823 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN6, reg1); 1824 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN7, reg2); 1825 /* Turn on 100k pull down on HPHL */ 1826 regmap_update_bits(wcd937x->regmap, 1827 WCD937X_ANA_MBHC_MECH, 0x01, 0x01); 1828 1829 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 1830 if (wcd937x->mbhc_cfg.hphl_swh) 1831 regmap_update_bits(wcd937x->regmap, 1832 WCD937X_ANA_MBHC_MECH, 0x80, 0x80); 1833 1834 snd_soc_component_write(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, reg4); 1835 snd_soc_component_write(component, WCD937X_MBHC_CTL_CLK, reg3); 1836 if (is_fsm_disable) 1837 regmap_update_bits(wcd937x->regmap, 1838 WCD937X_ANA_MBHC_ELECT, 0x80, 0x80); 1839 } 1840 1841 static void wcd937x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 1842 bool enable) 1843 { 1844 if (enable) { 1845 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1846 WCD937X_MBHC_HSG_PULLUP_COMP_EN, 1); 1847 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1848 WCD937X_MBHC_GND_DET_EN_MASK, 1); 1849 } else { 1850 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1851 WCD937X_MBHC_GND_DET_EN_MASK, 0); 1852 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1853 WCD937X_MBHC_HSG_PULLUP_COMP_EN, 0); 1854 } 1855 } 1856 1857 static void wcd937x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 1858 bool enable) 1859 { 1860 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1861 WCD937X_HPHPA_GND_R_MASK, enable); 1862 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1863 WCD937X_HPHPA_GND_L_MASK, enable); 1864 } 1865 1866 static void wcd937x_mbhc_moisture_config(struct snd_soc_component *component) 1867 { 1868 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1869 1870 if (wcd937x->mbhc_cfg.moist_rref == R_OFF) { 1871 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1872 WCD937X_M_RTH_CTL_MASK, R_OFF); 1873 return; 1874 } 1875 1876 /* Do not enable moisture detection if jack type is NC */ 1877 if (!wcd937x->mbhc_cfg.hphl_swh) { 1878 dev_err(component->dev, "%s: disable moisture detection for NC\n", 1879 __func__); 1880 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1881 WCD937X_M_RTH_CTL_MASK, R_OFF); 1882 return; 1883 } 1884 1885 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1886 WCD937X_M_RTH_CTL_MASK, wcd937x->mbhc_cfg.moist_rref); 1887 } 1888 1889 static void wcd937x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable) 1890 { 1891 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1892 1893 if (enable) 1894 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1895 WCD937X_M_RTH_CTL_MASK, wcd937x->mbhc_cfg.moist_rref); 1896 else 1897 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1898 WCD937X_M_RTH_CTL_MASK, R_OFF); 1899 } 1900 1901 static bool wcd937x_mbhc_get_moisture_status(struct snd_soc_component *component) 1902 { 1903 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1904 bool ret = false; 1905 1906 if (wcd937x->mbhc_cfg.moist_rref == R_OFF) { 1907 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1908 WCD937X_M_RTH_CTL_MASK, R_OFF); 1909 goto done; 1910 } 1911 1912 /* Do not enable moisture detection if jack type is NC */ 1913 if (!wcd937x->mbhc_cfg.hphl_swh) { 1914 dev_err(component->dev, "%s: disable moisture detection for NC\n", 1915 __func__); 1916 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1917 WCD937X_M_RTH_CTL_MASK, R_OFF); 1918 goto done; 1919 } 1920 1921 /* 1922 * If moisture_en is already enabled, then skip to plug type 1923 * detection. 1924 */ 1925 if (snd_soc_component_read_field(component, WCD937X_MBHC_NEW_CTL_2, WCD937X_M_RTH_CTL_MASK)) 1926 goto done; 1927 1928 wcd937x_mbhc_moisture_detect_en(component, true); 1929 /* Read moisture comparator status */ 1930 ret = ((snd_soc_component_read(component, WCD937X_MBHC_NEW_FSM_STATUS) 1931 & 0x20) ? 0 : 1); 1932 done: 1933 return ret; 1934 } 1935 1936 static void wcd937x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component, 1937 bool enable) 1938 { 1939 snd_soc_component_write_field(component, 1940 WCD937X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 1941 WCD937X_MOISTURE_EN_POLLING_MASK, enable); 1942 } 1943 1944 static const struct wcd_mbhc_cb mbhc_cb = { 1945 .clk_setup = wcd937x_mbhc_clk_setup, 1946 .mbhc_bias = wcd937x_mbhc_mbhc_bias_control, 1947 .set_btn_thr = wcd937x_mbhc_program_btn_thr, 1948 .micbias_enable_status = wcd937x_mbhc_micb_en_status, 1949 .hph_pull_up_control_v2 = wcd937x_mbhc_hph_l_pull_up_control, 1950 .mbhc_micbias_control = wcd937x_mbhc_request_micbias, 1951 .mbhc_micb_ramp_control = wcd937x_mbhc_micb_ramp_control, 1952 .mbhc_micb_ctrl_thr_mic = wcd937x_mbhc_micb_ctrl_threshold_mic, 1953 .compute_impedance = wcd937x_wcd_mbhc_calc_impedance, 1954 .mbhc_gnd_det_ctrl = wcd937x_mbhc_gnd_det_ctrl, 1955 .hph_pull_down_ctrl = wcd937x_mbhc_hph_pull_down_ctrl, 1956 .mbhc_moisture_config = wcd937x_mbhc_moisture_config, 1957 .mbhc_get_moisture_status = wcd937x_mbhc_get_moisture_status, 1958 .mbhc_moisture_polling_ctrl = wcd937x_mbhc_moisture_polling_ctrl, 1959 .mbhc_moisture_detect_en = wcd937x_mbhc_moisture_detect_en, 1960 }; 1961 1962 static int wcd937x_get_hph_type(struct snd_kcontrol *kcontrol, 1963 struct snd_ctl_elem_value *ucontrol) 1964 { 1965 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1966 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1967 1968 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd937x->wcd_mbhc); 1969 1970 return 0; 1971 } 1972 1973 static int wcd937x_hph_impedance_get(struct snd_kcontrol *kcontrol, 1974 struct snd_ctl_elem_value *ucontrol) 1975 { 1976 u32 zl, zr; 1977 bool hphr; 1978 struct soc_mixer_control *mc; 1979 struct snd_soc_component *component = 1980 snd_soc_kcontrol_component(kcontrol); 1981 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1982 1983 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1984 hphr = mc->shift; 1985 wcd_mbhc_get_impedance(wcd937x->wcd_mbhc, &zl, &zr); 1986 ucontrol->value.integer.value[0] = hphr ? zr : zl; 1987 1988 return 0; 1989 } 1990 1991 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 1992 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0, 1993 wcd937x_get_hph_type, NULL), 1994 }; 1995 1996 static const struct snd_kcontrol_new impedance_detect_controls[] = { 1997 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0, 1998 wcd937x_hph_impedance_get, NULL), 1999 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0, 2000 wcd937x_hph_impedance_get, NULL), 2001 }; 2002 2003 static int wcd937x_mbhc_init(struct snd_soc_component *component) 2004 { 2005 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2006 struct wcd_mbhc_intr *intr_ids = &wcd937x->intr_ids; 2007 2008 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2009 WCD937X_IRQ_MBHC_SW_DET); 2010 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2011 WCD937X_IRQ_MBHC_BUTTON_PRESS_DET); 2012 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2013 WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET); 2014 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2015 WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 2016 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2017 WCD937X_IRQ_MBHC_ELECT_INS_REM_DET); 2018 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd937x->irq_chip, 2019 WCD937X_IRQ_HPHL_OCP_INT); 2020 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd937x->irq_chip, 2021 WCD937X_IRQ_HPHR_OCP_INT); 2022 2023 wcd937x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 2024 if (IS_ERR(wcd937x->wcd_mbhc)) 2025 return PTR_ERR(wcd937x->wcd_mbhc); 2026 2027 snd_soc_add_component_controls(component, impedance_detect_controls, 2028 ARRAY_SIZE(impedance_detect_controls)); 2029 snd_soc_add_component_controls(component, hph_type_detect_controls, 2030 ARRAY_SIZE(hph_type_detect_controls)); 2031 2032 return 0; 2033 } 2034 2035 static void wcd937x_mbhc_deinit(struct snd_soc_component *component) 2036 { 2037 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2038 2039 wcd_mbhc_deinit(wcd937x->wcd_mbhc); 2040 } 2041 2042 /* END MBHC */ 2043 2044 static const struct snd_kcontrol_new wcd937x_snd_controls[] = { 2045 SOC_SINGLE_TLV("EAR_PA Volume", WCD937X_ANA_EAR_COMPANDER_CTL, 2046 2, 0x10, 0, ear_pa_gain), 2047 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 2048 wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put), 2049 2050 SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0, 2051 wcd937x_get_compander, wcd937x_set_compander), 2052 SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0, 2053 wcd937x_get_compander, wcd937x_set_compander), 2054 2055 SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain), 2056 SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain), 2057 SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0, analog_gain), 2058 SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0, analog_gain), 2059 SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0, analog_gain), 2060 2061 SOC_SINGLE_EXT("HPHL Switch", WCD937X_HPH_L, 0, 1, 0, 2062 wcd937x_get_swr_port, wcd937x_set_swr_port), 2063 SOC_SINGLE_EXT("HPHR Switch", WCD937X_HPH_R, 0, 1, 0, 2064 wcd937x_get_swr_port, wcd937x_set_swr_port), 2065 SOC_SINGLE_EXT("LO Switch", WCD937X_LO, 0, 1, 0, 2066 wcd937x_get_swr_port, wcd937x_set_swr_port), 2067 2068 SOC_SINGLE_EXT("ADC1 Switch", WCD937X_ADC1, 1, 1, 0, 2069 wcd937x_get_swr_port, wcd937x_set_swr_port), 2070 SOC_SINGLE_EXT("ADC2 Switch", WCD937X_ADC2, 1, 1, 0, 2071 wcd937x_get_swr_port, wcd937x_set_swr_port), 2072 SOC_SINGLE_EXT("ADC3 Switch", WCD937X_ADC3, 1, 1, 0, 2073 wcd937x_get_swr_port, wcd937x_set_swr_port), 2074 SOC_SINGLE_EXT("DMIC0 Switch", WCD937X_DMIC0, 1, 1, 0, 2075 wcd937x_get_swr_port, wcd937x_set_swr_port), 2076 SOC_SINGLE_EXT("DMIC1 Switch", WCD937X_DMIC1, 1, 1, 0, 2077 wcd937x_get_swr_port, wcd937x_set_swr_port), 2078 SOC_SINGLE_EXT("MBHC Switch", WCD937X_MBHC, 1, 1, 0, 2079 wcd937x_get_swr_port, wcd937x_set_swr_port), 2080 SOC_SINGLE_EXT("DMIC2 Switch", WCD937X_DMIC2, 1, 1, 0, 2081 wcd937x_get_swr_port, wcd937x_set_swr_port), 2082 SOC_SINGLE_EXT("DMIC3 Switch", WCD937X_DMIC3, 1, 1, 0, 2083 wcd937x_get_swr_port, wcd937x_set_swr_port), 2084 SOC_SINGLE_EXT("DMIC4 Switch", WCD937X_DMIC4, 1, 1, 0, 2085 wcd937x_get_swr_port, wcd937x_set_swr_port), 2086 SOC_SINGLE_EXT("DMIC5 Switch", WCD937X_DMIC5, 1, 1, 0, 2087 wcd937x_get_swr_port, wcd937x_set_swr_port), 2088 }; 2089 2090 static const struct snd_kcontrol_new adc1_switch[] = { 2091 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2092 }; 2093 2094 static const struct snd_kcontrol_new adc2_switch[] = { 2095 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2096 }; 2097 2098 static const struct snd_kcontrol_new adc3_switch[] = { 2099 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2100 }; 2101 2102 static const struct snd_kcontrol_new dmic1_switch[] = { 2103 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2104 }; 2105 2106 static const struct snd_kcontrol_new dmic2_switch[] = { 2107 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2108 }; 2109 2110 static const struct snd_kcontrol_new dmic3_switch[] = { 2111 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2112 }; 2113 2114 static const struct snd_kcontrol_new dmic4_switch[] = { 2115 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2116 }; 2117 2118 static const struct snd_kcontrol_new dmic5_switch[] = { 2119 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2120 }; 2121 2122 static const struct snd_kcontrol_new dmic6_switch[] = { 2123 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2124 }; 2125 2126 static const struct snd_kcontrol_new ear_rdac_switch[] = { 2127 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2128 }; 2129 2130 static const struct snd_kcontrol_new aux_rdac_switch[] = { 2131 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2132 }; 2133 2134 static const struct snd_kcontrol_new hphl_rdac_switch[] = { 2135 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2136 }; 2137 2138 static const struct snd_kcontrol_new hphr_rdac_switch[] = { 2139 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2140 }; 2141 2142 static const char * const adc2_mux_text[] = { 2143 "INP2", "INP3" 2144 }; 2145 2146 static const char * const rdac3_mux_text[] = { 2147 "RX1", "RX3" 2148 }; 2149 2150 static const struct soc_enum adc2_enum = 2151 SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7, 2152 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 2153 2154 static const struct soc_enum rdac3_enum = 2155 SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0, 2156 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text); 2157 2158 static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum); 2159 2160 static const struct snd_kcontrol_new rx_rdac3_mux = SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum); 2161 2162 static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = { 2163 /* Input widgets */ 2164 SND_SOC_DAPM_INPUT("AMIC1"), 2165 SND_SOC_DAPM_INPUT("AMIC2"), 2166 SND_SOC_DAPM_INPUT("AMIC3"), 2167 SND_SOC_DAPM_INPUT("IN1_HPHL"), 2168 SND_SOC_DAPM_INPUT("IN2_HPHR"), 2169 SND_SOC_DAPM_INPUT("IN3_AUX"), 2170 2171 /* TX widgets */ 2172 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0, 2173 wcd937x_codec_enable_adc, 2174 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2175 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0, 2176 wcd937x_codec_enable_adc, 2177 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2178 2179 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, 2180 NULL, 0, wcd937x_enable_req, 2181 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2182 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0, 2183 NULL, 0, wcd937x_enable_req, 2184 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2185 2186 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 2187 2188 /* TX mixers */ 2189 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, 2190 adc1_switch, ARRAY_SIZE(adc1_switch), 2191 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2192 SND_SOC_DAPM_POST_PMD), 2193 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 1, 0, 2194 adc2_switch, ARRAY_SIZE(adc2_switch), 2195 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2196 SND_SOC_DAPM_POST_PMD), 2197 2198 /* MIC_BIAS widgets */ 2199 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2200 wcd937x_codec_enable_micbias, 2201 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2202 SND_SOC_DAPM_POST_PMD), 2203 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2204 wcd937x_codec_enable_micbias, 2205 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2206 SND_SOC_DAPM_POST_PMD), 2207 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2208 wcd937x_codec_enable_micbias, 2209 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2210 SND_SOC_DAPM_POST_PMD), 2211 2212 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0), 2213 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0), 2214 2215 /* RX widgets */ 2216 SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0, 2217 wcd937x_codec_enable_ear_pa, 2218 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2219 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2220 SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0, 2221 wcd937x_codec_enable_aux_pa, 2222 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2223 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2224 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0, 2225 wcd937x_codec_enable_hphl_pa, 2226 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2227 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2228 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0, 2229 wcd937x_codec_enable_hphr_pa, 2230 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2231 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2232 2233 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0, 2234 wcd937x_codec_hphl_dac_event, 2235 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2236 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2237 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0, 2238 wcd937x_codec_hphr_dac_event, 2239 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2240 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2241 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0, 2242 wcd937x_codec_ear_dac_event, 2243 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2244 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2245 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0, 2246 wcd937x_codec_aux_dac_event, 2247 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2248 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2249 2250 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux), 2251 2252 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, 2253 wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU | 2254 SND_SOC_DAPM_POST_PMD), 2255 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, 2256 wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU | 2257 SND_SOC_DAPM_POST_PMD), 2258 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, 2259 wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU | 2260 SND_SOC_DAPM_POST_PMD), 2261 2262 /* RX mixer widgets*/ 2263 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0, 2264 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)), 2265 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0, 2266 aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)), 2267 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0, 2268 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)), 2269 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0, 2270 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)), 2271 2272 /* TX output widgets */ 2273 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"), 2274 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"), 2275 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"), 2276 SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"), 2277 2278 /* RX output widgets */ 2279 SND_SOC_DAPM_OUTPUT("EAR"), 2280 SND_SOC_DAPM_OUTPUT("AUX"), 2281 SND_SOC_DAPM_OUTPUT("HPHL"), 2282 SND_SOC_DAPM_OUTPUT("HPHR"), 2283 2284 /* MIC_BIAS pull up widgets */ 2285 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2286 wcd937x_codec_enable_micbias_pullup, 2287 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2288 SND_SOC_DAPM_POST_PMD), 2289 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2290 wcd937x_codec_enable_micbias_pullup, 2291 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2292 SND_SOC_DAPM_POST_PMD), 2293 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2294 wcd937x_codec_enable_micbias_pullup, 2295 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2296 SND_SOC_DAPM_POST_PMD), 2297 }; 2298 2299 static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = { 2300 /* Input widgets */ 2301 SND_SOC_DAPM_INPUT("AMIC4"), 2302 2303 /* TX widgets */ 2304 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0, 2305 wcd937x_codec_enable_adc, 2306 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2307 2308 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0, 2309 NULL, 0, wcd937x_enable_req, 2310 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2311 2312 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 2313 wcd937x_codec_enable_dmic, 2314 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2315 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0, 2316 wcd937x_codec_enable_dmic, 2317 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2318 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0, 2319 wcd937x_codec_enable_dmic, 2320 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2321 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0, 2322 wcd937x_codec_enable_dmic, 2323 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2324 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0, 2325 wcd937x_codec_enable_dmic, 2326 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2327 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0, 2328 wcd937x_codec_enable_dmic, 2329 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2330 2331 /* TX mixer widgets */ 2332 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 2333 0, dmic1_switch, ARRAY_SIZE(dmic1_switch), 2334 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2335 SND_SOC_DAPM_POST_PMD), 2336 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 1, 2337 0, dmic2_switch, ARRAY_SIZE(dmic2_switch), 2338 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2339 SND_SOC_DAPM_POST_PMD), 2340 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 2, 2341 0, dmic3_switch, ARRAY_SIZE(dmic3_switch), 2342 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2343 SND_SOC_DAPM_POST_PMD), 2344 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 3, 2345 0, dmic4_switch, ARRAY_SIZE(dmic4_switch), 2346 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2347 SND_SOC_DAPM_POST_PMD), 2348 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 4, 2349 0, dmic5_switch, ARRAY_SIZE(dmic5_switch), 2350 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2351 SND_SOC_DAPM_POST_PMD), 2352 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 5, 2353 0, dmic6_switch, ARRAY_SIZE(dmic6_switch), 2354 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2355 SND_SOC_DAPM_POST_PMD), 2356 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 2, 0, adc3_switch, 2357 ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl, 2358 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2359 2360 /* Output widgets */ 2361 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"), 2362 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"), 2363 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"), 2364 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"), 2365 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"), 2366 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"), 2367 }; 2368 2369 static const struct snd_soc_dapm_route wcd937x_audio_map[] = { 2370 { "ADC1_OUTPUT", NULL, "ADC1_MIXER" }, 2371 { "ADC1_MIXER", "Switch", "ADC1 REQ" }, 2372 { "ADC1 REQ", NULL, "ADC1" }, 2373 { "ADC1", NULL, "AMIC1" }, 2374 2375 { "ADC2_OUTPUT", NULL, "ADC2_MIXER" }, 2376 { "ADC2_MIXER", "Switch", "ADC2 REQ" }, 2377 { "ADC2 REQ", NULL, "ADC2" }, 2378 { "ADC2", NULL, "ADC2 MUX" }, 2379 { "ADC2 MUX", "INP3", "AMIC3" }, 2380 { "ADC2 MUX", "INP2", "AMIC2" }, 2381 2382 { "IN1_HPHL", NULL, "VDD_BUCK" }, 2383 { "IN1_HPHL", NULL, "CLS_H_PORT" }, 2384 { "RX1", NULL, "IN1_HPHL" }, 2385 { "RDAC1", NULL, "RX1" }, 2386 { "HPHL_RDAC", "Switch", "RDAC1" }, 2387 { "HPHL PGA", NULL, "HPHL_RDAC" }, 2388 { "HPHL", NULL, "HPHL PGA" }, 2389 2390 { "IN2_HPHR", NULL, "VDD_BUCK" }, 2391 { "IN2_HPHR", NULL, "CLS_H_PORT" }, 2392 { "RX2", NULL, "IN2_HPHR" }, 2393 { "RDAC2", NULL, "RX2" }, 2394 { "HPHR_RDAC", "Switch", "RDAC2" }, 2395 { "HPHR PGA", NULL, "HPHR_RDAC" }, 2396 { "HPHR", NULL, "HPHR PGA" }, 2397 2398 { "IN3_AUX", NULL, "VDD_BUCK" }, 2399 { "IN3_AUX", NULL, "CLS_H_PORT" }, 2400 { "RX3", NULL, "IN3_AUX" }, 2401 { "RDAC4", NULL, "RX3" }, 2402 { "AUX_RDAC", "Switch", "RDAC4" }, 2403 { "AUX PGA", NULL, "AUX_RDAC" }, 2404 { "AUX", NULL, "AUX PGA" }, 2405 2406 { "RDAC3_MUX", "RX3", "RX3" }, 2407 { "RDAC3_MUX", "RX1", "RX1" }, 2408 { "RDAC3", NULL, "RDAC3_MUX" }, 2409 { "EAR_RDAC", "Switch", "RDAC3" }, 2410 { "EAR PGA", NULL, "EAR_RDAC" }, 2411 { "EAR", NULL, "EAR PGA" }, 2412 }; 2413 2414 static const struct snd_soc_dapm_route wcd9375_audio_map[] = { 2415 { "ADC3_OUTPUT", NULL, "ADC3_MIXER" }, 2416 { "ADC3_OUTPUT", NULL, "ADC3_MIXER" }, 2417 { "ADC3_MIXER", "Switch", "ADC3 REQ" }, 2418 { "ADC3 REQ", NULL, "ADC3" }, 2419 { "ADC3", NULL, "AMIC4" }, 2420 2421 { "DMIC1_OUTPUT", NULL, "DMIC1_MIXER" }, 2422 { "DMIC1_MIXER", "Switch", "DMIC1" }, 2423 2424 { "DMIC2_OUTPUT", NULL, "DMIC2_MIXER" }, 2425 { "DMIC2_MIXER", "Switch", "DMIC2" }, 2426 2427 { "DMIC3_OUTPUT", NULL, "DMIC3_MIXER" }, 2428 { "DMIC3_MIXER", "Switch", "DMIC3" }, 2429 2430 { "DMIC4_OUTPUT", NULL, "DMIC4_MIXER" }, 2431 { "DMIC4_MIXER", "Switch", "DMIC4" }, 2432 2433 { "DMIC5_OUTPUT", NULL, "DMIC5_MIXER" }, 2434 { "DMIC5_MIXER", "Switch", "DMIC5" }, 2435 2436 { "DMIC6_OUTPUT", NULL, "DMIC6_MIXER" }, 2437 { "DMIC6_MIXER", "Switch", "DMIC6" }, 2438 }; 2439 2440 static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x) 2441 { 2442 int vout_ctl[3]; 2443 2444 /* Set micbias voltage */ 2445 vout_ctl[0] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb1_mv); 2446 vout_ctl[1] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb2_mv); 2447 vout_ctl[2] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb3_mv); 2448 if ((vout_ctl[0] | vout_ctl[1] | vout_ctl[2]) < 0) 2449 return -EINVAL; 2450 2451 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, WCD937X_ANA_MICB_VOUT, vout_ctl[0]); 2452 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, WCD937X_ANA_MICB_VOUT, vout_ctl[1]); 2453 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, WCD937X_ANA_MICB_VOUT, vout_ctl[2]); 2454 2455 return 0; 2456 } 2457 2458 static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data) 2459 { 2460 return IRQ_HANDLED; 2461 } 2462 2463 static const struct irq_chip wcd_irq_chip = { 2464 .name = "WCD937x", 2465 }; 2466 2467 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq, 2468 irq_hw_number_t hw) 2469 { 2470 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq); 2471 irq_set_nested_thread(virq, 1); 2472 irq_set_noprobe(virq); 2473 2474 return 0; 2475 } 2476 2477 static const struct irq_domain_ops wcd_domain_ops = { 2478 .map = wcd_irq_chip_map, 2479 }; 2480 2481 static int wcd937x_irq_init(struct wcd937x_priv *wcd, struct device *dev) 2482 { 2483 wcd->virq = irq_domain_create_linear(NULL, 1, &wcd_domain_ops, NULL); 2484 if (!(wcd->virq)) { 2485 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__); 2486 return -EINVAL; 2487 } 2488 2489 return devm_regmap_add_irq_chip(dev, wcd->regmap, 2490 irq_create_mapping(wcd->virq, 0), 2491 IRQF_ONESHOT, 0, &wcd937x_regmap_irq_chip, 2492 &wcd->irq_chip); 2493 } 2494 2495 static int wcd937x_soc_codec_probe(struct snd_soc_component *component) 2496 { 2497 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 2498 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2499 struct sdw_slave *tx_sdw_dev = wcd937x->tx_sdw_dev; 2500 struct device *dev = component->dev; 2501 unsigned long time_left; 2502 int i, ret; 2503 u32 chipid; 2504 2505 time_left = wait_for_completion_timeout(&tx_sdw_dev->initialization_complete, 2506 msecs_to_jiffies(5000)); 2507 if (!time_left) { 2508 dev_err(dev, "soundwire device init timeout\n"); 2509 return -ETIMEDOUT; 2510 } 2511 2512 snd_soc_component_init_regmap(component, wcd937x->regmap); 2513 ret = pm_runtime_resume_and_get(dev); 2514 if (ret < 0) 2515 return ret; 2516 2517 chipid = (snd_soc_component_read(component, 2518 WCD937X_DIGITAL_EFUSE_REG_0) & 0x1e) >> 1; 2519 if (chipid != CHIPID_WCD9370 && chipid != CHIPID_WCD9375) { 2520 dev_err(dev, "Got unknown chip id: 0x%x\n", chipid); 2521 pm_runtime_put(dev); 2522 return -EINVAL; 2523 } 2524 2525 wcd937x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD937X); 2526 if (IS_ERR(wcd937x->clsh_info)) { 2527 pm_runtime_put(dev); 2528 return PTR_ERR(wcd937x->clsh_info); 2529 } 2530 2531 wcd937x_io_init(wcd937x->regmap); 2532 /* Set all interrupts as edge triggered */ 2533 for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++) 2534 regmap_write(wcd937x->regmap, (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0); 2535 2536 pm_runtime_put(dev); 2537 2538 wcd937x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2539 WCD937X_IRQ_HPHR_PDM_WD_INT); 2540 wcd937x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2541 WCD937X_IRQ_HPHL_PDM_WD_INT); 2542 wcd937x->aux_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2543 WCD937X_IRQ_AUX_PDM_WD_INT); 2544 2545 /* Request for watchdog interrupt */ 2546 ret = devm_request_threaded_irq(dev, wcd937x->hphr_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2547 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2548 "HPHR PDM WDOG INT", wcd937x); 2549 if (ret) 2550 dev_err(dev, "Failed to request HPHR watchdog interrupt (%d)\n", ret); 2551 2552 ret = devm_request_threaded_irq(dev, wcd937x->hphl_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2553 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2554 "HPHL PDM WDOG INT", wcd937x); 2555 if (ret) 2556 dev_err(dev, "Failed to request HPHL watchdog interrupt (%d)\n", ret); 2557 2558 ret = devm_request_threaded_irq(dev, wcd937x->aux_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2559 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2560 "AUX PDM WDOG INT", wcd937x); 2561 if (ret) 2562 dev_err(dev, "Failed to request Aux watchdog interrupt (%d)\n", ret); 2563 2564 /* Disable watchdog interrupt for HPH and AUX */ 2565 disable_irq_nosync(wcd937x->hphr_pdm_wd_int); 2566 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 2567 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 2568 2569 if (chipid == CHIPID_WCD9375) { 2570 ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets, 2571 ARRAY_SIZE(wcd9375_dapm_widgets)); 2572 if (ret < 0) { 2573 dev_err(component->dev, "Failed to add snd_ctls\n"); 2574 wcd_clsh_ctrl_free(wcd937x->clsh_info); 2575 return ret; 2576 } 2577 2578 ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map, 2579 ARRAY_SIZE(wcd9375_audio_map)); 2580 if (ret < 0) { 2581 dev_err(component->dev, "Failed to add routes\n"); 2582 wcd_clsh_ctrl_free(wcd937x->clsh_info); 2583 return ret; 2584 } 2585 } 2586 2587 ret = wcd937x_mbhc_init(component); 2588 if (ret) 2589 dev_err(component->dev, "mbhc initialization failed\n"); 2590 2591 return ret; 2592 } 2593 2594 static void wcd937x_soc_codec_remove(struct snd_soc_component *component) 2595 { 2596 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2597 2598 wcd937x_mbhc_deinit(component); 2599 free_irq(wcd937x->aux_pdm_wd_int, wcd937x); 2600 free_irq(wcd937x->hphl_pdm_wd_int, wcd937x); 2601 free_irq(wcd937x->hphr_pdm_wd_int, wcd937x); 2602 2603 wcd_clsh_ctrl_free(wcd937x->clsh_info); 2604 } 2605 2606 static int wcd937x_codec_set_jack(struct snd_soc_component *comp, 2607 struct snd_soc_jack *jack, void *data) 2608 { 2609 struct wcd937x_priv *wcd = dev_get_drvdata(comp->dev); 2610 int ret = 0; 2611 2612 if (jack) 2613 ret = wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack); 2614 else 2615 wcd_mbhc_stop(wcd->wcd_mbhc); 2616 2617 return ret; 2618 } 2619 2620 static const struct snd_soc_component_driver soc_codec_dev_wcd937x = { 2621 .name = "wcd937x_codec", 2622 .probe = wcd937x_soc_codec_probe, 2623 .remove = wcd937x_soc_codec_remove, 2624 .controls = wcd937x_snd_controls, 2625 .num_controls = ARRAY_SIZE(wcd937x_snd_controls), 2626 .dapm_widgets = wcd937x_dapm_widgets, 2627 .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets), 2628 .dapm_routes = wcd937x_audio_map, 2629 .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map), 2630 .set_jack = wcd937x_codec_set_jack, 2631 .endianness = 1, 2632 }; 2633 2634 static void wcd937x_dt_parse_micbias_info(struct device *dev, struct wcd937x_priv *wcd) 2635 { 2636 struct device_node *np = dev->of_node; 2637 u32 prop_val = 0; 2638 int ret = 0; 2639 2640 ret = of_property_read_u32(np, "qcom,micbias1-microvolt", &prop_val); 2641 if (!ret) 2642 wcd->micb1_mv = prop_val / 1000; 2643 else 2644 dev_warn(dev, "Micbias1 DT property not found\n"); 2645 2646 ret = of_property_read_u32(np, "qcom,micbias2-microvolt", &prop_val); 2647 if (!ret) 2648 wcd->micb2_mv = prop_val / 1000; 2649 else 2650 dev_warn(dev, "Micbias2 DT property not found\n"); 2651 2652 ret = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val); 2653 if (!ret) 2654 wcd->micb3_mv = prop_val / 1000; 2655 else 2656 dev_warn(dev, "Micbias3 DT property not found\n"); 2657 } 2658 2659 static bool wcd937x_swap_gnd_mic(struct snd_soc_component *component, bool active) 2660 { 2661 int value; 2662 struct wcd937x_priv *wcd937x; 2663 2664 wcd937x = snd_soc_component_get_drvdata(component); 2665 2666 value = gpiod_get_value(wcd937x->us_euro_gpio); 2667 gpiod_set_value(wcd937x->us_euro_gpio, !value); 2668 2669 return true; 2670 } 2671 2672 static int wcd937x_codec_hw_params(struct snd_pcm_substream *substream, 2673 struct snd_pcm_hw_params *params, 2674 struct snd_soc_dai *dai) 2675 { 2676 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2677 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2678 2679 return wcd937x_sdw_hw_params(wcd, substream, params, dai); 2680 } 2681 2682 static int wcd937x_codec_free(struct snd_pcm_substream *substream, 2683 struct snd_soc_dai *dai) 2684 { 2685 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2686 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2687 2688 return sdw_stream_remove_slave(wcd->sdev, wcd->sruntime); 2689 } 2690 2691 static int wcd937x_codec_set_sdw_stream(struct snd_soc_dai *dai, 2692 void *stream, int direction) 2693 { 2694 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2695 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2696 2697 wcd->sruntime = stream; 2698 2699 return 0; 2700 } 2701 2702 static int wcd937x_get_channel_map(const struct snd_soc_dai *dai, 2703 unsigned int *tx_num, unsigned int *tx_slot, 2704 unsigned int *rx_num, unsigned int *rx_slot) 2705 { 2706 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2707 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2708 int i; 2709 2710 switch (dai->id) { 2711 case AIF1_PB: 2712 if (!rx_slot || !rx_num) { 2713 dev_err(dai->dev, "Invalid rx_slot %p or rx_num %p\n", 2714 rx_slot, rx_num); 2715 return -EINVAL; 2716 } 2717 2718 for (i = 0; i < SDW_MAX_PORTS; i++) 2719 rx_slot[i] = wcd->master_channel_map[i]; 2720 2721 *rx_num = i; 2722 break; 2723 case AIF1_CAP: 2724 if (!tx_slot || !tx_num) { 2725 dev_err(dai->dev, "Invalid tx_slot %p or tx_num %p\n", 2726 tx_slot, tx_num); 2727 return -EINVAL; 2728 } 2729 2730 for (i = 0; i < SDW_MAX_PORTS; i++) 2731 tx_slot[i] = wcd->master_channel_map[i]; 2732 2733 *tx_num = i; 2734 break; 2735 default: 2736 break; 2737 } 2738 2739 return 0; 2740 } 2741 2742 static const struct snd_soc_dai_ops wcd937x_sdw_dai_ops = { 2743 .hw_params = wcd937x_codec_hw_params, 2744 .hw_free = wcd937x_codec_free, 2745 .set_stream = wcd937x_codec_set_sdw_stream, 2746 .get_channel_map = wcd937x_get_channel_map, 2747 }; 2748 2749 static struct snd_soc_dai_driver wcd937x_dais[] = { 2750 [0] = { 2751 .name = "wcd937x-sdw-rx", 2752 .playback = { 2753 .stream_name = "WCD AIF Playback", 2754 .rates = WCD937X_RATES | WCD937X_FRAC_RATES, 2755 .formats = WCD937X_FORMATS, 2756 .rate_min = 8000, 2757 .rate_max = 384000, 2758 .channels_min = 1, 2759 .channels_max = 4, 2760 }, 2761 .ops = &wcd937x_sdw_dai_ops, 2762 }, 2763 [1] = { 2764 .name = "wcd937x-sdw-tx", 2765 .capture = { 2766 .stream_name = "WCD AIF Capture", 2767 .rates = WCD937X_RATES, 2768 .formats = WCD937X_FORMATS, 2769 .rate_min = 8000, 2770 .rate_max = 192000, 2771 .channels_min = 1, 2772 .channels_max = 4, 2773 }, 2774 .ops = &wcd937x_sdw_dai_ops, 2775 }, 2776 }; 2777 2778 static int wcd937x_bind(struct device *dev) 2779 { 2780 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev); 2781 int ret; 2782 2783 /* Give the SDW subdevices some more time to settle */ 2784 usleep_range(5000, 5010); 2785 2786 ret = component_bind_all(dev, wcd937x); 2787 if (ret) { 2788 dev_err(dev, "Slave bind failed, ret = %d\n", ret); 2789 return ret; 2790 } 2791 2792 wcd937x->rxdev = wcd937x_sdw_device_get(wcd937x->rxnode); 2793 if (!wcd937x->rxdev) { 2794 dev_err(dev, "could not find slave with matching of node\n"); 2795 return -EINVAL; 2796 } 2797 2798 wcd937x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd937x->rxdev); 2799 wcd937x->sdw_priv[AIF1_PB]->wcd937x = wcd937x; 2800 2801 wcd937x->txdev = wcd937x_sdw_device_get(wcd937x->txnode); 2802 if (!wcd937x->txdev) { 2803 dev_err(dev, "could not find txslave with matching of node\n"); 2804 return -EINVAL; 2805 } 2806 2807 wcd937x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd937x->txdev); 2808 wcd937x->sdw_priv[AIF1_CAP]->wcd937x = wcd937x; 2809 wcd937x->tx_sdw_dev = dev_to_sdw_dev(wcd937x->txdev); 2810 if (!wcd937x->tx_sdw_dev) { 2811 dev_err(dev, "could not get txslave with matching of dev\n"); 2812 return -EINVAL; 2813 } 2814 2815 /* 2816 * As TX is the main CSR reg interface, which should not be suspended first. 2817 * expicilty add the dependency link 2818 */ 2819 if (!device_link_add(wcd937x->rxdev, wcd937x->txdev, 2820 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2821 dev_err(dev, "Could not devlink TX and RX\n"); 2822 return -EINVAL; 2823 } 2824 2825 if (!device_link_add(dev, wcd937x->txdev, 2826 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2827 dev_err(dev, "Could not devlink WCD and TX\n"); 2828 return -EINVAL; 2829 } 2830 2831 if (!device_link_add(dev, wcd937x->rxdev, 2832 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2833 dev_err(dev, "Could not devlink WCD and RX\n"); 2834 return -EINVAL; 2835 } 2836 2837 wcd937x->regmap = dev_get_regmap(&wcd937x->tx_sdw_dev->dev, NULL); 2838 if (!wcd937x->regmap) { 2839 dev_err(dev, "could not get TX device regmap\n"); 2840 return -EINVAL; 2841 } 2842 2843 ret = wcd937x_irq_init(wcd937x, dev); 2844 if (ret) { 2845 dev_err(dev, "IRQ init failed: %d\n", ret); 2846 return ret; 2847 } 2848 2849 wcd937x->sdw_priv[AIF1_PB]->slave_irq = wcd937x->virq; 2850 wcd937x->sdw_priv[AIF1_CAP]->slave_irq = wcd937x->virq; 2851 2852 ret = wcd937x_set_micbias_data(wcd937x); 2853 if (ret < 0) { 2854 dev_err(dev, "Bad micbias pdata\n"); 2855 return ret; 2856 } 2857 2858 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x, 2859 wcd937x_dais, ARRAY_SIZE(wcd937x_dais)); 2860 if (ret) 2861 dev_err(dev, "Codec registration failed\n"); 2862 2863 return ret; 2864 } 2865 2866 static void wcd937x_unbind(struct device *dev) 2867 { 2868 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev); 2869 2870 snd_soc_unregister_component(dev); 2871 device_link_remove(dev, wcd937x->txdev); 2872 device_link_remove(dev, wcd937x->rxdev); 2873 device_link_remove(wcd937x->rxdev, wcd937x->txdev); 2874 component_unbind_all(dev, wcd937x); 2875 mutex_destroy(&wcd937x->micb_lock); 2876 } 2877 2878 static const struct component_master_ops wcd937x_comp_ops = { 2879 .bind = wcd937x_bind, 2880 .unbind = wcd937x_unbind, 2881 }; 2882 2883 static int wcd937x_add_slave_components(struct wcd937x_priv *wcd937x, 2884 struct device *dev, 2885 struct component_match **matchptr) 2886 { 2887 struct device_node *np = dev->of_node; 2888 2889 wcd937x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0); 2890 if (!wcd937x->rxnode) { 2891 dev_err(dev, "Couldn't parse phandle to qcom,rx-device!\n"); 2892 return -ENODEV; 2893 } 2894 of_node_get(wcd937x->rxnode); 2895 component_match_add_release(dev, matchptr, component_release_of, 2896 component_compare_of, wcd937x->rxnode); 2897 2898 wcd937x->txnode = of_parse_phandle(np, "qcom,tx-device", 0); 2899 if (!wcd937x->txnode) { 2900 dev_err(dev, "Couldn't parse phandle to qcom,tx-device\n"); 2901 return -ENODEV; 2902 } 2903 of_node_get(wcd937x->txnode); 2904 component_match_add_release(dev, matchptr, component_release_of, 2905 component_compare_of, wcd937x->txnode); 2906 2907 return 0; 2908 } 2909 2910 static int wcd937x_probe(struct platform_device *pdev) 2911 { 2912 struct component_match *match = NULL; 2913 struct device *dev = &pdev->dev; 2914 struct wcd937x_priv *wcd937x; 2915 struct wcd_mbhc_config *cfg; 2916 int ret; 2917 2918 wcd937x = devm_kzalloc(dev, sizeof(*wcd937x), GFP_KERNEL); 2919 if (!wcd937x) 2920 return -ENOMEM; 2921 2922 dev_set_drvdata(dev, wcd937x); 2923 mutex_init(&wcd937x->micb_lock); 2924 2925 wcd937x->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 2926 if (IS_ERR(wcd937x->reset_gpio)) 2927 return dev_err_probe(dev, PTR_ERR(wcd937x->reset_gpio), 2928 "failed to reset wcd gpio\n"); 2929 2930 wcd937x->us_euro_gpio = devm_gpiod_get_optional(dev, "us-euro", GPIOD_OUT_LOW); 2931 if (IS_ERR(wcd937x->us_euro_gpio)) 2932 return dev_err_probe(dev, PTR_ERR(wcd937x->us_euro_gpio), 2933 "us-euro swap Control GPIO not found\n"); 2934 2935 cfg = &wcd937x->mbhc_cfg; 2936 cfg->swap_gnd_mic = wcd937x_swap_gnd_mic; 2937 2938 wcd937x->supplies[0].supply = "vdd-rxtx"; 2939 wcd937x->supplies[1].supply = "vdd-px"; 2940 wcd937x->supplies[2].supply = "vdd-mic-bias"; 2941 wcd937x->supplies[3].supply = "vdd-buck"; 2942 2943 ret = devm_regulator_bulk_get(dev, WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2944 if (ret) 2945 return dev_err_probe(dev, ret, "Failed to get supplies\n"); 2946 2947 ret = regulator_bulk_enable(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2948 if (ret) { 2949 regulator_bulk_free(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2950 return dev_err_probe(dev, ret, "Failed to enable supplies\n"); 2951 } 2952 2953 wcd937x_dt_parse_micbias_info(dev, wcd937x); 2954 2955 cfg->mbhc_micbias = MIC_BIAS_2; 2956 cfg->anc_micbias = MIC_BIAS_2; 2957 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 2958 cfg->num_btn = WCD937X_MBHC_MAX_BUTTONS; 2959 cfg->micb_mv = wcd937x->micb2_mv; 2960 cfg->linein_th = 5000; 2961 cfg->hs_thr = 1700; 2962 cfg->hph_thr = 50; 2963 2964 wcd_dt_parse_mbhc_data(dev, &wcd937x->mbhc_cfg); 2965 2966 ret = wcd937x_add_slave_components(wcd937x, dev, &match); 2967 if (ret) 2968 goto err_disable_regulators; 2969 2970 wcd937x_reset(wcd937x); 2971 2972 ret = component_master_add_with_match(dev, &wcd937x_comp_ops, match); 2973 if (ret) 2974 goto err_disable_regulators; 2975 2976 pm_runtime_set_autosuspend_delay(dev, 1000); 2977 pm_runtime_use_autosuspend(dev); 2978 pm_runtime_mark_last_busy(dev); 2979 pm_runtime_set_active(dev); 2980 pm_runtime_enable(dev); 2981 pm_runtime_idle(dev); 2982 2983 return 0; 2984 2985 err_disable_regulators: 2986 regulator_bulk_disable(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2987 regulator_bulk_free(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2988 2989 return ret; 2990 } 2991 2992 static void wcd937x_remove(struct platform_device *pdev) 2993 { 2994 struct device *dev = &pdev->dev; 2995 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev); 2996 2997 component_master_del(&pdev->dev, &wcd937x_comp_ops); 2998 2999 pm_runtime_disable(dev); 3000 pm_runtime_set_suspended(dev); 3001 pm_runtime_dont_use_autosuspend(dev); 3002 3003 regulator_bulk_disable(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 3004 regulator_bulk_free(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 3005 } 3006 3007 #if defined(CONFIG_OF) 3008 static const struct of_device_id wcd937x_of_match[] = { 3009 { .compatible = "qcom,wcd9370-codec" }, 3010 { .compatible = "qcom,wcd9375-codec" }, 3011 { } 3012 }; 3013 MODULE_DEVICE_TABLE(of, wcd937x_of_match); 3014 #endif 3015 3016 static struct platform_driver wcd937x_codec_driver = { 3017 .probe = wcd937x_probe, 3018 .remove = wcd937x_remove, 3019 .driver = { 3020 .name = "wcd937x_codec", 3021 .of_match_table = of_match_ptr(wcd937x_of_match), 3022 .suppress_bind_attrs = true, 3023 }, 3024 }; 3025 3026 module_platform_driver(wcd937x_codec_driver); 3027 MODULE_DESCRIPTION("WCD937X Codec driver"); 3028 MODULE_LICENSE("GPL"); 3029