1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 4 #include <linux/component.h> 5 #include <linux/delay.h> 6 #include <linux/device.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of_gpio.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regmap.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/slab.h> 17 #include <sound/jack.h> 18 #include <sound/pcm_params.h> 19 #include <sound/pcm.h> 20 #include <sound/soc-dapm.h> 21 #include <sound/soc.h> 22 #include <sound/tlv.h> 23 24 #include "wcd-clsh-v2.h" 25 #include "wcd-mbhc-v2.h" 26 #include "wcd937x.h" 27 28 enum { 29 CHIPID_WCD9370 = 0, 30 CHIPID_WCD9375 = 5, 31 }; 32 33 /* Z value defined in milliohm */ 34 #define WCD937X_ZDET_VAL_32 (32000) 35 #define WCD937X_ZDET_VAL_400 (400000) 36 #define WCD937X_ZDET_VAL_1200 (1200000) 37 #define WCD937X_ZDET_VAL_100K (100000000) 38 /* Z floating defined in ohms */ 39 #define WCD937X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE) 40 #define WCD937X_ZDET_NUM_MEASUREMENTS (900) 41 #define WCD937X_MBHC_GET_C1(c) (((c) & 0xC000) >> 14) 42 #define WCD937X_MBHC_GET_X1(x) ((x) & 0x3FFF) 43 /* Z value compared in milliOhm */ 44 #define WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z) (((z) > 400000) || ((z) < 32000)) 45 #define WCD937X_MBHC_ZDET_CONST (86 * 16384) 46 #define WCD937X_MBHC_MOISTURE_RREF R_24_KOHM 47 #define WCD_MBHC_HS_V_MAX 1600 48 #define EAR_RX_PATH_AUX 1 49 #define WCD937X_MBHC_MAX_BUTTONS 8 50 51 #define WCD937X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 52 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 53 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\ 54 SNDRV_PCM_RATE_384000) 55 56 /* Fractional Rates */ 57 #define WCD937X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 58 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800) 59 60 #define WCD937X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |\ 61 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 62 63 enum { 64 ALLOW_BUCK_DISABLE, 65 HPH_COMP_DELAY, 66 HPH_PA_DELAY, 67 AMIC2_BCS_ENABLE, 68 }; 69 70 enum { 71 AIF1_PB = 0, 72 AIF1_CAP, 73 NUM_CODEC_DAIS, 74 }; 75 76 struct wcd937x_priv { 77 struct sdw_slave *tx_sdw_dev; 78 struct wcd937x_sdw_priv *sdw_priv[NUM_CODEC_DAIS]; 79 struct device *txdev; 80 struct device *rxdev; 81 struct device_node *rxnode; 82 struct device_node *txnode; 83 struct regmap *regmap; 84 /* micb setup lock */ 85 struct mutex micb_lock; 86 /* mbhc module */ 87 struct wcd_mbhc *wcd_mbhc; 88 struct wcd_mbhc_config mbhc_cfg; 89 struct wcd_mbhc_intr intr_ids; 90 struct wcd_clsh_ctrl *clsh_info; 91 struct irq_domain *virq; 92 struct regmap_irq_chip *wcd_regmap_irq_chip; 93 struct regmap_irq_chip_data *irq_chip; 94 struct regulator_bulk_data supplies[WCD937X_MAX_BULK_SUPPLY]; 95 struct regulator *buck_supply; 96 struct snd_soc_jack *jack; 97 unsigned long status_mask; 98 s32 micb_ref[WCD937X_MAX_MICBIAS]; 99 s32 pullup_ref[WCD937X_MAX_MICBIAS]; 100 u32 hph_mode; 101 int ear_rx_path; 102 u32 chipid; 103 u32 micb1_mv; 104 u32 micb2_mv; 105 u32 micb3_mv; 106 u32 micb4_mv; /* 9375 only */ 107 int hphr_pdm_wd_int; 108 int hphl_pdm_wd_int; 109 int aux_pdm_wd_int; 110 bool comp1_enable; 111 bool comp2_enable; 112 113 struct gpio_desc *us_euro_gpio; 114 struct gpio_desc *reset_gpio; 115 116 int dmic_0_1_clk_cnt; 117 int dmic_2_3_clk_cnt; 118 int dmic_4_5_clk_cnt; 119 atomic_t rx_clk_cnt; 120 atomic_t ana_clk_count; 121 }; 122 123 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800); 124 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 125 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 126 127 struct wcd937x_mbhc_zdet_param { 128 u16 ldo_ctl; 129 u16 noff; 130 u16 nshift; 131 u16 btn5; 132 u16 btn6; 133 u16 btn7; 134 }; 135 136 static struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 137 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD937X_ANA_MBHC_MECH, 0x80), 138 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD937X_ANA_MBHC_MECH, 0x40), 139 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD937X_ANA_MBHC_MECH, 0x20), 140 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD937X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 141 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD937X_ANA_MBHC_ELECT, 0x08), 142 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F), 143 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD937X_ANA_MBHC_MECH, 0x04), 144 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD937X_ANA_MBHC_MECH, 0x10), 145 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD937X_ANA_MBHC_MECH, 0x08), 146 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD937X_ANA_MBHC_MECH, 0x01), 147 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD937X_ANA_MBHC_ELECT, 0x06), 148 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD937X_ANA_MBHC_ELECT, 0x80), 149 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD937X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 150 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD937X_MBHC_NEW_CTL_1, 0x03), 151 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD937X_MBHC_NEW_CTL_2, 0x03), 152 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x08), 153 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD937X_ANA_MBHC_RESULT_3, 0x10), 154 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x20), 155 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x80), 156 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x40), 157 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD937X_HPH_OCP_CTL, 0x10), 158 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x07), 159 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD937X_ANA_MBHC_ELECT, 0x70), 160 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0xFF), 161 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD937X_ANA_MICB2, 0xC0), 162 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD937X_HPH_CNP_WG_TIME, 0xFF), 163 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD937X_ANA_HPH, 0x40), 164 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD937X_ANA_HPH, 0x80), 165 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD937X_ANA_HPH, 0xC0), 166 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD937X_ANA_MBHC_RESULT_3, 0x10), 167 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD937X_MBHC_CTL_BCS, 0x02), 168 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD937X_MBHC_NEW_FSM_STATUS, 0x01), 169 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD937X_MBHC_NEW_CTL_2, 0x70), 170 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD937X_MBHC_NEW_FSM_STATUS, 0x20), 171 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD937X_HPH_PA_CTL2, 0x40), 172 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD937X_HPH_PA_CTL2, 0x10), 173 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD937X_HPH_L_TEST, 0x01), 174 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD937X_HPH_R_TEST, 0x01), 175 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD937X_DIGITAL_INTR_STATUS_0, 0x80), 176 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD937X_DIGITAL_INTR_STATUS_0, 0x20), 177 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD937X_MBHC_NEW_CTL_1, 0x08), 178 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD937X_MBHC_NEW_FSM_STATUS, 0x40), 179 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD937X_MBHC_NEW_FSM_STATUS, 0x80), 180 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD937X_MBHC_NEW_ADC_RESULT, 0xFF), 181 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD937X_ANA_MICB2, 0x3F), 182 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD937X_MBHC_NEW_CTL_1, 0x10), 183 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD937X_MBHC_NEW_CTL_1, 0x04), 184 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD937X_ANA_MBHC_ZDET, 0x02), 185 }; 186 187 static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = { 188 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, BIT(0)), 189 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, BIT(1)), 190 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, BIT(2)), 191 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, BIT(3)), 192 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, BIT(4)), 193 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, BIT(5)), 194 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, BIT(6)), 195 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, BIT(7)), 196 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, BIT(0)), 197 REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, BIT(1)), 198 REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, BIT(2)), 199 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, BIT(3)), 200 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, BIT(4)), 201 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, BIT(5)), 202 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, BIT(6)), 203 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, BIT(7)), 204 REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, BIT(0)), 205 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, BIT(1)), 206 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, BIT(2)), 207 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, BIT(3)), 208 }; 209 210 static int wcd937x_handle_post_irq(void *data) 211 { 212 struct wcd937x_priv *wcd937x; 213 214 if (data) 215 wcd937x = (struct wcd937x_priv *)data; 216 else 217 return IRQ_HANDLED; 218 219 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_0, 0); 220 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_1, 0); 221 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_2, 0); 222 223 return IRQ_HANDLED; 224 } 225 226 static const u32 wcd937x_config_regs[] = { 227 WCD937X_DIGITAL_INTR_LEVEL_0, 228 }; 229 230 static struct regmap_irq_chip wcd937x_regmap_irq_chip = { 231 .name = "wcd937x", 232 .irqs = wcd937x_irqs, 233 .num_irqs = ARRAY_SIZE(wcd937x_irqs), 234 .num_regs = 3, 235 .status_base = WCD937X_DIGITAL_INTR_STATUS_0, 236 .mask_base = WCD937X_DIGITAL_INTR_MASK_0, 237 .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0, 238 .use_ack = 1, 239 .clear_ack = 1, 240 .config_base = wcd937x_config_regs, 241 .num_config_bases = ARRAY_SIZE(wcd937x_config_regs), 242 .num_config_regs = 1, 243 .runtime_pm = true, 244 .handle_post_irq = wcd937x_handle_post_irq, 245 .irq_drv_data = NULL, 246 }; 247 248 static void wcd937x_reset(struct wcd937x_priv *wcd937x) 249 { 250 usleep_range(20, 30); 251 252 gpiod_set_value(wcd937x->reset_gpio, 1); 253 254 usleep_range(20, 30); 255 } 256 257 static void wcd937x_io_init(struct regmap *regmap) 258 { 259 u32 val = 0, temp = 0, temp1 = 0; 260 261 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_29, &val); 262 263 val = val & 0x0F; 264 265 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_16, &temp); 266 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_17, &temp1); 267 268 if (temp == 0x02 || temp1 > 0x09) 269 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x0E, val); 270 else 271 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x0e, 0x0e); 272 273 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x80, 0x80); 274 usleep_range(1000, 1010); 275 276 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x40, 0x40); 277 usleep_range(1000, 1010); 278 279 regmap_update_bits(regmap, WCD937X_LDORXTX_CONFIG, BIT(4), 0x00); 280 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xf0, BIT(7)); 281 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(7), BIT(7)); 282 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(6), BIT(6)); 283 usleep_range(10000, 10010); 284 285 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(6), 0x00); 286 regmap_update_bits(regmap, WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xff, 0xd9); 287 regmap_update_bits(regmap, WCD937X_MICB1_TEST_CTL_1, 0xff, 0xfa); 288 regmap_update_bits(regmap, WCD937X_MICB2_TEST_CTL_1, 0xff, 0xfa); 289 regmap_update_bits(regmap, WCD937X_MICB3_TEST_CTL_1, 0xff, 0xfa); 290 291 regmap_update_bits(regmap, WCD937X_MICB1_TEST_CTL_2, 0x38, 0x00); 292 regmap_update_bits(regmap, WCD937X_MICB2_TEST_CTL_2, 0x38, 0x00); 293 regmap_update_bits(regmap, WCD937X_MICB3_TEST_CTL_2, 0x38, 0x00); 294 295 /* Set Bandgap Fine Adjustment to +5mV for Tanggu SMIC part */ 296 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_16, &val); 297 if (val == 0x01) { 298 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0); 299 } else if (val == 0x02) { 300 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x1F, 0x04); 301 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x1F, 0x04); 302 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0); 303 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL, 0xF0, 0x50); 304 } 305 } 306 307 static int wcd937x_rx_clk_enable(struct snd_soc_component *component) 308 { 309 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 310 311 if (atomic_read(&wcd937x->rx_clk_cnt)) 312 return 0; 313 314 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(3), BIT(3)); 315 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(0), BIT(0)); 316 snd_soc_component_update_bits(component, WCD937X_ANA_RX_SUPPLIES, BIT(0), BIT(0)); 317 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX0_CTL, BIT(6), 0x00); 318 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX1_CTL, BIT(6), 0x00); 319 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX2_CTL, BIT(6), 0x00); 320 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(1), BIT(1)); 321 322 atomic_inc(&wcd937x->rx_clk_cnt); 323 324 return 0; 325 } 326 327 static int wcd937x_rx_clk_disable(struct snd_soc_component *component) 328 { 329 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 330 331 if (!atomic_read(&wcd937x->rx_clk_cnt)) { 332 dev_err(component->dev, "clk already disabled\n"); 333 return 0; 334 } 335 336 atomic_dec(&wcd937x->rx_clk_cnt); 337 338 snd_soc_component_update_bits(component, WCD937X_ANA_RX_SUPPLIES, BIT(0), 0x00); 339 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(1), 0x00); 340 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(0), 0x00); 341 342 return 0; 343 } 344 345 static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 346 struct snd_kcontrol *kcontrol, 347 int event) 348 { 349 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 350 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 351 int hph_mode = wcd937x->hph_mode; 352 353 switch (event) { 354 case SND_SOC_DAPM_PRE_PMU: 355 wcd937x_rx_clk_enable(component); 356 snd_soc_component_update_bits(component, 357 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 358 BIT(0), BIT(0)); 359 snd_soc_component_update_bits(component, 360 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 361 BIT(2), BIT(2)); 362 snd_soc_component_update_bits(component, 363 WCD937X_HPH_RDAC_CLK_CTL1, 364 BIT(7), 0x00); 365 set_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 366 break; 367 case SND_SOC_DAPM_POST_PMU: 368 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 369 snd_soc_component_update_bits(component, 370 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 371 0x0f, BIT(1)); 372 else if (hph_mode == CLS_H_LOHIFI) 373 snd_soc_component_update_bits(component, 374 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 375 0x0f, 0x06); 376 377 if (wcd937x->comp1_enable) { 378 snd_soc_component_update_bits(component, 379 WCD937X_DIGITAL_CDC_COMP_CTL_0, 380 BIT(1), BIT(1)); 381 snd_soc_component_update_bits(component, 382 WCD937X_HPH_L_EN, 383 BIT(5), 0x00); 384 385 if (wcd937x->comp2_enable) { 386 snd_soc_component_update_bits(component, 387 WCD937X_DIGITAL_CDC_COMP_CTL_0, 388 BIT(0), BIT(0)); 389 snd_soc_component_update_bits(component, 390 WCD937X_HPH_R_EN, BIT(5), 0x00); 391 } 392 393 if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) { 394 usleep_range(5000, 5110); 395 clear_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 396 } 397 } else { 398 snd_soc_component_update_bits(component, 399 WCD937X_DIGITAL_CDC_COMP_CTL_0, 400 BIT(1), 0x00); 401 snd_soc_component_update_bits(component, 402 WCD937X_HPH_L_EN, 403 BIT(5), BIT(5)); 404 } 405 406 snd_soc_component_update_bits(component, 407 WCD937X_HPH_NEW_INT_HPH_TIMER1, 408 BIT(1), 0x00); 409 break; 410 case SND_SOC_DAPM_POST_PMD: 411 snd_soc_component_update_bits(component, 412 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 413 0x0f, BIT(0)); 414 break; 415 } 416 417 return 0; 418 } 419 420 static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 421 struct snd_kcontrol *kcontrol, 422 int event) 423 { 424 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 425 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 426 int hph_mode = wcd937x->hph_mode; 427 428 switch (event) { 429 case SND_SOC_DAPM_PRE_PMU: 430 wcd937x_rx_clk_enable(component); 431 snd_soc_component_update_bits(component, 432 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(1), BIT(1)); 433 snd_soc_component_update_bits(component, 434 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, BIT(3), BIT(3)); 435 snd_soc_component_update_bits(component, 436 WCD937X_HPH_RDAC_CLK_CTL1, BIT(7), 0x00); 437 set_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 438 break; 439 case SND_SOC_DAPM_POST_PMU: 440 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 441 snd_soc_component_update_bits(component, 442 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 443 0x0f, BIT(1)); 444 else if (hph_mode == CLS_H_LOHIFI) 445 snd_soc_component_update_bits(component, 446 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 447 0x0f, 0x06); 448 if (wcd937x->comp2_enable) { 449 snd_soc_component_update_bits(component, 450 WCD937X_DIGITAL_CDC_COMP_CTL_0, 451 BIT(0), BIT(0)); 452 snd_soc_component_update_bits(component, 453 WCD937X_HPH_R_EN, BIT(5), 0x00); 454 if (wcd937x->comp1_enable) { 455 snd_soc_component_update_bits(component, 456 WCD937X_DIGITAL_CDC_COMP_CTL_0, 457 BIT(1), BIT(1)); 458 snd_soc_component_update_bits(component, 459 WCD937X_HPH_L_EN, 460 BIT(5), 0x00); 461 } 462 463 if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) { 464 usleep_range(5000, 5110); 465 clear_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 466 } 467 } else { 468 snd_soc_component_update_bits(component, 469 WCD937X_DIGITAL_CDC_COMP_CTL_0, 470 BIT(0), 0x00); 471 snd_soc_component_update_bits(component, 472 WCD937X_HPH_R_EN, 473 BIT(5), BIT(5)); 474 } 475 snd_soc_component_update_bits(component, 476 WCD937X_HPH_NEW_INT_HPH_TIMER1, 477 BIT(1), 0x00); 478 break; 479 case SND_SOC_DAPM_POST_PMD: 480 snd_soc_component_update_bits(component, 481 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 482 0x0f, BIT(0)); 483 break; 484 } 485 486 return 0; 487 } 488 489 static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 490 struct snd_kcontrol *kcontrol, 491 int event) 492 { 493 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 494 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 495 int hph_mode = wcd937x->hph_mode; 496 497 switch (event) { 498 case SND_SOC_DAPM_PRE_PMU: 499 wcd937x_rx_clk_enable(component); 500 snd_soc_component_update_bits(component, 501 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 502 BIT(2), BIT(2)); 503 snd_soc_component_update_bits(component, 504 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 505 BIT(0), BIT(0)); 506 507 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 508 snd_soc_component_update_bits(component, 509 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 510 0x0f, BIT(1)); 511 else if (hph_mode == CLS_H_LOHIFI) 512 snd_soc_component_update_bits(component, 513 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 514 0x0f, 0x06); 515 if (wcd937x->comp1_enable) 516 snd_soc_component_update_bits(component, 517 WCD937X_DIGITAL_CDC_COMP_CTL_0, 518 BIT(1), BIT(1)); 519 usleep_range(5000, 5010); 520 521 snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN, BIT(2), 0x00); 522 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 523 WCD_CLSH_EVENT_PRE_DAC, 524 WCD_CLSH_STATE_EAR, 525 hph_mode); 526 527 break; 528 case SND_SOC_DAPM_POST_PMD: 529 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI || 530 hph_mode == CLS_H_HIFI) 531 snd_soc_component_update_bits(component, 532 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 533 0x0f, BIT(0)); 534 if (wcd937x->comp1_enable) 535 snd_soc_component_update_bits(component, 536 WCD937X_DIGITAL_CDC_COMP_CTL_0, 537 BIT(1), 0x00); 538 break; 539 } 540 541 return 0; 542 } 543 544 static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w, 545 struct snd_kcontrol *kcontrol, 546 int event) 547 { 548 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 549 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 550 int hph_mode = wcd937x->hph_mode; 551 552 switch (event) { 553 case SND_SOC_DAPM_PRE_PMU: 554 wcd937x_rx_clk_enable(component); 555 snd_soc_component_update_bits(component, 556 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 557 BIT(2), BIT(2)); 558 snd_soc_component_update_bits(component, 559 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 560 BIT(2), BIT(2)); 561 snd_soc_component_update_bits(component, 562 WCD937X_DIGITAL_CDC_AUX_GAIN_CTL, 563 BIT(0), BIT(0)); 564 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 565 WCD_CLSH_EVENT_PRE_DAC, 566 WCD_CLSH_STATE_AUX, 567 hph_mode); 568 569 break; 570 case SND_SOC_DAPM_POST_PMD: 571 snd_soc_component_update_bits(component, 572 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 573 BIT(2), 0x00); 574 break; 575 } 576 577 return 0; 578 } 579 580 static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 581 struct snd_kcontrol *kcontrol, 582 int event) 583 { 584 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 585 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 586 int hph_mode = wcd937x->hph_mode; 587 588 switch (event) { 589 case SND_SOC_DAPM_PRE_PMU: 590 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 591 WCD_CLSH_EVENT_PRE_DAC, 592 WCD_CLSH_STATE_HPHR, 593 hph_mode); 594 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 595 BIT(4), BIT(4)); 596 usleep_range(100, 110); 597 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 598 snd_soc_component_update_bits(component, 599 WCD937X_DIGITAL_PDM_WD_CTL1, 600 0x07, 0x03); 601 break; 602 case SND_SOC_DAPM_POST_PMU: 603 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 604 if (wcd937x->comp2_enable) 605 usleep_range(7000, 7100); 606 else 607 usleep_range(20000, 20100); 608 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 609 } 610 611 snd_soc_component_update_bits(component, 612 WCD937X_HPH_NEW_INT_HPH_TIMER1, 613 BIT(1), BIT(1)); 614 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 615 snd_soc_component_update_bits(component, 616 WCD937X_ANA_RX_SUPPLIES, 617 BIT(1), BIT(1)); 618 enable_irq(wcd937x->hphr_pdm_wd_int); 619 break; 620 case SND_SOC_DAPM_PRE_PMD: 621 disable_irq_nosync(wcd937x->hphr_pdm_wd_int); 622 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 623 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_PRE_HPHR_PA_OFF); 624 break; 625 case SND_SOC_DAPM_POST_PMD: 626 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 627 if (wcd937x->comp2_enable) 628 usleep_range(7000, 7100); 629 else 630 usleep_range(20000, 20100); 631 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 632 } 633 634 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_POST_HPHR_PA_OFF); 635 snd_soc_component_update_bits(component, 636 WCD937X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00); 637 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 638 BIT(4), 0x00); 639 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 640 WCD_CLSH_EVENT_POST_PA, 641 WCD_CLSH_STATE_HPHR, 642 hph_mode); 643 break; 644 } 645 646 return 0; 647 } 648 649 static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 650 struct snd_kcontrol *kcontrol, 651 int event) 652 { 653 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 654 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 655 int hph_mode = wcd937x->hph_mode; 656 657 switch (event) { 658 case SND_SOC_DAPM_PRE_PMU: 659 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 660 WCD_CLSH_EVENT_PRE_DAC, 661 WCD_CLSH_STATE_HPHL, 662 hph_mode); 663 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 664 BIT(5), BIT(5)); 665 usleep_range(100, 110); 666 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 667 snd_soc_component_update_bits(component, 668 WCD937X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03); 669 break; 670 case SND_SOC_DAPM_POST_PMU: 671 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 672 if (!wcd937x->comp1_enable) 673 usleep_range(20000, 20100); 674 else 675 usleep_range(7000, 7100); 676 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 677 } 678 679 snd_soc_component_update_bits(component, 680 WCD937X_HPH_NEW_INT_HPH_TIMER1, 681 BIT(1), BIT(1)); 682 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 683 snd_soc_component_update_bits(component, 684 WCD937X_ANA_RX_SUPPLIES, 685 BIT(1), BIT(1)); 686 enable_irq(wcd937x->hphl_pdm_wd_int); 687 break; 688 case SND_SOC_DAPM_PRE_PMD: 689 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 690 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 691 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF); 692 break; 693 case SND_SOC_DAPM_POST_PMD: 694 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 695 if (!wcd937x->comp1_enable) 696 usleep_range(20000, 20100); 697 else 698 usleep_range(7000, 7100); 699 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 700 } 701 702 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 703 snd_soc_component_update_bits(component, 704 WCD937X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00); 705 snd_soc_component_update_bits(component, 706 WCD937X_ANA_HPH, BIT(5), 0x00); 707 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 708 WCD_CLSH_EVENT_POST_PA, 709 WCD_CLSH_STATE_HPHL, 710 hph_mode); 711 break; 712 } 713 714 return 0; 715 } 716 717 static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w, 718 struct snd_kcontrol *kcontrol, 719 int event) 720 { 721 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 722 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 723 int hph_mode = wcd937x->hph_mode; 724 725 switch (event) { 726 case SND_SOC_DAPM_PRE_PMU: 727 snd_soc_component_update_bits(component, 728 WCD937X_DIGITAL_PDM_WD_CTL2, 729 BIT(0), BIT(0)); 730 break; 731 case SND_SOC_DAPM_POST_PMU: 732 usleep_range(1000, 1010); 733 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 734 snd_soc_component_update_bits(component, 735 WCD937X_ANA_RX_SUPPLIES, 736 BIT(1), BIT(1)); 737 enable_irq(wcd937x->aux_pdm_wd_int); 738 break; 739 case SND_SOC_DAPM_PRE_PMD: 740 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 741 break; 742 case SND_SOC_DAPM_POST_PMD: 743 usleep_range(2000, 2010); 744 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 745 WCD_CLSH_EVENT_POST_PA, 746 WCD_CLSH_STATE_AUX, 747 hph_mode); 748 snd_soc_component_update_bits(component, 749 WCD937X_DIGITAL_PDM_WD_CTL2, 750 BIT(0), 0x00); 751 break; 752 } 753 754 return 0; 755 } 756 757 static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 758 struct snd_kcontrol *kcontrol, 759 int event) 760 { 761 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 762 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 763 int hph_mode = wcd937x->hph_mode; 764 765 switch (event) { 766 case SND_SOC_DAPM_PRE_PMU: 767 /* Enable watchdog interrupt for HPHL or AUX depending on mux value */ 768 wcd937x->ear_rx_path = snd_soc_component_read(component, 769 WCD937X_DIGITAL_CDC_EAR_PATH_CTL); 770 771 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 772 snd_soc_component_update_bits(component, 773 WCD937X_DIGITAL_PDM_WD_CTL2, 774 BIT(0), BIT(0)); 775 else 776 snd_soc_component_update_bits(component, 777 WCD937X_DIGITAL_PDM_WD_CTL0, 778 0x07, 0x03); 779 if (!wcd937x->comp1_enable) 780 snd_soc_component_update_bits(component, 781 WCD937X_ANA_EAR_COMPANDER_CTL, 782 BIT(7), BIT(7)); 783 break; 784 case SND_SOC_DAPM_POST_PMU: 785 usleep_range(6000, 6010); 786 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 787 snd_soc_component_update_bits(component, 788 WCD937X_ANA_RX_SUPPLIES, 789 BIT(1), BIT(1)); 790 791 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 792 enable_irq(wcd937x->aux_pdm_wd_int); 793 else 794 enable_irq(wcd937x->hphl_pdm_wd_int); 795 break; 796 case SND_SOC_DAPM_PRE_PMD: 797 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 798 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 799 else 800 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 801 break; 802 case SND_SOC_DAPM_POST_PMD: 803 if (!wcd937x->comp1_enable) 804 snd_soc_component_update_bits(component, 805 WCD937X_ANA_EAR_COMPANDER_CTL, 806 BIT(7), 0x00); 807 usleep_range(7000, 7010); 808 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 809 WCD_CLSH_EVENT_POST_PA, 810 WCD_CLSH_STATE_EAR, 811 hph_mode); 812 snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN, 813 BIT(2), BIT(2)); 814 815 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 816 snd_soc_component_update_bits(component, 817 WCD937X_DIGITAL_PDM_WD_CTL2, 818 BIT(0), 0x00); 819 else 820 snd_soc_component_update_bits(component, 821 WCD937X_DIGITAL_PDM_WD_CTL0, 822 0x07, 0x00); 823 break; 824 } 825 826 return 0; 827 } 828 829 static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w, 830 struct snd_kcontrol *kcontrol, 831 int event) 832 { 833 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 834 835 if (event == SND_SOC_DAPM_POST_PMD) { 836 wcd937x_rx_clk_disable(component); 837 snd_soc_component_update_bits(component, 838 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 839 BIT(0), 0x00); 840 } 841 842 return 0; 843 } 844 845 static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w, 846 struct snd_kcontrol *kcontrol, int event) 847 { 848 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 849 850 if (event == SND_SOC_DAPM_POST_PMD) { 851 wcd937x_rx_clk_disable(component); 852 snd_soc_component_update_bits(component, 853 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 854 BIT(1), 0x00); 855 } 856 857 return 0; 858 } 859 860 static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w, 861 struct snd_kcontrol *kcontrol, 862 int event) 863 { 864 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 865 866 if (event == SND_SOC_DAPM_POST_PMD) { 867 usleep_range(6000, 6010); 868 wcd937x_rx_clk_disable(component); 869 snd_soc_component_update_bits(component, 870 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 871 BIT(2), 0x00); 872 } 873 874 return 0; 875 } 876 877 static int wcd937x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w, 878 struct snd_kcontrol *kcontrol, 879 int event) 880 { 881 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 882 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 883 int ret = 0; 884 885 switch (event) { 886 case SND_SOC_DAPM_PRE_PMU: 887 if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) { 888 dev_err(component->dev, "buck already in enabled state\n"); 889 clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask); 890 return 0; 891 } 892 ret = regulator_enable(wcd937x->buck_supply); 893 if (ret) { 894 dev_err(component->dev, "VDD_BUCK is not enabled\n"); 895 return ret; 896 } 897 clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask); 898 usleep_range(200, 250); 899 break; 900 case SND_SOC_DAPM_POST_PMD: 901 set_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask); 902 break; 903 } 904 905 return 0; 906 } 907 908 static int wcd937x_get_micb_vout_ctl_val(u32 micb_mv) 909 { 910 if (micb_mv < 1000 || micb_mv > 2850) { 911 pr_err("Unsupported micbias voltage (%u mV)\n", micb_mv); 912 return -EINVAL; 913 } 914 915 return (micb_mv - 1000) / 50; 916 } 917 918 static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w, 919 struct snd_kcontrol *kcontrol, int event) 920 { 921 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 922 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 923 bool use_amic3 = snd_soc_component_read(component, WCD937X_TX_NEW_TX_CH2_SEL) & BIT(7); 924 925 /* Enable BCS for Headset mic */ 926 if (event == SND_SOC_DAPM_PRE_PMU && strnstr(w->name, "ADC", sizeof("ADC"))) 927 if (w->shift == 1 && !use_amic3) 928 set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask); 929 930 return 0; 931 } 932 933 static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w, 934 struct snd_kcontrol *kcontrol, int event) 935 { 936 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 937 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 938 939 switch (event) { 940 case SND_SOC_DAPM_PRE_PMU: 941 atomic_inc(&wcd937x->ana_clk_count); 942 snd_soc_component_update_bits(component, 943 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(7), BIT(7)); 944 snd_soc_component_update_bits(component, 945 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(3), BIT(3)); 946 snd_soc_component_update_bits(component, 947 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(4), BIT(4)); 948 break; 949 case SND_SOC_DAPM_POST_PMD: 950 if (w->shift == 1 && test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) 951 clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask); 952 953 snd_soc_component_update_bits(component, 954 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(3), 0x00); 955 break; 956 } 957 958 return 0; 959 } 960 961 static int wcd937x_enable_req(struct snd_soc_dapm_widget *w, 962 struct snd_kcontrol *kcontrol, int event) 963 { 964 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 965 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 966 967 switch (event) { 968 case SND_SOC_DAPM_PRE_PMU: 969 snd_soc_component_update_bits(component, 970 WCD937X_DIGITAL_CDC_REQ_CTL, BIT(1), BIT(1)); 971 snd_soc_component_update_bits(component, 972 WCD937X_DIGITAL_CDC_REQ_CTL, BIT(0), 0x00); 973 snd_soc_component_update_bits(component, 974 WCD937X_ANA_TX_CH2, BIT(6), BIT(6)); 975 snd_soc_component_update_bits(component, 976 WCD937X_ANA_TX_CH3_HPF, BIT(6), BIT(6)); 977 snd_soc_component_update_bits(component, 978 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70); 979 snd_soc_component_update_bits(component, 980 WCD937X_ANA_TX_CH1, BIT(7), BIT(7)); 981 snd_soc_component_update_bits(component, 982 WCD937X_ANA_TX_CH2, BIT(6), 0x00); 983 snd_soc_component_update_bits(component, 984 WCD937X_ANA_TX_CH2, BIT(7), BIT(7)); 985 snd_soc_component_update_bits(component, 986 WCD937X_ANA_TX_CH3, BIT(7), BIT(7)); 987 break; 988 case SND_SOC_DAPM_POST_PMD: 989 snd_soc_component_update_bits(component, 990 WCD937X_ANA_TX_CH1, BIT(7), 0x00); 991 snd_soc_component_update_bits(component, 992 WCD937X_ANA_TX_CH2, BIT(7), 0x00); 993 snd_soc_component_update_bits(component, 994 WCD937X_ANA_TX_CH3, BIT(7), 0x00); 995 snd_soc_component_update_bits(component, 996 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(4), 0x00); 997 998 atomic_dec(&wcd937x->ana_clk_count); 999 if (atomic_read(&wcd937x->ana_clk_count) <= 0) { 1000 snd_soc_component_update_bits(component, 1001 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 1002 BIT(4), 0x00); 1003 atomic_set(&wcd937x->ana_clk_count, 0); 1004 } 1005 1006 snd_soc_component_update_bits(component, 1007 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 1008 BIT(7), 0x00); 1009 break; 1010 } 1011 1012 return 0; 1013 } 1014 1015 static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 1016 struct snd_kcontrol *kcontrol, 1017 int event) 1018 { 1019 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1020 u16 dmic_clk_reg; 1021 1022 switch (w->shift) { 1023 case 0: 1024 case 1: 1025 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL; 1026 break; 1027 case 2: 1028 case 3: 1029 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL; 1030 break; 1031 case 4: 1032 case 5: 1033 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL; 1034 break; 1035 default: 1036 dev_err(component->dev, "Invalid DMIC Selection\n"); 1037 return -EINVAL; 1038 } 1039 1040 switch (event) { 1041 case SND_SOC_DAPM_PRE_PMU: 1042 snd_soc_component_update_bits(component, 1043 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 1044 BIT(7), BIT(7)); 1045 snd_soc_component_update_bits(component, 1046 dmic_clk_reg, 0x07, BIT(1)); 1047 snd_soc_component_update_bits(component, 1048 dmic_clk_reg, BIT(3), BIT(3)); 1049 snd_soc_component_update_bits(component, 1050 dmic_clk_reg, 0x70, BIT(5)); 1051 break; 1052 } 1053 1054 return 0; 1055 } 1056 1057 static int wcd937x_micbias_control(struct snd_soc_component *component, 1058 int micb_num, int req, bool is_dapm) 1059 { 1060 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1061 int micb_index = micb_num - 1; 1062 u16 micb_reg; 1063 1064 if (micb_index < 0 || (micb_index > WCD937X_MAX_MICBIAS - 1)) { 1065 dev_err(component->dev, "Invalid micbias index, micb_ind:%d\n", micb_index); 1066 return -EINVAL; 1067 } 1068 switch (micb_num) { 1069 case MIC_BIAS_1: 1070 micb_reg = WCD937X_ANA_MICB1; 1071 break; 1072 case MIC_BIAS_2: 1073 micb_reg = WCD937X_ANA_MICB2; 1074 break; 1075 case MIC_BIAS_3: 1076 micb_reg = WCD937X_ANA_MICB3; 1077 break; 1078 default: 1079 dev_err(component->dev, "Invalid micbias number: %d\n", micb_num); 1080 return -EINVAL; 1081 } 1082 1083 mutex_lock(&wcd937x->micb_lock); 1084 switch (req) { 1085 case MICB_PULLUP_ENABLE: 1086 wcd937x->pullup_ref[micb_index]++; 1087 if (wcd937x->pullup_ref[micb_index] == 1 && 1088 wcd937x->micb_ref[micb_index] == 0) 1089 snd_soc_component_update_bits(component, micb_reg, 1090 0xc0, BIT(7)); 1091 break; 1092 case MICB_PULLUP_DISABLE: 1093 if (wcd937x->pullup_ref[micb_index] > 0) 1094 wcd937x->pullup_ref[micb_index]++; 1095 if (wcd937x->pullup_ref[micb_index] == 0 && 1096 wcd937x->micb_ref[micb_index] == 0) 1097 snd_soc_component_update_bits(component, micb_reg, 1098 0xc0, 0x00); 1099 break; 1100 case MICB_ENABLE: 1101 wcd937x->micb_ref[micb_index]++; 1102 atomic_inc(&wcd937x->ana_clk_count); 1103 if (wcd937x->micb_ref[micb_index] == 1) { 1104 snd_soc_component_update_bits(component, 1105 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 1106 0xf0, 0xf0); 1107 snd_soc_component_update_bits(component, 1108 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 1109 BIT(4), BIT(4)); 1110 snd_soc_component_update_bits(component, 1111 WCD937X_MICB1_TEST_CTL_2, 1112 BIT(0), BIT(0)); 1113 snd_soc_component_update_bits(component, 1114 WCD937X_MICB2_TEST_CTL_2, 1115 BIT(0), BIT(0)); 1116 snd_soc_component_update_bits(component, 1117 WCD937X_MICB3_TEST_CTL_2, 1118 BIT(0), BIT(0)); 1119 snd_soc_component_update_bits(component, 1120 micb_reg, 0xc0, BIT(6)); 1121 1122 if (micb_num == MIC_BIAS_2) 1123 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1124 WCD_EVENT_POST_MICBIAS_2_ON); 1125 1126 if (micb_num == MIC_BIAS_2 && is_dapm) 1127 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1128 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 1129 } 1130 break; 1131 case MICB_DISABLE: 1132 atomic_dec(&wcd937x->ana_clk_count); 1133 if (wcd937x->micb_ref[micb_index] > 0) 1134 wcd937x->micb_ref[micb_index]--; 1135 if (wcd937x->micb_ref[micb_index] == 0 && 1136 wcd937x->pullup_ref[micb_index] > 0) 1137 snd_soc_component_update_bits(component, micb_reg, 1138 0xc0, BIT(7)); 1139 else if (wcd937x->micb_ref[micb_index] == 0 && 1140 wcd937x->pullup_ref[micb_index] == 0) { 1141 if (micb_num == MIC_BIAS_2) 1142 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1143 WCD_EVENT_PRE_MICBIAS_2_OFF); 1144 1145 snd_soc_component_update_bits(component, micb_reg, 1146 0xc0, 0x00); 1147 if (micb_num == MIC_BIAS_2) 1148 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1149 WCD_EVENT_POST_MICBIAS_2_OFF); 1150 } 1151 1152 if (is_dapm && micb_num == MIC_BIAS_2) 1153 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1154 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 1155 if (atomic_read(&wcd937x->ana_clk_count) <= 0) { 1156 snd_soc_component_update_bits(component, 1157 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 1158 BIT(4), 0x00); 1159 atomic_set(&wcd937x->ana_clk_count, 0); 1160 } 1161 break; 1162 } 1163 mutex_unlock(&wcd937x->micb_lock); 1164 1165 return 0; 1166 } 1167 1168 static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1169 int event) 1170 { 1171 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1172 int micb_num; 1173 1174 if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1"))) 1175 micb_num = MIC_BIAS_1; 1176 else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2"))) 1177 micb_num = MIC_BIAS_2; 1178 else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3"))) 1179 micb_num = MIC_BIAS_3; 1180 else 1181 return -EINVAL; 1182 1183 switch (event) { 1184 case SND_SOC_DAPM_PRE_PMU: 1185 wcd937x_micbias_control(component, micb_num, 1186 MICB_ENABLE, true); 1187 break; 1188 case SND_SOC_DAPM_POST_PMU: 1189 usleep_range(1000, 1100); 1190 break; 1191 case SND_SOC_DAPM_POST_PMD: 1192 wcd937x_micbias_control(component, micb_num, 1193 MICB_DISABLE, true); 1194 break; 1195 } 1196 1197 return 0; 1198 } 1199 1200 static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1201 struct snd_kcontrol *kcontrol, 1202 int event) 1203 { 1204 return __wcd937x_codec_enable_micbias(w, event); 1205 } 1206 1207 static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1208 int event) 1209 { 1210 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1211 int micb_num; 1212 1213 if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1"))) 1214 micb_num = MIC_BIAS_1; 1215 else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2"))) 1216 micb_num = MIC_BIAS_2; 1217 else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3"))) 1218 micb_num = MIC_BIAS_3; 1219 else 1220 return -EINVAL; 1221 1222 switch (event) { 1223 case SND_SOC_DAPM_PRE_PMU: 1224 wcd937x_micbias_control(component, micb_num, MICB_PULLUP_ENABLE, true); 1225 break; 1226 case SND_SOC_DAPM_POST_PMU: 1227 usleep_range(1000, 1100); 1228 break; 1229 case SND_SOC_DAPM_POST_PMD: 1230 wcd937x_micbias_control(component, micb_num, MICB_PULLUP_DISABLE, true); 1231 break; 1232 } 1233 1234 return 0; 1235 } 1236 1237 static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1238 struct snd_kcontrol *kcontrol, 1239 int event) 1240 { 1241 return __wcd937x_codec_enable_micbias_pullup(w, event); 1242 } 1243 1244 static int wcd937x_connect_port(struct wcd937x_sdw_priv *wcd, u8 port_idx, u8 ch_id, bool enable) 1245 { 1246 struct sdw_port_config *port_config = &wcd->port_config[port_idx - 1]; 1247 struct wcd937x_sdw_ch_info *ch_info = &wcd->ch_info[ch_id]; 1248 u8 port_num = ch_info->port_num; 1249 u8 ch_mask = ch_info->ch_mask; 1250 1251 port_config->num = port_num; 1252 1253 if (enable) 1254 port_config->ch_mask |= ch_mask; 1255 else 1256 port_config->ch_mask &= ~ch_mask; 1257 1258 return 0; 1259 } 1260 1261 static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol, 1262 struct snd_ctl_elem_value *ucontrol) 1263 { 1264 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1265 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1266 1267 ucontrol->value.integer.value[0] = wcd937x->hph_mode; 1268 return 0; 1269 } 1270 1271 static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol, 1272 struct snd_ctl_elem_value *ucontrol) 1273 { 1274 struct snd_soc_component *component = 1275 snd_soc_kcontrol_component(kcontrol); 1276 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1277 u32 mode_val; 1278 1279 mode_val = ucontrol->value.enumerated.item[0]; 1280 1281 if (!mode_val) 1282 mode_val = CLS_AB; 1283 1284 if (mode_val == wcd937x->hph_mode) 1285 return 0; 1286 1287 switch (mode_val) { 1288 case CLS_H_NORMAL: 1289 case CLS_H_HIFI: 1290 case CLS_H_LP: 1291 case CLS_AB: 1292 case CLS_H_LOHIFI: 1293 case CLS_H_ULP: 1294 case CLS_AB_LP: 1295 case CLS_AB_HIFI: 1296 wcd937x->hph_mode = mode_val; 1297 return 1; 1298 } 1299 1300 dev_dbg(component->dev, "%s: Invalid HPH Mode\n", __func__); 1301 return -EINVAL; 1302 } 1303 1304 static int wcd937x_get_compander(struct snd_kcontrol *kcontrol, 1305 struct snd_ctl_elem_value *ucontrol) 1306 { 1307 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1308 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1309 struct soc_mixer_control *mc; 1310 bool hphr; 1311 1312 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1313 hphr = mc->shift; 1314 1315 ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable : 1316 wcd937x->comp1_enable; 1317 return 0; 1318 } 1319 1320 static int wcd937x_set_compander(struct snd_kcontrol *kcontrol, 1321 struct snd_ctl_elem_value *ucontrol) 1322 { 1323 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1324 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1325 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[AIF1_PB]; 1326 int value = ucontrol->value.integer.value[0]; 1327 struct soc_mixer_control *mc; 1328 int portidx; 1329 bool hphr; 1330 1331 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1332 hphr = mc->shift; 1333 1334 if (hphr) { 1335 if (value == wcd937x->comp2_enable) 1336 return 0; 1337 1338 wcd937x->comp2_enable = value; 1339 } else { 1340 if (value == wcd937x->comp1_enable) 1341 return 0; 1342 1343 wcd937x->comp1_enable = value; 1344 } 1345 1346 portidx = wcd->ch_info[mc->reg].port_num; 1347 1348 if (value) 1349 wcd937x_connect_port(wcd, portidx, mc->reg, true); 1350 else 1351 wcd937x_connect_port(wcd, portidx, mc->reg, false); 1352 1353 return 1; 1354 } 1355 1356 static int wcd937x_get_swr_port(struct snd_kcontrol *kcontrol, 1357 struct snd_ctl_elem_value *ucontrol) 1358 { 1359 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1360 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 1361 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(comp); 1362 struct wcd937x_sdw_priv *wcd; 1363 int dai_id = mixer->shift; 1364 int ch_idx = mixer->reg; 1365 int portidx; 1366 1367 wcd = wcd937x->sdw_priv[dai_id]; 1368 portidx = wcd->ch_info[ch_idx].port_num; 1369 1370 ucontrol->value.integer.value[0] = wcd->port_enable[portidx]; 1371 1372 return 0; 1373 } 1374 1375 static int wcd937x_set_swr_port(struct snd_kcontrol *kcontrol, 1376 struct snd_ctl_elem_value *ucontrol) 1377 { 1378 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1379 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 1380 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(comp); 1381 struct wcd937x_sdw_priv *wcd; 1382 int dai_id = mixer->shift; 1383 int ch_idx = mixer->reg; 1384 int portidx; 1385 bool enable; 1386 1387 wcd = wcd937x->sdw_priv[dai_id]; 1388 1389 portidx = wcd->ch_info[ch_idx].port_num; 1390 1391 enable = ucontrol->value.integer.value[0]; 1392 1393 if (enable == wcd->port_enable[portidx]) { 1394 wcd937x_connect_port(wcd, portidx, ch_idx, enable); 1395 return 0; 1396 } 1397 1398 wcd->port_enable[portidx] = enable; 1399 wcd937x_connect_port(wcd, portidx, ch_idx, enable); 1400 1401 return 1; 1402 } 1403 1404 static const char * const rx_hph_mode_mux_text[] = { 1405 "CLS_H_NORMAL", "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", 1406 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_AB_LP", "CLS_AB_HIFI", 1407 }; 1408 1409 static const struct soc_enum rx_hph_mode_mux_enum = 1410 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), rx_hph_mode_mux_text); 1411 1412 /* MBHC related */ 1413 static void wcd937x_mbhc_clk_setup(struct snd_soc_component *component, 1414 bool enable) 1415 { 1416 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_1, 1417 WCD937X_MBHC_CTL_RCO_EN_MASK, enable); 1418 } 1419 1420 static void wcd937x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 1421 bool enable) 1422 { 1423 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_ELECT, 1424 WCD937X_ANA_MBHC_BIAS_EN, enable); 1425 } 1426 1427 static void wcd937x_mbhc_program_btn_thr(struct snd_soc_component *component, 1428 int *btn_low, int *btn_high, 1429 int num_btn, bool is_micbias) 1430 { 1431 int i, vth; 1432 1433 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 1434 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 1435 __func__, num_btn); 1436 return; 1437 } 1438 1439 for (i = 0; i < num_btn; i++) { 1440 vth = ((btn_high[i] * 2) / 25) & 0x3F; 1441 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_BTN0 + i, 1442 WCD937X_MBHC_BTN_VTH_MASK, vth); 1443 } 1444 } 1445 1446 static bool wcd937x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 1447 { 1448 u8 val; 1449 1450 if (micb_num == MIC_BIAS_2) { 1451 val = snd_soc_component_read_field(component, 1452 WCD937X_ANA_MICB2, 1453 WCD937X_ANA_MICB2_ENABLE_MASK); 1454 if (val == WCD937X_MICB_ENABLE) 1455 return true; 1456 } 1457 return false; 1458 } 1459 1460 static void wcd937x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 1461 int pull_up_cur) 1462 { 1463 /* Default pull up current to 2uA */ 1464 if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA) 1465 pull_up_cur = HS_PULLUP_I_2P0_UA; 1466 1467 snd_soc_component_write_field(component, 1468 WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT, 1469 WCD937X_HSDET_PULLUP_C_MASK, pull_up_cur); 1470 } 1471 1472 static int wcd937x_mbhc_request_micbias(struct snd_soc_component *component, 1473 int micb_num, int req) 1474 { 1475 return wcd937x_micbias_control(component, micb_num, req, false); 1476 } 1477 1478 static void wcd937x_mbhc_micb_ramp_control(struct snd_soc_component *component, 1479 bool enable) 1480 { 1481 if (enable) { 1482 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1483 WCD937X_RAMP_SHIFT_CTRL_MASK, 0x0C); 1484 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1485 WCD937X_RAMP_EN_MASK, 1); 1486 } else { 1487 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1488 WCD937X_RAMP_EN_MASK, 0); 1489 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1490 WCD937X_RAMP_SHIFT_CTRL_MASK, 0); 1491 } 1492 } 1493 1494 static int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 1495 int req_volt, int micb_num) 1496 { 1497 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1498 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0; 1499 1500 switch (micb_num) { 1501 case MIC_BIAS_1: 1502 micb_reg = WCD937X_ANA_MICB1; 1503 break; 1504 case MIC_BIAS_2: 1505 micb_reg = WCD937X_ANA_MICB2; 1506 break; 1507 case MIC_BIAS_3: 1508 micb_reg = WCD937X_ANA_MICB3; 1509 break; 1510 default: 1511 return -EINVAL; 1512 } 1513 mutex_lock(&wcd937x->micb_lock); 1514 /* 1515 * If requested micbias voltage is same as current micbias 1516 * voltage, then just return. Otherwise, adjust voltage as 1517 * per requested value. If micbias is already enabled, then 1518 * to avoid slow micbias ramp-up or down enable pull-up 1519 * momentarily, change the micbias value and then re-enable 1520 * micbias. 1521 */ 1522 micb_en = snd_soc_component_read_field(component, micb_reg, 1523 WCD937X_MICB_EN_MASK); 1524 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 1525 WCD937X_MICB_VOUT_MASK); 1526 1527 req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt); 1528 if (req_vout_ctl < 0) { 1529 ret = -EINVAL; 1530 goto exit; 1531 } 1532 1533 if (cur_vout_ctl == req_vout_ctl) { 1534 ret = 0; 1535 goto exit; 1536 } 1537 1538 if (micb_en == WCD937X_MICB_ENABLE) 1539 snd_soc_component_write_field(component, micb_reg, 1540 WCD937X_MICB_EN_MASK, 1541 WCD937X_MICB_PULL_UP); 1542 1543 snd_soc_component_write_field(component, micb_reg, 1544 WCD937X_MICB_VOUT_MASK, 1545 req_vout_ctl); 1546 1547 if (micb_en == WCD937X_MICB_ENABLE) { 1548 snd_soc_component_write_field(component, micb_reg, 1549 WCD937X_MICB_EN_MASK, 1550 WCD937X_MICB_ENABLE); 1551 /* 1552 * Add 2ms delay as per HW requirement after enabling 1553 * micbias 1554 */ 1555 usleep_range(2000, 2100); 1556 } 1557 exit: 1558 mutex_unlock(&wcd937x->micb_lock); 1559 return ret; 1560 } 1561 1562 static int wcd937x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 1563 int micb_num, bool req_en) 1564 { 1565 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1566 int micb_mv; 1567 1568 if (micb_num != MIC_BIAS_2) 1569 return -EINVAL; 1570 /* 1571 * If device tree micbias level is already above the minimum 1572 * voltage needed to detect threshold microphone, then do 1573 * not change the micbias, just return. 1574 */ 1575 if (wcd937x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV) 1576 return 0; 1577 1578 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd937x->micb2_mv; 1579 1580 return wcd937x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 1581 } 1582 1583 static void wcd937x_mbhc_get_result_params(struct snd_soc_component *component, 1584 s16 *d1_a, u16 noff, 1585 int32_t *zdet) 1586 { 1587 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1588 int i; 1589 int val, val1; 1590 s16 c1; 1591 s32 x1, d1; 1592 s32 denom; 1593 static const int minCode_param[] = { 1594 3277, 1639, 820, 410, 205, 103, 52, 26 1595 }; 1596 1597 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MBHC_ZDET, 0x20, 0x20); 1598 for (i = 0; i < WCD937X_ZDET_NUM_MEASUREMENTS; i++) { 1599 regmap_read(wcd937x->regmap, WCD937X_ANA_MBHC_RESULT_2, &val); 1600 if (val & 0x80) 1601 break; 1602 } 1603 val = val << 0x8; 1604 regmap_read(wcd937x->regmap, WCD937X_ANA_MBHC_RESULT_1, &val1); 1605 val |= val1; 1606 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MBHC_ZDET, 0x20, 0x00); 1607 x1 = WCD937X_MBHC_GET_X1(val); 1608 c1 = WCD937X_MBHC_GET_C1(val); 1609 /* If ramp is not complete, give additional 5ms */ 1610 if (c1 < 2 && x1) 1611 usleep_range(5000, 5050); 1612 1613 if (!c1 || !x1) { 1614 dev_err(component->dev, "Impedance detect ramp error, c1=%d, x1=0x%x\n", 1615 c1, x1); 1616 goto ramp_down; 1617 } 1618 d1 = d1_a[c1]; 1619 denom = (x1 * d1) - (1 << (14 - noff)); 1620 if (denom > 0) 1621 *zdet = (WCD937X_MBHC_ZDET_CONST * 1000) / denom; 1622 else if (x1 < minCode_param[noff]) 1623 *zdet = WCD937X_ZDET_FLOATING_IMPEDANCE; 1624 1625 dev_err(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d (milliohm)\n", 1626 __func__, d1, c1, x1, *zdet); 1627 ramp_down: 1628 i = 0; 1629 while (x1) { 1630 regmap_read(wcd937x->regmap, 1631 WCD937X_ANA_MBHC_RESULT_1, &val); 1632 regmap_read(wcd937x->regmap, 1633 WCD937X_ANA_MBHC_RESULT_2, &val1); 1634 val = val << 0x08; 1635 val |= val1; 1636 x1 = WCD937X_MBHC_GET_X1(val); 1637 i++; 1638 if (i == WCD937X_ZDET_NUM_MEASUREMENTS) 1639 break; 1640 } 1641 } 1642 1643 static void wcd937x_mbhc_zdet_ramp(struct snd_soc_component *component, 1644 struct wcd937x_mbhc_zdet_param *zdet_param, 1645 s32 *zl, s32 *zr, s16 *d1_a) 1646 { 1647 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1648 s32 zdet = 0; 1649 1650 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, 1651 WCD937X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 1652 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN5, 1653 WCD937X_VTH_MASK, zdet_param->btn5); 1654 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN6, 1655 WCD937X_VTH_MASK, zdet_param->btn6); 1656 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN7, 1657 WCD937X_VTH_MASK, zdet_param->btn7); 1658 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, 1659 WCD937X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 1660 snd_soc_component_update_bits(component, WCD937X_MBHC_NEW_ZDET_RAMP_CTL, 1661 0x0F, zdet_param->nshift); 1662 1663 if (!zl) 1664 goto z_right; 1665 /* Start impedance measurement for HPH_L */ 1666 regmap_update_bits(wcd937x->regmap, 1667 WCD937X_ANA_MBHC_ZDET, 0x80, 0x80); 1668 wcd937x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 1669 regmap_update_bits(wcd937x->regmap, 1670 WCD937X_ANA_MBHC_ZDET, 0x80, 0x00); 1671 1672 *zl = zdet; 1673 1674 z_right: 1675 if (!zr) 1676 return; 1677 /* Start impedance measurement for HPH_R */ 1678 regmap_update_bits(wcd937x->regmap, 1679 WCD937X_ANA_MBHC_ZDET, 0x40, 0x40); 1680 wcd937x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 1681 regmap_update_bits(wcd937x->regmap, 1682 WCD937X_ANA_MBHC_ZDET, 0x40, 0x00); 1683 1684 *zr = zdet; 1685 } 1686 1687 static void wcd937x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 1688 s32 *z_val, int flag_l_r) 1689 { 1690 s16 q1; 1691 int q1_cal; 1692 1693 if (*z_val < (WCD937X_ZDET_VAL_400 / 1000)) 1694 q1 = snd_soc_component_read(component, 1695 WCD937X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r)); 1696 else 1697 q1 = snd_soc_component_read(component, 1698 WCD937X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r)); 1699 if (q1 & 0x80) 1700 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 1701 else 1702 q1_cal = (10000 + (q1 * 25)); 1703 if (q1_cal > 0) 1704 *z_val = ((*z_val) * 10000) / q1_cal; 1705 } 1706 1707 static void wcd937x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 1708 u32 *zl, u32 *zr) 1709 { 1710 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1711 s16 reg0, reg1, reg2, reg3, reg4; 1712 s32 z1l, z1r, z1ls; 1713 int zMono, z_diff1, z_diff2; 1714 bool is_fsm_disable = false; 1715 struct wcd937x_mbhc_zdet_param zdet_param[] = { 1716 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 1717 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 1718 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 1719 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 1720 }; 1721 struct wcd937x_mbhc_zdet_param *zdet_param_ptr = NULL; 1722 s16 d1_a[][4] = { 1723 {0, 30, 90, 30}, 1724 {0, 30, 30, 5}, 1725 {0, 30, 30, 5}, 1726 {0, 30, 30, 5}, 1727 }; 1728 s16 *d1 = NULL; 1729 1730 reg0 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN5); 1731 reg1 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN6); 1732 reg2 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN7); 1733 reg3 = snd_soc_component_read(component, WCD937X_MBHC_CTL_CLK); 1734 reg4 = snd_soc_component_read(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL); 1735 1736 if (snd_soc_component_read(component, WCD937X_ANA_MBHC_ELECT) & 0x80) { 1737 is_fsm_disable = true; 1738 regmap_update_bits(wcd937x->regmap, 1739 WCD937X_ANA_MBHC_ELECT, 0x80, 0x00); 1740 } 1741 1742 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 1743 if (wcd937x->mbhc_cfg.hphl_swh) 1744 regmap_update_bits(wcd937x->regmap, 1745 WCD937X_ANA_MBHC_MECH, 0x80, 0x00); 1746 1747 /* Turn off 100k pull down on HPHL */ 1748 regmap_update_bits(wcd937x->regmap, 1749 WCD937X_ANA_MBHC_MECH, 0x01, 0x00); 1750 1751 /* Disable surge protection before impedance detection. 1752 * This is done to give correct value for high impedance. 1753 */ 1754 regmap_update_bits(wcd937x->regmap, 1755 WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00); 1756 /* 1ms delay needed after disable surge protection */ 1757 usleep_range(1000, 1010); 1758 1759 /* First get impedance on Left */ 1760 d1 = d1_a[1]; 1761 zdet_param_ptr = &zdet_param[1]; 1762 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1l, NULL, d1); 1763 1764 if (!WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z1l)) 1765 goto left_ch_impedance; 1766 1767 /* Second ramp for left ch */ 1768 if (z1l < WCD937X_ZDET_VAL_32) { 1769 zdet_param_ptr = &zdet_param[0]; 1770 d1 = d1_a[0]; 1771 } else if ((z1l > WCD937X_ZDET_VAL_400) && 1772 (z1l <= WCD937X_ZDET_VAL_1200)) { 1773 zdet_param_ptr = &zdet_param[2]; 1774 d1 = d1_a[2]; 1775 } else if (z1l > WCD937X_ZDET_VAL_1200) { 1776 zdet_param_ptr = &zdet_param[3]; 1777 d1 = d1_a[3]; 1778 } 1779 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1l, NULL, d1); 1780 1781 left_ch_impedance: 1782 if (z1l == WCD937X_ZDET_FLOATING_IMPEDANCE || 1783 z1l > WCD937X_ZDET_VAL_100K) { 1784 *zl = WCD937X_ZDET_FLOATING_IMPEDANCE; 1785 zdet_param_ptr = &zdet_param[1]; 1786 d1 = d1_a[1]; 1787 } else { 1788 *zl = z1l / 1000; 1789 wcd937x_wcd_mbhc_qfuse_cal(component, zl, 0); 1790 } 1791 1792 /* Start of right impedance ramp and calculation */ 1793 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1r, d1); 1794 if (WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z1r)) { 1795 if ((z1r > WCD937X_ZDET_VAL_1200 && 1796 zdet_param_ptr->noff == 0x6) || 1797 ((*zl) != WCD937X_ZDET_FLOATING_IMPEDANCE)) 1798 goto right_ch_impedance; 1799 /* Second ramp for right ch */ 1800 if (z1r < WCD937X_ZDET_VAL_32) { 1801 zdet_param_ptr = &zdet_param[0]; 1802 d1 = d1_a[0]; 1803 } else if ((z1r > WCD937X_ZDET_VAL_400) && 1804 (z1r <= WCD937X_ZDET_VAL_1200)) { 1805 zdet_param_ptr = &zdet_param[2]; 1806 d1 = d1_a[2]; 1807 } else if (z1r > WCD937X_ZDET_VAL_1200) { 1808 zdet_param_ptr = &zdet_param[3]; 1809 d1 = d1_a[3]; 1810 } 1811 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1r, d1); 1812 } 1813 right_ch_impedance: 1814 if (z1r == WCD937X_ZDET_FLOATING_IMPEDANCE || 1815 z1r > WCD937X_ZDET_VAL_100K) { 1816 *zr = WCD937X_ZDET_FLOATING_IMPEDANCE; 1817 } else { 1818 *zr = z1r / 1000; 1819 wcd937x_wcd_mbhc_qfuse_cal(component, zr, 1); 1820 } 1821 1822 /* Mono/stereo detection */ 1823 if ((*zl == WCD937X_ZDET_FLOATING_IMPEDANCE) && 1824 (*zr == WCD937X_ZDET_FLOATING_IMPEDANCE)) { 1825 dev_err(component->dev, 1826 "%s: plug type is invalid or extension cable\n", 1827 __func__); 1828 goto zdet_complete; 1829 } 1830 if ((*zl == WCD937X_ZDET_FLOATING_IMPEDANCE) || 1831 (*zr == WCD937X_ZDET_FLOATING_IMPEDANCE) || 1832 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 1833 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 1834 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_MONO); 1835 goto zdet_complete; 1836 } 1837 snd_soc_component_write_field(component, WCD937X_HPH_R_ATEST, 1838 WCD937X_HPHPA_GND_OVR_MASK, 1); 1839 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1840 WCD937X_HPHPA_GND_R_MASK, 1); 1841 if (*zl < (WCD937X_ZDET_VAL_32 / 1000)) 1842 wcd937x_mbhc_zdet_ramp(component, &zdet_param[0], &z1ls, NULL, d1); 1843 else 1844 wcd937x_mbhc_zdet_ramp(component, &zdet_param[1], &z1ls, NULL, d1); 1845 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1846 WCD937X_HPHPA_GND_R_MASK, 0); 1847 snd_soc_component_write_field(component, WCD937X_HPH_R_ATEST, 1848 WCD937X_HPHPA_GND_OVR_MASK, 0); 1849 z1ls /= 1000; 1850 wcd937x_wcd_mbhc_qfuse_cal(component, &z1ls, 0); 1851 /* Parallel of left Z and 9 ohm pull down resistor */ 1852 zMono = ((*zl) * 9) / ((*zl) + 9); 1853 z_diff1 = (z1ls > zMono) ? (z1ls - zMono) : (zMono - z1ls); 1854 z_diff2 = ((*zl) > z1ls) ? ((*zl) - z1ls) : (z1ls - (*zl)); 1855 if ((z_diff1 * (*zl + z1ls)) > (z_diff2 * (z1ls + zMono))) 1856 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_STEREO); 1857 else 1858 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_MONO); 1859 1860 /* Enable surge protection again after impedance detection */ 1861 regmap_update_bits(wcd937x->regmap, 1862 WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 1863 zdet_complete: 1864 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN5, reg0); 1865 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN6, reg1); 1866 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN7, reg2); 1867 /* Turn on 100k pull down on HPHL */ 1868 regmap_update_bits(wcd937x->regmap, 1869 WCD937X_ANA_MBHC_MECH, 0x01, 0x01); 1870 1871 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 1872 if (wcd937x->mbhc_cfg.hphl_swh) 1873 regmap_update_bits(wcd937x->regmap, 1874 WCD937X_ANA_MBHC_MECH, 0x80, 0x80); 1875 1876 snd_soc_component_write(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, reg4); 1877 snd_soc_component_write(component, WCD937X_MBHC_CTL_CLK, reg3); 1878 if (is_fsm_disable) 1879 regmap_update_bits(wcd937x->regmap, 1880 WCD937X_ANA_MBHC_ELECT, 0x80, 0x80); 1881 } 1882 1883 static void wcd937x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 1884 bool enable) 1885 { 1886 if (enable) { 1887 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1888 WCD937X_MBHC_HSG_PULLUP_COMP_EN, 1); 1889 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1890 WCD937X_MBHC_GND_DET_EN_MASK, 1); 1891 } else { 1892 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1893 WCD937X_MBHC_GND_DET_EN_MASK, 0); 1894 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1895 WCD937X_MBHC_HSG_PULLUP_COMP_EN, 0); 1896 } 1897 } 1898 1899 static void wcd937x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 1900 bool enable) 1901 { 1902 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1903 WCD937X_HPHPA_GND_R_MASK, enable); 1904 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1905 WCD937X_HPHPA_GND_L_MASK, enable); 1906 } 1907 1908 static void wcd937x_mbhc_moisture_config(struct snd_soc_component *component) 1909 { 1910 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1911 1912 if (wcd937x->mbhc_cfg.moist_rref == R_OFF) { 1913 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1914 WCD937X_M_RTH_CTL_MASK, R_OFF); 1915 return; 1916 } 1917 1918 /* Do not enable moisture detection if jack type is NC */ 1919 if (!wcd937x->mbhc_cfg.hphl_swh) { 1920 dev_err(component->dev, "%s: disable moisture detection for NC\n", 1921 __func__); 1922 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1923 WCD937X_M_RTH_CTL_MASK, R_OFF); 1924 return; 1925 } 1926 1927 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1928 WCD937X_M_RTH_CTL_MASK, wcd937x->mbhc_cfg.moist_rref); 1929 } 1930 1931 static void wcd937x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable) 1932 { 1933 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1934 1935 if (enable) 1936 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1937 WCD937X_M_RTH_CTL_MASK, wcd937x->mbhc_cfg.moist_rref); 1938 else 1939 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1940 WCD937X_M_RTH_CTL_MASK, R_OFF); 1941 } 1942 1943 static bool wcd937x_mbhc_get_moisture_status(struct snd_soc_component *component) 1944 { 1945 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1946 bool ret = false; 1947 1948 if (wcd937x->mbhc_cfg.moist_rref == R_OFF) { 1949 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1950 WCD937X_M_RTH_CTL_MASK, R_OFF); 1951 goto done; 1952 } 1953 1954 /* Do not enable moisture detection if jack type is NC */ 1955 if (!wcd937x->mbhc_cfg.hphl_swh) { 1956 dev_err(component->dev, "%s: disable moisture detection for NC\n", 1957 __func__); 1958 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1959 WCD937X_M_RTH_CTL_MASK, R_OFF); 1960 goto done; 1961 } 1962 1963 /* 1964 * If moisture_en is already enabled, then skip to plug type 1965 * detection. 1966 */ 1967 if (snd_soc_component_read_field(component, WCD937X_MBHC_NEW_CTL_2, WCD937X_M_RTH_CTL_MASK)) 1968 goto done; 1969 1970 wcd937x_mbhc_moisture_detect_en(component, true); 1971 /* Read moisture comparator status */ 1972 ret = ((snd_soc_component_read(component, WCD937X_MBHC_NEW_FSM_STATUS) 1973 & 0x20) ? 0 : 1); 1974 done: 1975 return ret; 1976 } 1977 1978 static void wcd937x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component, 1979 bool enable) 1980 { 1981 snd_soc_component_write_field(component, 1982 WCD937X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 1983 WCD937X_MOISTURE_EN_POLLING_MASK, enable); 1984 } 1985 1986 static const struct wcd_mbhc_cb mbhc_cb = { 1987 .clk_setup = wcd937x_mbhc_clk_setup, 1988 .mbhc_bias = wcd937x_mbhc_mbhc_bias_control, 1989 .set_btn_thr = wcd937x_mbhc_program_btn_thr, 1990 .micbias_enable_status = wcd937x_mbhc_micb_en_status, 1991 .hph_pull_up_control_v2 = wcd937x_mbhc_hph_l_pull_up_control, 1992 .mbhc_micbias_control = wcd937x_mbhc_request_micbias, 1993 .mbhc_micb_ramp_control = wcd937x_mbhc_micb_ramp_control, 1994 .mbhc_micb_ctrl_thr_mic = wcd937x_mbhc_micb_ctrl_threshold_mic, 1995 .compute_impedance = wcd937x_wcd_mbhc_calc_impedance, 1996 .mbhc_gnd_det_ctrl = wcd937x_mbhc_gnd_det_ctrl, 1997 .hph_pull_down_ctrl = wcd937x_mbhc_hph_pull_down_ctrl, 1998 .mbhc_moisture_config = wcd937x_mbhc_moisture_config, 1999 .mbhc_get_moisture_status = wcd937x_mbhc_get_moisture_status, 2000 .mbhc_moisture_polling_ctrl = wcd937x_mbhc_moisture_polling_ctrl, 2001 .mbhc_moisture_detect_en = wcd937x_mbhc_moisture_detect_en, 2002 }; 2003 2004 static int wcd937x_get_hph_type(struct snd_kcontrol *kcontrol, 2005 struct snd_ctl_elem_value *ucontrol) 2006 { 2007 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2008 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2009 2010 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd937x->wcd_mbhc); 2011 2012 return 0; 2013 } 2014 2015 static int wcd937x_hph_impedance_get(struct snd_kcontrol *kcontrol, 2016 struct snd_ctl_elem_value *ucontrol) 2017 { 2018 u32 zl, zr; 2019 bool hphr; 2020 struct soc_mixer_control *mc; 2021 struct snd_soc_component *component = 2022 snd_soc_kcontrol_component(kcontrol); 2023 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2024 2025 mc = (struct soc_mixer_control *)(kcontrol->private_value); 2026 hphr = mc->shift; 2027 wcd_mbhc_get_impedance(wcd937x->wcd_mbhc, &zl, &zr); 2028 ucontrol->value.integer.value[0] = hphr ? zr : zl; 2029 2030 return 0; 2031 } 2032 2033 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 2034 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0, 2035 wcd937x_get_hph_type, NULL), 2036 }; 2037 2038 static const struct snd_kcontrol_new impedance_detect_controls[] = { 2039 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0, 2040 wcd937x_hph_impedance_get, NULL), 2041 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0, 2042 wcd937x_hph_impedance_get, NULL), 2043 }; 2044 2045 static int wcd937x_mbhc_init(struct snd_soc_component *component) 2046 { 2047 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2048 struct wcd_mbhc_intr *intr_ids = &wcd937x->intr_ids; 2049 2050 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2051 WCD937X_IRQ_MBHC_SW_DET); 2052 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2053 WCD937X_IRQ_MBHC_BUTTON_PRESS_DET); 2054 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2055 WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET); 2056 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2057 WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 2058 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2059 WCD937X_IRQ_MBHC_ELECT_INS_REM_DET); 2060 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd937x->irq_chip, 2061 WCD937X_IRQ_HPHL_OCP_INT); 2062 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd937x->irq_chip, 2063 WCD937X_IRQ_HPHR_OCP_INT); 2064 2065 wcd937x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 2066 if (IS_ERR(wcd937x->wcd_mbhc)) 2067 return PTR_ERR(wcd937x->wcd_mbhc); 2068 2069 snd_soc_add_component_controls(component, impedance_detect_controls, 2070 ARRAY_SIZE(impedance_detect_controls)); 2071 snd_soc_add_component_controls(component, hph_type_detect_controls, 2072 ARRAY_SIZE(hph_type_detect_controls)); 2073 2074 return 0; 2075 } 2076 2077 static void wcd937x_mbhc_deinit(struct snd_soc_component *component) 2078 { 2079 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2080 2081 wcd_mbhc_deinit(wcd937x->wcd_mbhc); 2082 } 2083 2084 /* END MBHC */ 2085 2086 static const struct snd_kcontrol_new wcd937x_snd_controls[] = { 2087 SOC_SINGLE_TLV("EAR_PA Volume", WCD937X_ANA_EAR_COMPANDER_CTL, 2088 2, 0x10, 0, ear_pa_gain), 2089 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 2090 wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put), 2091 2092 SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0, 2093 wcd937x_get_compander, wcd937x_set_compander), 2094 SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0, 2095 wcd937x_get_compander, wcd937x_set_compander), 2096 2097 SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain), 2098 SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain), 2099 SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0, analog_gain), 2100 SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0, analog_gain), 2101 SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0, analog_gain), 2102 2103 SOC_SINGLE_EXT("HPHL Switch", WCD937X_HPH_L, 0, 1, 0, 2104 wcd937x_get_swr_port, wcd937x_set_swr_port), 2105 SOC_SINGLE_EXT("HPHR Switch", WCD937X_HPH_R, 0, 1, 0, 2106 wcd937x_get_swr_port, wcd937x_set_swr_port), 2107 2108 SOC_SINGLE_EXT("ADC1 Switch", WCD937X_ADC1, 1, 1, 0, 2109 wcd937x_get_swr_port, wcd937x_set_swr_port), 2110 SOC_SINGLE_EXT("ADC2 Switch", WCD937X_ADC2, 1, 1, 0, 2111 wcd937x_get_swr_port, wcd937x_set_swr_port), 2112 SOC_SINGLE_EXT("ADC3 Switch", WCD937X_ADC3, 1, 1, 0, 2113 wcd937x_get_swr_port, wcd937x_set_swr_port), 2114 SOC_SINGLE_EXT("DMIC0 Switch", WCD937X_DMIC0, 1, 1, 0, 2115 wcd937x_get_swr_port, wcd937x_set_swr_port), 2116 SOC_SINGLE_EXT("DMIC1 Switch", WCD937X_DMIC1, 1, 1, 0, 2117 wcd937x_get_swr_port, wcd937x_set_swr_port), 2118 SOC_SINGLE_EXT("MBHC Switch", WCD937X_MBHC, 1, 1, 0, 2119 wcd937x_get_swr_port, wcd937x_set_swr_port), 2120 SOC_SINGLE_EXT("DMIC2 Switch", WCD937X_DMIC2, 1, 1, 0, 2121 wcd937x_get_swr_port, wcd937x_set_swr_port), 2122 SOC_SINGLE_EXT("DMIC3 Switch", WCD937X_DMIC3, 1, 1, 0, 2123 wcd937x_get_swr_port, wcd937x_set_swr_port), 2124 SOC_SINGLE_EXT("DMIC4 Switch", WCD937X_DMIC4, 1, 1, 0, 2125 wcd937x_get_swr_port, wcd937x_set_swr_port), 2126 SOC_SINGLE_EXT("DMIC5 Switch", WCD937X_DMIC5, 1, 1, 0, 2127 wcd937x_get_swr_port, wcd937x_set_swr_port), 2128 }; 2129 2130 static const struct snd_kcontrol_new adc1_switch[] = { 2131 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2132 }; 2133 2134 static const struct snd_kcontrol_new adc2_switch[] = { 2135 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2136 }; 2137 2138 static const struct snd_kcontrol_new adc3_switch[] = { 2139 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2140 }; 2141 2142 static const struct snd_kcontrol_new dmic1_switch[] = { 2143 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2144 }; 2145 2146 static const struct snd_kcontrol_new dmic2_switch[] = { 2147 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2148 }; 2149 2150 static const struct snd_kcontrol_new dmic3_switch[] = { 2151 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2152 }; 2153 2154 static const struct snd_kcontrol_new dmic4_switch[] = { 2155 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2156 }; 2157 2158 static const struct snd_kcontrol_new dmic5_switch[] = { 2159 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2160 }; 2161 2162 static const struct snd_kcontrol_new dmic6_switch[] = { 2163 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2164 }; 2165 2166 static const struct snd_kcontrol_new ear_rdac_switch[] = { 2167 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2168 }; 2169 2170 static const struct snd_kcontrol_new aux_rdac_switch[] = { 2171 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2172 }; 2173 2174 static const struct snd_kcontrol_new hphl_rdac_switch[] = { 2175 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2176 }; 2177 2178 static const struct snd_kcontrol_new hphr_rdac_switch[] = { 2179 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2180 }; 2181 2182 static const char * const adc2_mux_text[] = { 2183 "INP2", "INP3" 2184 }; 2185 2186 static const char * const rdac3_mux_text[] = { 2187 "RX1", "RX3" 2188 }; 2189 2190 static const struct soc_enum adc2_enum = 2191 SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7, 2192 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 2193 2194 static const struct soc_enum rdac3_enum = 2195 SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0, 2196 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text); 2197 2198 static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum); 2199 2200 static const struct snd_kcontrol_new rx_rdac3_mux = SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum); 2201 2202 static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = { 2203 /* Input widgets */ 2204 SND_SOC_DAPM_INPUT("AMIC1"), 2205 SND_SOC_DAPM_INPUT("AMIC2"), 2206 SND_SOC_DAPM_INPUT("AMIC3"), 2207 SND_SOC_DAPM_INPUT("IN1_HPHL"), 2208 SND_SOC_DAPM_INPUT("IN2_HPHR"), 2209 SND_SOC_DAPM_INPUT("IN3_AUX"), 2210 2211 /* TX widgets */ 2212 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0, 2213 wcd937x_codec_enable_adc, 2214 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2215 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0, 2216 wcd937x_codec_enable_adc, 2217 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2218 2219 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, 2220 NULL, 0, wcd937x_enable_req, 2221 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2222 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0, 2223 NULL, 0, wcd937x_enable_req, 2224 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2225 2226 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 2227 2228 /* TX mixers */ 2229 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, 2230 adc1_switch, ARRAY_SIZE(adc1_switch), 2231 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2232 SND_SOC_DAPM_POST_PMD), 2233 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 1, 0, 2234 adc2_switch, ARRAY_SIZE(adc2_switch), 2235 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2236 SND_SOC_DAPM_POST_PMD), 2237 2238 /* MIC_BIAS widgets */ 2239 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0, 2240 wcd937x_codec_enable_micbias, 2241 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2242 SND_SOC_DAPM_POST_PMD), 2243 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0, 2244 wcd937x_codec_enable_micbias, 2245 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2246 SND_SOC_DAPM_POST_PMD), 2247 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0, 2248 wcd937x_codec_enable_micbias, 2249 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2250 SND_SOC_DAPM_POST_PMD), 2251 2252 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, 2253 wcd937x_codec_enable_vdd_buck, 2254 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2255 2256 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0), 2257 2258 /* RX widgets */ 2259 SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0, 2260 wcd937x_codec_enable_ear_pa, 2261 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2262 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2263 SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0, 2264 wcd937x_codec_enable_aux_pa, 2265 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2266 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2267 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0, 2268 wcd937x_codec_enable_hphl_pa, 2269 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2270 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2271 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0, 2272 wcd937x_codec_enable_hphr_pa, 2273 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2274 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2275 2276 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0, 2277 wcd937x_codec_hphl_dac_event, 2278 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2279 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2280 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0, 2281 wcd937x_codec_hphr_dac_event, 2282 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2283 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2284 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0, 2285 wcd937x_codec_ear_dac_event, 2286 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2287 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2288 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0, 2289 wcd937x_codec_aux_dac_event, 2290 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2291 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2292 2293 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux), 2294 2295 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, 2296 wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU | 2297 SND_SOC_DAPM_POST_PMD), 2298 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, 2299 wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU | 2300 SND_SOC_DAPM_POST_PMD), 2301 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, 2302 wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU | 2303 SND_SOC_DAPM_POST_PMD), 2304 2305 /* RX mixer widgets*/ 2306 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0, 2307 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)), 2308 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0, 2309 aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)), 2310 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0, 2311 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)), 2312 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0, 2313 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)), 2314 2315 /* TX output widgets */ 2316 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"), 2317 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"), 2318 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"), 2319 SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"), 2320 2321 /* RX output widgets */ 2322 SND_SOC_DAPM_OUTPUT("EAR"), 2323 SND_SOC_DAPM_OUTPUT("AUX"), 2324 SND_SOC_DAPM_OUTPUT("HPHL"), 2325 SND_SOC_DAPM_OUTPUT("HPHR"), 2326 2327 /* MIC_BIAS pull up widgets */ 2328 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0, 2329 wcd937x_codec_enable_micbias_pullup, 2330 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2331 SND_SOC_DAPM_POST_PMD), 2332 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0, 2333 wcd937x_codec_enable_micbias_pullup, 2334 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2335 SND_SOC_DAPM_POST_PMD), 2336 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0, 2337 wcd937x_codec_enable_micbias_pullup, 2338 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2339 SND_SOC_DAPM_POST_PMD), 2340 }; 2341 2342 static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = { 2343 /* Input widgets */ 2344 SND_SOC_DAPM_INPUT("AMIC4"), 2345 2346 /* TX widgets */ 2347 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0, 2348 wcd937x_codec_enable_adc, 2349 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2350 2351 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0, 2352 NULL, 0, wcd937x_enable_req, 2353 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2354 2355 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 2356 wcd937x_codec_enable_dmic, 2357 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2358 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0, 2359 wcd937x_codec_enable_dmic, 2360 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2361 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0, 2362 wcd937x_codec_enable_dmic, 2363 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2364 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0, 2365 wcd937x_codec_enable_dmic, 2366 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2367 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0, 2368 wcd937x_codec_enable_dmic, 2369 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2370 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0, 2371 wcd937x_codec_enable_dmic, 2372 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2373 2374 /* TX mixer widgets */ 2375 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 2376 0, dmic1_switch, ARRAY_SIZE(dmic1_switch), 2377 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2378 SND_SOC_DAPM_POST_PMD), 2379 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 1, 2380 0, dmic2_switch, ARRAY_SIZE(dmic2_switch), 2381 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2382 SND_SOC_DAPM_POST_PMD), 2383 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 2, 2384 0, dmic3_switch, ARRAY_SIZE(dmic3_switch), 2385 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2386 SND_SOC_DAPM_POST_PMD), 2387 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 3, 2388 0, dmic4_switch, ARRAY_SIZE(dmic4_switch), 2389 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2390 SND_SOC_DAPM_POST_PMD), 2391 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 4, 2392 0, dmic5_switch, ARRAY_SIZE(dmic5_switch), 2393 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2394 SND_SOC_DAPM_POST_PMD), 2395 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 5, 2396 0, dmic6_switch, ARRAY_SIZE(dmic6_switch), 2397 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2398 SND_SOC_DAPM_POST_PMD), 2399 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 2, 0, adc3_switch, 2400 ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl, 2401 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2402 2403 /* Output widgets */ 2404 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"), 2405 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"), 2406 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"), 2407 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"), 2408 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"), 2409 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"), 2410 }; 2411 2412 static const struct snd_soc_dapm_route wcd937x_audio_map[] = { 2413 { "ADC1_OUTPUT", NULL, "ADC1_MIXER" }, 2414 { "ADC1_MIXER", "Switch", "ADC1 REQ" }, 2415 { "ADC1 REQ", NULL, "ADC1" }, 2416 { "ADC1", NULL, "AMIC1" }, 2417 2418 { "ADC2_OUTPUT", NULL, "ADC2_MIXER" }, 2419 { "ADC2_MIXER", "Switch", "ADC2 REQ" }, 2420 { "ADC2 REQ", NULL, "ADC2" }, 2421 { "ADC2", NULL, "ADC2 MUX" }, 2422 { "ADC2 MUX", "INP3", "AMIC3" }, 2423 { "ADC2 MUX", "INP2", "AMIC2" }, 2424 2425 { "IN1_HPHL", NULL, "VDD_BUCK" }, 2426 { "IN1_HPHL", NULL, "CLS_H_PORT" }, 2427 { "RX1", NULL, "IN1_HPHL" }, 2428 { "RDAC1", NULL, "RX1" }, 2429 { "HPHL_RDAC", "Switch", "RDAC1" }, 2430 { "HPHL PGA", NULL, "HPHL_RDAC" }, 2431 { "HPHL", NULL, "HPHL PGA" }, 2432 2433 { "IN2_HPHR", NULL, "VDD_BUCK" }, 2434 { "IN2_HPHR", NULL, "CLS_H_PORT" }, 2435 { "RX2", NULL, "IN2_HPHR" }, 2436 { "RDAC2", NULL, "RX2" }, 2437 { "HPHR_RDAC", "Switch", "RDAC2" }, 2438 { "HPHR PGA", NULL, "HPHR_RDAC" }, 2439 { "HPHR", NULL, "HPHR PGA" }, 2440 2441 { "IN3_AUX", NULL, "VDD_BUCK" }, 2442 { "IN3_AUX", NULL, "CLS_H_PORT" }, 2443 { "RX3", NULL, "IN3_AUX" }, 2444 { "RDAC4", NULL, "RX3" }, 2445 { "AUX_RDAC", "Switch", "RDAC4" }, 2446 { "AUX PGA", NULL, "AUX_RDAC" }, 2447 { "AUX", NULL, "AUX PGA" }, 2448 2449 { "RDAC3_MUX", "RX3", "RX3" }, 2450 { "RDAC3_MUX", "RX1", "RX1" }, 2451 { "RDAC3", NULL, "RDAC3_MUX" }, 2452 { "EAR_RDAC", "Switch", "RDAC3" }, 2453 { "EAR PGA", NULL, "EAR_RDAC" }, 2454 { "EAR", NULL, "EAR PGA" }, 2455 }; 2456 2457 static const struct snd_soc_dapm_route wcd9375_audio_map[] = { 2458 { "ADC3_OUTPUT", NULL, "ADC3_MIXER" }, 2459 { "ADC3_OUTPUT", NULL, "ADC3_MIXER" }, 2460 { "ADC3_MIXER", "Switch", "ADC3 REQ" }, 2461 { "ADC3 REQ", NULL, "ADC3" }, 2462 { "ADC3", NULL, "AMIC4" }, 2463 2464 { "DMIC1_OUTPUT", NULL, "DMIC1_MIXER" }, 2465 { "DMIC1_MIXER", "Switch", "DMIC1" }, 2466 2467 { "DMIC2_OUTPUT", NULL, "DMIC2_MIXER" }, 2468 { "DMIC2_MIXER", "Switch", "DMIC2" }, 2469 2470 { "DMIC3_OUTPUT", NULL, "DMIC3_MIXER" }, 2471 { "DMIC3_MIXER", "Switch", "DMIC3" }, 2472 2473 { "DMIC4_OUTPUT", NULL, "DMIC4_MIXER" }, 2474 { "DMIC4_MIXER", "Switch", "DMIC4" }, 2475 2476 { "DMIC5_OUTPUT", NULL, "DMIC5_MIXER" }, 2477 { "DMIC5_MIXER", "Switch", "DMIC5" }, 2478 2479 { "DMIC6_OUTPUT", NULL, "DMIC6_MIXER" }, 2480 { "DMIC6_MIXER", "Switch", "DMIC6" }, 2481 }; 2482 2483 static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x) 2484 { 2485 int vout_ctl[3]; 2486 2487 /* Set micbias voltage */ 2488 vout_ctl[0] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb1_mv); 2489 vout_ctl[1] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb2_mv); 2490 vout_ctl[2] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb3_mv); 2491 if ((vout_ctl[0] | vout_ctl[1] | vout_ctl[2]) < 0) 2492 return -EINVAL; 2493 2494 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, WCD937X_ANA_MICB_VOUT, vout_ctl[0]); 2495 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, WCD937X_ANA_MICB_VOUT, vout_ctl[1]); 2496 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, WCD937X_ANA_MICB_VOUT, vout_ctl[2]); 2497 2498 return 0; 2499 } 2500 2501 static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data) 2502 { 2503 return IRQ_HANDLED; 2504 } 2505 2506 static struct irq_chip wcd_irq_chip = { 2507 .name = "WCD937x", 2508 }; 2509 2510 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq, 2511 irq_hw_number_t hw) 2512 { 2513 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq); 2514 irq_set_nested_thread(virq, 1); 2515 irq_set_noprobe(virq); 2516 2517 return 0; 2518 } 2519 2520 static const struct irq_domain_ops wcd_domain_ops = { 2521 .map = wcd_irq_chip_map, 2522 }; 2523 2524 static int wcd937x_irq_init(struct wcd937x_priv *wcd, struct device *dev) 2525 { 2526 wcd->virq = irq_domain_add_linear(NULL, 1, &wcd_domain_ops, NULL); 2527 if (!(wcd->virq)) { 2528 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__); 2529 return -EINVAL; 2530 } 2531 2532 return devm_regmap_add_irq_chip(dev, wcd->regmap, 2533 irq_create_mapping(wcd->virq, 0), 2534 IRQF_ONESHOT, 0, &wcd937x_regmap_irq_chip, 2535 &wcd->irq_chip); 2536 } 2537 2538 static int wcd937x_soc_codec_probe(struct snd_soc_component *component) 2539 { 2540 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 2541 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2542 struct sdw_slave *tx_sdw_dev = wcd937x->tx_sdw_dev; 2543 struct device *dev = component->dev; 2544 unsigned long time_left; 2545 int i, ret; 2546 2547 time_left = wait_for_completion_timeout(&tx_sdw_dev->initialization_complete, 2548 msecs_to_jiffies(5000)); 2549 if (!time_left) { 2550 dev_err(dev, "soundwire device init timeout\n"); 2551 return -ETIMEDOUT; 2552 } 2553 2554 snd_soc_component_init_regmap(component, wcd937x->regmap); 2555 ret = pm_runtime_resume_and_get(dev); 2556 if (ret < 0) 2557 return ret; 2558 2559 wcd937x->chipid = (snd_soc_component_read(component, 2560 WCD937X_DIGITAL_EFUSE_REG_0) & 0x1e) >> 1; 2561 if (wcd937x->chipid != CHIPID_WCD9370 && 2562 wcd937x->chipid != CHIPID_WCD9375) { 2563 dev_err(dev, "Got unknown chip id: 0x%x\n", wcd937x->chipid); 2564 pm_runtime_put(dev); 2565 return -EINVAL; 2566 } 2567 2568 wcd937x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD937X); 2569 if (IS_ERR(wcd937x->clsh_info)) { 2570 pm_runtime_put(dev); 2571 return PTR_ERR(wcd937x->clsh_info); 2572 } 2573 2574 wcd937x_io_init(wcd937x->regmap); 2575 /* Set all interrupts as edge triggered */ 2576 for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++) 2577 regmap_write(wcd937x->regmap, (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0); 2578 2579 pm_runtime_put(dev); 2580 2581 wcd937x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2582 WCD937X_IRQ_HPHR_PDM_WD_INT); 2583 wcd937x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2584 WCD937X_IRQ_HPHL_PDM_WD_INT); 2585 wcd937x->aux_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2586 WCD937X_IRQ_AUX_PDM_WD_INT); 2587 2588 /* Request for watchdog interrupt */ 2589 ret = devm_request_threaded_irq(dev, wcd937x->hphr_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2590 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2591 "HPHR PDM WDOG INT", wcd937x); 2592 if (ret) 2593 dev_err(dev, "Failed to request HPHR watchdog interrupt (%d)\n", ret); 2594 2595 ret = devm_request_threaded_irq(dev, wcd937x->hphl_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2596 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2597 "HPHL PDM WDOG INT", wcd937x); 2598 if (ret) 2599 dev_err(dev, "Failed to request HPHL watchdog interrupt (%d)\n", ret); 2600 2601 ret = devm_request_threaded_irq(dev, wcd937x->aux_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2602 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2603 "AUX PDM WDOG INT", wcd937x); 2604 if (ret) 2605 dev_err(dev, "Failed to request Aux watchdog interrupt (%d)\n", ret); 2606 2607 /* Disable watchdog interrupt for HPH and AUX */ 2608 disable_irq_nosync(wcd937x->hphr_pdm_wd_int); 2609 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 2610 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 2611 2612 if (wcd937x->chipid == CHIPID_WCD9375) { 2613 ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets, 2614 ARRAY_SIZE(wcd9375_dapm_widgets)); 2615 if (ret < 0) { 2616 dev_err(component->dev, "Failed to add snd_ctls\n"); 2617 return ret; 2618 } 2619 2620 ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map, 2621 ARRAY_SIZE(wcd9375_audio_map)); 2622 if (ret < 0) { 2623 dev_err(component->dev, "Failed to add routes\n"); 2624 return ret; 2625 } 2626 } 2627 2628 ret = wcd937x_mbhc_init(component); 2629 if (ret) 2630 dev_err(component->dev, "mbhc initialization failed\n"); 2631 2632 return ret; 2633 } 2634 2635 static void wcd937x_soc_codec_remove(struct snd_soc_component *component) 2636 { 2637 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2638 2639 wcd937x_mbhc_deinit(component); 2640 free_irq(wcd937x->aux_pdm_wd_int, wcd937x); 2641 free_irq(wcd937x->hphl_pdm_wd_int, wcd937x); 2642 free_irq(wcd937x->hphr_pdm_wd_int, wcd937x); 2643 2644 wcd_clsh_ctrl_free(wcd937x->clsh_info); 2645 } 2646 2647 static int wcd937x_codec_set_jack(struct snd_soc_component *comp, 2648 struct snd_soc_jack *jack, void *data) 2649 { 2650 struct wcd937x_priv *wcd = dev_get_drvdata(comp->dev); 2651 int ret = 0; 2652 2653 if (jack) 2654 ret = wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack); 2655 else 2656 wcd_mbhc_stop(wcd->wcd_mbhc); 2657 2658 return ret; 2659 } 2660 2661 static const struct snd_soc_component_driver soc_codec_dev_wcd937x = { 2662 .name = "wcd937x_codec", 2663 .probe = wcd937x_soc_codec_probe, 2664 .remove = wcd937x_soc_codec_remove, 2665 .controls = wcd937x_snd_controls, 2666 .num_controls = ARRAY_SIZE(wcd937x_snd_controls), 2667 .dapm_widgets = wcd937x_dapm_widgets, 2668 .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets), 2669 .dapm_routes = wcd937x_audio_map, 2670 .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map), 2671 .set_jack = wcd937x_codec_set_jack, 2672 .endianness = 1, 2673 }; 2674 2675 static void wcd937x_dt_parse_micbias_info(struct device *dev, struct wcd937x_priv *wcd) 2676 { 2677 struct device_node *np = dev->of_node; 2678 u32 prop_val = 0; 2679 int ret = 0; 2680 2681 ret = of_property_read_u32(np, "qcom,micbias1-microvolt", &prop_val); 2682 if (!ret) 2683 wcd->micb1_mv = prop_val / 1000; 2684 else 2685 dev_warn(dev, "Micbias1 DT property not found\n"); 2686 2687 ret = of_property_read_u32(np, "qcom,micbias2-microvolt", &prop_val); 2688 if (!ret) 2689 wcd->micb2_mv = prop_val / 1000; 2690 else 2691 dev_warn(dev, "Micbias2 DT property not found\n"); 2692 2693 ret = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val); 2694 if (!ret) 2695 wcd->micb3_mv = prop_val / 1000; 2696 else 2697 dev_warn(dev, "Micbias3 DT property not found\n"); 2698 } 2699 2700 static bool wcd937x_swap_gnd_mic(struct snd_soc_component *component, bool active) 2701 { 2702 int value; 2703 struct wcd937x_priv *wcd937x; 2704 2705 wcd937x = snd_soc_component_get_drvdata(component); 2706 2707 value = gpiod_get_value(wcd937x->us_euro_gpio); 2708 gpiod_set_value(wcd937x->us_euro_gpio, !value); 2709 2710 return true; 2711 } 2712 2713 static int wcd937x_codec_hw_params(struct snd_pcm_substream *substream, 2714 struct snd_pcm_hw_params *params, 2715 struct snd_soc_dai *dai) 2716 { 2717 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2718 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2719 2720 return wcd937x_sdw_hw_params(wcd, substream, params, dai); 2721 } 2722 2723 static int wcd937x_codec_free(struct snd_pcm_substream *substream, 2724 struct snd_soc_dai *dai) 2725 { 2726 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2727 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2728 2729 return sdw_stream_remove_slave(wcd->sdev, wcd->sruntime); 2730 } 2731 2732 static int wcd937x_codec_set_sdw_stream(struct snd_soc_dai *dai, 2733 void *stream, int direction) 2734 { 2735 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2736 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2737 2738 wcd->sruntime = stream; 2739 2740 return 0; 2741 } 2742 2743 static const struct snd_soc_dai_ops wcd937x_sdw_dai_ops = { 2744 .hw_params = wcd937x_codec_hw_params, 2745 .hw_free = wcd937x_codec_free, 2746 .set_stream = wcd937x_codec_set_sdw_stream, 2747 }; 2748 2749 static struct snd_soc_dai_driver wcd937x_dais[] = { 2750 [0] = { 2751 .name = "wcd937x-sdw-rx", 2752 .playback = { 2753 .stream_name = "WCD AIF Playback", 2754 .rates = WCD937X_RATES | WCD937X_FRAC_RATES, 2755 .formats = WCD937X_FORMATS, 2756 .rate_min = 8000, 2757 .rate_max = 384000, 2758 .channels_min = 1, 2759 .channels_max = 4, 2760 }, 2761 .ops = &wcd937x_sdw_dai_ops, 2762 }, 2763 [1] = { 2764 .name = "wcd937x-sdw-tx", 2765 .capture = { 2766 .stream_name = "WCD AIF Capture", 2767 .rates = WCD937X_RATES, 2768 .formats = WCD937X_FORMATS, 2769 .rate_min = 8000, 2770 .rate_max = 192000, 2771 .channels_min = 1, 2772 .channels_max = 4, 2773 }, 2774 .ops = &wcd937x_sdw_dai_ops, 2775 }, 2776 }; 2777 2778 static int wcd937x_bind(struct device *dev) 2779 { 2780 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev); 2781 int ret; 2782 2783 /* Give the SDW subdevices some more time to settle */ 2784 usleep_range(5000, 5010); 2785 2786 ret = component_bind_all(dev, wcd937x); 2787 if (ret) { 2788 dev_err(dev, "Slave bind failed, ret = %d\n", ret); 2789 return ret; 2790 } 2791 2792 wcd937x->rxdev = wcd937x_sdw_device_get(wcd937x->rxnode); 2793 if (!wcd937x->rxdev) { 2794 dev_err(dev, "could not find slave with matching of node\n"); 2795 return -EINVAL; 2796 } 2797 2798 wcd937x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd937x->rxdev); 2799 wcd937x->sdw_priv[AIF1_PB]->wcd937x = wcd937x; 2800 2801 wcd937x->txdev = wcd937x_sdw_device_get(wcd937x->txnode); 2802 if (!wcd937x->txdev) { 2803 dev_err(dev, "could not find txslave with matching of node\n"); 2804 return -EINVAL; 2805 } 2806 2807 wcd937x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd937x->txdev); 2808 wcd937x->sdw_priv[AIF1_CAP]->wcd937x = wcd937x; 2809 wcd937x->tx_sdw_dev = dev_to_sdw_dev(wcd937x->txdev); 2810 if (!wcd937x->tx_sdw_dev) { 2811 dev_err(dev, "could not get txslave with matching of dev\n"); 2812 return -EINVAL; 2813 } 2814 2815 /* 2816 * As TX is the main CSR reg interface, which should not be suspended first. 2817 * expicilty add the dependency link 2818 */ 2819 if (!device_link_add(wcd937x->rxdev, wcd937x->txdev, 2820 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2821 dev_err(dev, "Could not devlink TX and RX\n"); 2822 return -EINVAL; 2823 } 2824 2825 if (!device_link_add(dev, wcd937x->txdev, 2826 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2827 dev_err(dev, "Could not devlink WCD and TX\n"); 2828 return -EINVAL; 2829 } 2830 2831 if (!device_link_add(dev, wcd937x->rxdev, 2832 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2833 dev_err(dev, "Could not devlink WCD and RX\n"); 2834 return -EINVAL; 2835 } 2836 2837 wcd937x->regmap = dev_get_regmap(&wcd937x->tx_sdw_dev->dev, NULL); 2838 if (!wcd937x->regmap) { 2839 dev_err(dev, "could not get TX device regmap\n"); 2840 return -EINVAL; 2841 } 2842 2843 ret = wcd937x_irq_init(wcd937x, dev); 2844 if (ret) { 2845 dev_err(dev, "IRQ init failed: %d\n", ret); 2846 return ret; 2847 } 2848 2849 wcd937x->sdw_priv[AIF1_PB]->slave_irq = wcd937x->virq; 2850 wcd937x->sdw_priv[AIF1_CAP]->slave_irq = wcd937x->virq; 2851 2852 ret = wcd937x_set_micbias_data(wcd937x); 2853 if (ret < 0) { 2854 dev_err(dev, "Bad micbias pdata\n"); 2855 return ret; 2856 } 2857 2858 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x, 2859 wcd937x_dais, ARRAY_SIZE(wcd937x_dais)); 2860 if (ret) 2861 dev_err(dev, "Codec registration failed\n"); 2862 2863 return ret; 2864 } 2865 2866 static void wcd937x_unbind(struct device *dev) 2867 { 2868 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev); 2869 2870 snd_soc_unregister_component(dev); 2871 device_link_remove(dev, wcd937x->txdev); 2872 device_link_remove(dev, wcd937x->rxdev); 2873 device_link_remove(wcd937x->rxdev, wcd937x->txdev); 2874 component_unbind_all(dev, wcd937x); 2875 mutex_destroy(&wcd937x->micb_lock); 2876 } 2877 2878 static const struct component_master_ops wcd937x_comp_ops = { 2879 .bind = wcd937x_bind, 2880 .unbind = wcd937x_unbind, 2881 }; 2882 2883 static int wcd937x_add_slave_components(struct wcd937x_priv *wcd937x, 2884 struct device *dev, 2885 struct component_match **matchptr) 2886 { 2887 struct device_node *np = dev->of_node; 2888 2889 wcd937x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0); 2890 if (!wcd937x->rxnode) { 2891 dev_err(dev, "Couldn't parse phandle to qcom,rx-device!\n"); 2892 return -ENODEV; 2893 } 2894 of_node_get(wcd937x->rxnode); 2895 component_match_add_release(dev, matchptr, component_release_of, 2896 component_compare_of, wcd937x->rxnode); 2897 2898 wcd937x->txnode = of_parse_phandle(np, "qcom,tx-device", 0); 2899 if (!wcd937x->txnode) { 2900 dev_err(dev, "Couldn't parse phandle to qcom,tx-device\n"); 2901 return -ENODEV; 2902 } 2903 of_node_get(wcd937x->txnode); 2904 component_match_add_release(dev, matchptr, component_release_of, 2905 component_compare_of, wcd937x->txnode); 2906 2907 return 0; 2908 } 2909 2910 static int wcd937x_probe(struct platform_device *pdev) 2911 { 2912 struct component_match *match = NULL; 2913 struct device *dev = &pdev->dev; 2914 struct wcd937x_priv *wcd937x; 2915 struct wcd_mbhc_config *cfg; 2916 int ret; 2917 2918 wcd937x = devm_kzalloc(dev, sizeof(*wcd937x), GFP_KERNEL); 2919 if (!wcd937x) 2920 return -ENOMEM; 2921 2922 dev_set_drvdata(dev, wcd937x); 2923 mutex_init(&wcd937x->micb_lock); 2924 2925 wcd937x->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 2926 if (IS_ERR(wcd937x->reset_gpio)) 2927 return dev_err_probe(dev, PTR_ERR(wcd937x->reset_gpio), 2928 "failed to reset wcd gpio\n"); 2929 2930 wcd937x->us_euro_gpio = devm_gpiod_get_optional(dev, "us-euro", GPIOD_OUT_LOW); 2931 if (IS_ERR(wcd937x->us_euro_gpio)) 2932 return dev_err_probe(dev, PTR_ERR(wcd937x->us_euro_gpio), 2933 "us-euro swap Control GPIO not found\n"); 2934 2935 cfg = &wcd937x->mbhc_cfg; 2936 cfg->swap_gnd_mic = wcd937x_swap_gnd_mic; 2937 2938 wcd937x->supplies[0].supply = "vdd-rxtx"; 2939 wcd937x->supplies[1].supply = "vdd-px"; 2940 wcd937x->supplies[2].supply = "vdd-mic-bias"; 2941 2942 ret = devm_regulator_bulk_get(dev, WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2943 if (ret) 2944 return dev_err_probe(dev, ret, "Failed to get supplies\n"); 2945 2946 ret = regulator_bulk_enable(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2947 if (ret) 2948 return dev_err_probe(dev, ret, "Failed to enable supplies\n"); 2949 2950 /* Get the buck separately, as it needs special handling */ 2951 wcd937x->buck_supply = devm_regulator_get(dev, "vdd-buck"); 2952 if (IS_ERR(wcd937x->buck_supply)) 2953 return dev_err_probe(dev, PTR_ERR(wcd937x->buck_supply), 2954 "Failed to get buck supply\n"); 2955 2956 ret = regulator_enable(wcd937x->buck_supply); 2957 if (ret) 2958 return dev_err_probe(dev, ret, "Failed to enable buck supply\n"); 2959 2960 wcd937x_dt_parse_micbias_info(dev, wcd937x); 2961 2962 cfg->mbhc_micbias = MIC_BIAS_2; 2963 cfg->anc_micbias = MIC_BIAS_2; 2964 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 2965 cfg->num_btn = WCD937X_MBHC_MAX_BUTTONS; 2966 cfg->micb_mv = wcd937x->micb2_mv; 2967 cfg->linein_th = 5000; 2968 cfg->hs_thr = 1700; 2969 cfg->hph_thr = 50; 2970 2971 wcd_dt_parse_mbhc_data(dev, &wcd937x->mbhc_cfg); 2972 2973 ret = wcd937x_add_slave_components(wcd937x, dev, &match); 2974 if (ret) 2975 return ret; 2976 2977 wcd937x_reset(wcd937x); 2978 2979 ret = component_master_add_with_match(dev, &wcd937x_comp_ops, match); 2980 if (ret) 2981 return ret; 2982 2983 pm_runtime_set_autosuspend_delay(dev, 1000); 2984 pm_runtime_use_autosuspend(dev); 2985 pm_runtime_mark_last_busy(dev); 2986 pm_runtime_set_active(dev); 2987 pm_runtime_enable(dev); 2988 pm_runtime_idle(dev); 2989 2990 return ret; 2991 } 2992 2993 static void wcd937x_remove(struct platform_device *pdev) 2994 { 2995 struct device *dev = &pdev->dev; 2996 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev); 2997 2998 component_master_del(&pdev->dev, &wcd937x_comp_ops); 2999 3000 pm_runtime_disable(dev); 3001 pm_runtime_set_suspended(dev); 3002 pm_runtime_dont_use_autosuspend(dev); 3003 3004 regulator_bulk_disable(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 3005 regulator_bulk_free(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 3006 } 3007 3008 #if defined(CONFIG_OF) 3009 static const struct of_device_id wcd937x_of_match[] = { 3010 { .compatible = "qcom,wcd9370-codec" }, 3011 { .compatible = "qcom,wcd9375-codec" }, 3012 { } 3013 }; 3014 MODULE_DEVICE_TABLE(of, wcd937x_of_match); 3015 #endif 3016 3017 static struct platform_driver wcd937x_codec_driver = { 3018 .probe = wcd937x_probe, 3019 .remove_new = wcd937x_remove, 3020 .driver = { 3021 .name = "wcd937x_codec", 3022 .of_match_table = of_match_ptr(wcd937x_of_match), 3023 .suppress_bind_attrs = true, 3024 }, 3025 }; 3026 3027 module_platform_driver(wcd937x_codec_driver); 3028 MODULE_DESCRIPTION("WCD937X Codec driver"); 3029 MODULE_LICENSE("GPL"); 3030