1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 4 #include <linux/component.h> 5 #include <linux/delay.h> 6 #include <linux/device.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/slab.h> 16 #include <sound/jack.h> 17 #include <sound/pcm_params.h> 18 #include <sound/pcm.h> 19 #include <sound/soc-dapm.h> 20 #include <sound/soc.h> 21 #include <sound/tlv.h> 22 23 #include "wcd-clsh-v2.h" 24 #include "wcd-mbhc-v2.h" 25 #include "wcd937x.h" 26 27 enum { 28 CHIPID_WCD9370 = 0, 29 CHIPID_WCD9375 = 5, 30 }; 31 32 /* Z value defined in milliohm */ 33 #define WCD937X_ZDET_VAL_32 (32000) 34 #define WCD937X_ZDET_VAL_400 (400000) 35 #define WCD937X_ZDET_VAL_1200 (1200000) 36 #define WCD937X_ZDET_VAL_100K (100000000) 37 /* Z floating defined in ohms */ 38 #define WCD937X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE) 39 #define WCD937X_ZDET_NUM_MEASUREMENTS (900) 40 #define WCD937X_MBHC_GET_C1(c) (((c) & 0xC000) >> 14) 41 #define WCD937X_MBHC_GET_X1(x) ((x) & 0x3FFF) 42 /* Z value compared in milliOhm */ 43 #define WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z) (((z) > 400000) || ((z) < 32000)) 44 #define WCD937X_MBHC_ZDET_CONST (86 * 16384) 45 #define WCD937X_MBHC_MOISTURE_RREF R_24_KOHM 46 #define WCD_MBHC_HS_V_MAX 1600 47 #define EAR_RX_PATH_AUX 1 48 #define WCD937X_MBHC_MAX_BUTTONS 8 49 50 #define WCD937X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 51 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 52 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\ 53 SNDRV_PCM_RATE_384000) 54 55 /* Fractional Rates */ 56 #define WCD937X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 57 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800) 58 59 #define WCD937X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |\ 60 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 61 62 enum { 63 ALLOW_BUCK_DISABLE, 64 HPH_COMP_DELAY, 65 HPH_PA_DELAY, 66 AMIC2_BCS_ENABLE, 67 }; 68 69 enum { 70 AIF1_PB = 0, 71 AIF1_CAP, 72 NUM_CODEC_DAIS, 73 }; 74 75 struct wcd937x_priv { 76 struct sdw_slave *tx_sdw_dev; 77 struct wcd937x_sdw_priv *sdw_priv[NUM_CODEC_DAIS]; 78 struct device *txdev; 79 struct device *rxdev; 80 struct device_node *rxnode; 81 struct device_node *txnode; 82 struct regmap *regmap; 83 /* micb setup lock */ 84 struct mutex micb_lock; 85 /* mbhc module */ 86 struct wcd_mbhc *wcd_mbhc; 87 struct wcd_mbhc_config mbhc_cfg; 88 struct wcd_mbhc_intr intr_ids; 89 struct wcd_clsh_ctrl *clsh_info; 90 struct irq_domain *virq; 91 struct regmap_irq_chip *wcd_regmap_irq_chip; 92 struct regmap_irq_chip_data *irq_chip; 93 struct regulator_bulk_data supplies[WCD937X_MAX_BULK_SUPPLY]; 94 struct regulator *buck_supply; 95 struct snd_soc_jack *jack; 96 unsigned long status_mask; 97 s32 micb_ref[WCD937X_MAX_MICBIAS]; 98 s32 pullup_ref[WCD937X_MAX_MICBIAS]; 99 u32 hph_mode; 100 int ear_rx_path; 101 u32 micb1_mv; 102 u32 micb2_mv; 103 u32 micb3_mv; 104 int hphr_pdm_wd_int; 105 int hphl_pdm_wd_int; 106 int aux_pdm_wd_int; 107 bool comp1_enable; 108 bool comp2_enable; 109 110 struct gpio_desc *us_euro_gpio; 111 struct gpio_desc *reset_gpio; 112 113 atomic_t rx_clk_cnt; 114 atomic_t ana_clk_count; 115 }; 116 117 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800); 118 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 119 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 120 121 struct wcd937x_mbhc_zdet_param { 122 u16 ldo_ctl; 123 u16 noff; 124 u16 nshift; 125 u16 btn5; 126 u16 btn6; 127 u16 btn7; 128 }; 129 130 static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 131 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD937X_ANA_MBHC_MECH, 0x80), 132 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD937X_ANA_MBHC_MECH, 0x40), 133 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD937X_ANA_MBHC_MECH, 0x20), 134 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD937X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 135 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD937X_ANA_MBHC_ELECT, 0x08), 136 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F), 137 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD937X_ANA_MBHC_MECH, 0x04), 138 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD937X_ANA_MBHC_MECH, 0x10), 139 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD937X_ANA_MBHC_MECH, 0x08), 140 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD937X_ANA_MBHC_MECH, 0x01), 141 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD937X_ANA_MBHC_ELECT, 0x06), 142 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD937X_ANA_MBHC_ELECT, 0x80), 143 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD937X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 144 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD937X_MBHC_NEW_CTL_1, 0x03), 145 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD937X_MBHC_NEW_CTL_2, 0x03), 146 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x08), 147 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD937X_ANA_MBHC_RESULT_3, 0x10), 148 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x20), 149 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x80), 150 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x40), 151 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD937X_HPH_OCP_CTL, 0x10), 152 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x07), 153 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD937X_ANA_MBHC_ELECT, 0x70), 154 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0xFF), 155 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD937X_ANA_MICB2, 0xC0), 156 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD937X_HPH_CNP_WG_TIME, 0xFF), 157 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD937X_ANA_HPH, 0x40), 158 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD937X_ANA_HPH, 0x80), 159 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD937X_ANA_HPH, 0xC0), 160 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD937X_ANA_MBHC_RESULT_3, 0x10), 161 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD937X_MBHC_CTL_BCS, 0x02), 162 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD937X_MBHC_NEW_FSM_STATUS, 0x01), 163 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD937X_MBHC_NEW_CTL_2, 0x70), 164 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD937X_MBHC_NEW_FSM_STATUS, 0x20), 165 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD937X_HPH_PA_CTL2, 0x40), 166 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD937X_HPH_PA_CTL2, 0x10), 167 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD937X_HPH_L_TEST, 0x01), 168 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD937X_HPH_R_TEST, 0x01), 169 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD937X_DIGITAL_INTR_STATUS_0, 0x80), 170 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD937X_DIGITAL_INTR_STATUS_0, 0x20), 171 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD937X_MBHC_NEW_CTL_1, 0x08), 172 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD937X_MBHC_NEW_FSM_STATUS, 0x40), 173 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD937X_MBHC_NEW_FSM_STATUS, 0x80), 174 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD937X_MBHC_NEW_ADC_RESULT, 0xFF), 175 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD937X_ANA_MICB2, 0x3F), 176 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD937X_MBHC_NEW_CTL_1, 0x10), 177 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD937X_MBHC_NEW_CTL_1, 0x04), 178 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD937X_ANA_MBHC_ZDET, 0x02), 179 }; 180 181 static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = { 182 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, BIT(0)), 183 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, BIT(1)), 184 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, BIT(2)), 185 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, BIT(3)), 186 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, BIT(4)), 187 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, BIT(5)), 188 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, BIT(6)), 189 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, BIT(7)), 190 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, BIT(0)), 191 REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, BIT(1)), 192 REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, BIT(2)), 193 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, BIT(3)), 194 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, BIT(4)), 195 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, BIT(5)), 196 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, BIT(6)), 197 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, BIT(7)), 198 REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, BIT(0)), 199 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, BIT(1)), 200 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, BIT(2)), 201 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, BIT(3)), 202 }; 203 204 static int wcd937x_handle_post_irq(void *data) 205 { 206 struct wcd937x_priv *wcd937x; 207 208 if (data) 209 wcd937x = (struct wcd937x_priv *)data; 210 else 211 return IRQ_HANDLED; 212 213 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_0, 0); 214 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_1, 0); 215 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_2, 0); 216 217 return IRQ_HANDLED; 218 } 219 220 static const u32 wcd937x_config_regs[] = { 221 WCD937X_DIGITAL_INTR_LEVEL_0, 222 }; 223 224 static const struct regmap_irq_chip wcd937x_regmap_irq_chip = { 225 .name = "wcd937x", 226 .irqs = wcd937x_irqs, 227 .num_irqs = ARRAY_SIZE(wcd937x_irqs), 228 .num_regs = 3, 229 .status_base = WCD937X_DIGITAL_INTR_STATUS_0, 230 .mask_base = WCD937X_DIGITAL_INTR_MASK_0, 231 .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0, 232 .use_ack = 1, 233 .clear_ack = 1, 234 .config_base = wcd937x_config_regs, 235 .num_config_bases = ARRAY_SIZE(wcd937x_config_regs), 236 .num_config_regs = 1, 237 .runtime_pm = true, 238 .handle_post_irq = wcd937x_handle_post_irq, 239 .irq_drv_data = NULL, 240 }; 241 242 static void wcd937x_reset(struct wcd937x_priv *wcd937x) 243 { 244 gpiod_set_value(wcd937x->reset_gpio, 1); 245 usleep_range(20, 30); 246 gpiod_set_value(wcd937x->reset_gpio, 0); 247 usleep_range(20, 30); 248 } 249 250 static void wcd937x_io_init(struct regmap *regmap) 251 { 252 u32 val = 0, temp = 0, temp1 = 0; 253 254 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_29, &val); 255 256 val = val & 0x0F; 257 258 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_16, &temp); 259 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_17, &temp1); 260 261 if (temp == 0x02 || temp1 > 0x09) 262 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x0E, val); 263 else 264 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x0e, 0x0e); 265 266 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x80, 0x80); 267 usleep_range(1000, 1010); 268 269 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x40, 0x40); 270 usleep_range(1000, 1010); 271 272 regmap_update_bits(regmap, WCD937X_LDORXTX_CONFIG, BIT(4), 0x00); 273 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xf0, BIT(7)); 274 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(7), BIT(7)); 275 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(6), BIT(6)); 276 usleep_range(10000, 10010); 277 278 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(6), 0x00); 279 regmap_update_bits(regmap, WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xff, 0xd9); 280 regmap_update_bits(regmap, WCD937X_MICB1_TEST_CTL_1, 0xff, 0xfa); 281 regmap_update_bits(regmap, WCD937X_MICB2_TEST_CTL_1, 0xff, 0xfa); 282 regmap_update_bits(regmap, WCD937X_MICB3_TEST_CTL_1, 0xff, 0xfa); 283 284 regmap_update_bits(regmap, WCD937X_MICB1_TEST_CTL_2, 0x38, 0x00); 285 regmap_update_bits(regmap, WCD937X_MICB2_TEST_CTL_2, 0x38, 0x00); 286 regmap_update_bits(regmap, WCD937X_MICB3_TEST_CTL_2, 0x38, 0x00); 287 288 /* Set Bandgap Fine Adjustment to +5mV for Tanggu SMIC part */ 289 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_16, &val); 290 if (val == 0x01) { 291 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0); 292 } else if (val == 0x02) { 293 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x1F, 0x04); 294 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x1F, 0x04); 295 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0); 296 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL, 0xF0, 0x50); 297 } 298 } 299 300 static int wcd937x_rx_clk_enable(struct snd_soc_component *component) 301 { 302 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 303 304 if (atomic_read(&wcd937x->rx_clk_cnt)) 305 return 0; 306 307 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(3), BIT(3)); 308 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(0), BIT(0)); 309 snd_soc_component_update_bits(component, WCD937X_ANA_RX_SUPPLIES, BIT(0), BIT(0)); 310 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX0_CTL, BIT(6), 0x00); 311 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX1_CTL, BIT(6), 0x00); 312 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX2_CTL, BIT(6), 0x00); 313 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(1), BIT(1)); 314 315 atomic_inc(&wcd937x->rx_clk_cnt); 316 317 return 0; 318 } 319 320 static int wcd937x_rx_clk_disable(struct snd_soc_component *component) 321 { 322 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 323 324 if (!atomic_read(&wcd937x->rx_clk_cnt)) { 325 dev_err(component->dev, "clk already disabled\n"); 326 return 0; 327 } 328 329 atomic_dec(&wcd937x->rx_clk_cnt); 330 331 snd_soc_component_update_bits(component, WCD937X_ANA_RX_SUPPLIES, BIT(0), 0x00); 332 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(1), 0x00); 333 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(0), 0x00); 334 335 return 0; 336 } 337 338 static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 339 struct snd_kcontrol *kcontrol, 340 int event) 341 { 342 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 343 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 344 int hph_mode = wcd937x->hph_mode; 345 346 switch (event) { 347 case SND_SOC_DAPM_PRE_PMU: 348 wcd937x_rx_clk_enable(component); 349 snd_soc_component_update_bits(component, 350 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 351 BIT(0), BIT(0)); 352 snd_soc_component_update_bits(component, 353 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 354 BIT(2), BIT(2)); 355 snd_soc_component_update_bits(component, 356 WCD937X_HPH_RDAC_CLK_CTL1, 357 BIT(7), 0x00); 358 set_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 359 break; 360 case SND_SOC_DAPM_POST_PMU: 361 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 362 snd_soc_component_update_bits(component, 363 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 364 0x0f, BIT(1)); 365 else if (hph_mode == CLS_H_LOHIFI) 366 snd_soc_component_update_bits(component, 367 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 368 0x0f, 0x06); 369 370 if (wcd937x->comp1_enable) { 371 snd_soc_component_update_bits(component, 372 WCD937X_DIGITAL_CDC_COMP_CTL_0, 373 BIT(1), BIT(1)); 374 snd_soc_component_update_bits(component, 375 WCD937X_HPH_L_EN, 376 BIT(5), 0x00); 377 378 if (wcd937x->comp2_enable) { 379 snd_soc_component_update_bits(component, 380 WCD937X_DIGITAL_CDC_COMP_CTL_0, 381 BIT(0), BIT(0)); 382 snd_soc_component_update_bits(component, 383 WCD937X_HPH_R_EN, BIT(5), 0x00); 384 } 385 386 if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) { 387 usleep_range(5000, 5110); 388 clear_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 389 } 390 } else { 391 snd_soc_component_update_bits(component, 392 WCD937X_DIGITAL_CDC_COMP_CTL_0, 393 BIT(1), 0x00); 394 snd_soc_component_update_bits(component, 395 WCD937X_HPH_L_EN, 396 BIT(5), BIT(5)); 397 } 398 399 snd_soc_component_update_bits(component, 400 WCD937X_HPH_NEW_INT_HPH_TIMER1, 401 BIT(1), 0x00); 402 break; 403 case SND_SOC_DAPM_POST_PMD: 404 snd_soc_component_update_bits(component, 405 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 406 0x0f, BIT(0)); 407 break; 408 } 409 410 return 0; 411 } 412 413 static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 414 struct snd_kcontrol *kcontrol, 415 int event) 416 { 417 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 418 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 419 int hph_mode = wcd937x->hph_mode; 420 421 switch (event) { 422 case SND_SOC_DAPM_PRE_PMU: 423 wcd937x_rx_clk_enable(component); 424 snd_soc_component_update_bits(component, 425 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(1), BIT(1)); 426 snd_soc_component_update_bits(component, 427 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, BIT(3), BIT(3)); 428 snd_soc_component_update_bits(component, 429 WCD937X_HPH_RDAC_CLK_CTL1, BIT(7), 0x00); 430 set_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 431 break; 432 case SND_SOC_DAPM_POST_PMU: 433 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 434 snd_soc_component_update_bits(component, 435 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 436 0x0f, BIT(1)); 437 else if (hph_mode == CLS_H_LOHIFI) 438 snd_soc_component_update_bits(component, 439 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 440 0x0f, 0x06); 441 if (wcd937x->comp2_enable) { 442 snd_soc_component_update_bits(component, 443 WCD937X_DIGITAL_CDC_COMP_CTL_0, 444 BIT(0), BIT(0)); 445 snd_soc_component_update_bits(component, 446 WCD937X_HPH_R_EN, BIT(5), 0x00); 447 if (wcd937x->comp1_enable) { 448 snd_soc_component_update_bits(component, 449 WCD937X_DIGITAL_CDC_COMP_CTL_0, 450 BIT(1), BIT(1)); 451 snd_soc_component_update_bits(component, 452 WCD937X_HPH_L_EN, 453 BIT(5), 0x00); 454 } 455 456 if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) { 457 usleep_range(5000, 5110); 458 clear_bit(HPH_COMP_DELAY, &wcd937x->status_mask); 459 } 460 } else { 461 snd_soc_component_update_bits(component, 462 WCD937X_DIGITAL_CDC_COMP_CTL_0, 463 BIT(0), 0x00); 464 snd_soc_component_update_bits(component, 465 WCD937X_HPH_R_EN, 466 BIT(5), BIT(5)); 467 } 468 snd_soc_component_update_bits(component, 469 WCD937X_HPH_NEW_INT_HPH_TIMER1, 470 BIT(1), 0x00); 471 break; 472 case SND_SOC_DAPM_POST_PMD: 473 snd_soc_component_update_bits(component, 474 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 475 0x0f, BIT(0)); 476 break; 477 } 478 479 return 0; 480 } 481 482 static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 483 struct snd_kcontrol *kcontrol, 484 int event) 485 { 486 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 487 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 488 int hph_mode = wcd937x->hph_mode; 489 490 switch (event) { 491 case SND_SOC_DAPM_PRE_PMU: 492 wcd937x_rx_clk_enable(component); 493 snd_soc_component_update_bits(component, 494 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 495 BIT(2), BIT(2)); 496 snd_soc_component_update_bits(component, 497 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 498 BIT(0), BIT(0)); 499 500 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) 501 snd_soc_component_update_bits(component, 502 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 503 0x0f, BIT(1)); 504 else if (hph_mode == CLS_H_LOHIFI) 505 snd_soc_component_update_bits(component, 506 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 507 0x0f, 0x06); 508 if (wcd937x->comp1_enable) 509 snd_soc_component_update_bits(component, 510 WCD937X_DIGITAL_CDC_COMP_CTL_0, 511 BIT(1), BIT(1)); 512 usleep_range(5000, 5010); 513 514 snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN, BIT(2), 0x00); 515 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 516 WCD_CLSH_EVENT_PRE_DAC, 517 WCD_CLSH_STATE_EAR, 518 hph_mode); 519 520 break; 521 case SND_SOC_DAPM_POST_PMD: 522 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI || 523 hph_mode == CLS_H_HIFI) 524 snd_soc_component_update_bits(component, 525 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 526 0x0f, BIT(0)); 527 if (wcd937x->comp1_enable) 528 snd_soc_component_update_bits(component, 529 WCD937X_DIGITAL_CDC_COMP_CTL_0, 530 BIT(1), 0x00); 531 break; 532 } 533 534 return 0; 535 } 536 537 static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w, 538 struct snd_kcontrol *kcontrol, 539 int event) 540 { 541 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 542 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 543 int hph_mode = wcd937x->hph_mode; 544 545 switch (event) { 546 case SND_SOC_DAPM_PRE_PMU: 547 wcd937x_rx_clk_enable(component); 548 snd_soc_component_update_bits(component, 549 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 550 BIT(2), BIT(2)); 551 snd_soc_component_update_bits(component, 552 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 553 BIT(2), BIT(2)); 554 snd_soc_component_update_bits(component, 555 WCD937X_DIGITAL_CDC_AUX_GAIN_CTL, 556 BIT(0), BIT(0)); 557 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 558 WCD_CLSH_EVENT_PRE_DAC, 559 WCD_CLSH_STATE_AUX, 560 hph_mode); 561 562 break; 563 case SND_SOC_DAPM_POST_PMD: 564 snd_soc_component_update_bits(component, 565 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 566 BIT(2), 0x00); 567 break; 568 } 569 570 return 0; 571 } 572 573 static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 574 struct snd_kcontrol *kcontrol, 575 int event) 576 { 577 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 578 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 579 int hph_mode = wcd937x->hph_mode; 580 581 switch (event) { 582 case SND_SOC_DAPM_PRE_PMU: 583 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 584 WCD_CLSH_EVENT_PRE_DAC, 585 WCD_CLSH_STATE_HPHR, 586 hph_mode); 587 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 588 BIT(4), BIT(4)); 589 usleep_range(100, 110); 590 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 591 snd_soc_component_update_bits(component, 592 WCD937X_DIGITAL_PDM_WD_CTL1, 593 0x07, 0x03); 594 break; 595 case SND_SOC_DAPM_POST_PMU: 596 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 597 if (wcd937x->comp2_enable) 598 usleep_range(7000, 7100); 599 else 600 usleep_range(20000, 20100); 601 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 602 } 603 604 snd_soc_component_update_bits(component, 605 WCD937X_HPH_NEW_INT_HPH_TIMER1, 606 BIT(1), BIT(1)); 607 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 608 snd_soc_component_update_bits(component, 609 WCD937X_ANA_RX_SUPPLIES, 610 BIT(1), BIT(1)); 611 enable_irq(wcd937x->hphr_pdm_wd_int); 612 break; 613 case SND_SOC_DAPM_PRE_PMD: 614 disable_irq_nosync(wcd937x->hphr_pdm_wd_int); 615 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 616 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_PRE_HPHR_PA_OFF); 617 break; 618 case SND_SOC_DAPM_POST_PMD: 619 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 620 if (wcd937x->comp2_enable) 621 usleep_range(7000, 7100); 622 else 623 usleep_range(20000, 20100); 624 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 625 } 626 627 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_POST_HPHR_PA_OFF); 628 snd_soc_component_update_bits(component, 629 WCD937X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00); 630 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 631 BIT(4), 0x00); 632 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 633 WCD_CLSH_EVENT_POST_PA, 634 WCD_CLSH_STATE_HPHR, 635 hph_mode); 636 break; 637 } 638 639 return 0; 640 } 641 642 static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 643 struct snd_kcontrol *kcontrol, 644 int event) 645 { 646 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 647 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 648 int hph_mode = wcd937x->hph_mode; 649 650 switch (event) { 651 case SND_SOC_DAPM_PRE_PMU: 652 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 653 WCD_CLSH_EVENT_PRE_DAC, 654 WCD_CLSH_STATE_HPHL, 655 hph_mode); 656 snd_soc_component_update_bits(component, WCD937X_ANA_HPH, 657 BIT(5), BIT(5)); 658 usleep_range(100, 110); 659 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 660 snd_soc_component_update_bits(component, 661 WCD937X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03); 662 break; 663 case SND_SOC_DAPM_POST_PMU: 664 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 665 if (!wcd937x->comp1_enable) 666 usleep_range(20000, 20100); 667 else 668 usleep_range(7000, 7100); 669 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 670 } 671 672 snd_soc_component_update_bits(component, 673 WCD937X_HPH_NEW_INT_HPH_TIMER1, 674 BIT(1), BIT(1)); 675 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 676 snd_soc_component_update_bits(component, 677 WCD937X_ANA_RX_SUPPLIES, 678 BIT(1), BIT(1)); 679 enable_irq(wcd937x->hphl_pdm_wd_int); 680 break; 681 case SND_SOC_DAPM_PRE_PMD: 682 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 683 set_bit(HPH_PA_DELAY, &wcd937x->status_mask); 684 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF); 685 break; 686 case SND_SOC_DAPM_POST_PMD: 687 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) { 688 if (!wcd937x->comp1_enable) 689 usleep_range(20000, 20100); 690 else 691 usleep_range(7000, 7100); 692 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask); 693 } 694 695 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 696 snd_soc_component_update_bits(component, 697 WCD937X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00); 698 snd_soc_component_update_bits(component, 699 WCD937X_ANA_HPH, BIT(5), 0x00); 700 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 701 WCD_CLSH_EVENT_POST_PA, 702 WCD_CLSH_STATE_HPHL, 703 hph_mode); 704 break; 705 } 706 707 return 0; 708 } 709 710 static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w, 711 struct snd_kcontrol *kcontrol, 712 int event) 713 { 714 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 715 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 716 int hph_mode = wcd937x->hph_mode; 717 718 switch (event) { 719 case SND_SOC_DAPM_PRE_PMU: 720 snd_soc_component_update_bits(component, 721 WCD937X_DIGITAL_PDM_WD_CTL2, 722 BIT(0), BIT(0)); 723 break; 724 case SND_SOC_DAPM_POST_PMU: 725 usleep_range(1000, 1010); 726 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 727 snd_soc_component_update_bits(component, 728 WCD937X_ANA_RX_SUPPLIES, 729 BIT(1), BIT(1)); 730 enable_irq(wcd937x->aux_pdm_wd_int); 731 break; 732 case SND_SOC_DAPM_PRE_PMD: 733 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 734 break; 735 case SND_SOC_DAPM_POST_PMD: 736 usleep_range(2000, 2010); 737 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 738 WCD_CLSH_EVENT_POST_PA, 739 WCD_CLSH_STATE_AUX, 740 hph_mode); 741 snd_soc_component_update_bits(component, 742 WCD937X_DIGITAL_PDM_WD_CTL2, 743 BIT(0), 0x00); 744 break; 745 } 746 747 return 0; 748 } 749 750 static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 751 struct snd_kcontrol *kcontrol, 752 int event) 753 { 754 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 755 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 756 int hph_mode = wcd937x->hph_mode; 757 758 switch (event) { 759 case SND_SOC_DAPM_PRE_PMU: 760 /* Enable watchdog interrupt for HPHL or AUX depending on mux value */ 761 wcd937x->ear_rx_path = snd_soc_component_read(component, 762 WCD937X_DIGITAL_CDC_EAR_PATH_CTL); 763 764 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 765 snd_soc_component_update_bits(component, 766 WCD937X_DIGITAL_PDM_WD_CTL2, 767 BIT(0), BIT(0)); 768 else 769 snd_soc_component_update_bits(component, 770 WCD937X_DIGITAL_PDM_WD_CTL0, 771 0x07, 0x03); 772 if (!wcd937x->comp1_enable) 773 snd_soc_component_update_bits(component, 774 WCD937X_ANA_EAR_COMPANDER_CTL, 775 BIT(7), BIT(7)); 776 break; 777 case SND_SOC_DAPM_POST_PMU: 778 usleep_range(6000, 6010); 779 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI) 780 snd_soc_component_update_bits(component, 781 WCD937X_ANA_RX_SUPPLIES, 782 BIT(1), BIT(1)); 783 784 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 785 enable_irq(wcd937x->aux_pdm_wd_int); 786 else 787 enable_irq(wcd937x->hphl_pdm_wd_int); 788 break; 789 case SND_SOC_DAPM_PRE_PMD: 790 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 791 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 792 else 793 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 794 break; 795 case SND_SOC_DAPM_POST_PMD: 796 if (!wcd937x->comp1_enable) 797 snd_soc_component_update_bits(component, 798 WCD937X_ANA_EAR_COMPANDER_CTL, 799 BIT(7), 0x00); 800 usleep_range(7000, 7010); 801 wcd_clsh_ctrl_set_state(wcd937x->clsh_info, 802 WCD_CLSH_EVENT_POST_PA, 803 WCD_CLSH_STATE_EAR, 804 hph_mode); 805 snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN, 806 BIT(2), BIT(2)); 807 808 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) 809 snd_soc_component_update_bits(component, 810 WCD937X_DIGITAL_PDM_WD_CTL2, 811 BIT(0), 0x00); 812 else 813 snd_soc_component_update_bits(component, 814 WCD937X_DIGITAL_PDM_WD_CTL0, 815 0x07, 0x00); 816 break; 817 } 818 819 return 0; 820 } 821 822 static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w, 823 struct snd_kcontrol *kcontrol, 824 int event) 825 { 826 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 827 828 if (event == SND_SOC_DAPM_POST_PMD) { 829 wcd937x_rx_clk_disable(component); 830 snd_soc_component_update_bits(component, 831 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 832 BIT(0), 0x00); 833 } 834 835 return 0; 836 } 837 838 static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w, 839 struct snd_kcontrol *kcontrol, int event) 840 { 841 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 842 843 if (event == SND_SOC_DAPM_POST_PMD) { 844 wcd937x_rx_clk_disable(component); 845 snd_soc_component_update_bits(component, 846 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 847 BIT(1), 0x00); 848 } 849 850 return 0; 851 } 852 853 static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w, 854 struct snd_kcontrol *kcontrol, 855 int event) 856 { 857 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 858 859 if (event == SND_SOC_DAPM_POST_PMD) { 860 usleep_range(6000, 6010); 861 wcd937x_rx_clk_disable(component); 862 snd_soc_component_update_bits(component, 863 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 864 BIT(2), 0x00); 865 } 866 867 return 0; 868 } 869 870 static int wcd937x_get_micb_vout_ctl_val(u32 micb_mv) 871 { 872 if (micb_mv < 1000 || micb_mv > 2850) { 873 pr_err("Unsupported micbias voltage (%u mV)\n", micb_mv); 874 return -EINVAL; 875 } 876 877 return (micb_mv - 1000) / 50; 878 } 879 880 static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w, 881 struct snd_kcontrol *kcontrol, int event) 882 { 883 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 884 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 885 bool use_amic3 = snd_soc_component_read(component, WCD937X_TX_NEW_TX_CH2_SEL) & BIT(7); 886 887 /* Enable BCS for Headset mic */ 888 if (event == SND_SOC_DAPM_PRE_PMU && strnstr(w->name, "ADC", sizeof("ADC"))) 889 if (w->shift == 1 && !use_amic3) 890 set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask); 891 892 return 0; 893 } 894 895 static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w, 896 struct snd_kcontrol *kcontrol, int event) 897 { 898 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 899 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 900 901 switch (event) { 902 case SND_SOC_DAPM_PRE_PMU: 903 atomic_inc(&wcd937x->ana_clk_count); 904 snd_soc_component_update_bits(component, 905 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(7), BIT(7)); 906 snd_soc_component_update_bits(component, 907 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(3), BIT(3)); 908 snd_soc_component_update_bits(component, 909 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(4), BIT(4)); 910 break; 911 case SND_SOC_DAPM_POST_PMD: 912 if (w->shift == 1 && test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) 913 clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask); 914 915 snd_soc_component_update_bits(component, 916 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(3), 0x00); 917 break; 918 } 919 920 return 0; 921 } 922 923 static int wcd937x_enable_req(struct snd_soc_dapm_widget *w, 924 struct snd_kcontrol *kcontrol, int event) 925 { 926 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 927 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 928 929 switch (event) { 930 case SND_SOC_DAPM_PRE_PMU: 931 snd_soc_component_update_bits(component, 932 WCD937X_DIGITAL_CDC_REQ_CTL, BIT(1), BIT(1)); 933 snd_soc_component_update_bits(component, 934 WCD937X_DIGITAL_CDC_REQ_CTL, BIT(0), 0x00); 935 snd_soc_component_update_bits(component, 936 WCD937X_ANA_TX_CH2, BIT(6), BIT(6)); 937 snd_soc_component_update_bits(component, 938 WCD937X_ANA_TX_CH3_HPF, BIT(6), BIT(6)); 939 snd_soc_component_update_bits(component, 940 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70); 941 snd_soc_component_update_bits(component, 942 WCD937X_ANA_TX_CH1, BIT(7), BIT(7)); 943 snd_soc_component_update_bits(component, 944 WCD937X_ANA_TX_CH2, BIT(6), 0x00); 945 snd_soc_component_update_bits(component, 946 WCD937X_ANA_TX_CH2, BIT(7), BIT(7)); 947 snd_soc_component_update_bits(component, 948 WCD937X_ANA_TX_CH3, BIT(7), BIT(7)); 949 break; 950 case SND_SOC_DAPM_POST_PMD: 951 snd_soc_component_update_bits(component, 952 WCD937X_ANA_TX_CH1, BIT(7), 0x00); 953 snd_soc_component_update_bits(component, 954 WCD937X_ANA_TX_CH2, BIT(7), 0x00); 955 snd_soc_component_update_bits(component, 956 WCD937X_ANA_TX_CH3, BIT(7), 0x00); 957 snd_soc_component_update_bits(component, 958 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(4), 0x00); 959 960 atomic_dec(&wcd937x->ana_clk_count); 961 if (atomic_read(&wcd937x->ana_clk_count) <= 0) { 962 snd_soc_component_update_bits(component, 963 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 964 BIT(4), 0x00); 965 atomic_set(&wcd937x->ana_clk_count, 0); 966 } 967 968 snd_soc_component_update_bits(component, 969 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 970 BIT(7), 0x00); 971 break; 972 } 973 974 return 0; 975 } 976 977 static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 978 struct snd_kcontrol *kcontrol, 979 int event) 980 { 981 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 982 u16 dmic_clk_reg; 983 984 switch (w->shift) { 985 case 0: 986 case 1: 987 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL; 988 break; 989 case 2: 990 case 3: 991 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL; 992 break; 993 case 4: 994 case 5: 995 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL; 996 break; 997 default: 998 dev_err(component->dev, "Invalid DMIC Selection\n"); 999 return -EINVAL; 1000 } 1001 1002 switch (event) { 1003 case SND_SOC_DAPM_PRE_PMU: 1004 snd_soc_component_update_bits(component, 1005 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 1006 BIT(7), BIT(7)); 1007 snd_soc_component_update_bits(component, 1008 dmic_clk_reg, 0x07, BIT(1)); 1009 snd_soc_component_update_bits(component, 1010 dmic_clk_reg, BIT(3), BIT(3)); 1011 snd_soc_component_update_bits(component, 1012 dmic_clk_reg, 0x70, BIT(5)); 1013 break; 1014 } 1015 1016 return 0; 1017 } 1018 1019 static int wcd937x_micbias_control(struct snd_soc_component *component, 1020 int micb_num, int req, bool is_dapm) 1021 { 1022 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1023 int micb_index = micb_num - 1; 1024 u16 micb_reg; 1025 1026 if (micb_index < 0 || (micb_index > WCD937X_MAX_MICBIAS - 1)) { 1027 dev_err(component->dev, "Invalid micbias index, micb_ind:%d\n", micb_index); 1028 return -EINVAL; 1029 } 1030 switch (micb_num) { 1031 case MIC_BIAS_1: 1032 micb_reg = WCD937X_ANA_MICB1; 1033 break; 1034 case MIC_BIAS_2: 1035 micb_reg = WCD937X_ANA_MICB2; 1036 break; 1037 case MIC_BIAS_3: 1038 micb_reg = WCD937X_ANA_MICB3; 1039 break; 1040 default: 1041 dev_err(component->dev, "Invalid micbias number: %d\n", micb_num); 1042 return -EINVAL; 1043 } 1044 1045 mutex_lock(&wcd937x->micb_lock); 1046 switch (req) { 1047 case MICB_PULLUP_ENABLE: 1048 wcd937x->pullup_ref[micb_index]++; 1049 if (wcd937x->pullup_ref[micb_index] == 1 && 1050 wcd937x->micb_ref[micb_index] == 0) 1051 snd_soc_component_update_bits(component, micb_reg, 1052 0xc0, BIT(7)); 1053 break; 1054 case MICB_PULLUP_DISABLE: 1055 if (wcd937x->pullup_ref[micb_index] > 0) 1056 wcd937x->pullup_ref[micb_index]++; 1057 if (wcd937x->pullup_ref[micb_index] == 0 && 1058 wcd937x->micb_ref[micb_index] == 0) 1059 snd_soc_component_update_bits(component, micb_reg, 1060 0xc0, 0x00); 1061 break; 1062 case MICB_ENABLE: 1063 wcd937x->micb_ref[micb_index]++; 1064 atomic_inc(&wcd937x->ana_clk_count); 1065 if (wcd937x->micb_ref[micb_index] == 1) { 1066 snd_soc_component_update_bits(component, 1067 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 1068 0xf0, 0xf0); 1069 snd_soc_component_update_bits(component, 1070 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 1071 BIT(4), BIT(4)); 1072 snd_soc_component_update_bits(component, 1073 WCD937X_MICB1_TEST_CTL_2, 1074 BIT(0), BIT(0)); 1075 snd_soc_component_update_bits(component, 1076 WCD937X_MICB2_TEST_CTL_2, 1077 BIT(0), BIT(0)); 1078 snd_soc_component_update_bits(component, 1079 WCD937X_MICB3_TEST_CTL_2, 1080 BIT(0), BIT(0)); 1081 snd_soc_component_update_bits(component, 1082 micb_reg, 0xc0, BIT(6)); 1083 1084 if (micb_num == MIC_BIAS_2) 1085 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1086 WCD_EVENT_POST_MICBIAS_2_ON); 1087 1088 if (micb_num == MIC_BIAS_2 && is_dapm) 1089 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1090 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 1091 } 1092 break; 1093 case MICB_DISABLE: 1094 atomic_dec(&wcd937x->ana_clk_count); 1095 if (wcd937x->micb_ref[micb_index] > 0) 1096 wcd937x->micb_ref[micb_index]--; 1097 if (wcd937x->micb_ref[micb_index] == 0 && 1098 wcd937x->pullup_ref[micb_index] > 0) 1099 snd_soc_component_update_bits(component, micb_reg, 1100 0xc0, BIT(7)); 1101 else if (wcd937x->micb_ref[micb_index] == 0 && 1102 wcd937x->pullup_ref[micb_index] == 0) { 1103 if (micb_num == MIC_BIAS_2) 1104 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1105 WCD_EVENT_PRE_MICBIAS_2_OFF); 1106 1107 snd_soc_component_update_bits(component, micb_reg, 1108 0xc0, 0x00); 1109 if (micb_num == MIC_BIAS_2) 1110 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1111 WCD_EVENT_POST_MICBIAS_2_OFF); 1112 } 1113 1114 if (is_dapm && micb_num == MIC_BIAS_2) 1115 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, 1116 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 1117 if (atomic_read(&wcd937x->ana_clk_count) <= 0) { 1118 snd_soc_component_update_bits(component, 1119 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 1120 BIT(4), 0x00); 1121 atomic_set(&wcd937x->ana_clk_count, 0); 1122 } 1123 break; 1124 } 1125 mutex_unlock(&wcd937x->micb_lock); 1126 1127 return 0; 1128 } 1129 1130 static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1131 int event) 1132 { 1133 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1134 int micb_num = w->shift; 1135 1136 switch (event) { 1137 case SND_SOC_DAPM_PRE_PMU: 1138 wcd937x_micbias_control(component, micb_num, 1139 MICB_ENABLE, true); 1140 break; 1141 case SND_SOC_DAPM_POST_PMU: 1142 usleep_range(1000, 1100); 1143 break; 1144 case SND_SOC_DAPM_POST_PMD: 1145 wcd937x_micbias_control(component, micb_num, 1146 MICB_DISABLE, true); 1147 break; 1148 } 1149 1150 return 0; 1151 } 1152 1153 static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1154 struct snd_kcontrol *kcontrol, 1155 int event) 1156 { 1157 return __wcd937x_codec_enable_micbias(w, event); 1158 } 1159 1160 static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1161 int event) 1162 { 1163 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1164 int micb_num = w->shift; 1165 1166 switch (event) { 1167 case SND_SOC_DAPM_PRE_PMU: 1168 wcd937x_micbias_control(component, micb_num, MICB_PULLUP_ENABLE, true); 1169 break; 1170 case SND_SOC_DAPM_POST_PMU: 1171 usleep_range(1000, 1100); 1172 break; 1173 case SND_SOC_DAPM_POST_PMD: 1174 wcd937x_micbias_control(component, micb_num, MICB_PULLUP_DISABLE, true); 1175 break; 1176 } 1177 1178 return 0; 1179 } 1180 1181 static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1182 struct snd_kcontrol *kcontrol, 1183 int event) 1184 { 1185 return __wcd937x_codec_enable_micbias_pullup(w, event); 1186 } 1187 1188 static int wcd937x_connect_port(struct wcd937x_sdw_priv *wcd, u8 port_idx, u8 ch_id, bool enable) 1189 { 1190 struct sdw_port_config *port_config = &wcd->port_config[port_idx - 1]; 1191 const struct wcd937x_sdw_ch_info *ch_info = &wcd->ch_info[ch_id]; 1192 u8 port_num = ch_info->port_num; 1193 u8 ch_mask = ch_info->ch_mask; 1194 1195 port_config->num = port_num; 1196 1197 if (enable) 1198 port_config->ch_mask |= ch_mask; 1199 else 1200 port_config->ch_mask &= ~ch_mask; 1201 1202 return 0; 1203 } 1204 1205 static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol, 1206 struct snd_ctl_elem_value *ucontrol) 1207 { 1208 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1209 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1210 1211 ucontrol->value.integer.value[0] = wcd937x->hph_mode; 1212 return 0; 1213 } 1214 1215 static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol, 1216 struct snd_ctl_elem_value *ucontrol) 1217 { 1218 struct snd_soc_component *component = 1219 snd_soc_kcontrol_component(kcontrol); 1220 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1221 u32 mode_val; 1222 1223 mode_val = ucontrol->value.enumerated.item[0]; 1224 1225 if (!mode_val) 1226 mode_val = CLS_AB; 1227 1228 if (mode_val == wcd937x->hph_mode) 1229 return 0; 1230 1231 switch (mode_val) { 1232 case CLS_H_NORMAL: 1233 case CLS_H_HIFI: 1234 case CLS_H_LP: 1235 case CLS_AB: 1236 case CLS_H_LOHIFI: 1237 case CLS_H_ULP: 1238 case CLS_AB_LP: 1239 case CLS_AB_HIFI: 1240 wcd937x->hph_mode = mode_val; 1241 return 1; 1242 } 1243 1244 dev_dbg(component->dev, "%s: Invalid HPH Mode\n", __func__); 1245 return -EINVAL; 1246 } 1247 1248 static int wcd937x_get_compander(struct snd_kcontrol *kcontrol, 1249 struct snd_ctl_elem_value *ucontrol) 1250 { 1251 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1252 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1253 struct soc_mixer_control *mc; 1254 bool hphr; 1255 1256 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1257 hphr = mc->shift; 1258 1259 ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable : 1260 wcd937x->comp1_enable; 1261 return 0; 1262 } 1263 1264 static int wcd937x_set_compander(struct snd_kcontrol *kcontrol, 1265 struct snd_ctl_elem_value *ucontrol) 1266 { 1267 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1268 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1269 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[AIF1_PB]; 1270 int value = ucontrol->value.integer.value[0]; 1271 struct soc_mixer_control *mc; 1272 int portidx; 1273 bool hphr; 1274 1275 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1276 hphr = mc->shift; 1277 1278 if (hphr) { 1279 if (value == wcd937x->comp2_enable) 1280 return 0; 1281 1282 wcd937x->comp2_enable = value; 1283 } else { 1284 if (value == wcd937x->comp1_enable) 1285 return 0; 1286 1287 wcd937x->comp1_enable = value; 1288 } 1289 1290 portidx = wcd->ch_info[mc->reg].port_num; 1291 1292 if (value) 1293 wcd937x_connect_port(wcd, portidx, mc->reg, true); 1294 else 1295 wcd937x_connect_port(wcd, portidx, mc->reg, false); 1296 1297 return 1; 1298 } 1299 1300 static int wcd937x_get_swr_port(struct snd_kcontrol *kcontrol, 1301 struct snd_ctl_elem_value *ucontrol) 1302 { 1303 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1304 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 1305 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(comp); 1306 struct wcd937x_sdw_priv *wcd; 1307 int dai_id = mixer->shift; 1308 int ch_idx = mixer->reg; 1309 int portidx; 1310 1311 wcd = wcd937x->sdw_priv[dai_id]; 1312 portidx = wcd->ch_info[ch_idx].port_num; 1313 1314 ucontrol->value.integer.value[0] = wcd->port_enable[portidx]; 1315 1316 return 0; 1317 } 1318 1319 static int wcd937x_set_swr_port(struct snd_kcontrol *kcontrol, 1320 struct snd_ctl_elem_value *ucontrol) 1321 { 1322 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1323 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 1324 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(comp); 1325 struct wcd937x_sdw_priv *wcd; 1326 int dai_id = mixer->shift; 1327 int ch_idx = mixer->reg; 1328 int portidx; 1329 bool enable; 1330 1331 wcd = wcd937x->sdw_priv[dai_id]; 1332 1333 portidx = wcd->ch_info[ch_idx].port_num; 1334 1335 enable = ucontrol->value.integer.value[0]; 1336 1337 if (enable == wcd->port_enable[portidx]) { 1338 wcd937x_connect_port(wcd, portidx, ch_idx, enable); 1339 return 0; 1340 } 1341 1342 wcd->port_enable[portidx] = enable; 1343 wcd937x_connect_port(wcd, portidx, ch_idx, enable); 1344 1345 return 1; 1346 } 1347 1348 static const char * const rx_hph_mode_mux_text[] = { 1349 "CLS_H_NORMAL", "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", 1350 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_AB_LP", "CLS_AB_HIFI", 1351 }; 1352 1353 static const struct soc_enum rx_hph_mode_mux_enum = 1354 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), rx_hph_mode_mux_text); 1355 1356 /* MBHC related */ 1357 static void wcd937x_mbhc_clk_setup(struct snd_soc_component *component, 1358 bool enable) 1359 { 1360 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_1, 1361 WCD937X_MBHC_CTL_RCO_EN_MASK, enable); 1362 } 1363 1364 static void wcd937x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 1365 bool enable) 1366 { 1367 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_ELECT, 1368 WCD937X_ANA_MBHC_BIAS_EN, enable); 1369 } 1370 1371 static void wcd937x_mbhc_program_btn_thr(struct snd_soc_component *component, 1372 int *btn_low, int *btn_high, 1373 int num_btn, bool is_micbias) 1374 { 1375 int i, vth; 1376 1377 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 1378 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 1379 __func__, num_btn); 1380 return; 1381 } 1382 1383 for (i = 0; i < num_btn; i++) { 1384 vth = ((btn_high[i] * 2) / 25) & 0x3F; 1385 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_BTN0 + i, 1386 WCD937X_MBHC_BTN_VTH_MASK, vth); 1387 } 1388 } 1389 1390 static bool wcd937x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 1391 { 1392 u8 val; 1393 1394 if (micb_num == MIC_BIAS_2) { 1395 val = snd_soc_component_read_field(component, 1396 WCD937X_ANA_MICB2, 1397 WCD937X_ANA_MICB2_ENABLE_MASK); 1398 if (val == WCD937X_MICB_ENABLE) 1399 return true; 1400 } 1401 return false; 1402 } 1403 1404 static void wcd937x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 1405 int pull_up_cur) 1406 { 1407 /* Default pull up current to 2uA */ 1408 if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA) 1409 pull_up_cur = HS_PULLUP_I_2P0_UA; 1410 1411 snd_soc_component_write_field(component, 1412 WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT, 1413 WCD937X_HSDET_PULLUP_C_MASK, pull_up_cur); 1414 } 1415 1416 static int wcd937x_mbhc_request_micbias(struct snd_soc_component *component, 1417 int micb_num, int req) 1418 { 1419 return wcd937x_micbias_control(component, micb_num, req, false); 1420 } 1421 1422 static void wcd937x_mbhc_micb_ramp_control(struct snd_soc_component *component, 1423 bool enable) 1424 { 1425 if (enable) { 1426 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1427 WCD937X_RAMP_SHIFT_CTRL_MASK, 0x0C); 1428 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1429 WCD937X_RAMP_EN_MASK, 1); 1430 } else { 1431 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1432 WCD937X_RAMP_EN_MASK, 0); 1433 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP, 1434 WCD937X_RAMP_SHIFT_CTRL_MASK, 0); 1435 } 1436 } 1437 1438 static int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 1439 int req_volt, int micb_num) 1440 { 1441 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1442 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0; 1443 1444 switch (micb_num) { 1445 case MIC_BIAS_1: 1446 micb_reg = WCD937X_ANA_MICB1; 1447 break; 1448 case MIC_BIAS_2: 1449 micb_reg = WCD937X_ANA_MICB2; 1450 break; 1451 case MIC_BIAS_3: 1452 micb_reg = WCD937X_ANA_MICB3; 1453 break; 1454 default: 1455 return -EINVAL; 1456 } 1457 mutex_lock(&wcd937x->micb_lock); 1458 /* 1459 * If requested micbias voltage is same as current micbias 1460 * voltage, then just return. Otherwise, adjust voltage as 1461 * per requested value. If micbias is already enabled, then 1462 * to avoid slow micbias ramp-up or down enable pull-up 1463 * momentarily, change the micbias value and then re-enable 1464 * micbias. 1465 */ 1466 micb_en = snd_soc_component_read_field(component, micb_reg, 1467 WCD937X_MICB_EN_MASK); 1468 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 1469 WCD937X_MICB_VOUT_MASK); 1470 1471 req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt); 1472 if (req_vout_ctl < 0) { 1473 ret = -EINVAL; 1474 goto exit; 1475 } 1476 1477 if (cur_vout_ctl == req_vout_ctl) { 1478 ret = 0; 1479 goto exit; 1480 } 1481 1482 if (micb_en == WCD937X_MICB_ENABLE) 1483 snd_soc_component_write_field(component, micb_reg, 1484 WCD937X_MICB_EN_MASK, 1485 WCD937X_MICB_PULL_UP); 1486 1487 snd_soc_component_write_field(component, micb_reg, 1488 WCD937X_MICB_VOUT_MASK, 1489 req_vout_ctl); 1490 1491 if (micb_en == WCD937X_MICB_ENABLE) { 1492 snd_soc_component_write_field(component, micb_reg, 1493 WCD937X_MICB_EN_MASK, 1494 WCD937X_MICB_ENABLE); 1495 /* 1496 * Add 2ms delay as per HW requirement after enabling 1497 * micbias 1498 */ 1499 usleep_range(2000, 2100); 1500 } 1501 exit: 1502 mutex_unlock(&wcd937x->micb_lock); 1503 return ret; 1504 } 1505 1506 static int wcd937x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 1507 int micb_num, bool req_en) 1508 { 1509 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1510 int micb_mv; 1511 1512 if (micb_num != MIC_BIAS_2) 1513 return -EINVAL; 1514 /* 1515 * If device tree micbias level is already above the minimum 1516 * voltage needed to detect threshold microphone, then do 1517 * not change the micbias, just return. 1518 */ 1519 if (wcd937x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV) 1520 return 0; 1521 1522 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd937x->micb2_mv; 1523 1524 return wcd937x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 1525 } 1526 1527 static void wcd937x_mbhc_get_result_params(struct snd_soc_component *component, 1528 s16 *d1_a, u16 noff, 1529 int32_t *zdet) 1530 { 1531 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1532 int i; 1533 int val, val1; 1534 s16 c1; 1535 s32 x1, d1; 1536 s32 denom; 1537 static const int minCode_param[] = { 1538 3277, 1639, 820, 410, 205, 103, 52, 26 1539 }; 1540 1541 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MBHC_ZDET, 0x20, 0x20); 1542 for (i = 0; i < WCD937X_ZDET_NUM_MEASUREMENTS; i++) { 1543 regmap_read(wcd937x->regmap, WCD937X_ANA_MBHC_RESULT_2, &val); 1544 if (val & 0x80) 1545 break; 1546 } 1547 val = val << 0x8; 1548 regmap_read(wcd937x->regmap, WCD937X_ANA_MBHC_RESULT_1, &val1); 1549 val |= val1; 1550 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MBHC_ZDET, 0x20, 0x00); 1551 x1 = WCD937X_MBHC_GET_X1(val); 1552 c1 = WCD937X_MBHC_GET_C1(val); 1553 /* If ramp is not complete, give additional 5ms */ 1554 if (c1 < 2 && x1) 1555 usleep_range(5000, 5050); 1556 1557 if (!c1 || !x1) { 1558 dev_err(component->dev, "Impedance detect ramp error, c1=%d, x1=0x%x\n", 1559 c1, x1); 1560 goto ramp_down; 1561 } 1562 d1 = d1_a[c1]; 1563 denom = (x1 * d1) - (1 << (14 - noff)); 1564 if (denom > 0) 1565 *zdet = (WCD937X_MBHC_ZDET_CONST * 1000) / denom; 1566 else if (x1 < minCode_param[noff]) 1567 *zdet = WCD937X_ZDET_FLOATING_IMPEDANCE; 1568 1569 dev_err(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d (milliohm)\n", 1570 __func__, d1, c1, x1, *zdet); 1571 ramp_down: 1572 i = 0; 1573 while (x1) { 1574 regmap_read(wcd937x->regmap, 1575 WCD937X_ANA_MBHC_RESULT_1, &val); 1576 regmap_read(wcd937x->regmap, 1577 WCD937X_ANA_MBHC_RESULT_2, &val1); 1578 val = val << 0x08; 1579 val |= val1; 1580 x1 = WCD937X_MBHC_GET_X1(val); 1581 i++; 1582 if (i == WCD937X_ZDET_NUM_MEASUREMENTS) 1583 break; 1584 } 1585 } 1586 1587 static void wcd937x_mbhc_zdet_ramp(struct snd_soc_component *component, 1588 struct wcd937x_mbhc_zdet_param *zdet_param, 1589 s32 *zl, s32 *zr, s16 *d1_a) 1590 { 1591 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1592 s32 zdet = 0; 1593 1594 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, 1595 WCD937X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 1596 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN5, 1597 WCD937X_VTH_MASK, zdet_param->btn5); 1598 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN6, 1599 WCD937X_VTH_MASK, zdet_param->btn6); 1600 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN7, 1601 WCD937X_VTH_MASK, zdet_param->btn7); 1602 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, 1603 WCD937X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 1604 snd_soc_component_update_bits(component, WCD937X_MBHC_NEW_ZDET_RAMP_CTL, 1605 0x0F, zdet_param->nshift); 1606 1607 if (!zl) 1608 goto z_right; 1609 /* Start impedance measurement for HPH_L */ 1610 regmap_update_bits(wcd937x->regmap, 1611 WCD937X_ANA_MBHC_ZDET, 0x80, 0x80); 1612 wcd937x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 1613 regmap_update_bits(wcd937x->regmap, 1614 WCD937X_ANA_MBHC_ZDET, 0x80, 0x00); 1615 1616 *zl = zdet; 1617 1618 z_right: 1619 if (!zr) 1620 return; 1621 /* Start impedance measurement for HPH_R */ 1622 regmap_update_bits(wcd937x->regmap, 1623 WCD937X_ANA_MBHC_ZDET, 0x40, 0x40); 1624 wcd937x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 1625 regmap_update_bits(wcd937x->regmap, 1626 WCD937X_ANA_MBHC_ZDET, 0x40, 0x00); 1627 1628 *zr = zdet; 1629 } 1630 1631 static void wcd937x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 1632 s32 *z_val, int flag_l_r) 1633 { 1634 s16 q1; 1635 int q1_cal; 1636 1637 if (*z_val < (WCD937X_ZDET_VAL_400 / 1000)) 1638 q1 = snd_soc_component_read(component, 1639 WCD937X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r)); 1640 else 1641 q1 = snd_soc_component_read(component, 1642 WCD937X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r)); 1643 if (q1 & 0x80) 1644 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 1645 else 1646 q1_cal = (10000 + (q1 * 25)); 1647 if (q1_cal > 0) 1648 *z_val = ((*z_val) * 10000) / q1_cal; 1649 } 1650 1651 static void wcd937x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 1652 u32 *zl, u32 *zr) 1653 { 1654 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1655 s16 reg0, reg1, reg2, reg3, reg4; 1656 s32 z1l, z1r, z1ls; 1657 int zMono, z_diff1, z_diff2; 1658 bool is_fsm_disable = false; 1659 struct wcd937x_mbhc_zdet_param zdet_param[] = { 1660 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 1661 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 1662 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 1663 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 1664 }; 1665 struct wcd937x_mbhc_zdet_param *zdet_param_ptr = NULL; 1666 s16 d1_a[][4] = { 1667 {0, 30, 90, 30}, 1668 {0, 30, 30, 5}, 1669 {0, 30, 30, 5}, 1670 {0, 30, 30, 5}, 1671 }; 1672 s16 *d1 = NULL; 1673 1674 reg0 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN5); 1675 reg1 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN6); 1676 reg2 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN7); 1677 reg3 = snd_soc_component_read(component, WCD937X_MBHC_CTL_CLK); 1678 reg4 = snd_soc_component_read(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL); 1679 1680 if (snd_soc_component_read(component, WCD937X_ANA_MBHC_ELECT) & 0x80) { 1681 is_fsm_disable = true; 1682 regmap_update_bits(wcd937x->regmap, 1683 WCD937X_ANA_MBHC_ELECT, 0x80, 0x00); 1684 } 1685 1686 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 1687 if (wcd937x->mbhc_cfg.hphl_swh) 1688 regmap_update_bits(wcd937x->regmap, 1689 WCD937X_ANA_MBHC_MECH, 0x80, 0x00); 1690 1691 /* Turn off 100k pull down on HPHL */ 1692 regmap_update_bits(wcd937x->regmap, 1693 WCD937X_ANA_MBHC_MECH, 0x01, 0x00); 1694 1695 /* Disable surge protection before impedance detection. 1696 * This is done to give correct value for high impedance. 1697 */ 1698 regmap_update_bits(wcd937x->regmap, 1699 WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00); 1700 /* 1ms delay needed after disable surge protection */ 1701 usleep_range(1000, 1010); 1702 1703 /* First get impedance on Left */ 1704 d1 = d1_a[1]; 1705 zdet_param_ptr = &zdet_param[1]; 1706 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1l, NULL, d1); 1707 1708 if (!WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z1l)) 1709 goto left_ch_impedance; 1710 1711 /* Second ramp for left ch */ 1712 if (z1l < WCD937X_ZDET_VAL_32) { 1713 zdet_param_ptr = &zdet_param[0]; 1714 d1 = d1_a[0]; 1715 } else if ((z1l > WCD937X_ZDET_VAL_400) && 1716 (z1l <= WCD937X_ZDET_VAL_1200)) { 1717 zdet_param_ptr = &zdet_param[2]; 1718 d1 = d1_a[2]; 1719 } else if (z1l > WCD937X_ZDET_VAL_1200) { 1720 zdet_param_ptr = &zdet_param[3]; 1721 d1 = d1_a[3]; 1722 } 1723 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1l, NULL, d1); 1724 1725 left_ch_impedance: 1726 if (z1l == WCD937X_ZDET_FLOATING_IMPEDANCE || 1727 z1l > WCD937X_ZDET_VAL_100K) { 1728 *zl = WCD937X_ZDET_FLOATING_IMPEDANCE; 1729 zdet_param_ptr = &zdet_param[1]; 1730 d1 = d1_a[1]; 1731 } else { 1732 *zl = z1l / 1000; 1733 wcd937x_wcd_mbhc_qfuse_cal(component, zl, 0); 1734 } 1735 1736 /* Start of right impedance ramp and calculation */ 1737 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1r, d1); 1738 if (WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z1r)) { 1739 if ((z1r > WCD937X_ZDET_VAL_1200 && 1740 zdet_param_ptr->noff == 0x6) || 1741 ((*zl) != WCD937X_ZDET_FLOATING_IMPEDANCE)) 1742 goto right_ch_impedance; 1743 /* Second ramp for right ch */ 1744 if (z1r < WCD937X_ZDET_VAL_32) { 1745 zdet_param_ptr = &zdet_param[0]; 1746 d1 = d1_a[0]; 1747 } else if ((z1r > WCD937X_ZDET_VAL_400) && 1748 (z1r <= WCD937X_ZDET_VAL_1200)) { 1749 zdet_param_ptr = &zdet_param[2]; 1750 d1 = d1_a[2]; 1751 } else if (z1r > WCD937X_ZDET_VAL_1200) { 1752 zdet_param_ptr = &zdet_param[3]; 1753 d1 = d1_a[3]; 1754 } 1755 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1r, d1); 1756 } 1757 right_ch_impedance: 1758 if (z1r == WCD937X_ZDET_FLOATING_IMPEDANCE || 1759 z1r > WCD937X_ZDET_VAL_100K) { 1760 *zr = WCD937X_ZDET_FLOATING_IMPEDANCE; 1761 } else { 1762 *zr = z1r / 1000; 1763 wcd937x_wcd_mbhc_qfuse_cal(component, zr, 1); 1764 } 1765 1766 /* Mono/stereo detection */ 1767 if ((*zl == WCD937X_ZDET_FLOATING_IMPEDANCE) && 1768 (*zr == WCD937X_ZDET_FLOATING_IMPEDANCE)) { 1769 dev_err(component->dev, 1770 "%s: plug type is invalid or extension cable\n", 1771 __func__); 1772 goto zdet_complete; 1773 } 1774 if ((*zl == WCD937X_ZDET_FLOATING_IMPEDANCE) || 1775 (*zr == WCD937X_ZDET_FLOATING_IMPEDANCE) || 1776 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 1777 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 1778 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_MONO); 1779 goto zdet_complete; 1780 } 1781 snd_soc_component_write_field(component, WCD937X_HPH_R_ATEST, 1782 WCD937X_HPHPA_GND_OVR_MASK, 1); 1783 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1784 WCD937X_HPHPA_GND_R_MASK, 1); 1785 if (*zl < (WCD937X_ZDET_VAL_32 / 1000)) 1786 wcd937x_mbhc_zdet_ramp(component, &zdet_param[0], &z1ls, NULL, d1); 1787 else 1788 wcd937x_mbhc_zdet_ramp(component, &zdet_param[1], &z1ls, NULL, d1); 1789 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1790 WCD937X_HPHPA_GND_R_MASK, 0); 1791 snd_soc_component_write_field(component, WCD937X_HPH_R_ATEST, 1792 WCD937X_HPHPA_GND_OVR_MASK, 0); 1793 z1ls /= 1000; 1794 wcd937x_wcd_mbhc_qfuse_cal(component, &z1ls, 0); 1795 /* Parallel of left Z and 9 ohm pull down resistor */ 1796 zMono = ((*zl) * 9) / ((*zl) + 9); 1797 z_diff1 = (z1ls > zMono) ? (z1ls - zMono) : (zMono - z1ls); 1798 z_diff2 = ((*zl) > z1ls) ? ((*zl) - z1ls) : (z1ls - (*zl)); 1799 if ((z_diff1 * (*zl + z1ls)) > (z_diff2 * (z1ls + zMono))) 1800 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_STEREO); 1801 else 1802 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_MONO); 1803 1804 /* Enable surge protection again after impedance detection */ 1805 regmap_update_bits(wcd937x->regmap, 1806 WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 1807 zdet_complete: 1808 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN5, reg0); 1809 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN6, reg1); 1810 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN7, reg2); 1811 /* Turn on 100k pull down on HPHL */ 1812 regmap_update_bits(wcd937x->regmap, 1813 WCD937X_ANA_MBHC_MECH, 0x01, 0x01); 1814 1815 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 1816 if (wcd937x->mbhc_cfg.hphl_swh) 1817 regmap_update_bits(wcd937x->regmap, 1818 WCD937X_ANA_MBHC_MECH, 0x80, 0x80); 1819 1820 snd_soc_component_write(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, reg4); 1821 snd_soc_component_write(component, WCD937X_MBHC_CTL_CLK, reg3); 1822 if (is_fsm_disable) 1823 regmap_update_bits(wcd937x->regmap, 1824 WCD937X_ANA_MBHC_ELECT, 0x80, 0x80); 1825 } 1826 1827 static void wcd937x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 1828 bool enable) 1829 { 1830 if (enable) { 1831 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1832 WCD937X_MBHC_HSG_PULLUP_COMP_EN, 1); 1833 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1834 WCD937X_MBHC_GND_DET_EN_MASK, 1); 1835 } else { 1836 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1837 WCD937X_MBHC_GND_DET_EN_MASK, 0); 1838 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH, 1839 WCD937X_MBHC_HSG_PULLUP_COMP_EN, 0); 1840 } 1841 } 1842 1843 static void wcd937x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 1844 bool enable) 1845 { 1846 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1847 WCD937X_HPHPA_GND_R_MASK, enable); 1848 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2, 1849 WCD937X_HPHPA_GND_L_MASK, enable); 1850 } 1851 1852 static void wcd937x_mbhc_moisture_config(struct snd_soc_component *component) 1853 { 1854 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1855 1856 if (wcd937x->mbhc_cfg.moist_rref == R_OFF) { 1857 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1858 WCD937X_M_RTH_CTL_MASK, R_OFF); 1859 return; 1860 } 1861 1862 /* Do not enable moisture detection if jack type is NC */ 1863 if (!wcd937x->mbhc_cfg.hphl_swh) { 1864 dev_err(component->dev, "%s: disable moisture detection for NC\n", 1865 __func__); 1866 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1867 WCD937X_M_RTH_CTL_MASK, R_OFF); 1868 return; 1869 } 1870 1871 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1872 WCD937X_M_RTH_CTL_MASK, wcd937x->mbhc_cfg.moist_rref); 1873 } 1874 1875 static void wcd937x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable) 1876 { 1877 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1878 1879 if (enable) 1880 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1881 WCD937X_M_RTH_CTL_MASK, wcd937x->mbhc_cfg.moist_rref); 1882 else 1883 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1884 WCD937X_M_RTH_CTL_MASK, R_OFF); 1885 } 1886 1887 static bool wcd937x_mbhc_get_moisture_status(struct snd_soc_component *component) 1888 { 1889 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1890 bool ret = false; 1891 1892 if (wcd937x->mbhc_cfg.moist_rref == R_OFF) { 1893 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1894 WCD937X_M_RTH_CTL_MASK, R_OFF); 1895 goto done; 1896 } 1897 1898 /* Do not enable moisture detection if jack type is NC */ 1899 if (!wcd937x->mbhc_cfg.hphl_swh) { 1900 dev_err(component->dev, "%s: disable moisture detection for NC\n", 1901 __func__); 1902 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2, 1903 WCD937X_M_RTH_CTL_MASK, R_OFF); 1904 goto done; 1905 } 1906 1907 /* 1908 * If moisture_en is already enabled, then skip to plug type 1909 * detection. 1910 */ 1911 if (snd_soc_component_read_field(component, WCD937X_MBHC_NEW_CTL_2, WCD937X_M_RTH_CTL_MASK)) 1912 goto done; 1913 1914 wcd937x_mbhc_moisture_detect_en(component, true); 1915 /* Read moisture comparator status */ 1916 ret = ((snd_soc_component_read(component, WCD937X_MBHC_NEW_FSM_STATUS) 1917 & 0x20) ? 0 : 1); 1918 done: 1919 return ret; 1920 } 1921 1922 static void wcd937x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component, 1923 bool enable) 1924 { 1925 snd_soc_component_write_field(component, 1926 WCD937X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 1927 WCD937X_MOISTURE_EN_POLLING_MASK, enable); 1928 } 1929 1930 static const struct wcd_mbhc_cb mbhc_cb = { 1931 .clk_setup = wcd937x_mbhc_clk_setup, 1932 .mbhc_bias = wcd937x_mbhc_mbhc_bias_control, 1933 .set_btn_thr = wcd937x_mbhc_program_btn_thr, 1934 .micbias_enable_status = wcd937x_mbhc_micb_en_status, 1935 .hph_pull_up_control_v2 = wcd937x_mbhc_hph_l_pull_up_control, 1936 .mbhc_micbias_control = wcd937x_mbhc_request_micbias, 1937 .mbhc_micb_ramp_control = wcd937x_mbhc_micb_ramp_control, 1938 .mbhc_micb_ctrl_thr_mic = wcd937x_mbhc_micb_ctrl_threshold_mic, 1939 .compute_impedance = wcd937x_wcd_mbhc_calc_impedance, 1940 .mbhc_gnd_det_ctrl = wcd937x_mbhc_gnd_det_ctrl, 1941 .hph_pull_down_ctrl = wcd937x_mbhc_hph_pull_down_ctrl, 1942 .mbhc_moisture_config = wcd937x_mbhc_moisture_config, 1943 .mbhc_get_moisture_status = wcd937x_mbhc_get_moisture_status, 1944 .mbhc_moisture_polling_ctrl = wcd937x_mbhc_moisture_polling_ctrl, 1945 .mbhc_moisture_detect_en = wcd937x_mbhc_moisture_detect_en, 1946 }; 1947 1948 static int wcd937x_get_hph_type(struct snd_kcontrol *kcontrol, 1949 struct snd_ctl_elem_value *ucontrol) 1950 { 1951 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1952 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1953 1954 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd937x->wcd_mbhc); 1955 1956 return 0; 1957 } 1958 1959 static int wcd937x_hph_impedance_get(struct snd_kcontrol *kcontrol, 1960 struct snd_ctl_elem_value *ucontrol) 1961 { 1962 u32 zl, zr; 1963 bool hphr; 1964 struct soc_mixer_control *mc; 1965 struct snd_soc_component *component = 1966 snd_soc_kcontrol_component(kcontrol); 1967 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1968 1969 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1970 hphr = mc->shift; 1971 wcd_mbhc_get_impedance(wcd937x->wcd_mbhc, &zl, &zr); 1972 ucontrol->value.integer.value[0] = hphr ? zr : zl; 1973 1974 return 0; 1975 } 1976 1977 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 1978 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0, 1979 wcd937x_get_hph_type, NULL), 1980 }; 1981 1982 static const struct snd_kcontrol_new impedance_detect_controls[] = { 1983 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0, 1984 wcd937x_hph_impedance_get, NULL), 1985 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0, 1986 wcd937x_hph_impedance_get, NULL), 1987 }; 1988 1989 static int wcd937x_mbhc_init(struct snd_soc_component *component) 1990 { 1991 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 1992 struct wcd_mbhc_intr *intr_ids = &wcd937x->intr_ids; 1993 1994 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd937x->irq_chip, 1995 WCD937X_IRQ_MBHC_SW_DET); 1996 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd937x->irq_chip, 1997 WCD937X_IRQ_MBHC_BUTTON_PRESS_DET); 1998 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd937x->irq_chip, 1999 WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET); 2000 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2001 WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 2002 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd937x->irq_chip, 2003 WCD937X_IRQ_MBHC_ELECT_INS_REM_DET); 2004 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd937x->irq_chip, 2005 WCD937X_IRQ_HPHL_OCP_INT); 2006 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd937x->irq_chip, 2007 WCD937X_IRQ_HPHR_OCP_INT); 2008 2009 wcd937x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 2010 if (IS_ERR(wcd937x->wcd_mbhc)) 2011 return PTR_ERR(wcd937x->wcd_mbhc); 2012 2013 snd_soc_add_component_controls(component, impedance_detect_controls, 2014 ARRAY_SIZE(impedance_detect_controls)); 2015 snd_soc_add_component_controls(component, hph_type_detect_controls, 2016 ARRAY_SIZE(hph_type_detect_controls)); 2017 2018 return 0; 2019 } 2020 2021 static void wcd937x_mbhc_deinit(struct snd_soc_component *component) 2022 { 2023 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2024 2025 wcd_mbhc_deinit(wcd937x->wcd_mbhc); 2026 } 2027 2028 /* END MBHC */ 2029 2030 static const struct snd_kcontrol_new wcd937x_snd_controls[] = { 2031 SOC_SINGLE_TLV("EAR_PA Volume", WCD937X_ANA_EAR_COMPANDER_CTL, 2032 2, 0x10, 0, ear_pa_gain), 2033 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 2034 wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put), 2035 2036 SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0, 2037 wcd937x_get_compander, wcd937x_set_compander), 2038 SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0, 2039 wcd937x_get_compander, wcd937x_set_compander), 2040 2041 SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain), 2042 SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain), 2043 SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0, analog_gain), 2044 SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0, analog_gain), 2045 SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0, analog_gain), 2046 2047 SOC_SINGLE_EXT("HPHL Switch", WCD937X_HPH_L, 0, 1, 0, 2048 wcd937x_get_swr_port, wcd937x_set_swr_port), 2049 SOC_SINGLE_EXT("HPHR Switch", WCD937X_HPH_R, 0, 1, 0, 2050 wcd937x_get_swr_port, wcd937x_set_swr_port), 2051 2052 SOC_SINGLE_EXT("ADC1 Switch", WCD937X_ADC1, 1, 1, 0, 2053 wcd937x_get_swr_port, wcd937x_set_swr_port), 2054 SOC_SINGLE_EXT("ADC2 Switch", WCD937X_ADC2, 1, 1, 0, 2055 wcd937x_get_swr_port, wcd937x_set_swr_port), 2056 SOC_SINGLE_EXT("ADC3 Switch", WCD937X_ADC3, 1, 1, 0, 2057 wcd937x_get_swr_port, wcd937x_set_swr_port), 2058 SOC_SINGLE_EXT("DMIC0 Switch", WCD937X_DMIC0, 1, 1, 0, 2059 wcd937x_get_swr_port, wcd937x_set_swr_port), 2060 SOC_SINGLE_EXT("DMIC1 Switch", WCD937X_DMIC1, 1, 1, 0, 2061 wcd937x_get_swr_port, wcd937x_set_swr_port), 2062 SOC_SINGLE_EXT("MBHC Switch", WCD937X_MBHC, 1, 1, 0, 2063 wcd937x_get_swr_port, wcd937x_set_swr_port), 2064 SOC_SINGLE_EXT("DMIC2 Switch", WCD937X_DMIC2, 1, 1, 0, 2065 wcd937x_get_swr_port, wcd937x_set_swr_port), 2066 SOC_SINGLE_EXT("DMIC3 Switch", WCD937X_DMIC3, 1, 1, 0, 2067 wcd937x_get_swr_port, wcd937x_set_swr_port), 2068 SOC_SINGLE_EXT("DMIC4 Switch", WCD937X_DMIC4, 1, 1, 0, 2069 wcd937x_get_swr_port, wcd937x_set_swr_port), 2070 SOC_SINGLE_EXT("DMIC5 Switch", WCD937X_DMIC5, 1, 1, 0, 2071 wcd937x_get_swr_port, wcd937x_set_swr_port), 2072 }; 2073 2074 static const struct snd_kcontrol_new adc1_switch[] = { 2075 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2076 }; 2077 2078 static const struct snd_kcontrol_new adc2_switch[] = { 2079 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2080 }; 2081 2082 static const struct snd_kcontrol_new adc3_switch[] = { 2083 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2084 }; 2085 2086 static const struct snd_kcontrol_new dmic1_switch[] = { 2087 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2088 }; 2089 2090 static const struct snd_kcontrol_new dmic2_switch[] = { 2091 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2092 }; 2093 2094 static const struct snd_kcontrol_new dmic3_switch[] = { 2095 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2096 }; 2097 2098 static const struct snd_kcontrol_new dmic4_switch[] = { 2099 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2100 }; 2101 2102 static const struct snd_kcontrol_new dmic5_switch[] = { 2103 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2104 }; 2105 2106 static const struct snd_kcontrol_new dmic6_switch[] = { 2107 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2108 }; 2109 2110 static const struct snd_kcontrol_new ear_rdac_switch[] = { 2111 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2112 }; 2113 2114 static const struct snd_kcontrol_new aux_rdac_switch[] = { 2115 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2116 }; 2117 2118 static const struct snd_kcontrol_new hphl_rdac_switch[] = { 2119 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2120 }; 2121 2122 static const struct snd_kcontrol_new hphr_rdac_switch[] = { 2123 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2124 }; 2125 2126 static const char * const adc2_mux_text[] = { 2127 "INP2", "INP3" 2128 }; 2129 2130 static const char * const rdac3_mux_text[] = { 2131 "RX1", "RX3" 2132 }; 2133 2134 static const struct soc_enum adc2_enum = 2135 SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7, 2136 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 2137 2138 static const struct soc_enum rdac3_enum = 2139 SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0, 2140 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text); 2141 2142 static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum); 2143 2144 static const struct snd_kcontrol_new rx_rdac3_mux = SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum); 2145 2146 static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = { 2147 /* Input widgets */ 2148 SND_SOC_DAPM_INPUT("AMIC1"), 2149 SND_SOC_DAPM_INPUT("AMIC2"), 2150 SND_SOC_DAPM_INPUT("AMIC3"), 2151 SND_SOC_DAPM_INPUT("IN1_HPHL"), 2152 SND_SOC_DAPM_INPUT("IN2_HPHR"), 2153 SND_SOC_DAPM_INPUT("IN3_AUX"), 2154 2155 /* TX widgets */ 2156 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0, 2157 wcd937x_codec_enable_adc, 2158 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2159 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0, 2160 wcd937x_codec_enable_adc, 2161 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2162 2163 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, 2164 NULL, 0, wcd937x_enable_req, 2165 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2166 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0, 2167 NULL, 0, wcd937x_enable_req, 2168 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2169 2170 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 2171 2172 /* TX mixers */ 2173 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, 2174 adc1_switch, ARRAY_SIZE(adc1_switch), 2175 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2176 SND_SOC_DAPM_POST_PMD), 2177 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 1, 0, 2178 adc2_switch, ARRAY_SIZE(adc2_switch), 2179 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2180 SND_SOC_DAPM_POST_PMD), 2181 2182 /* MIC_BIAS widgets */ 2183 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2184 wcd937x_codec_enable_micbias, 2185 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2186 SND_SOC_DAPM_POST_PMD), 2187 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2188 wcd937x_codec_enable_micbias, 2189 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2190 SND_SOC_DAPM_POST_PMD), 2191 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2192 wcd937x_codec_enable_micbias, 2193 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2194 SND_SOC_DAPM_POST_PMD), 2195 2196 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0), 2197 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0), 2198 2199 /* RX widgets */ 2200 SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0, 2201 wcd937x_codec_enable_ear_pa, 2202 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2203 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2204 SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0, 2205 wcd937x_codec_enable_aux_pa, 2206 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2207 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2208 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0, 2209 wcd937x_codec_enable_hphl_pa, 2210 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2211 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2212 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0, 2213 wcd937x_codec_enable_hphr_pa, 2214 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2215 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2216 2217 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0, 2218 wcd937x_codec_hphl_dac_event, 2219 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2220 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2221 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0, 2222 wcd937x_codec_hphr_dac_event, 2223 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2224 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2225 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0, 2226 wcd937x_codec_ear_dac_event, 2227 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2228 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2229 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0, 2230 wcd937x_codec_aux_dac_event, 2231 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2232 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2233 2234 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux), 2235 2236 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, 2237 wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU | 2238 SND_SOC_DAPM_POST_PMD), 2239 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, 2240 wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU | 2241 SND_SOC_DAPM_POST_PMD), 2242 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, 2243 wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU | 2244 SND_SOC_DAPM_POST_PMD), 2245 2246 /* RX mixer widgets*/ 2247 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0, 2248 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)), 2249 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0, 2250 aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)), 2251 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0, 2252 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)), 2253 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0, 2254 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)), 2255 2256 /* TX output widgets */ 2257 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"), 2258 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"), 2259 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"), 2260 SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"), 2261 2262 /* RX output widgets */ 2263 SND_SOC_DAPM_OUTPUT("EAR"), 2264 SND_SOC_DAPM_OUTPUT("AUX"), 2265 SND_SOC_DAPM_OUTPUT("HPHL"), 2266 SND_SOC_DAPM_OUTPUT("HPHR"), 2267 2268 /* MIC_BIAS pull up widgets */ 2269 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2270 wcd937x_codec_enable_micbias_pullup, 2271 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2272 SND_SOC_DAPM_POST_PMD), 2273 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2274 wcd937x_codec_enable_micbias_pullup, 2275 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2276 SND_SOC_DAPM_POST_PMD), 2277 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2278 wcd937x_codec_enable_micbias_pullup, 2279 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2280 SND_SOC_DAPM_POST_PMD), 2281 }; 2282 2283 static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = { 2284 /* Input widgets */ 2285 SND_SOC_DAPM_INPUT("AMIC4"), 2286 2287 /* TX widgets */ 2288 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0, 2289 wcd937x_codec_enable_adc, 2290 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2291 2292 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0, 2293 NULL, 0, wcd937x_enable_req, 2294 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2295 2296 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 2297 wcd937x_codec_enable_dmic, 2298 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2299 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0, 2300 wcd937x_codec_enable_dmic, 2301 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2302 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0, 2303 wcd937x_codec_enable_dmic, 2304 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2305 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0, 2306 wcd937x_codec_enable_dmic, 2307 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2308 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0, 2309 wcd937x_codec_enable_dmic, 2310 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2311 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0, 2312 wcd937x_codec_enable_dmic, 2313 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2314 2315 /* TX mixer widgets */ 2316 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 2317 0, dmic1_switch, ARRAY_SIZE(dmic1_switch), 2318 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2319 SND_SOC_DAPM_POST_PMD), 2320 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 1, 2321 0, dmic2_switch, ARRAY_SIZE(dmic2_switch), 2322 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2323 SND_SOC_DAPM_POST_PMD), 2324 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 2, 2325 0, dmic3_switch, ARRAY_SIZE(dmic3_switch), 2326 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2327 SND_SOC_DAPM_POST_PMD), 2328 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 3, 2329 0, dmic4_switch, ARRAY_SIZE(dmic4_switch), 2330 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2331 SND_SOC_DAPM_POST_PMD), 2332 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 4, 2333 0, dmic5_switch, ARRAY_SIZE(dmic5_switch), 2334 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2335 SND_SOC_DAPM_POST_PMD), 2336 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 5, 2337 0, dmic6_switch, ARRAY_SIZE(dmic6_switch), 2338 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | 2339 SND_SOC_DAPM_POST_PMD), 2340 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 2, 0, adc3_switch, 2341 ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl, 2342 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2343 2344 /* Output widgets */ 2345 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"), 2346 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"), 2347 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"), 2348 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"), 2349 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"), 2350 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"), 2351 }; 2352 2353 static const struct snd_soc_dapm_route wcd937x_audio_map[] = { 2354 { "ADC1_OUTPUT", NULL, "ADC1_MIXER" }, 2355 { "ADC1_MIXER", "Switch", "ADC1 REQ" }, 2356 { "ADC1 REQ", NULL, "ADC1" }, 2357 { "ADC1", NULL, "AMIC1" }, 2358 2359 { "ADC2_OUTPUT", NULL, "ADC2_MIXER" }, 2360 { "ADC2_MIXER", "Switch", "ADC2 REQ" }, 2361 { "ADC2 REQ", NULL, "ADC2" }, 2362 { "ADC2", NULL, "ADC2 MUX" }, 2363 { "ADC2 MUX", "INP3", "AMIC3" }, 2364 { "ADC2 MUX", "INP2", "AMIC2" }, 2365 2366 { "IN1_HPHL", NULL, "VDD_BUCK" }, 2367 { "IN1_HPHL", NULL, "CLS_H_PORT" }, 2368 { "RX1", NULL, "IN1_HPHL" }, 2369 { "RDAC1", NULL, "RX1" }, 2370 { "HPHL_RDAC", "Switch", "RDAC1" }, 2371 { "HPHL PGA", NULL, "HPHL_RDAC" }, 2372 { "HPHL", NULL, "HPHL PGA" }, 2373 2374 { "IN2_HPHR", NULL, "VDD_BUCK" }, 2375 { "IN2_HPHR", NULL, "CLS_H_PORT" }, 2376 { "RX2", NULL, "IN2_HPHR" }, 2377 { "RDAC2", NULL, "RX2" }, 2378 { "HPHR_RDAC", "Switch", "RDAC2" }, 2379 { "HPHR PGA", NULL, "HPHR_RDAC" }, 2380 { "HPHR", NULL, "HPHR PGA" }, 2381 2382 { "IN3_AUX", NULL, "VDD_BUCK" }, 2383 { "IN3_AUX", NULL, "CLS_H_PORT" }, 2384 { "RX3", NULL, "IN3_AUX" }, 2385 { "RDAC4", NULL, "RX3" }, 2386 { "AUX_RDAC", "Switch", "RDAC4" }, 2387 { "AUX PGA", NULL, "AUX_RDAC" }, 2388 { "AUX", NULL, "AUX PGA" }, 2389 2390 { "RDAC3_MUX", "RX3", "RX3" }, 2391 { "RDAC3_MUX", "RX1", "RX1" }, 2392 { "RDAC3", NULL, "RDAC3_MUX" }, 2393 { "EAR_RDAC", "Switch", "RDAC3" }, 2394 { "EAR PGA", NULL, "EAR_RDAC" }, 2395 { "EAR", NULL, "EAR PGA" }, 2396 }; 2397 2398 static const struct snd_soc_dapm_route wcd9375_audio_map[] = { 2399 { "ADC3_OUTPUT", NULL, "ADC3_MIXER" }, 2400 { "ADC3_OUTPUT", NULL, "ADC3_MIXER" }, 2401 { "ADC3_MIXER", "Switch", "ADC3 REQ" }, 2402 { "ADC3 REQ", NULL, "ADC3" }, 2403 { "ADC3", NULL, "AMIC4" }, 2404 2405 { "DMIC1_OUTPUT", NULL, "DMIC1_MIXER" }, 2406 { "DMIC1_MIXER", "Switch", "DMIC1" }, 2407 2408 { "DMIC2_OUTPUT", NULL, "DMIC2_MIXER" }, 2409 { "DMIC2_MIXER", "Switch", "DMIC2" }, 2410 2411 { "DMIC3_OUTPUT", NULL, "DMIC3_MIXER" }, 2412 { "DMIC3_MIXER", "Switch", "DMIC3" }, 2413 2414 { "DMIC4_OUTPUT", NULL, "DMIC4_MIXER" }, 2415 { "DMIC4_MIXER", "Switch", "DMIC4" }, 2416 2417 { "DMIC5_OUTPUT", NULL, "DMIC5_MIXER" }, 2418 { "DMIC5_MIXER", "Switch", "DMIC5" }, 2419 2420 { "DMIC6_OUTPUT", NULL, "DMIC6_MIXER" }, 2421 { "DMIC6_MIXER", "Switch", "DMIC6" }, 2422 }; 2423 2424 static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x) 2425 { 2426 int vout_ctl[3]; 2427 2428 /* Set micbias voltage */ 2429 vout_ctl[0] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb1_mv); 2430 vout_ctl[1] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb2_mv); 2431 vout_ctl[2] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb3_mv); 2432 if ((vout_ctl[0] | vout_ctl[1] | vout_ctl[2]) < 0) 2433 return -EINVAL; 2434 2435 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, WCD937X_ANA_MICB_VOUT, vout_ctl[0]); 2436 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, WCD937X_ANA_MICB_VOUT, vout_ctl[1]); 2437 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, WCD937X_ANA_MICB_VOUT, vout_ctl[2]); 2438 2439 return 0; 2440 } 2441 2442 static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data) 2443 { 2444 return IRQ_HANDLED; 2445 } 2446 2447 static const struct irq_chip wcd_irq_chip = { 2448 .name = "WCD937x", 2449 }; 2450 2451 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq, 2452 irq_hw_number_t hw) 2453 { 2454 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq); 2455 irq_set_nested_thread(virq, 1); 2456 irq_set_noprobe(virq); 2457 2458 return 0; 2459 } 2460 2461 static const struct irq_domain_ops wcd_domain_ops = { 2462 .map = wcd_irq_chip_map, 2463 }; 2464 2465 static int wcd937x_irq_init(struct wcd937x_priv *wcd, struct device *dev) 2466 { 2467 wcd->virq = irq_domain_add_linear(NULL, 1, &wcd_domain_ops, NULL); 2468 if (!(wcd->virq)) { 2469 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__); 2470 return -EINVAL; 2471 } 2472 2473 return devm_regmap_add_irq_chip(dev, wcd->regmap, 2474 irq_create_mapping(wcd->virq, 0), 2475 IRQF_ONESHOT, 0, &wcd937x_regmap_irq_chip, 2476 &wcd->irq_chip); 2477 } 2478 2479 static int wcd937x_soc_codec_probe(struct snd_soc_component *component) 2480 { 2481 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 2482 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2483 struct sdw_slave *tx_sdw_dev = wcd937x->tx_sdw_dev; 2484 struct device *dev = component->dev; 2485 unsigned long time_left; 2486 int i, ret; 2487 u32 chipid; 2488 2489 time_left = wait_for_completion_timeout(&tx_sdw_dev->initialization_complete, 2490 msecs_to_jiffies(5000)); 2491 if (!time_left) { 2492 dev_err(dev, "soundwire device init timeout\n"); 2493 return -ETIMEDOUT; 2494 } 2495 2496 snd_soc_component_init_regmap(component, wcd937x->regmap); 2497 ret = pm_runtime_resume_and_get(dev); 2498 if (ret < 0) 2499 return ret; 2500 2501 chipid = (snd_soc_component_read(component, 2502 WCD937X_DIGITAL_EFUSE_REG_0) & 0x1e) >> 1; 2503 if (chipid != CHIPID_WCD9370 && chipid != CHIPID_WCD9375) { 2504 dev_err(dev, "Got unknown chip id: 0x%x\n", chipid); 2505 pm_runtime_put(dev); 2506 return -EINVAL; 2507 } 2508 2509 wcd937x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD937X); 2510 if (IS_ERR(wcd937x->clsh_info)) { 2511 pm_runtime_put(dev); 2512 return PTR_ERR(wcd937x->clsh_info); 2513 } 2514 2515 wcd937x_io_init(wcd937x->regmap); 2516 /* Set all interrupts as edge triggered */ 2517 for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++) 2518 regmap_write(wcd937x->regmap, (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0); 2519 2520 pm_runtime_put(dev); 2521 2522 wcd937x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2523 WCD937X_IRQ_HPHR_PDM_WD_INT); 2524 wcd937x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2525 WCD937X_IRQ_HPHL_PDM_WD_INT); 2526 wcd937x->aux_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip, 2527 WCD937X_IRQ_AUX_PDM_WD_INT); 2528 2529 /* Request for watchdog interrupt */ 2530 ret = devm_request_threaded_irq(dev, wcd937x->hphr_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2531 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2532 "HPHR PDM WDOG INT", wcd937x); 2533 if (ret) 2534 dev_err(dev, "Failed to request HPHR watchdog interrupt (%d)\n", ret); 2535 2536 ret = devm_request_threaded_irq(dev, wcd937x->hphl_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2537 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2538 "HPHL PDM WDOG INT", wcd937x); 2539 if (ret) 2540 dev_err(dev, "Failed to request HPHL watchdog interrupt (%d)\n", ret); 2541 2542 ret = devm_request_threaded_irq(dev, wcd937x->aux_pdm_wd_int, NULL, wcd937x_wd_handle_irq, 2543 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 2544 "AUX PDM WDOG INT", wcd937x); 2545 if (ret) 2546 dev_err(dev, "Failed to request Aux watchdog interrupt (%d)\n", ret); 2547 2548 /* Disable watchdog interrupt for HPH and AUX */ 2549 disable_irq_nosync(wcd937x->hphr_pdm_wd_int); 2550 disable_irq_nosync(wcd937x->hphl_pdm_wd_int); 2551 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 2552 2553 if (chipid == CHIPID_WCD9375) { 2554 ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets, 2555 ARRAY_SIZE(wcd9375_dapm_widgets)); 2556 if (ret < 0) { 2557 dev_err(component->dev, "Failed to add snd_ctls\n"); 2558 return ret; 2559 } 2560 2561 ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map, 2562 ARRAY_SIZE(wcd9375_audio_map)); 2563 if (ret < 0) { 2564 dev_err(component->dev, "Failed to add routes\n"); 2565 return ret; 2566 } 2567 } 2568 2569 ret = wcd937x_mbhc_init(component); 2570 if (ret) 2571 dev_err(component->dev, "mbhc initialization failed\n"); 2572 2573 return ret; 2574 } 2575 2576 static void wcd937x_soc_codec_remove(struct snd_soc_component *component) 2577 { 2578 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component); 2579 2580 wcd937x_mbhc_deinit(component); 2581 free_irq(wcd937x->aux_pdm_wd_int, wcd937x); 2582 free_irq(wcd937x->hphl_pdm_wd_int, wcd937x); 2583 free_irq(wcd937x->hphr_pdm_wd_int, wcd937x); 2584 2585 wcd_clsh_ctrl_free(wcd937x->clsh_info); 2586 } 2587 2588 static int wcd937x_codec_set_jack(struct snd_soc_component *comp, 2589 struct snd_soc_jack *jack, void *data) 2590 { 2591 struct wcd937x_priv *wcd = dev_get_drvdata(comp->dev); 2592 int ret = 0; 2593 2594 if (jack) 2595 ret = wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack); 2596 else 2597 wcd_mbhc_stop(wcd->wcd_mbhc); 2598 2599 return ret; 2600 } 2601 2602 static const struct snd_soc_component_driver soc_codec_dev_wcd937x = { 2603 .name = "wcd937x_codec", 2604 .probe = wcd937x_soc_codec_probe, 2605 .remove = wcd937x_soc_codec_remove, 2606 .controls = wcd937x_snd_controls, 2607 .num_controls = ARRAY_SIZE(wcd937x_snd_controls), 2608 .dapm_widgets = wcd937x_dapm_widgets, 2609 .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets), 2610 .dapm_routes = wcd937x_audio_map, 2611 .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map), 2612 .set_jack = wcd937x_codec_set_jack, 2613 .endianness = 1, 2614 }; 2615 2616 static void wcd937x_dt_parse_micbias_info(struct device *dev, struct wcd937x_priv *wcd) 2617 { 2618 struct device_node *np = dev->of_node; 2619 u32 prop_val = 0; 2620 int ret = 0; 2621 2622 ret = of_property_read_u32(np, "qcom,micbias1-microvolt", &prop_val); 2623 if (!ret) 2624 wcd->micb1_mv = prop_val / 1000; 2625 else 2626 dev_warn(dev, "Micbias1 DT property not found\n"); 2627 2628 ret = of_property_read_u32(np, "qcom,micbias2-microvolt", &prop_val); 2629 if (!ret) 2630 wcd->micb2_mv = prop_val / 1000; 2631 else 2632 dev_warn(dev, "Micbias2 DT property not found\n"); 2633 2634 ret = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val); 2635 if (!ret) 2636 wcd->micb3_mv = prop_val / 1000; 2637 else 2638 dev_warn(dev, "Micbias3 DT property not found\n"); 2639 } 2640 2641 static bool wcd937x_swap_gnd_mic(struct snd_soc_component *component, bool active) 2642 { 2643 int value; 2644 struct wcd937x_priv *wcd937x; 2645 2646 wcd937x = snd_soc_component_get_drvdata(component); 2647 2648 value = gpiod_get_value(wcd937x->us_euro_gpio); 2649 gpiod_set_value(wcd937x->us_euro_gpio, !value); 2650 2651 return true; 2652 } 2653 2654 static int wcd937x_codec_hw_params(struct snd_pcm_substream *substream, 2655 struct snd_pcm_hw_params *params, 2656 struct snd_soc_dai *dai) 2657 { 2658 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2659 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2660 2661 return wcd937x_sdw_hw_params(wcd, substream, params, dai); 2662 } 2663 2664 static int wcd937x_codec_free(struct snd_pcm_substream *substream, 2665 struct snd_soc_dai *dai) 2666 { 2667 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2668 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2669 2670 return sdw_stream_remove_slave(wcd->sdev, wcd->sruntime); 2671 } 2672 2673 static int wcd937x_codec_set_sdw_stream(struct snd_soc_dai *dai, 2674 void *stream, int direction) 2675 { 2676 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev); 2677 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id]; 2678 2679 wcd->sruntime = stream; 2680 2681 return 0; 2682 } 2683 2684 static const struct snd_soc_dai_ops wcd937x_sdw_dai_ops = { 2685 .hw_params = wcd937x_codec_hw_params, 2686 .hw_free = wcd937x_codec_free, 2687 .set_stream = wcd937x_codec_set_sdw_stream, 2688 }; 2689 2690 static struct snd_soc_dai_driver wcd937x_dais[] = { 2691 [0] = { 2692 .name = "wcd937x-sdw-rx", 2693 .playback = { 2694 .stream_name = "WCD AIF Playback", 2695 .rates = WCD937X_RATES | WCD937X_FRAC_RATES, 2696 .formats = WCD937X_FORMATS, 2697 .rate_min = 8000, 2698 .rate_max = 384000, 2699 .channels_min = 1, 2700 .channels_max = 4, 2701 }, 2702 .ops = &wcd937x_sdw_dai_ops, 2703 }, 2704 [1] = { 2705 .name = "wcd937x-sdw-tx", 2706 .capture = { 2707 .stream_name = "WCD AIF Capture", 2708 .rates = WCD937X_RATES, 2709 .formats = WCD937X_FORMATS, 2710 .rate_min = 8000, 2711 .rate_max = 192000, 2712 .channels_min = 1, 2713 .channels_max = 4, 2714 }, 2715 .ops = &wcd937x_sdw_dai_ops, 2716 }, 2717 }; 2718 2719 static int wcd937x_bind(struct device *dev) 2720 { 2721 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev); 2722 int ret; 2723 2724 /* Give the SDW subdevices some more time to settle */ 2725 usleep_range(5000, 5010); 2726 2727 ret = component_bind_all(dev, wcd937x); 2728 if (ret) { 2729 dev_err(dev, "Slave bind failed, ret = %d\n", ret); 2730 return ret; 2731 } 2732 2733 wcd937x->rxdev = wcd937x_sdw_device_get(wcd937x->rxnode); 2734 if (!wcd937x->rxdev) { 2735 dev_err(dev, "could not find slave with matching of node\n"); 2736 return -EINVAL; 2737 } 2738 2739 wcd937x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd937x->rxdev); 2740 wcd937x->sdw_priv[AIF1_PB]->wcd937x = wcd937x; 2741 2742 wcd937x->txdev = wcd937x_sdw_device_get(wcd937x->txnode); 2743 if (!wcd937x->txdev) { 2744 dev_err(dev, "could not find txslave with matching of node\n"); 2745 return -EINVAL; 2746 } 2747 2748 wcd937x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd937x->txdev); 2749 wcd937x->sdw_priv[AIF1_CAP]->wcd937x = wcd937x; 2750 wcd937x->tx_sdw_dev = dev_to_sdw_dev(wcd937x->txdev); 2751 if (!wcd937x->tx_sdw_dev) { 2752 dev_err(dev, "could not get txslave with matching of dev\n"); 2753 return -EINVAL; 2754 } 2755 2756 /* 2757 * As TX is the main CSR reg interface, which should not be suspended first. 2758 * expicilty add the dependency link 2759 */ 2760 if (!device_link_add(wcd937x->rxdev, wcd937x->txdev, 2761 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2762 dev_err(dev, "Could not devlink TX and RX\n"); 2763 return -EINVAL; 2764 } 2765 2766 if (!device_link_add(dev, wcd937x->txdev, 2767 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2768 dev_err(dev, "Could not devlink WCD and TX\n"); 2769 return -EINVAL; 2770 } 2771 2772 if (!device_link_add(dev, wcd937x->rxdev, 2773 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) { 2774 dev_err(dev, "Could not devlink WCD and RX\n"); 2775 return -EINVAL; 2776 } 2777 2778 wcd937x->regmap = dev_get_regmap(&wcd937x->tx_sdw_dev->dev, NULL); 2779 if (!wcd937x->regmap) { 2780 dev_err(dev, "could not get TX device regmap\n"); 2781 return -EINVAL; 2782 } 2783 2784 ret = wcd937x_irq_init(wcd937x, dev); 2785 if (ret) { 2786 dev_err(dev, "IRQ init failed: %d\n", ret); 2787 return ret; 2788 } 2789 2790 wcd937x->sdw_priv[AIF1_PB]->slave_irq = wcd937x->virq; 2791 wcd937x->sdw_priv[AIF1_CAP]->slave_irq = wcd937x->virq; 2792 2793 ret = wcd937x_set_micbias_data(wcd937x); 2794 if (ret < 0) { 2795 dev_err(dev, "Bad micbias pdata\n"); 2796 return ret; 2797 } 2798 2799 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x, 2800 wcd937x_dais, ARRAY_SIZE(wcd937x_dais)); 2801 if (ret) 2802 dev_err(dev, "Codec registration failed\n"); 2803 2804 return ret; 2805 } 2806 2807 static void wcd937x_unbind(struct device *dev) 2808 { 2809 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev); 2810 2811 snd_soc_unregister_component(dev); 2812 device_link_remove(dev, wcd937x->txdev); 2813 device_link_remove(dev, wcd937x->rxdev); 2814 device_link_remove(wcd937x->rxdev, wcd937x->txdev); 2815 component_unbind_all(dev, wcd937x); 2816 mutex_destroy(&wcd937x->micb_lock); 2817 } 2818 2819 static const struct component_master_ops wcd937x_comp_ops = { 2820 .bind = wcd937x_bind, 2821 .unbind = wcd937x_unbind, 2822 }; 2823 2824 static int wcd937x_add_slave_components(struct wcd937x_priv *wcd937x, 2825 struct device *dev, 2826 struct component_match **matchptr) 2827 { 2828 struct device_node *np = dev->of_node; 2829 2830 wcd937x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0); 2831 if (!wcd937x->rxnode) { 2832 dev_err(dev, "Couldn't parse phandle to qcom,rx-device!\n"); 2833 return -ENODEV; 2834 } 2835 of_node_get(wcd937x->rxnode); 2836 component_match_add_release(dev, matchptr, component_release_of, 2837 component_compare_of, wcd937x->rxnode); 2838 2839 wcd937x->txnode = of_parse_phandle(np, "qcom,tx-device", 0); 2840 if (!wcd937x->txnode) { 2841 dev_err(dev, "Couldn't parse phandle to qcom,tx-device\n"); 2842 return -ENODEV; 2843 } 2844 of_node_get(wcd937x->txnode); 2845 component_match_add_release(dev, matchptr, component_release_of, 2846 component_compare_of, wcd937x->txnode); 2847 2848 return 0; 2849 } 2850 2851 static int wcd937x_probe(struct platform_device *pdev) 2852 { 2853 struct component_match *match = NULL; 2854 struct device *dev = &pdev->dev; 2855 struct wcd937x_priv *wcd937x; 2856 struct wcd_mbhc_config *cfg; 2857 int ret; 2858 2859 wcd937x = devm_kzalloc(dev, sizeof(*wcd937x), GFP_KERNEL); 2860 if (!wcd937x) 2861 return -ENOMEM; 2862 2863 dev_set_drvdata(dev, wcd937x); 2864 mutex_init(&wcd937x->micb_lock); 2865 2866 wcd937x->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 2867 if (IS_ERR(wcd937x->reset_gpio)) 2868 return dev_err_probe(dev, PTR_ERR(wcd937x->reset_gpio), 2869 "failed to reset wcd gpio\n"); 2870 2871 wcd937x->us_euro_gpio = devm_gpiod_get_optional(dev, "us-euro", GPIOD_OUT_LOW); 2872 if (IS_ERR(wcd937x->us_euro_gpio)) 2873 return dev_err_probe(dev, PTR_ERR(wcd937x->us_euro_gpio), 2874 "us-euro swap Control GPIO not found\n"); 2875 2876 cfg = &wcd937x->mbhc_cfg; 2877 cfg->swap_gnd_mic = wcd937x_swap_gnd_mic; 2878 2879 wcd937x->supplies[0].supply = "vdd-rxtx"; 2880 wcd937x->supplies[1].supply = "vdd-px"; 2881 wcd937x->supplies[2].supply = "vdd-mic-bias"; 2882 wcd937x->supplies[3].supply = "vdd-buck"; 2883 2884 ret = devm_regulator_bulk_get(dev, WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2885 if (ret) 2886 return dev_err_probe(dev, ret, "Failed to get supplies\n"); 2887 2888 ret = regulator_bulk_enable(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2889 if (ret) { 2890 regulator_bulk_free(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2891 return dev_err_probe(dev, ret, "Failed to enable supplies\n"); 2892 } 2893 2894 wcd937x_dt_parse_micbias_info(dev, wcd937x); 2895 2896 cfg->mbhc_micbias = MIC_BIAS_2; 2897 cfg->anc_micbias = MIC_BIAS_2; 2898 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 2899 cfg->num_btn = WCD937X_MBHC_MAX_BUTTONS; 2900 cfg->micb_mv = wcd937x->micb2_mv; 2901 cfg->linein_th = 5000; 2902 cfg->hs_thr = 1700; 2903 cfg->hph_thr = 50; 2904 2905 wcd_dt_parse_mbhc_data(dev, &wcd937x->mbhc_cfg); 2906 2907 ret = wcd937x_add_slave_components(wcd937x, dev, &match); 2908 if (ret) 2909 goto err_disable_regulators; 2910 2911 wcd937x_reset(wcd937x); 2912 2913 ret = component_master_add_with_match(dev, &wcd937x_comp_ops, match); 2914 if (ret) 2915 goto err_disable_regulators; 2916 2917 pm_runtime_set_autosuspend_delay(dev, 1000); 2918 pm_runtime_use_autosuspend(dev); 2919 pm_runtime_mark_last_busy(dev); 2920 pm_runtime_set_active(dev); 2921 pm_runtime_enable(dev); 2922 pm_runtime_idle(dev); 2923 2924 return 0; 2925 2926 err_disable_regulators: 2927 regulator_bulk_disable(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2928 regulator_bulk_free(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2929 2930 return ret; 2931 } 2932 2933 static void wcd937x_remove(struct platform_device *pdev) 2934 { 2935 struct device *dev = &pdev->dev; 2936 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev); 2937 2938 component_master_del(&pdev->dev, &wcd937x_comp_ops); 2939 2940 pm_runtime_disable(dev); 2941 pm_runtime_set_suspended(dev); 2942 pm_runtime_dont_use_autosuspend(dev); 2943 2944 regulator_bulk_disable(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2945 regulator_bulk_free(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies); 2946 } 2947 2948 #if defined(CONFIG_OF) 2949 static const struct of_device_id wcd937x_of_match[] = { 2950 { .compatible = "qcom,wcd9370-codec" }, 2951 { .compatible = "qcom,wcd9375-codec" }, 2952 { } 2953 }; 2954 MODULE_DEVICE_TABLE(of, wcd937x_of_match); 2955 #endif 2956 2957 static struct platform_driver wcd937x_codec_driver = { 2958 .probe = wcd937x_probe, 2959 .remove = wcd937x_remove, 2960 .driver = { 2961 .name = "wcd937x_codec", 2962 .of_match_table = of_match_ptr(wcd937x_of_match), 2963 .suppress_bind_attrs = true, 2964 }, 2965 }; 2966 2967 module_platform_driver(wcd937x_codec_driver); 2968 MODULE_DESCRIPTION("WCD937X Codec driver"); 2969 MODULE_LICENSE("GPL"); 2970