1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * ALSA SoC Texas Instruments TAS675x Quad-Channel Audio Amplifier 4 * 5 * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/ 6 * Author: Sen Wang <sen@ti.com> 7 */ 8 9 #ifndef __TAS675X_H__ 10 #define __TAS675X_H__ 11 12 /* 13 * Book 0, Page 0 — Register Addresses 14 */ 15 16 #define TAS675X_PAGE_SIZE 256 17 #define TAS675X_PAGE_REG(page, reg) ((page) * TAS675X_PAGE_SIZE + (reg)) 18 19 /* Page Control & Basic Config */ 20 #define TAS675X_PAGE_CTRL_REG 0x00 21 #define TAS675X_RESET_REG 0x01 22 #define TAS675X_OUTPUT_CTRL_REG 0x02 23 #define TAS675X_STATE_CTRL_CH1_CH2_REG 0x03 24 #define TAS675X_STATE_CTRL_CH3_CH4_REG 0x04 25 #define TAS675X_ISENSE_CTRL_REG 0x05 26 #define TAS675X_DC_DETECT_CTRL_REG 0x06 27 28 /* Serial Audio Port */ 29 #define TAS675X_SCLK_INV_CTRL_REG 0x20 30 #define TAS675X_AUDIO_IF_CTRL_REG 0x21 31 #define TAS675X_SDIN_CTRL_REG 0x23 32 #define TAS675X_SDOUT_CTRL_REG 0x25 33 #define TAS675X_SDIN_OFFSET_MSB_REG 0x27 34 #define TAS675X_SDIN_AUDIO_OFFSET_REG 0x28 35 #define TAS675X_SDIN_LL_OFFSET_REG 0x29 36 #define TAS675X_SDIN_CH_SWAP_REG 0x2A 37 #define TAS675X_SDOUT_OFFSET_MSB_REG 0x2C 38 #define TAS675X_VPREDICT_OFFSET_REG 0x2D 39 #define TAS675X_ISENSE_OFFSET_REG 0x2E 40 #define TAS675X_SDOUT_EN_REG 0x31 41 #define TAS675X_LL_EN_REG 0x32 42 43 /* DSP & Core Audio Control */ 44 #define TAS675X_RTLDG_EN_REG 0x37 45 #define TAS675X_DC_BLOCK_BYP_REG 0x39 46 #define TAS675X_DSP_CTRL_REG 0x3A 47 #define TAS675X_PAGE_AUTO_INC_REG 0x3B 48 49 /* Volume & Mute */ 50 #define TAS675X_DIG_VOL_CH1_REG 0x40 51 #define TAS675X_DIG_VOL_CH2_REG 0x41 52 #define TAS675X_DIG_VOL_CH3_REG 0x42 53 #define TAS675X_DIG_VOL_CH4_REG 0x43 54 #define TAS675X_DIG_VOL_RAMP_CTRL_REG 0x44 55 #define TAS675X_DIG_VOL_COMBINE_CTRL_REG 0x46 56 #define TAS675X_AUTO_MUTE_EN_REG 0x47 57 #define TAS675X_AUTO_MUTE_TIMING_CH1_CH2_REG 0x48 58 #define TAS675X_AUTO_MUTE_TIMING_CH3_CH4_REG 0x49 59 60 /* Analog Gain & Power Stage */ 61 #define TAS675X_ANALOG_GAIN_CH1_CH2_REG 0x4A 62 #define TAS675X_ANALOG_GAIN_CH3_CH4_REG 0x4B 63 #define TAS675X_ANALOG_GAIN_RAMP_CTRL_REG 0x4E 64 #define TAS675X_PULSE_INJECTION_EN_REG 0x52 65 #define TAS675X_CBC_CTRL_REG 0x54 66 #define TAS675X_CURRENT_LIMIT_CTRL_REG 0x55 67 #define TAS675X_DAC_CLK_REG 0x5A 68 #define TAS675X_ISENSE_CAL_REG 0x5B 69 70 /* Spread Spectrum & PWM Phase */ 71 #define TAS675X_PWM_PHASE_CTRL_REG 0x60 72 #define TAS675X_SS_CTRL_REG 0x61 73 #define TAS675X_SS_RANGE_CTRL_REG 0x62 74 #define TAS675X_SS_DWELL_CTRL_REG 0x66 75 #define TAS675X_RAMP_PHASE_CTRL_GPO_REG 0x68 76 #define TAS675X_PWM_PHASE_M_CTRL_CH1_REG 0x69 77 #define TAS675X_PWM_PHASE_M_CTRL_CH2_REG 0x6A 78 #define TAS675X_PWM_PHASE_M_CTRL_CH3_REG 0x6B 79 #define TAS675X_PWM_PHASE_M_CTRL_CH4_REG 0x6C 80 81 /* Status & Reporting */ 82 #define TAS675X_AUTO_MUTE_STATUS_REG 0x71 83 #define TAS675X_STATE_REPORT_CH1_CH2_REG 0x72 84 #define TAS675X_STATE_REPORT_CH3_CH4_REG 0x73 85 #define TAS675X_PVDD_SENSE_REG 0x74 86 #define TAS675X_TEMP_GLOBAL_REG 0x75 87 #define TAS675X_FS_MON_REG 0x76 88 #define TAS675X_SCLK_MON_REG 0x77 89 #define TAS675X_REPORT_ROUTING_1_REG 0x7C 90 91 /* Memory Paging & Book Control */ 92 #define TAS675X_SETUP_REG1 0x7D 93 #define TAS675X_SETUP_REG2 0x7E 94 #define TAS675X_BOOK_CTRL_REG 0x7F 95 96 /* Fault Status */ 97 #define TAS675X_POWER_FAULT_STATUS_1_REG 0x7D 98 #define TAS675X_POWER_FAULT_STATUS_2_REG 0x80 99 #define TAS675X_OT_FAULT_REG 0x81 100 #define TAS675X_OTW_STATUS_REG 0x82 101 #define TAS675X_CLIP_WARN_STATUS_REG 0x83 102 #define TAS675X_CBC_WARNING_STATUS_REG 0x85 103 104 /* Latched Fault Registers */ 105 #define TAS675X_POWER_FAULT_LATCHED_REG 0x86 106 #define TAS675X_OTSD_LATCHED_REG 0x87 107 #define TAS675X_OTW_LATCHED_REG 0x88 108 #define TAS675X_CLIP_WARN_LATCHED_REG 0x89 109 #define TAS675X_CLK_FAULT_LATCHED_REG 0x8A 110 #define TAS675X_RTLDG_OL_SL_FAULT_LATCHED_REG 0x8B 111 #define TAS675X_CBC_FAULT_WARN_LATCHED_REG 0x8D 112 #define TAS675X_OC_DC_FAULT_LATCHED_REG 0x8E 113 #define TAS675X_OTSD_RECOVERY_EN_REG 0x8F 114 115 /* Protection & Routing Controls */ 116 #define TAS675X_REPORT_ROUTING_2_REG 0x90 117 #define TAS675X_REPORT_ROUTING_3_REG 0x91 118 #define TAS675X_REPORT_ROUTING_4_REG 0x92 119 #define TAS675X_CLIP_DETECT_CTRL_REG 0x93 120 #define TAS675X_REPORT_ROUTING_5_REG 0x94 121 122 /* GPIO Pin Configuration */ 123 #define TAS675X_GPIO1_OUTPUT_SEL_REG 0x95 124 #define TAS675X_GPIO2_OUTPUT_SEL_REG 0x96 125 #define TAS675X_GPIO_INPUT_SLEEP_HIZ_REG 0x9B 126 #define TAS675X_GPIO_INPUT_PLAY_SLEEP_REG 0x9C 127 #define TAS675X_GPIO_INPUT_MUTE_REG 0x9D 128 #define TAS675X_GPIO_INPUT_SYNC_REG 0x9E 129 #define TAS675X_GPIO_INPUT_SDIN2_REG 0x9F 130 #define TAS675X_GPIO_CTRL_REG 0xA0 131 #define TAS675X_GPIO_INVERT_REG 0xA1 132 133 /* Load Diagnostics Config */ 134 #define TAS675X_DC_LDG_CTRL_REG 0xB0 135 #define TAS675X_DC_LDG_LO_CTRL_REG 0xB1 136 #define TAS675X_DC_LDG_TIME_CTRL_REG 0xB2 137 #define TAS675X_DC_LDG_SL_CH1_CH2_CTRL_REG 0xB3 138 #define TAS675X_DC_LDG_SL_CH3_CH4_CTRL_REG 0xB4 139 #define TAS675X_AC_LDG_CTRL_REG 0xB5 140 #define TAS675X_TWEETER_DETECT_CTRL_REG 0xB6 141 #define TAS675X_TWEETER_DETECT_THRESH_REG 0xB7 142 #define TAS675X_AC_LDG_FREQ_CTRL_REG 0xB8 143 #define TAS675X_TEMP_CH1_CH2_REG 0xBB 144 #define TAS675X_TEMP_CH3_CH4_REG 0xBC 145 #define TAS675X_WARN_OT_MAX_FLAG_REG 0xBD 146 147 /* DC Load Diagnostic Reports */ 148 #define TAS675X_DC_LDG_REPORT_CH1_CH2_REG 0xC0 149 #define TAS675X_DC_LDG_REPORT_CH3_CH4_REG 0xC1 150 #define TAS675X_DC_LDG_RESULT_REG 0xC2 151 #define TAS675X_AC_LDG_REPORT_CH1_R_REG 0xC3 152 #define TAS675X_AC_LDG_REPORT_CH1_I_REG 0xC4 153 #define TAS675X_AC_LDG_REPORT_CH2_R_REG 0xC5 154 #define TAS675X_AC_LDG_REPORT_CH2_I_REG 0xC6 155 #define TAS675X_AC_LDG_REPORT_CH3_R_REG 0xC7 156 #define TAS675X_AC_LDG_REPORT_CH3_I_REG 0xC8 157 #define TAS675X_AC_LDG_REPORT_CH4_R_REG 0xC9 158 #define TAS675X_AC_LDG_REPORT_CH4_I_REG 0xCA 159 #define TAS675X_TWEETER_REPORT_REG 0xCB 160 161 /* RTLDG Impedance */ 162 #define TAS675X_CH1_RTLDG_IMP_MSB_REG 0xD1 163 #define TAS675X_CH1_RTLDG_IMP_LSB_REG 0xD2 164 #define TAS675X_CH2_RTLDG_IMP_MSB_REG 0xD3 165 #define TAS675X_CH2_RTLDG_IMP_LSB_REG 0xD4 166 #define TAS675X_CH3_RTLDG_IMP_MSB_REG 0xD5 167 #define TAS675X_CH3_RTLDG_IMP_LSB_REG 0xD6 168 #define TAS675X_CH4_RTLDG_IMP_MSB_REG 0xD7 169 #define TAS675X_CH4_RTLDG_IMP_LSB_REG 0xD8 170 171 /* DC Load Diagnostic Resistance */ 172 #define TAS675X_DC_LDG_DCR_MSB_REG 0xD9 173 #define TAS675X_CH1_DC_LDG_DCR_LSB_REG 0xDA 174 #define TAS675X_CH2_DC_LDG_DCR_LSB_REG 0xDB 175 #define TAS675X_CH3_DC_LDG_DCR_LSB_REG 0xDC 176 #define TAS675X_CH4_DC_LDG_DCR_LSB_REG 0xDD 177 178 /* Over-Temperature Warning */ 179 #define TAS675X_OTW_CTRL_CH1_CH2_REG 0xE2 180 #define TAS675X_OTW_CTRL_CH3_CH4_REG 0xE3 181 182 /* RESET_REG (all bits auto-clear) */ 183 #define TAS675X_DEVICE_RESET BIT(4) 184 #define TAS675X_FAULT_CLEAR BIT(3) 185 #define TAS675X_REGISTER_RESET BIT(0) 186 187 /* STATE_CTRL and STATE_REPORT — Channel state values */ 188 #define TAS675X_STATE_DEEPSLEEP 0x00 189 #define TAS675X_STATE_LOAD_DIAG 0x01 190 #define TAS675X_STATE_SLEEP 0x02 191 #define TAS675X_STATE_HIZ 0x03 192 #define TAS675X_STATE_PLAY 0x04 193 194 /* Additional STATE_REPORT values */ 195 #define TAS675X_STATE_FAULT 0x05 196 #define TAS675X_STATE_AUTOREC 0x06 197 198 /* Combined values for both channel pairs in one register */ 199 #define TAS675X_STATE_DEEPSLEEP_BOTH \ 200 (TAS675X_STATE_DEEPSLEEP | (TAS675X_STATE_DEEPSLEEP << 4)) 201 #define TAS675X_STATE_LOAD_DIAG_BOTH \ 202 (TAS675X_STATE_LOAD_DIAG | (TAS675X_STATE_LOAD_DIAG << 4)) 203 #define TAS675X_STATE_SLEEP_BOTH \ 204 (TAS675X_STATE_SLEEP | (TAS675X_STATE_SLEEP << 4)) 205 #define TAS675X_STATE_HIZ_BOTH \ 206 (TAS675X_STATE_HIZ | (TAS675X_STATE_HIZ << 4)) 207 #define TAS675X_STATE_PLAY_BOTH \ 208 (TAS675X_STATE_PLAY | (TAS675X_STATE_PLAY << 4)) 209 #define TAS675X_STATE_FAULT_BOTH \ 210 (TAS675X_STATE_FAULT | (TAS675X_STATE_FAULT << 4)) 211 212 /* STATE_CTRL_CH1_CH2 / STATE_CTRL_CH3_CH4 — mute bits */ 213 #define TAS675X_CH1_MUTE_BIT BIT(7) 214 #define TAS675X_CH2_MUTE_BIT BIT(3) 215 #define TAS675X_CH_MUTE_BOTH (TAS675X_CH1_MUTE_BIT | TAS675X_CH2_MUTE_BIT) 216 217 /* SCLK_INV_CTRL_REG */ 218 #define TAS675X_SCLK_INV_TX_BIT BIT(5) 219 #define TAS675X_SCLK_INV_RX_BIT BIT(4) 220 #define TAS675X_SCLK_INV_MASK (TAS675X_SCLK_INV_TX_BIT | TAS675X_SCLK_INV_RX_BIT) 221 222 /* AUDIO_IF_CTRL_REG */ 223 #define TAS675X_TDM_EN_BIT BIT(4) 224 #define TAS675X_SAP_FMT_MASK GENMASK(3, 2) 225 #define TAS675X_SAP_FMT_I2S (0x00 << 2) 226 #define TAS675X_SAP_FMT_TDM (0x01 << 2) 227 #define TAS675X_SAP_FMT_RIGHT_J (0x02 << 2) 228 #define TAS675X_SAP_FMT_LEFT_J (0x03 << 2) 229 #define TAS675X_FS_PULSE_MASK GENMASK(1, 0) 230 #define TAS675X_FS_PULSE_SHORT 0x01 231 232 /* SDIN_CTRL_REG */ 233 #define TAS675X_SDIN_AUDIO_WL_MASK GENMASK(3, 2) 234 #define TAS675X_SDIN_LL_WL_MASK GENMASK(1, 0) 235 #define TAS675X_SDIN_WL_MASK (TAS675X_SDIN_AUDIO_WL_MASK | TAS675X_SDIN_LL_WL_MASK) 236 237 /* SDOUT_CTRL_REG */ 238 #define TAS675X_SDOUT_SELECT_MASK GENMASK(7, 4) 239 #define TAS675X_SDOUT_SELECT_TDM_SDOUT1 0x00 240 #define TAS675X_SDOUT_SELECT_NON_TDM 0x10 241 #define TAS675X_SDOUT_VP_WL_MASK GENMASK(3, 2) 242 #define TAS675X_SDOUT_IS_WL_MASK GENMASK(1, 0) 243 #define TAS675X_SDOUT_WL_MASK (TAS675X_SDOUT_VP_WL_MASK | TAS675X_SDOUT_IS_WL_MASK) 244 245 /* SDOUT_EN_REG */ 246 #define TAS675X_SDOUT_NON_TDM_SEL_MASK GENMASK(5, 4) 247 #define TAS675X_SDOUT_NON_TDM_SEL_VPREDICT (0x0 << 4) 248 #define TAS675X_SDOUT_NON_TDM_SEL_ISENSE (0x1 << 4) 249 #define TAS675X_SDOUT_EN_VPREDICT BIT(0) 250 #define TAS675X_SDOUT_EN_ISENSE BIT(1) 251 #define TAS675X_SDOUT_EN_NON_TDM_ALL GENMASK(1, 0) 252 253 /* Word length values (shared by SDIN_CTRL and SDOUT_CTRL) */ 254 #define TAS675X_WL_16BIT 0x00 255 #define TAS675X_WL_20BIT 0x01 256 #define TAS675X_WL_24BIT 0x02 257 #define TAS675X_WL_32BIT 0x03 258 259 /* SDIN_OFFSET_MSB_REG */ 260 #define TAS675X_SDIN_AUDIO_OFF_MSB_MASK GENMASK(7, 6) 261 #define TAS675X_SDIN_LL_OFF_MSB_MASK GENMASK(5, 4) 262 263 /* SDOUT_OFFSET_MSB_REG */ 264 #define TAS675X_SDOUT_VP_OFF_MSB_MASK GENMASK(7, 6) 265 #define TAS675X_SDOUT_IS_OFF_MSB_MASK GENMASK(5, 4) 266 267 /* RTLDG_EN_REG */ 268 #define TAS675X_RTLDG_CLIP_MASK_BIT BIT(4) 269 #define TAS675X_RTLDG_CH_EN_MASK GENMASK(3, 0) 270 271 /* DC_LDG_CTRL_REG */ 272 #define TAS675X_LDG_ABORT_BIT BIT(7) 273 #define TAS675X_LDG_BUFFER_WAIT_MASK GENMASK(6, 5) 274 #define TAS675X_LDG_WAIT_BYPASS_BIT BIT(2) 275 #define TAS675X_SLOL_DISABLE_BIT BIT(1) 276 #define TAS675X_LDG_BYPASS_BIT BIT(0) 277 278 /* DC_LDG_TIME_CTRL_REG */ 279 #define TAS675X_LDG_RAMP_SLOL_MASK GENMASK(7, 6) 280 #define TAS675X_LDG_SETTLING_SLOL_MASK GENMASK(5, 4) 281 #define TAS675X_LDG_RAMP_S2PG_MASK GENMASK(3, 2) 282 #define TAS675X_LDG_SETTLING_S2PG_MASK GENMASK(1, 0) 283 284 /* AC_LDG_CTRL_REG */ 285 #define TAS675X_AC_DIAG_GAIN_BIT BIT(4) 286 #define TAS675X_AC_DIAG_START_MASK GENMASK(3, 0) 287 288 /* DC_LDG_RESULT_REG */ 289 #define TAS675X_DC_LDG_LO_RESULT_MASK GENMASK(7, 4) 290 #define TAS675X_DC_LDG_PASS_MASK GENMASK(3, 0) 291 292 /* Load Diagnostics Timing Constants */ 293 #define TAS675X_POLL_INTERVAL_US 10000 294 #define TAS675X_STATE_TRANSITION_TIMEOUT_US 50000 295 #define TAS675X_DC_LDG_TIMEOUT_US 300000 296 #define TAS675X_AC_LDG_TIMEOUT_US 400000 297 298 /* GPIO_CTRL_REG */ 299 #define TAS675X_GPIO1_OUTPUT_EN BIT(7) 300 #define TAS675X_GPIO2_OUTPUT_EN BIT(6) 301 #define TAS675X_GPIO_CTRL_RSTVAL 0x22 302 303 /* GPIO output select values */ 304 #define TAS675X_GPIO_SEL_LOW 0x00 305 #define TAS675X_GPIO_SEL_AUTO_MUTE_ALL 0x02 306 #define TAS675X_GPIO_SEL_AUTO_MUTE_CH4 0x03 307 #define TAS675X_GPIO_SEL_AUTO_MUTE_CH3 0x04 308 #define TAS675X_GPIO_SEL_AUTO_MUTE_CH2 0x05 309 #define TAS675X_GPIO_SEL_AUTO_MUTE_CH1 0x06 310 #define TAS675X_GPIO_SEL_SDOUT2 0x08 311 #define TAS675X_GPIO_SEL_SDOUT1 0x09 312 #define TAS675X_GPIO_SEL_WARN 0x0A 313 #define TAS675X_GPIO_SEL_FAULT 0x0B 314 #define TAS675X_GPIO_SEL_CLOCK_SYNC 0x0E 315 #define TAS675X_GPIO_SEL_INVALID_CLK 0x0F 316 #define TAS675X_GPIO_SEL_HIGH 0x13 317 318 /* GPIO input function encoding (flag bit | function ID) */ 319 #define TAS675X_GPIO_FUNC_INPUT 0x100 320 321 /* Input Function IDs */ 322 #define TAS675X_GPIO_IN_ID_MUTE 0 323 #define TAS675X_GPIO_IN_ID_PHASE_SYNC 1 324 #define TAS675X_GPIO_IN_ID_SDIN2 2 325 #define TAS675X_GPIO_IN_ID_DEEP_SLEEP 3 326 #define TAS675X_GPIO_IN_ID_HIZ 4 327 #define TAS675X_GPIO_IN_ID_PLAY 5 328 #define TAS675X_GPIO_IN_ID_SLEEP 6 329 #define TAS675X_GPIO_IN_NUM 7 330 331 #define TAS675X_GPIO_IN_MUTE (TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_MUTE) 332 #define TAS675X_GPIO_IN_PHASE_SYNC \ 333 (TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_PHASE_SYNC) 334 #define TAS675X_GPIO_IN_SDIN2 (TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_SDIN2) 335 #define TAS675X_GPIO_IN_DEEP_SLEEP \ 336 (TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_DEEP_SLEEP) 337 #define TAS675X_GPIO_IN_HIZ (TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_HIZ) 338 #define TAS675X_GPIO_IN_PLAY (TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_PLAY) 339 #define TAS675X_GPIO_IN_SLEEP (TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_SLEEP) 340 341 /* GPIO input 3-bit mux field masks */ 342 #define TAS675X_GPIO_IN_MUTE_MASK GENMASK(2, 0) 343 #define TAS675X_GPIO_IN_SYNC_MASK GENMASK(2, 0) 344 #define TAS675X_GPIO_IN_SDIN2_MASK GENMASK(6, 4) 345 #define TAS675X_GPIO_IN_DEEP_SLEEP_MASK GENMASK(6, 4) 346 #define TAS675X_GPIO_IN_HIZ_MASK GENMASK(2, 0) 347 #define TAS675X_GPIO_IN_PLAY_MASK GENMASK(6, 4) 348 #define TAS675X_GPIO_IN_SLEEP_MASK GENMASK(2, 0) 349 350 /* Book addresses for tas675x_select_book() */ 351 #define TAS675X_BOOK_DEFAULT 0x00 352 #define TAS675X_BOOK_DSP 0x8C 353 354 /* DSP memory addresses (DSP Book) */ 355 #define TAS675X_DSP_PAGE_RTLDG 0x22 356 #define TAS675X_DSP_RTLDG_OL_THRESH_REG 0x98 357 #define TAS675X_DSP_RTLDG_SL_THRESH_REG 0x9C 358 359 #define TAS675X_DSP_PARAM_ID_OL_THRESH 0 360 #define TAS675X_DSP_PARAM_ID_SL_THRESH 1 361 362 /* Setup Mode Entry/Exit*/ 363 #define TAS675X_SETUP_ENTER_VAL1 0x11 364 #define TAS675X_SETUP_ENTER_VAL2 0xFF 365 #define TAS675X_SETUP_EXIT_VAL 0x00 366 367 #endif /* __TAS675X_H__ */ 368