1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ALSA SoC Texas Instruments TAS67524 Quad-Channel Audio Amplifier
4 *
5 * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
6 * Author: Sen Wang <sen@ti.com>
7 */
8
9 #include <linux/bitfield.h>
10 #include <linux/module.h>
11 #include <linux/mutex.h>
12 #include <linux/i2c.h>
13 #include <linux/regmap.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/delay.h>
17 #include <linux/property.h>
18 #include <linux/interrupt.h>
19 #include <linux/workqueue.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/iopoll.h>
22 #include <sound/soc.h>
23 #include <sound/tlv.h>
24 #include <sound/pcm_params.h>
25
26 #include "tas675x.h"
27
28 #define TAS675X_FAULT_CHECK_INTERVAL_MS 200
29
30 enum tas675x_type {
31 TAS67524,
32 };
33
34 struct tas675x_reg_param {
35 u8 page;
36 u8 reg;
37 u32 val;
38 };
39
40 struct tas675x_priv {
41 struct device *dev;
42 struct regmap *regmap;
43 enum tas675x_type dev_type;
44 /* Custom regmap lock; protects writes across books */
45 struct mutex io_lock;
46
47 struct gpio_desc *pd_gpio;
48 struct gpio_desc *stby_gpio;
49 struct regulator_bulk_data supplies[2];
50 struct regulator *vbat;
51 bool fast_boot;
52
53 int audio_slot;
54 int llp_slot;
55 int vpredict_slot;
56 int isense_slot;
57 int bclk_offset;
58 int slot_width;
59 unsigned int tx_mask;
60
61 int gpio1_func;
62 int gpio2_func;
63
64 unsigned long active_playback_dais;
65 unsigned long active_capture_dais;
66 unsigned int rate;
67 unsigned int saved_rtldg_en;
68 #define TAS675X_DSP_PARAM_NUM 2
69 struct tas675x_reg_param dsp_params[TAS675X_DSP_PARAM_NUM];
70
71 /* Fault monitor, disabled when Fault IRQ is used */
72 struct delayed_work fault_check_work;
73 #define TAS675X_FAULT_REGS_NUM 9
74 unsigned int last_status[TAS675X_FAULT_REGS_NUM];
75 };
76
77 static const char * const tas675x_supply_names[] = {
78 "dvdd", /* Digital power supply */
79 "pvdd", /* Output powerstage supply */
80 };
81
82 /* Page 1 setup initialization defaults */
83 static const struct reg_sequence tas675x_page1_init[] = {
84 REG_SEQ0(TAS675X_PAGE_REG(1, 0xC8), 0x20), /* Charge pump clock */
85 REG_SEQ0(TAS675X_PAGE_REG(1, 0x2F), 0x90), /* VBAT idle */
86 REG_SEQ0(TAS675X_PAGE_REG(1, 0x29), 0x40), /* OC/CBC threshold */
87 REG_SEQ0(TAS675X_PAGE_REG(1, 0x2E), 0x0C), /* OC/CBC config */
88 REG_SEQ0(TAS675X_PAGE_REG(1, 0xC5), 0x02), /* OC/CBC config */
89 REG_SEQ0(TAS675X_PAGE_REG(1, 0xC6), 0x10), /* OC/CBC config */
90 REG_SEQ0(TAS675X_PAGE_REG(1, 0x1F), 0x20), /* OC/CBC config */
91 REG_SEQ0(TAS675X_PAGE_REG(1, 0x16), 0x01), /* OC/CBC config */
92 REG_SEQ0(TAS675X_PAGE_REG(1, 0x1E), 0x04), /* OC/CBC config */
93 REG_SEQ0(TAS675X_PAGE_REG(1, 0xC1), 0x00), /* CH1 DC fault */
94 REG_SEQ0(TAS675X_PAGE_REG(1, 0xC2), 0x04), /* CH2 DC fault */
95 REG_SEQ0(TAS675X_PAGE_REG(1, 0xC3), 0x00), /* CH3 DC fault */
96 REG_SEQ0(TAS675X_PAGE_REG(1, 0xC4), 0x00), /* CH4 DC fault */
97 };
98
tas675x_state_name(unsigned int state)99 static inline const char *tas675x_state_name(unsigned int state)
100 {
101 switch (state & 0x0F) {
102 case TAS675X_STATE_DEEPSLEEP: return "DEEPSLEEP";
103 case TAS675X_STATE_LOAD_DIAG: return "LOAD_DIAG";
104 case TAS675X_STATE_SLEEP: return "SLEEP";
105 case TAS675X_STATE_HIZ: return "HIZ";
106 case TAS675X_STATE_PLAY: return "PLAY";
107 case TAS675X_STATE_FAULT: return "FAULT";
108 case TAS675X_STATE_AUTOREC: return "AUTOREC";
109 default: return "UNKNOWN";
110 }
111 }
112
tas675x_set_state_all(struct tas675x_priv * tas,u8 state)113 static inline int tas675x_set_state_all(struct tas675x_priv *tas, u8 state)
114 {
115 const struct reg_sequence seq[] = {
116 REG_SEQ0(TAS675X_STATE_CTRL_CH1_CH2_REG, state),
117 REG_SEQ0(TAS675X_STATE_CTRL_CH3_CH4_REG, state),
118 };
119
120 return regmap_multi_reg_write(tas->regmap, seq, ARRAY_SIZE(seq));
121 }
122
tas675x_select_book(struct regmap * regmap,u8 book)123 static inline int tas675x_select_book(struct regmap *regmap, u8 book)
124 {
125 int ret;
126
127 /* Reset page to 0 before switching books */
128 ret = regmap_write(regmap, TAS675X_PAGE_CTRL_REG, 0x00);
129 if (!ret)
130 ret = regmap_write(regmap, TAS675X_BOOK_CTRL_REG, book);
131
132 return ret;
133 }
134
135 /* Raw I2C version of tas675x_select_book, must be called with io_lock held */
__tas675x_select_book(struct tas675x_priv * tas,u8 book)136 static inline int __tas675x_select_book(struct tas675x_priv *tas, u8 book)
137 {
138 struct i2c_client *client = to_i2c_client(tas->dev);
139 int ret;
140
141 /* Reset page to 0 before switching books */
142 ret = i2c_smbus_write_byte_data(client, TAS675X_PAGE_CTRL_REG, 0x00);
143 if (ret)
144 return ret;
145
146 return i2c_smbus_write_byte_data(client, TAS675X_BOOK_CTRL_REG, book);
147 }
148
tas675x_dsp_mem_write(struct tas675x_priv * tas,u8 page,u8 reg,u32 val)149 static int tas675x_dsp_mem_write(struct tas675x_priv *tas, u8 page, u8 reg, u32 val)
150 {
151 struct i2c_client *client = to_i2c_client(tas->dev);
152 u8 buf[4];
153 int ret;
154
155 /* DSP registers are 32 bit big-endian */
156 buf[0] = (val >> 24) & 0xFF;
157 buf[1] = (val >> 16) & 0xFF;
158 buf[2] = (val >> 8) & 0xFF;
159 buf[3] = val & 0xFF;
160
161 /*
162 * DSP regs in a different book, therefore block
163 * regmap access before completion.
164 */
165 mutex_lock(&tas->io_lock);
166
167 ret = __tas675x_select_book(tas, TAS675X_BOOK_DSP);
168 if (ret)
169 goto out;
170
171 ret = i2c_smbus_write_byte_data(client, TAS675X_PAGE_CTRL_REG, page);
172 if (ret)
173 goto out;
174
175 ret = i2c_smbus_write_i2c_block_data(client, reg, sizeof(buf), buf);
176
177 out:
178 __tas675x_select_book(tas, TAS675X_BOOK_DEFAULT);
179 mutex_unlock(&tas->io_lock);
180
181 return ret;
182 }
183
tas675x_dsp_mem_read(struct tas675x_priv * tas,u8 page,u8 reg,u32 * val)184 static int tas675x_dsp_mem_read(struct tas675x_priv *tas, u8 page, u8 reg, u32 *val)
185 {
186 struct i2c_client *client = to_i2c_client(tas->dev);
187 u8 buf[4];
188 int ret;
189
190 /*
191 * DSP regs in a different book, therefore block
192 * regmap access before completion.
193 */
194 mutex_lock(&tas->io_lock);
195
196 ret = __tas675x_select_book(tas, TAS675X_BOOK_DSP);
197 if (ret)
198 goto out;
199
200 ret = i2c_smbus_write_byte_data(client, TAS675X_PAGE_CTRL_REG, page);
201 if (ret)
202 goto out;
203
204 ret = i2c_smbus_read_i2c_block_data(client, reg, sizeof(buf), buf);
205 if (ret == sizeof(buf)) {
206 *val = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
207 ret = 0;
208 } else if (ret >= 0) {
209 ret = -EIO;
210 }
211
212 out:
213 __tas675x_select_book(tas, TAS675X_BOOK_DEFAULT);
214 mutex_unlock(&tas->io_lock);
215
216 return ret;
217 }
218
219 static const struct {
220 const char *name;
221 int val;
222 } tas675x_gpio_func_map[] = {
223 /* Output functions */
224 { "low", TAS675X_GPIO_SEL_LOW },
225 { "auto-mute", TAS675X_GPIO_SEL_AUTO_MUTE_ALL },
226 { "auto-mute-ch4", TAS675X_GPIO_SEL_AUTO_MUTE_CH4 },
227 { "auto-mute-ch3", TAS675X_GPIO_SEL_AUTO_MUTE_CH3 },
228 { "auto-mute-ch2", TAS675X_GPIO_SEL_AUTO_MUTE_CH2 },
229 { "auto-mute-ch1", TAS675X_GPIO_SEL_AUTO_MUTE_CH1 },
230 { "sdout2", TAS675X_GPIO_SEL_SDOUT2 },
231 { "sdout1", TAS675X_GPIO_SEL_SDOUT1 },
232 { "warn", TAS675X_GPIO_SEL_WARN },
233 { "fault", TAS675X_GPIO_SEL_FAULT },
234 { "clock-sync", TAS675X_GPIO_SEL_CLOCK_SYNC },
235 { "invalid-clock", TAS675X_GPIO_SEL_INVALID_CLK },
236 { "high", TAS675X_GPIO_SEL_HIGH },
237 /* Input functions */
238 { "mute", TAS675X_GPIO_IN_MUTE },
239 { "phase-sync", TAS675X_GPIO_IN_PHASE_SYNC },
240 { "sdin2", TAS675X_GPIO_IN_SDIN2 },
241 { "deep-sleep", TAS675X_GPIO_IN_DEEP_SLEEP },
242 { "hiz", TAS675X_GPIO_IN_HIZ },
243 { "play", TAS675X_GPIO_IN_PLAY },
244 { "sleep", TAS675X_GPIO_IN_SLEEP },
245 };
246
tas675x_gpio_func_parse(struct device * dev,const char * propname)247 static int tas675x_gpio_func_parse(struct device *dev, const char *propname)
248 {
249 const char *str;
250 int i, ret;
251
252 ret = device_property_read_string(dev, propname, &str);
253 if (ret)
254 return -1;
255
256 for (i = 0; i < ARRAY_SIZE(tas675x_gpio_func_map); i++) {
257 if (!strcmp(str, tas675x_gpio_func_map[i].name))
258 return tas675x_gpio_func_map[i].val;
259 }
260
261 dev_warn(dev, "Invalid %s value '%s'\n", propname, str);
262 return -1;
263 }
264
265 static const struct {
266 unsigned int reg;
267 unsigned int mask;
268 } tas675x_gpio_input_table[TAS675X_GPIO_IN_NUM] = {
269 [TAS675X_GPIO_IN_ID_MUTE] = {
270 TAS675X_GPIO_INPUT_MUTE_REG, TAS675X_GPIO_IN_MUTE_MASK },
271 [TAS675X_GPIO_IN_ID_PHASE_SYNC] = {
272 TAS675X_GPIO_INPUT_SYNC_REG, TAS675X_GPIO_IN_SYNC_MASK },
273 [TAS675X_GPIO_IN_ID_SDIN2] = {
274 TAS675X_GPIO_INPUT_SDIN2_REG, TAS675X_GPIO_IN_SDIN2_MASK },
275 [TAS675X_GPIO_IN_ID_DEEP_SLEEP] = {
276 TAS675X_GPIO_INPUT_SLEEP_HIZ_REG, TAS675X_GPIO_IN_DEEP_SLEEP_MASK },
277 [TAS675X_GPIO_IN_ID_HIZ] = {
278 TAS675X_GPIO_INPUT_SLEEP_HIZ_REG, TAS675X_GPIO_IN_HIZ_MASK },
279 [TAS675X_GPIO_IN_ID_PLAY] = {
280 TAS675X_GPIO_INPUT_PLAY_SLEEP_REG, TAS675X_GPIO_IN_PLAY_MASK },
281 [TAS675X_GPIO_IN_ID_SLEEP] = {
282 TAS675X_GPIO_INPUT_PLAY_SLEEP_REG, TAS675X_GPIO_IN_SLEEP_MASK },
283 };
284
tas675x_config_gpio_pin(struct regmap * regmap,int func_id,unsigned int out_sel_reg,unsigned int pin_idx,unsigned int * gpio_ctrl)285 static void tas675x_config_gpio_pin(struct regmap *regmap, int func_id,
286 unsigned int out_sel_reg,
287 unsigned int pin_idx,
288 unsigned int *gpio_ctrl)
289 {
290 int id;
291
292 if (func_id < 0)
293 return;
294
295 if (func_id & TAS675X_GPIO_FUNC_INPUT) {
296 /* 3-bit mux: 0 = disabled, 0b1 = GPIO1, 0b10 = GPIO2 */
297 id = func_id & ~TAS675X_GPIO_FUNC_INPUT;
298 regmap_update_bits(regmap,
299 tas675x_gpio_input_table[id].reg,
300 tas675x_gpio_input_table[id].mask,
301 (pin_idx + 1) << __ffs(tas675x_gpio_input_table[id].mask));
302 } else {
303 /* Output GPIO, update selection register and enable bit */
304 regmap_write(regmap, out_sel_reg, func_id);
305 *gpio_ctrl |= pin_idx ? TAS675X_GPIO2_OUTPUT_EN : TAS675X_GPIO1_OUTPUT_EN;
306 }
307 }
308
tas675x_rtldg_thresh_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)309 static int tas675x_rtldg_thresh_info(struct snd_kcontrol *kcontrol,
310 struct snd_ctl_elem_info *uinfo)
311 {
312 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
313 uinfo->count = 1;
314 uinfo->value.integer.min = 0;
315 /* threshold reg ranges up to 24bit */
316 uinfo->value.integer.max = 0x00FFFFFF;
317 return 0;
318 }
319
tas675x_set_rtldg_thresh(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)320 static int tas675x_set_rtldg_thresh(struct snd_kcontrol *kcontrol,
321 struct snd_ctl_elem_value *ucontrol)
322 {
323 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
324 struct tas675x_priv *tas = snd_soc_component_get_drvdata(comp);
325 const struct tas675x_reg_param *t =
326 (const struct tas675x_reg_param *)kcontrol->private_value;
327 u32 val = ucontrol->value.integer.value[0];
328 int ret;
329
330 ret = tas675x_dsp_mem_write(tas, t->page, t->reg, val);
331
332 /* Cache the value */
333 if (!ret) {
334 int i;
335
336 for (i = 0; i < ARRAY_SIZE(tas->dsp_params); i++) {
337 if (tas->dsp_params[i].page == t->page &&
338 tas->dsp_params[i].reg == t->reg) {
339 tas->dsp_params[i].val = val;
340 break;
341 }
342 }
343 }
344
345 /* Return 1 to notify change, or propagate error */
346 return ret ? ret : 1;
347 }
348
tas675x_get_rtldg_thresh(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)349 static int tas675x_get_rtldg_thresh(struct snd_kcontrol *kcontrol,
350 struct snd_ctl_elem_value *ucontrol)
351 {
352 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
353 struct tas675x_priv *tas = snd_soc_component_get_drvdata(comp);
354 const struct tas675x_reg_param *t =
355 (const struct tas675x_reg_param *)kcontrol->private_value;
356 u32 val = 0;
357 int ret;
358
359 ret = tas675x_dsp_mem_read(tas, t->page, t->reg, &val);
360 if (!ret)
361 ucontrol->value.integer.value[0] = val;
362
363 return ret;
364 }
365
366 static const struct tas675x_reg_param tas675x_dsp_defaults[] = {
367 [TAS675X_DSP_PARAM_ID_OL_THRESH] = {
368 TAS675X_DSP_PAGE_RTLDG, TAS675X_DSP_RTLDG_OL_THRESH_REG },
369 [TAS675X_DSP_PARAM_ID_SL_THRESH] = {
370 TAS675X_DSP_PAGE_RTLDG, TAS675X_DSP_RTLDG_SL_THRESH_REG },
371 };
372
373 static_assert(ARRAY_SIZE(tas675x_dsp_defaults) == TAS675X_DSP_PARAM_NUM);
374
tas675x_set_dcldg_trigger(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)375 static int tas675x_set_dcldg_trigger(struct snd_kcontrol *kcontrol,
376 struct snd_ctl_elem_value *ucontrol)
377 {
378 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
379 struct tas675x_priv *tas = snd_soc_component_get_drvdata(comp);
380 unsigned int state, state34;
381 int ret;
382
383 if (!ucontrol->value.integer.value[0])
384 return 0;
385
386 if (snd_soc_component_active(comp))
387 return -EBUSY;
388
389 ret = pm_runtime_resume_and_get(tas->dev);
390 if (ret < 0)
391 return ret;
392
393 /*
394 * Abort automatic DC LDG retry loops (startup or init-after-fault)
395 * and clear faults before manual diagnostics.
396 */
397 regmap_update_bits(tas->regmap, TAS675X_DC_LDG_CTRL_REG,
398 TAS675X_LDG_ABORT_BIT | TAS675X_LDG_BYPASS_BIT,
399 TAS675X_LDG_ABORT_BIT | TAS675X_LDG_BYPASS_BIT);
400 regmap_write(tas->regmap, TAS675X_RESET_REG, TAS675X_FAULT_CLEAR);
401
402 /* Wait for LOAD_DIAG to exit */
403 ret = regmap_read_poll_timeout(tas->regmap, TAS675X_STATE_REPORT_CH1_CH2_REG,
404 state, (state & 0x0F) != TAS675X_STATE_LOAD_DIAG &&
405 (state >> 4) != TAS675X_STATE_LOAD_DIAG,
406 TAS675X_POLL_INTERVAL_US,
407 TAS675X_STATE_TRANSITION_TIMEOUT_US);
408 ret |= regmap_read_poll_timeout(tas->regmap, TAS675X_STATE_REPORT_CH3_CH4_REG,
409 state34, (state34 & 0x0F) != TAS675X_STATE_LOAD_DIAG &&
410 (state34 >> 4) != TAS675X_STATE_LOAD_DIAG,
411 TAS675X_POLL_INTERVAL_US,
412 TAS675X_STATE_TRANSITION_TIMEOUT_US);
413 if (ret) {
414 dev_err(tas->dev,
415 "DC LDG: abort timeout (CH1/2=0x%02x [%s/%s], CH3/4=0x%02x [%s/%s])\n",
416 state, tas675x_state_name(state), tas675x_state_name(state >> 4),
417 state34, tas675x_state_name(state34), tas675x_state_name(state34 >> 4));
418 goto out_restore_ldg_ctrl;
419 }
420
421 /* Transition to HIZ state */
422 ret = tas675x_set_state_all(tas, TAS675X_STATE_HIZ_BOTH);
423 if (ret)
424 goto out_restore_ldg_ctrl;
425
426 /* Set LOAD_DIAG state for manual DC LDG */
427 ret = tas675x_set_state_all(tas, TAS675X_STATE_LOAD_DIAG_BOTH);
428 if (ret)
429 goto out_restore_ldg_ctrl;
430
431 /* Wait for device to transition to LOAD_DIAG state */
432 ret = regmap_read_poll_timeout(tas->regmap, TAS675X_STATE_REPORT_CH1_CH2_REG,
433 state, state == TAS675X_STATE_LOAD_DIAG_BOTH,
434 TAS675X_POLL_INTERVAL_US,
435 TAS675X_STATE_TRANSITION_TIMEOUT_US);
436 ret |= regmap_read_poll_timeout(tas->regmap, TAS675X_STATE_REPORT_CH3_CH4_REG,
437 state34, state34 == TAS675X_STATE_LOAD_DIAG_BOTH,
438 TAS675X_POLL_INTERVAL_US,
439 TAS675X_STATE_TRANSITION_TIMEOUT_US);
440 if (ret) {
441 dev_err(tas->dev,
442 "DC LDG: LOAD_DIAG timeout (CH1/2=0x%02x [%s/%s], CH3/4=0x%02x [%s/%s])\n",
443 state, tas675x_state_name(state), tas675x_state_name(state >> 4),
444 state34, tas675x_state_name(state34), tas675x_state_name(state34 >> 4));
445 goto out_restore_hiz;
446 }
447
448 /* Clear ABORT and BYPASS bits to enable manual DC LDG */
449 ret = regmap_update_bits(tas->regmap, TAS675X_DC_LDG_CTRL_REG,
450 TAS675X_LDG_ABORT_BIT | TAS675X_LDG_BYPASS_BIT,
451 0);
452 if (ret)
453 goto out_restore_hiz;
454
455 dev_dbg(tas->dev, "DC LDG: Started\n");
456
457 /* Poll all channels for SLEEP state */
458 ret = regmap_read_poll_timeout(tas->regmap, TAS675X_STATE_REPORT_CH1_CH2_REG,
459 state, state == TAS675X_STATE_SLEEP_BOTH,
460 TAS675X_POLL_INTERVAL_US,
461 TAS675X_DC_LDG_TIMEOUT_US);
462 ret |= regmap_read_poll_timeout(tas->regmap, TAS675X_STATE_REPORT_CH3_CH4_REG,
463 state34, state34 == TAS675X_STATE_SLEEP_BOTH,
464 TAS675X_POLL_INTERVAL_US,
465 TAS675X_DC_LDG_TIMEOUT_US);
466 if (ret) {
467 dev_err(tas->dev,
468 "DC LDG: SLEEP timeout (CH1/2=0x%02x [%s/%s], CH3/4=0x%02x [%s/%s])\n",
469 state, tas675x_state_name(state), tas675x_state_name(state >> 4),
470 state34, tas675x_state_name(state34), tas675x_state_name(state34 >> 4));
471 goto out_restore_hiz;
472 }
473
474 dev_dbg(tas->dev, "DC LDG: Completed successfully (CH1/2=0x%02x, CH3/4=0x%02x)\n",
475 state, state34);
476
477 out_restore_hiz:
478 tas675x_set_state_all(tas, TAS675X_STATE_HIZ_BOTH);
479
480 out_restore_ldg_ctrl:
481 regmap_update_bits(tas->regmap, TAS675X_DC_LDG_CTRL_REG,
482 TAS675X_LDG_ABORT_BIT | TAS675X_LDG_BYPASS_BIT,
483 0);
484
485 pm_runtime_mark_last_busy(tas->dev);
486 pm_runtime_put_autosuspend(tas->dev);
487
488 return ret;
489 }
490
tas675x_set_acldg_trigger(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)491 static int tas675x_set_acldg_trigger(struct snd_kcontrol *kcontrol,
492 struct snd_ctl_elem_value *ucontrol)
493 {
494 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
495 struct tas675x_priv *tas = snd_soc_component_get_drvdata(comp);
496 unsigned int state, state34;
497 int ret;
498
499 if (!ucontrol->value.integer.value[0])
500 return 0;
501
502 if (snd_soc_component_active(comp))
503 return -EBUSY;
504
505 ret = pm_runtime_resume_and_get(tas->dev);
506 if (ret < 0)
507 return ret;
508
509 /* AC Load Diagnostics requires SLEEP state */
510 ret = tas675x_set_state_all(tas, TAS675X_STATE_SLEEP_BOTH);
511 if (ret) {
512 dev_err(tas->dev, "AC LDG: Failed to set SLEEP state: %d\n", ret);
513 goto out;
514 }
515
516 /* Start AC LDG on all 4 channels (0x0F) */
517 ret = regmap_write(tas->regmap, TAS675X_AC_LDG_CTRL_REG, 0x0F);
518 if (ret) {
519 dev_err(tas->dev, "AC LDG: Failed to start: %d\n", ret);
520 goto out;
521 }
522
523 dev_dbg(tas->dev, "AC LDG: Started\n");
524
525 /* Poll all channels for SLEEP state */
526 ret = regmap_read_poll_timeout(tas->regmap, TAS675X_STATE_REPORT_CH1_CH2_REG,
527 state, (state == TAS675X_STATE_SLEEP_BOTH),
528 TAS675X_POLL_INTERVAL_US,
529 TAS675X_AC_LDG_TIMEOUT_US);
530 if (ret) {
531 dev_err(tas->dev,
532 "AC LDG: CH1/CH2 timeout: %d (state=0x%02x [%s/%s])\n",
533 ret, state, tas675x_state_name(state),
534 tas675x_state_name(state >> 4));
535 regmap_write(tas->regmap, TAS675X_AC_LDG_CTRL_REG, 0x00);
536 goto out;
537 }
538
539 ret = regmap_read_poll_timeout(tas->regmap, TAS675X_STATE_REPORT_CH3_CH4_REG,
540 state34, (state34 == TAS675X_STATE_SLEEP_BOTH),
541 TAS675X_POLL_INTERVAL_US,
542 TAS675X_AC_LDG_TIMEOUT_US);
543 if (ret) {
544 dev_err(tas->dev,
545 "AC LDG: CH3/CH4 timeout: %d (state=0x%02x [%s/%s])\n",
546 ret, state34, tas675x_state_name(state34),
547 tas675x_state_name(state34 >> 4));
548 regmap_write(tas->regmap, TAS675X_AC_LDG_CTRL_REG, 0x00);
549 goto out;
550 }
551
552 dev_dbg(tas->dev, "AC LDG: Completed successfully (CH1/2=0x%02x, CH3/4=0x%02x)\n",
553 state, state34);
554 regmap_write(tas->regmap, TAS675X_AC_LDG_CTRL_REG, 0x00);
555
556 out:
557 pm_runtime_mark_last_busy(tas->dev);
558 pm_runtime_put_autosuspend(tas->dev);
559
560 return ret;
561 }
562
tas675x_rtldg_impedance_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)563 static int tas675x_rtldg_impedance_info(struct snd_kcontrol *kcontrol,
564 struct snd_ctl_elem_info *uinfo)
565 {
566 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
567 uinfo->count = 1;
568 uinfo->value.integer.min = 0;
569 uinfo->value.integer.max = 0xFFFF;
570 return 0;
571 }
572
tas675x_get_rtldg_impedance(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)573 static int tas675x_get_rtldg_impedance(struct snd_kcontrol *kcontrol,
574 struct snd_ctl_elem_value *ucontrol)
575 {
576 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
577 struct tas675x_priv *tas = snd_soc_component_get_drvdata(comp);
578 unsigned int msb_reg = (unsigned int)kcontrol->private_value;
579 u8 buf[2];
580 int ret;
581
582 ret = regmap_bulk_read(tas->regmap, msb_reg, buf, 2);
583 if (ret)
584 return ret;
585
586 ucontrol->value.integer.value[0] = (buf[0] << 8) | buf[1];
587 return 0;
588 }
589
tas675x_dc_resistance_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)590 static int tas675x_dc_resistance_info(struct snd_kcontrol *kcontrol,
591 struct snd_ctl_elem_info *uinfo)
592 {
593 /* 10-bit: 2-bit MSB + 8-bit LSB, 0.1 ohm/code, 0-102.3 ohm */
594 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
595 uinfo->count = 1;
596 uinfo->value.integer.min = 0;
597 uinfo->value.integer.max = 1023;
598 return 0;
599 }
600
tas675x_get_dc_resistance(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)601 static int tas675x_get_dc_resistance(struct snd_kcontrol *kcontrol,
602 struct snd_ctl_elem_value *ucontrol)
603 {
604 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
605 struct tas675x_priv *tas = snd_soc_component_get_drvdata(comp);
606 unsigned int lsb_reg = (unsigned int)kcontrol->private_value;
607 unsigned int msb, lsb, shift;
608 int ret;
609
610 ret = regmap_read(tas->regmap, TAS675X_DC_LDG_DCR_MSB_REG, &msb);
611 if (ret)
612 return ret;
613
614 ret = regmap_read(tas->regmap, lsb_reg, &lsb);
615 if (ret)
616 return ret;
617
618 /* 2-bit MSB: CH1=[7:6], CH2=[5:4], CH3=[3:2], CH4=[1:0] */
619 shift = 6 - (lsb_reg - TAS675X_CH1_DC_LDG_DCR_LSB_REG) * 2;
620 msb = (msb >> shift) & 0x3;
621
622 ucontrol->value.integer.value[0] = (msb << 8) | lsb;
623 return 0;
624 }
625
626 /* Counterparts with read-only access */
627 #define SOC_SINGLE_RO(xname, xreg, xshift, xmax) \
628 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
629 .name = xname, \
630 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
631 .info = snd_soc_info_volsw, \
632 .get = snd_soc_get_volsw, \
633 .private_value = SOC_SINGLE_VALUE(xreg, xshift, 0, xmax, 0, 0) }
634 #define SOC_DC_RESIST_RO(xname, xlsb_reg) \
635 { .name = xname, \
636 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
637 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
638 .info = tas675x_dc_resistance_info, \
639 .get = tas675x_get_dc_resistance, \
640 .private_value = (xlsb_reg) }
641 #define SOC_RTLDG_IMP_RO(xname, xreg) \
642 { .name = xname, \
643 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
644 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
645 .info = tas675x_rtldg_impedance_info, \
646 .get = tas675x_get_rtldg_impedance, \
647 .private_value = (xreg) }
648
649 #define SOC_DSP_THRESH_EXT(xname, xthresh) \
650 { .name = xname, \
651 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
652 .info = tas675x_rtldg_thresh_info, \
653 .get = tas675x_get_rtldg_thresh, \
654 .put = tas675x_set_rtldg_thresh, \
655 .private_value = (unsigned long)&(xthresh) }
656
657 /*
658 * DAC digital volumes. From -103 to 0 dB in 0.5 dB steps, -103.5 dB means mute.
659 * DAC analog gain. From -15.5 to 0 dB in 0.5 dB steps, no mute.
660 */
661 static const DECLARE_TLV_DB_SCALE(tas675x_dig_vol_tlv, -10350, 50, 1);
662 static const DECLARE_TLV_DB_SCALE(tas675x_ana_gain_tlv, -1550, 50, 0);
663
664 static const char * const tas675x_ss_texts[] = {
665 "Disabled", "Triangle", "Random", "Triangle and Random"
666 };
667
668 static SOC_ENUM_SINGLE_DECL(tas675x_ss_enum, TAS675X_SS_CTRL_REG, 0, tas675x_ss_texts);
669
670 static const char * const tas675x_ss_tri_range_texts[] = {
671 "6.5%", "13.5%", "5%", "10%"
672 };
673
674 static SOC_ENUM_SINGLE_DECL(tas675x_ss_tri_range_enum,
675 TAS675X_SS_RANGE_CTRL_REG, 0,
676 tas675x_ss_tri_range_texts);
677
678 static const char * const tas675x_ss_rdm_range_texts[] = {
679 "0.83%", "2.50%", "5.83%", "12.50%", "25.83%"
680 };
681
682 static SOC_ENUM_SINGLE_DECL(tas675x_ss_rdm_range_enum,
683 TAS675X_SS_RANGE_CTRL_REG, 4,
684 tas675x_ss_rdm_range_texts);
685
686 static const char * const tas675x_ss_rdm_dwell_texts[] = {
687 "1/FSS to 2/FSS", "1/FSS to 4/FSS", "1/FSS to 8/FSS", "1/FSS to 15/FSS"
688 };
689
690 static SOC_ENUM_SINGLE_DECL(tas675x_ss_rdm_dwell_enum,
691 TAS675X_SS_RANGE_CTRL_REG, 2,
692 tas675x_ss_rdm_dwell_texts);
693
694 static const char * const tas675x_oc_limit_texts[] = {
695 "Level 4", "Level 3", "Level 2", "Level 1"
696 };
697
698 static SOC_ENUM_SINGLE_DECL(tas675x_oc_limit_enum, TAS675X_CURRENT_LIMIT_CTRL_REG,
699 0, tas675x_oc_limit_texts);
700
701 static const char * const tas675x_otw_texts[] = {
702 "Disabled", ">95C", ">110C", ">125C", ">135C", ">145C", ">155C", ">165C"
703 };
704
705 static SOC_ENUM_SINGLE_DECL(tas675x_ch1_otw_enum,
706 TAS675X_OTW_CTRL_CH1_CH2_REG, 4,
707 tas675x_otw_texts);
708 static SOC_ENUM_SINGLE_DECL(tas675x_ch2_otw_enum,
709 TAS675X_OTW_CTRL_CH1_CH2_REG, 0,
710 tas675x_otw_texts);
711 static SOC_ENUM_SINGLE_DECL(tas675x_ch3_otw_enum,
712 TAS675X_OTW_CTRL_CH3_CH4_REG, 4,
713 tas675x_otw_texts);
714 static SOC_ENUM_SINGLE_DECL(tas675x_ch4_otw_enum,
715 TAS675X_OTW_CTRL_CH3_CH4_REG, 0,
716 tas675x_otw_texts);
717
718 static const char * const tas675x_dc_ldg_sl_texts[] = {
719 "0.5 Ohm", "1 Ohm", "1.5 Ohm", "2 Ohm", "2.5 Ohm",
720 "3 Ohm", "3.5 Ohm", "4 Ohm", "4.5 Ohm", "5 Ohm"
721 };
722
723 static SOC_ENUM_SINGLE_DECL(tas675x_ch1_dc_ldg_sl_enum,
724 TAS675X_DC_LDG_SL_CH1_CH2_CTRL_REG, 4,
725 tas675x_dc_ldg_sl_texts);
726 static SOC_ENUM_SINGLE_DECL(tas675x_ch2_dc_ldg_sl_enum,
727 TAS675X_DC_LDG_SL_CH1_CH2_CTRL_REG, 0,
728 tas675x_dc_ldg_sl_texts);
729 static SOC_ENUM_SINGLE_DECL(tas675x_ch3_dc_ldg_sl_enum,
730 TAS675X_DC_LDG_SL_CH3_CH4_CTRL_REG, 4,
731 tas675x_dc_ldg_sl_texts);
732 static SOC_ENUM_SINGLE_DECL(tas675x_ch4_dc_ldg_sl_enum,
733 TAS675X_DC_LDG_SL_CH3_CH4_CTRL_REG, 0,
734 tas675x_dc_ldg_sl_texts);
735
736 static const char * const tas675x_dc_slol_ramp_texts[] = {
737 "15 ms", "30 ms", "10 ms", "20 ms"
738 };
739
740 static SOC_ENUM_SINGLE_DECL(tas675x_dc_slol_ramp_enum,
741 TAS675X_DC_LDG_TIME_CTRL_REG, 6,
742 tas675x_dc_slol_ramp_texts);
743
744 static const char * const tas675x_dc_slol_settling_texts[] = {
745 "10 ms", "5 ms", "20 ms", "15 ms"
746 };
747
748 static SOC_ENUM_SINGLE_DECL(tas675x_dc_slol_settling_enum,
749 TAS675X_DC_LDG_TIME_CTRL_REG, 4,
750 tas675x_dc_slol_settling_texts);
751
752 static const char * const tas675x_dc_s2pg_ramp_texts[] = {
753 "5 ms", "2.5 ms", "10 ms", "15 ms"
754 };
755
756 static SOC_ENUM_SINGLE_DECL(tas675x_dc_s2pg_ramp_enum,
757 TAS675X_DC_LDG_TIME_CTRL_REG, 2,
758 tas675x_dc_s2pg_ramp_texts);
759
760 static const char * const tas675x_dc_s2pg_settling_texts[] = {
761 "10 ms", "5 ms", "20 ms", "30 ms"
762 };
763
764 static SOC_ENUM_SINGLE_DECL(tas675x_dc_s2pg_settling_enum,
765 TAS675X_DC_LDG_TIME_CTRL_REG, 0,
766 tas675x_dc_s2pg_settling_texts);
767
768 static const char * const tas675x_dsp_mode_texts[] = {
769 "Normal", "LLP", "FFLP"
770 };
771
772 static SOC_ENUM_SINGLE_DECL(tas675x_dsp_mode_enum,
773 TAS675X_LL_EN_REG, 0,
774 tas675x_dsp_mode_texts);
775
776 static const char * const tas675x_ana_ramp_texts[] = {
777 "15us", "60us", "200us", "400us"
778 };
779
780 static SOC_ENUM_SINGLE_DECL(tas675x_ana_ramp_enum,
781 TAS675X_ANALOG_GAIN_RAMP_CTRL_REG, 2,
782 tas675x_ana_ramp_texts);
783
784 static const char * const tas675x_ramp_rate_texts[] = {
785 "4 FS", "16 FS", "32 FS", "Instant"
786 };
787
788 static SOC_ENUM_SINGLE_DECL(tas675x_ramp_down_rate_enum,
789 TAS675X_DIG_VOL_RAMP_CTRL_REG, 6,
790 tas675x_ramp_rate_texts);
791 static SOC_ENUM_SINGLE_DECL(tas675x_ramp_up_rate_enum,
792 TAS675X_DIG_VOL_RAMP_CTRL_REG, 2,
793 tas675x_ramp_rate_texts);
794
795 static const char * const tas675x_ramp_step_texts[] = {
796 "4dB", "2dB", "1dB", "0.5dB"
797 };
798
799 static SOC_ENUM_SINGLE_DECL(tas675x_ramp_down_step_enum,
800 TAS675X_DIG_VOL_RAMP_CTRL_REG, 4,
801 tas675x_ramp_step_texts);
802 static SOC_ENUM_SINGLE_DECL(tas675x_ramp_up_step_enum,
803 TAS675X_DIG_VOL_RAMP_CTRL_REG, 0,
804 tas675x_ramp_step_texts);
805
806 static const char * const tas675x_vol_combine_ch12_texts[] = {
807 "Independent", "CH2 follows CH1", "CH1 follows CH2"
808 };
809
810 static SOC_ENUM_SINGLE_DECL(tas675x_vol_combine_ch12_enum,
811 TAS675X_DIG_VOL_COMBINE_CTRL_REG, 0,
812 tas675x_vol_combine_ch12_texts);
813
814 static const char * const tas675x_vol_combine_ch34_texts[] = {
815 "Independent", "CH4 follows CH3", "CH3 follows CH4"
816 };
817
818 static SOC_ENUM_SINGLE_DECL(tas675x_vol_combine_ch34_enum,
819 TAS675X_DIG_VOL_COMBINE_CTRL_REG, 2,
820 tas675x_vol_combine_ch34_texts);
821
822 static const char * const tas675x_auto_mute_time_texts[] = {
823 "11.5ms", "53ms", "106.5ms", "266.5ms",
824 "535ms", "1065ms", "2665ms", "5330ms"
825 };
826
827 static SOC_ENUM_SINGLE_DECL(tas675x_ch1_mute_time_enum,
828 TAS675X_AUTO_MUTE_TIMING_CH1_CH2_REG, 4,
829 tas675x_auto_mute_time_texts);
830 static SOC_ENUM_SINGLE_DECL(tas675x_ch2_mute_time_enum,
831 TAS675X_AUTO_MUTE_TIMING_CH1_CH2_REG, 0,
832 tas675x_auto_mute_time_texts);
833 static SOC_ENUM_SINGLE_DECL(tas675x_ch3_mute_time_enum,
834 TAS675X_AUTO_MUTE_TIMING_CH3_CH4_REG, 4,
835 tas675x_auto_mute_time_texts);
836 static SOC_ENUM_SINGLE_DECL(tas675x_ch4_mute_time_enum,
837 TAS675X_AUTO_MUTE_TIMING_CH3_CH4_REG, 0,
838 tas675x_auto_mute_time_texts);
839
840 /*
841 * ALSA Mixer Controls
842 *
843 * For detailed documentation of each control see:
844 * Documentation/sound/codecs/tas675x.rst
845 */
846 static const struct snd_kcontrol_new tas675x_snd_controls[] = {
847 /* Volume & Gain Control */
848 SOC_DOUBLE_R_TLV("Analog Playback Volume", TAS675X_ANALOG_GAIN_CH1_CH2_REG,
849 TAS675X_ANALOG_GAIN_CH3_CH4_REG, 1, 0x1F, 1, tas675x_ana_gain_tlv),
850 SOC_ENUM("Analog Gain Ramp Step", tas675x_ana_ramp_enum),
851 SOC_SINGLE_RANGE_TLV("CH1 Digital Playback Volume",
852 TAS675X_DIG_VOL_CH1_REG, 0, 0x30, 0xFF, 1,
853 tas675x_dig_vol_tlv),
854 SOC_SINGLE_RANGE_TLV("CH2 Digital Playback Volume",
855 TAS675X_DIG_VOL_CH2_REG, 0, 0x30, 0xFF, 1,
856 tas675x_dig_vol_tlv),
857 SOC_SINGLE_RANGE_TLV("CH3 Digital Playback Volume",
858 TAS675X_DIG_VOL_CH3_REG, 0, 0x30, 0xFF, 1,
859 tas675x_dig_vol_tlv),
860 SOC_SINGLE_RANGE_TLV("CH4 Digital Playback Volume",
861 TAS675X_DIG_VOL_CH4_REG, 0, 0x30, 0xFF, 1,
862 tas675x_dig_vol_tlv),
863 SOC_ENUM("Volume Ramp Down Rate", tas675x_ramp_down_rate_enum),
864 SOC_ENUM("Volume Ramp Down Step", tas675x_ramp_down_step_enum),
865 SOC_ENUM("Volume Ramp Up Rate", tas675x_ramp_up_rate_enum),
866 SOC_ENUM("Volume Ramp Up Step", tas675x_ramp_up_step_enum),
867 SOC_ENUM("CH1/2 Volume Combine", tas675x_vol_combine_ch12_enum),
868 SOC_ENUM("CH3/4 Volume Combine", tas675x_vol_combine_ch34_enum),
869
870 /* Auto Mute & Silence Detection */
871 SOC_SINGLE("CH1 Auto Mute Switch", TAS675X_AUTO_MUTE_EN_REG, 0, 1, 0),
872 SOC_SINGLE("CH2 Auto Mute Switch", TAS675X_AUTO_MUTE_EN_REG, 1, 1, 0),
873 SOC_SINGLE("CH3 Auto Mute Switch", TAS675X_AUTO_MUTE_EN_REG, 2, 1, 0),
874 SOC_SINGLE("CH4 Auto Mute Switch", TAS675X_AUTO_MUTE_EN_REG, 3, 1, 0),
875 SOC_SINGLE("Auto Mute Combine Switch", TAS675X_AUTO_MUTE_EN_REG, 4, 1, 0),
876 SOC_ENUM("CH1 Auto Mute Time", tas675x_ch1_mute_time_enum),
877 SOC_ENUM("CH2 Auto Mute Time", tas675x_ch2_mute_time_enum),
878 SOC_ENUM("CH3 Auto Mute Time", tas675x_ch3_mute_time_enum),
879 SOC_ENUM("CH4 Auto Mute Time", tas675x_ch4_mute_time_enum),
880
881 /* Clock & EMI Management */
882 SOC_ENUM("Spread Spectrum Mode", tas675x_ss_enum),
883 SOC_ENUM("SS Triangle Range", tas675x_ss_tri_range_enum),
884 SOC_ENUM("SS Random Range", tas675x_ss_rdm_range_enum),
885 SOC_ENUM("SS Random Dwell Range", tas675x_ss_rdm_dwell_enum),
886 SOC_SINGLE("SS Triangle Dwell Min", TAS675X_SS_DWELL_CTRL_REG, 4, 15, 0),
887 SOC_SINGLE("SS Triangle Dwell Max", TAS675X_SS_DWELL_CTRL_REG, 0, 15, 0),
888
889 /* Hardware Protection */
890 SOC_SINGLE("OTSD Auto Recovery Switch", TAS675X_OTSD_RECOVERY_EN_REG, 1, 1, 0),
891 SOC_ENUM("Overcurrent Limit Level", tas675x_oc_limit_enum),
892 SOC_ENUM("CH1 OTW Threshold", tas675x_ch1_otw_enum),
893 SOC_ENUM("CH2 OTW Threshold", tas675x_ch2_otw_enum),
894 SOC_ENUM("CH3 OTW Threshold", tas675x_ch3_otw_enum),
895 SOC_ENUM("CH4 OTW Threshold", tas675x_ch4_otw_enum),
896
897 /* DSP Signal Path & Mode */
898 SOC_ENUM("DSP Signal Path Mode", tas675x_dsp_mode_enum),
899
900 /* DC Load Diagnostics */
901 {
902 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
903 .name = "DC LDG Trigger",
904 .access = SNDRV_CTL_ELEM_ACCESS_WRITE,
905 .info = snd_ctl_boolean_mono_info,
906 .put = tas675x_set_dcldg_trigger,
907 },
908 SOC_SINGLE("DC LDG Auto Diagnostics Switch", TAS675X_DC_LDG_CTRL_REG, 0, 1, 1),
909 SOC_SINGLE("CH1 LO LDG Switch", TAS675X_DC_LDG_LO_CTRL_REG, 3, 1, 0),
910 SOC_SINGLE("CH2 LO LDG Switch", TAS675X_DC_LDG_LO_CTRL_REG, 2, 1, 0),
911 SOC_SINGLE("CH3 LO LDG Switch", TAS675X_DC_LDG_LO_CTRL_REG, 1, 1, 0),
912 SOC_SINGLE("CH4 LO LDG Switch", TAS675X_DC_LDG_LO_CTRL_REG, 0, 1, 0),
913 SOC_ENUM("DC LDG SLOL Ramp Time", tas675x_dc_slol_ramp_enum),
914 SOC_ENUM("DC LDG SLOL Settling Time", tas675x_dc_slol_settling_enum),
915 SOC_ENUM("DC LDG S2PG Ramp Time", tas675x_dc_s2pg_ramp_enum),
916 SOC_ENUM("DC LDG S2PG Settling Time", tas675x_dc_s2pg_settling_enum),
917 SOC_ENUM("CH1 DC LDG SL Threshold", tas675x_ch1_dc_ldg_sl_enum),
918 SOC_ENUM("CH2 DC LDG SL Threshold", tas675x_ch2_dc_ldg_sl_enum),
919 SOC_ENUM("CH3 DC LDG SL Threshold", tas675x_ch3_dc_ldg_sl_enum),
920 SOC_ENUM("CH4 DC LDG SL Threshold", tas675x_ch4_dc_ldg_sl_enum),
921 SOC_SINGLE_RO("DC LDG Result", TAS675X_DC_LDG_RESULT_REG, 0, 0xFF),
922 SOC_SINGLE_RO("CH1 DC LDG Report", TAS675X_DC_LDG_REPORT_CH1_CH2_REG, 4, 0x0F),
923 SOC_SINGLE_RO("CH2 DC LDG Report", TAS675X_DC_LDG_REPORT_CH1_CH2_REG, 0, 0x0F),
924 SOC_SINGLE_RO("CH3 DC LDG Report", TAS675X_DC_LDG_REPORT_CH3_CH4_REG, 4, 0x0F),
925 SOC_SINGLE_RO("CH4 DC LDG Report", TAS675X_DC_LDG_REPORT_CH3_CH4_REG, 0, 0x0F),
926 SOC_SINGLE_RO("CH1 LO LDG Report", TAS675X_DC_LDG_RESULT_REG, 7, 1),
927 SOC_SINGLE_RO("CH2 LO LDG Report", TAS675X_DC_LDG_RESULT_REG, 6, 1),
928 SOC_SINGLE_RO("CH3 LO LDG Report", TAS675X_DC_LDG_RESULT_REG, 5, 1),
929 SOC_SINGLE_RO("CH4 LO LDG Report", TAS675X_DC_LDG_RESULT_REG, 4, 1),
930 SOC_DC_RESIST_RO("CH1 DC Resistance", TAS675X_CH1_DC_LDG_DCR_LSB_REG),
931 SOC_DC_RESIST_RO("CH2 DC Resistance", TAS675X_CH2_DC_LDG_DCR_LSB_REG),
932 SOC_DC_RESIST_RO("CH3 DC Resistance", TAS675X_CH3_DC_LDG_DCR_LSB_REG),
933 SOC_DC_RESIST_RO("CH4 DC Resistance", TAS675X_CH4_DC_LDG_DCR_LSB_REG),
934
935 /* AC Load Diagnostics */
936 {
937 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
938 .name = "AC LDG Trigger",
939 .access = SNDRV_CTL_ELEM_ACCESS_WRITE,
940 .info = snd_ctl_boolean_mono_info,
941 .put = tas675x_set_acldg_trigger,
942 },
943 SOC_SINGLE("AC LDG Gain", TAS675X_AC_LDG_CTRL_REG, 4, 1, 0),
944 SOC_SINGLE("AC LDG Test Frequency", TAS675X_AC_LDG_FREQ_CTRL_REG, 0, 0xFF, 0),
945 SOC_SINGLE_RO("CH1 AC LDG Real", TAS675X_AC_LDG_REPORT_CH1_R_REG, 0, 0xFF),
946 SOC_SINGLE_RO("CH1 AC LDG Imag", TAS675X_AC_LDG_REPORT_CH1_I_REG, 0, 0xFF),
947 SOC_SINGLE_RO("CH2 AC LDG Real", TAS675X_AC_LDG_REPORT_CH2_R_REG, 0, 0xFF),
948 SOC_SINGLE_RO("CH2 AC LDG Imag", TAS675X_AC_LDG_REPORT_CH2_I_REG, 0, 0xFF),
949 SOC_SINGLE_RO("CH3 AC LDG Real", TAS675X_AC_LDG_REPORT_CH3_R_REG, 0, 0xFF),
950 SOC_SINGLE_RO("CH3 AC LDG Imag", TAS675X_AC_LDG_REPORT_CH3_I_REG, 0, 0xFF),
951 SOC_SINGLE_RO("CH4 AC LDG Real", TAS675X_AC_LDG_REPORT_CH4_R_REG, 0, 0xFF),
952 SOC_SINGLE_RO("CH4 AC LDG Imag", TAS675X_AC_LDG_REPORT_CH4_I_REG, 0, 0xFF),
953
954 /* Temperature and Voltage Monitoring */
955 SOC_SINGLE_RO("PVDD Sense", TAS675X_PVDD_SENSE_REG, 0, 0xFF),
956 SOC_SINGLE_RO("Global Temperature", TAS675X_TEMP_GLOBAL_REG, 0, 0xFF),
957 SOC_SINGLE_RO("CH1 Temperature Range", TAS675X_TEMP_CH1_CH2_REG, 0, 7),
958 SOC_SINGLE_RO("CH2 Temperature Range", TAS675X_TEMP_CH1_CH2_REG, 3, 7),
959 SOC_SINGLE_RO("CH3 Temperature Range", TAS675X_TEMP_CH3_CH4_REG, 0, 7),
960 SOC_SINGLE_RO("CH4 Temperature Range", TAS675X_TEMP_CH3_CH4_REG, 3, 7),
961
962 /* Speaker Protection & Detection */
963 SOC_SINGLE("Tweeter Detection Switch", TAS675X_TWEETER_DETECT_CTRL_REG, 0, 1, 1),
964 SOC_SINGLE("Tweeter Detect Threshold", TAS675X_TWEETER_DETECT_THRESH_REG, 0, 0xFF, 0),
965 SOC_SINGLE_RO("CH1 Tweeter Detect Report", TAS675X_TWEETER_REPORT_REG, 3, 1),
966 SOC_SINGLE_RO("CH2 Tweeter Detect Report", TAS675X_TWEETER_REPORT_REG, 2, 1),
967 SOC_SINGLE_RO("CH3 Tweeter Detect Report", TAS675X_TWEETER_REPORT_REG, 1, 1),
968 SOC_SINGLE_RO("CH4 Tweeter Detect Report", TAS675X_TWEETER_REPORT_REG, 0, 1),
969
970 /*
971 * Unavailable in LLP, available in Normal & FFLP
972 */
973 SOC_SINGLE("Thermal Foldback Switch", TAS675X_DSP_CTRL_REG, 0, 1, 0),
974 SOC_SINGLE("PVDD Foldback Switch", TAS675X_DSP_CTRL_REG, 4, 1, 0),
975 SOC_SINGLE("DC Blocker Bypass Switch", TAS675X_DC_BLOCK_BYP_REG, 0, 1, 0),
976 SOC_SINGLE("Clip Detect Switch", TAS675X_CLIP_DETECT_CTRL_REG, 6, 1, 0),
977 SOC_SINGLE("Audio SDOUT Switch", TAS675X_DSP_CTRL_REG, 5, 1, 0),
978
979 /*
980 * Unavailable in both FFLP and LLP, Normal mode only
981 */
982 /* Real-Time Load Diagnostics */
983 SOC_SINGLE("CH1 RTLDG Switch", TAS675X_RTLDG_EN_REG, 3, 1, 0),
984 SOC_SINGLE("CH2 RTLDG Switch", TAS675X_RTLDG_EN_REG, 2, 1, 0),
985 SOC_SINGLE("CH3 RTLDG Switch", TAS675X_RTLDG_EN_REG, 1, 1, 0),
986 SOC_SINGLE("CH4 RTLDG Switch", TAS675X_RTLDG_EN_REG, 0, 1, 0),
987 SOC_SINGLE("RTLDG Clip Mask Switch", TAS675X_RTLDG_EN_REG, 4, 1, 0),
988 SOC_SINGLE("ISENSE Calibration Switch", TAS675X_ISENSE_CAL_REG, 3, 1, 0),
989 SOC_DSP_THRESH_EXT("RTLDG Open Load Threshold",
990 tas675x_dsp_defaults[TAS675X_DSP_PARAM_ID_OL_THRESH]),
991 SOC_DSP_THRESH_EXT("RTLDG Short Load Threshold",
992 tas675x_dsp_defaults[TAS675X_DSP_PARAM_ID_SL_THRESH]),
993 SOC_RTLDG_IMP_RO("CH1 RTLDG Impedance", TAS675X_CH1_RTLDG_IMP_MSB_REG),
994 SOC_RTLDG_IMP_RO("CH2 RTLDG Impedance", TAS675X_CH2_RTLDG_IMP_MSB_REG),
995 SOC_RTLDG_IMP_RO("CH3 RTLDG Impedance", TAS675X_CH3_RTLDG_IMP_MSB_REG),
996 SOC_RTLDG_IMP_RO("CH4 RTLDG Impedance", TAS675X_CH4_RTLDG_IMP_MSB_REG),
997 };
998
999 static const struct snd_kcontrol_new tas675x_audio_path_switch =
1000 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 1);
1001
1002 static const struct snd_kcontrol_new tas675x_anc_path_switch =
1003 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 1);
1004
1005 static const struct snd_soc_dapm_widget tas675x_dapm_widgets[] = {
1006 SND_SOC_DAPM_SUPPLY("Analog Core", SND_SOC_NOPM, 0, 0, NULL, 0),
1007 SND_SOC_DAPM_SUPPLY("SDOUT Vpredict", SND_SOC_NOPM, 0, 0, NULL, 0),
1008 SND_SOC_DAPM_SUPPLY("SDOUT Isense", SND_SOC_NOPM, 0, 0, NULL, 0),
1009
1010 SND_SOC_DAPM_DAC("Audio DAC", "Playback", SND_SOC_NOPM, 0, 0),
1011 SND_SOC_DAPM_DAC("ANC DAC", "ANC Playback", SND_SOC_NOPM, 0, 0),
1012 SND_SOC_DAPM_ADC("Feedback ADC", "Feedback Capture", SND_SOC_NOPM, 0, 0),
1013
1014 SND_SOC_DAPM_SWITCH("Audio Path", SND_SOC_NOPM, 0, 0,
1015 &tas675x_audio_path_switch),
1016 SND_SOC_DAPM_SWITCH("ANC Path", SND_SOC_NOPM, 0, 0,
1017 &tas675x_anc_path_switch),
1018
1019 /*
1020 * Even though all channels are coupled in terms of power control,
1021 * use logical outputs for each channel to allow independent routing
1022 * and DAPM controls if needed.
1023 */
1024 SND_SOC_DAPM_OUTPUT("OUT_CH1"),
1025 SND_SOC_DAPM_OUTPUT("OUT_CH2"),
1026 SND_SOC_DAPM_OUTPUT("OUT_CH3"),
1027 SND_SOC_DAPM_OUTPUT("OUT_CH4"),
1028 SND_SOC_DAPM_INPUT("SPEAKER_LOAD"),
1029 };
1030
1031 static const struct snd_soc_dapm_route tas675x_dapm_routes[] = {
1032 { "Audio DAC", NULL, "Analog Core" },
1033 { "Audio Path", "Switch", "Audio DAC" },
1034 { "OUT_CH1", NULL, "Audio Path" },
1035 { "OUT_CH2", NULL, "Audio Path" },
1036 { "OUT_CH3", NULL, "Audio Path" },
1037 { "OUT_CH4", NULL, "Audio Path" },
1038
1039 { "ANC DAC", NULL, "Analog Core" },
1040 { "ANC Path", "Switch", "ANC DAC" },
1041 { "OUT_CH1", NULL, "ANC Path" },
1042 { "OUT_CH2", NULL, "ANC Path" },
1043 { "OUT_CH3", NULL, "ANC Path" },
1044 { "OUT_CH4", NULL, "ANC Path" },
1045
1046 { "Feedback ADC", NULL, "Analog Core" },
1047 { "Feedback ADC", NULL, "SDOUT Vpredict" },
1048 { "Feedback ADC", NULL, "SDOUT Isense" },
1049 { "Feedback ADC", NULL, "SPEAKER_LOAD" },
1050 };
1051
tas675x_program_slot_offsets(struct tas675x_priv * tas,int dai_id,int slot_width)1052 static void tas675x_program_slot_offsets(struct tas675x_priv *tas,
1053 int dai_id, int slot_width)
1054 {
1055 int offset = 0;
1056
1057 switch (dai_id) {
1058 case 0:
1059 /* Standard Audio on SDIN */
1060 if (tas->audio_slot >= 0)
1061 offset = tas->audio_slot * slot_width;
1062 else if (tas->tx_mask)
1063 offset = __ffs(tas->tx_mask) * slot_width;
1064 else
1065 return;
1066 offset += tas->bclk_offset;
1067 regmap_update_bits(tas->regmap, TAS675X_SDIN_OFFSET_MSB_REG,
1068 TAS675X_SDIN_AUDIO_OFF_MSB_MASK,
1069 FIELD_PREP(TAS675X_SDIN_AUDIO_OFF_MSB_MASK, offset >> 8));
1070 regmap_write(tas->regmap, TAS675X_SDIN_AUDIO_OFFSET_REG,
1071 offset & 0xFF);
1072 break;
1073 case 1:
1074 /*
1075 * Low-Latency Playback on SDIN, **only** enabled in LLP mode
1076 * and to be mixed with main audio before output amplification
1077 * to achieve ANC/RNC.
1078 */
1079 if (tas->llp_slot >= 0)
1080 offset = tas->llp_slot * slot_width;
1081 else if (tas->tx_mask)
1082 offset = __ffs(tas->tx_mask) * slot_width;
1083 else
1084 return;
1085 offset += tas->bclk_offset;
1086 regmap_update_bits(tas->regmap, TAS675X_SDIN_OFFSET_MSB_REG,
1087 TAS675X_SDIN_LL_OFF_MSB_MASK,
1088 FIELD_PREP(TAS675X_SDIN_LL_OFF_MSB_MASK, offset >> 8));
1089 regmap_write(tas->regmap, TAS675X_SDIN_LL_OFFSET_REG,
1090 offset & 0xFF);
1091 break;
1092 case 2:
1093 /* SDOUT Data Output (Vpredict + Isense feedback) */
1094 if (!tas->slot_width)
1095 break;
1096 if (tas->vpredict_slot >= 0) {
1097 offset = tas->vpredict_slot * slot_width;
1098 offset += tas->bclk_offset;
1099 regmap_update_bits(tas->regmap, TAS675X_SDOUT_OFFSET_MSB_REG,
1100 TAS675X_SDOUT_VP_OFF_MSB_MASK,
1101 FIELD_PREP(TAS675X_SDOUT_VP_OFF_MSB_MASK, offset >> 8));
1102 regmap_write(tas->regmap, TAS675X_VPREDICT_OFFSET_REG,
1103 offset & 0xFF);
1104 }
1105 if (tas->isense_slot >= 0) {
1106 offset = tas->isense_slot * slot_width;
1107 offset += tas->bclk_offset;
1108 regmap_update_bits(tas->regmap, TAS675X_SDOUT_OFFSET_MSB_REG,
1109 TAS675X_SDOUT_IS_OFF_MSB_MASK,
1110 FIELD_PREP(TAS675X_SDOUT_IS_OFF_MSB_MASK, offset >> 8));
1111 regmap_write(tas->regmap, TAS675X_ISENSE_OFFSET_REG,
1112 offset & 0xFF);
1113 }
1114 break;
1115 }
1116
1117 if (offset > 511)
1118 dev_warn(tas->dev,
1119 "DAI %d slot offset %d exceeds 511 SCLK limit\n",
1120 dai_id, offset);
1121 }
1122
tas675x_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1123 static int tas675x_hw_params(struct snd_pcm_substream *substream,
1124 struct snd_pcm_hw_params *params,
1125 struct snd_soc_dai *dai)
1126 {
1127 struct snd_soc_component *component = dai->component;
1128 struct tas675x_priv *tas = snd_soc_component_get_drvdata(component);
1129 unsigned int rate = params_rate(params);
1130 u8 word_length;
1131
1132 /*
1133 * Single clock domain: SDIN and SDOUT share one SCLK/FSYNC pair,
1134 * so all active DAIs must use the same sample rate.
1135 */
1136 if ((READ_ONCE(tas->active_playback_dais) || READ_ONCE(tas->active_capture_dais)) &&
1137 tas->rate && tas->rate != rate) {
1138 dev_err(component->dev,
1139 "Rate %u conflicts with active rate %u\n",
1140 rate, tas->rate);
1141 return -EINVAL;
1142 }
1143
1144 switch (params_width(params)) {
1145 case 16:
1146 word_length = TAS675X_WL_16BIT;
1147 break;
1148 case 20:
1149 word_length = TAS675X_WL_20BIT;
1150 break;
1151 case 24:
1152 word_length = TAS675X_WL_24BIT;
1153 break;
1154 case 32:
1155 word_length = TAS675X_WL_32BIT;
1156 break;
1157 default:
1158 return -EINVAL;
1159 }
1160
1161 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1162 /*
1163 * RTLDG is not supported above 96kHz. Auto-disable to
1164 * prevent DSP overload and restore when rate drops back.
1165 */
1166 if (rate > 96000) {
1167 unsigned int val;
1168
1169 regmap_read(component->regmap, TAS675X_RTLDG_EN_REG,
1170 &val);
1171 if (val & TAS675X_RTLDG_CH_EN_MASK) {
1172 tas->saved_rtldg_en = val;
1173 dev_dbg(component->dev,
1174 "Sample rate %dHz > 96kHz: Auto-disabling RTLDG\n",
1175 rate);
1176 regmap_update_bits(component->regmap,
1177 TAS675X_RTLDG_EN_REG,
1178 TAS675X_RTLDG_CH_EN_MASK,
1179 0x00);
1180 }
1181 } else if (tas->saved_rtldg_en) {
1182 unsigned int cur;
1183
1184 /*
1185 * Respect overrides and only restore if RTLDG is still auto-disabled
1186 */
1187 regmap_read(component->regmap, TAS675X_RTLDG_EN_REG,
1188 &cur);
1189 if (!(cur & TAS675X_RTLDG_CH_EN_MASK)) {
1190 dev_dbg(component->dev,
1191 "Restoring RTLDG config after high-rate stream\n");
1192 regmap_update_bits(component->regmap,
1193 TAS675X_RTLDG_EN_REG,
1194 TAS675X_RTLDG_CH_EN_MASK,
1195 TAS675X_RTLDG_CH_EN_MASK &
1196 tas->saved_rtldg_en);
1197 }
1198 tas->saved_rtldg_en = 0;
1199 }
1200
1201 /* Set SDIN word length (audio path + low-latency path) */
1202 regmap_update_bits(component->regmap, TAS675X_SDIN_CTRL_REG,
1203 TAS675X_SDIN_WL_MASK,
1204 FIELD_PREP(TAS675X_SDIN_AUDIO_WL_MASK, word_length) |
1205 FIELD_PREP(TAS675X_SDIN_LL_WL_MASK, word_length));
1206 } else {
1207 /* Set SDOUT word length (VPREDICT + ISENSE) for capture */
1208 regmap_update_bits(component->regmap, TAS675X_SDOUT_CTRL_REG,
1209 TAS675X_SDOUT_WL_MASK,
1210 FIELD_PREP(TAS675X_SDOUT_VP_WL_MASK, word_length) |
1211 FIELD_PREP(TAS675X_SDOUT_IS_WL_MASK, word_length));
1212 }
1213
1214 tas675x_program_slot_offsets(tas, dai->id,
1215 tas->slot_width ?: params_width(params));
1216
1217 tas->rate = rate;
1218
1219 return 0;
1220 }
1221
tas675x_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)1222 static int tas675x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1223 {
1224 struct snd_soc_component *component = dai->component;
1225 struct tas675x_priv *tas = snd_soc_component_get_drvdata(component);
1226 bool tdm_mode = false, i2s_mode = false;
1227
1228 /* Enforce Clocking Direction (Codec is strictly a consumer) */
1229 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1230 case SND_SOC_DAIFMT_BC_FC:
1231 break;
1232 default:
1233 dev_err(component->dev, "Unsupported clock provider format\n");
1234 return -EINVAL;
1235 }
1236
1237 /* SCLK polarity: NB_NF or IB_NF only (no FSYNC inversion support) */
1238 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1239 case SND_SOC_DAIFMT_NB_NF:
1240 regmap_update_bits(component->regmap, TAS675X_SCLK_INV_CTRL_REG,
1241 TAS675X_SCLK_INV_MASK, 0x00);
1242 break;
1243 case SND_SOC_DAIFMT_IB_NF:
1244 regmap_update_bits(component->regmap, TAS675X_SCLK_INV_CTRL_REG,
1245 TAS675X_SCLK_INV_MASK, TAS675X_SCLK_INV_MASK);
1246 break;
1247 default:
1248 dev_err(component->dev, "Unsupported clock inversion\n");
1249 return -EINVAL;
1250 }
1251
1252 /* Configure Audio Format and TDM Enable */
1253 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1254 case SND_SOC_DAIFMT_I2S:
1255 i2s_mode = true;
1256 tas->bclk_offset = 0;
1257 regmap_update_bits(component->regmap, TAS675X_AUDIO_IF_CTRL_REG,
1258 TAS675X_TDM_EN_BIT | TAS675X_SAP_FMT_MASK |
1259 TAS675X_FS_PULSE_MASK,
1260 TAS675X_SAP_FMT_I2S);
1261 regmap_update_bits(component->regmap, TAS675X_SDOUT_CTRL_REG,
1262 TAS675X_SDOUT_SELECT_MASK,
1263 TAS675X_SDOUT_SELECT_NON_TDM);
1264 break;
1265 case SND_SOC_DAIFMT_RIGHT_J:
1266 tas->bclk_offset = 0;
1267 regmap_update_bits(component->regmap, TAS675X_AUDIO_IF_CTRL_REG,
1268 TAS675X_TDM_EN_BIT | TAS675X_SAP_FMT_MASK |
1269 TAS675X_FS_PULSE_MASK,
1270 TAS675X_SAP_FMT_RIGHT_J);
1271 regmap_update_bits(component->regmap, TAS675X_SDOUT_CTRL_REG,
1272 TAS675X_SDOUT_SELECT_MASK,
1273 TAS675X_SDOUT_SELECT_NON_TDM);
1274 break;
1275 case SND_SOC_DAIFMT_LEFT_J:
1276 tas->bclk_offset = 0;
1277 regmap_update_bits(component->regmap, TAS675X_AUDIO_IF_CTRL_REG,
1278 TAS675X_TDM_EN_BIT | TAS675X_SAP_FMT_MASK |
1279 TAS675X_FS_PULSE_MASK,
1280 TAS675X_SAP_FMT_LEFT_J);
1281 regmap_update_bits(component->regmap, TAS675X_SDOUT_CTRL_REG,
1282 TAS675X_SDOUT_SELECT_MASK,
1283 TAS675X_SDOUT_SELECT_NON_TDM);
1284 break;
1285 case SND_SOC_DAIFMT_DSP_A:
1286 tdm_mode = true;
1287 tas->bclk_offset = 1;
1288 regmap_update_bits(component->regmap, TAS675X_AUDIO_IF_CTRL_REG,
1289 TAS675X_TDM_EN_BIT | TAS675X_SAP_FMT_MASK |
1290 TAS675X_FS_PULSE_MASK,
1291 TAS675X_TDM_EN_BIT | TAS675X_SAP_FMT_TDM |
1292 TAS675X_FS_PULSE_SHORT);
1293 regmap_update_bits(component->regmap, TAS675X_SDOUT_CTRL_REG,
1294 TAS675X_SDOUT_SELECT_MASK,
1295 TAS675X_SDOUT_SELECT_TDM_SDOUT1);
1296 break;
1297 case SND_SOC_DAIFMT_DSP_B:
1298 tdm_mode = true;
1299 tas->bclk_offset = 0;
1300 regmap_update_bits(component->regmap, TAS675X_AUDIO_IF_CTRL_REG,
1301 TAS675X_TDM_EN_BIT | TAS675X_SAP_FMT_MASK |
1302 TAS675X_FS_PULSE_MASK,
1303 TAS675X_TDM_EN_BIT | TAS675X_SAP_FMT_TDM |
1304 TAS675X_FS_PULSE_SHORT);
1305 regmap_update_bits(component->regmap, TAS675X_SDOUT_CTRL_REG,
1306 TAS675X_SDOUT_SELECT_MASK,
1307 TAS675X_SDOUT_SELECT_TDM_SDOUT1);
1308 break;
1309 default:
1310 dev_err(component->dev, "Unsupported DAI format\n");
1311 return -EINVAL;
1312 }
1313
1314 /* Setup Vpredict and Isense outputs */
1315 if (dai->id == 2) {
1316 unsigned int sdout_en = 0;
1317
1318 if (tdm_mode) {
1319 /* TDM: Vpredict and Isense may coexist on separate slots */
1320 if (tas->vpredict_slot >= 0)
1321 sdout_en |= TAS675X_SDOUT_EN_VPREDICT;
1322 if (tas->isense_slot >= 0)
1323 sdout_en |= TAS675X_SDOUT_EN_ISENSE;
1324 regmap_update_bits(component->regmap,
1325 TAS675X_SDOUT_EN_REG,
1326 TAS675X_SDOUT_EN_VPREDICT |
1327 TAS675X_SDOUT_EN_ISENSE,
1328 sdout_en);
1329 if (tas->vpredict_slot >= 0 && tas->isense_slot >= 0 &&
1330 abs(tas->vpredict_slot - tas->isense_slot) < 4)
1331 dev_warn(component->dev,
1332 "ti,vpredict-slot-no and ti,isense-slot-no overlaps (each occupies 4 consecutive slots)\n");
1333 } else if (i2s_mode) {
1334 /* I2S: only one source at a time; Vpredict takes priority */
1335 if (tas->vpredict_slot >= 0)
1336 sdout_en = TAS675X_SDOUT_NON_TDM_SEL_VPREDICT |
1337 TAS675X_SDOUT_EN_NON_TDM_ALL;
1338 else if (tas->isense_slot >= 0)
1339 sdout_en = TAS675X_SDOUT_NON_TDM_SEL_ISENSE |
1340 TAS675X_SDOUT_EN_NON_TDM_ALL;
1341 regmap_update_bits(component->regmap,
1342 TAS675X_SDOUT_EN_REG,
1343 TAS675X_SDOUT_NON_TDM_SEL_MASK |
1344 TAS675X_SDOUT_EN_NON_TDM_ALL,
1345 sdout_en);
1346 if (sdout_en &&
1347 tas->gpio1_func != TAS675X_GPIO_SEL_SDOUT2 &&
1348 tas->gpio2_func != TAS675X_GPIO_SEL_SDOUT2)
1349 dev_warn(component->dev,
1350 "sdout enabled in I2S mode but no GPIO configured as SDOUT2; Ch3/Ch4 will be absent\n");
1351 }
1352 }
1353
1354 return 0;
1355 }
1356
tas675x_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1357 static int tas675x_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1358 unsigned int rx_mask, int slots, int slot_width)
1359 {
1360 struct tas675x_priv *tas = snd_soc_component_get_drvdata(dai->component);
1361
1362 if (slots == 0) {
1363 tas->slot_width = 0;
1364 tas->tx_mask = 0;
1365 return 0;
1366 }
1367
1368 /* No rx_mask as hardware does not support channel muxing for capture */
1369 tas->slot_width = slot_width;
1370 tas->tx_mask = tx_mask;
1371 return 0;
1372 }
1373
tas675x_mute_stream(struct snd_soc_dai * dai,int mute,int direction)1374 static int tas675x_mute_stream(struct snd_soc_dai *dai, int mute, int direction)
1375 {
1376 struct snd_soc_component *component = dai->component;
1377 struct tas675x_priv *tas = snd_soc_component_get_drvdata(component);
1378 unsigned int discard;
1379 int ret;
1380
1381 if (direction == SNDRV_PCM_STREAM_CAPTURE) {
1382 if (mute)
1383 clear_bit(dai->id, &tas->active_capture_dais);
1384 else
1385 set_bit(dai->id, &tas->active_capture_dais);
1386 return 0;
1387 }
1388
1389 /*
1390 * Track which playback DAIs are active.
1391 * The TAS675x has two playback DAIs (main audio and LLP).
1392 * Only transition to SLEEP when ALL are muted.
1393 */
1394 if (mute)
1395 clear_bit(dai->id, &tas->active_playback_dais);
1396 else
1397 set_bit(dai->id, &tas->active_playback_dais);
1398
1399 /* Last playback stream */
1400 if (mute && !READ_ONCE(tas->active_playback_dais)) {
1401 ret = tas675x_set_state_all(tas, TAS675X_STATE_SLEEP_BOTH);
1402 regmap_read(tas->regmap, TAS675X_CLK_FAULT_LATCHED_REG, &discard);
1403 return ret;
1404 }
1405
1406 return tas675x_set_state_all(tas,
1407 READ_ONCE(tas->active_playback_dais) ?
1408 TAS675X_STATE_PLAY_BOTH :
1409 TAS675X_STATE_SLEEP_BOTH);
1410 }
1411
1412 static const struct snd_soc_dai_ops tas675x_dai_ops = {
1413 .hw_params = tas675x_hw_params,
1414 .set_fmt = tas675x_set_fmt,
1415 .set_tdm_slot = tas675x_set_tdm_slot,
1416 .mute_stream = tas675x_mute_stream,
1417 };
1418
1419 static struct snd_soc_dai_driver tas675x_dais[] = {
1420 {
1421 .name = "tas675x-audio",
1422 .id = 0,
1423 .playback = {
1424 .stream_name = "Playback",
1425 .channels_min = 2,
1426 .channels_max = 4,
1427 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
1428 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
1429 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_LE |
1430 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
1431 },
1432 .ops = &tas675x_dai_ops,
1433 },
1434 /* Only available when Low Latency Path (LLP) is enabled */
1435 {
1436 .name = "tas675x-anc",
1437 .id = 1,
1438 .playback = {
1439 .stream_name = "ANC Playback",
1440 .channels_min = 2,
1441 .channels_max = 4,
1442 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000,
1443 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_LE |
1444 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
1445 },
1446 .ops = &tas675x_dai_ops,
1447 },
1448 {
1449 .name = "tas675x-feedback",
1450 .id = 2,
1451 .capture = {
1452 .stream_name = "Feedback Capture",
1453 .channels_min = 2,
1454 .channels_max = 8,
1455 .rates = SNDRV_PCM_RATE_48000,
1456 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_LE |
1457 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
1458 },
1459 .ops = &tas675x_dai_ops,
1460 }
1461 };
1462
1463 /*
1464 * Enable regulators and release hardware reset GPIOs.
1465 * The device is not I2C-accessible until this returns.
1466 */
tas675x_hw_enable(struct tas675x_priv * tas)1467 static int tas675x_hw_enable(struct tas675x_priv *tas)
1468 {
1469 int ret;
1470
1471 ret = regulator_bulk_enable(ARRAY_SIZE(tas->supplies), tas->supplies);
1472 if (ret) {
1473 dev_err(tas->dev, "Failed to enable regulators: %d\n", ret);
1474 return ret;
1475 }
1476
1477 if (!IS_ERR(tas->vbat)) {
1478 ret = regulator_enable(tas->vbat);
1479 if (ret) {
1480 dev_err(tas->dev, "Failed to enable vbat: %d\n", ret);
1481 regulator_bulk_disable(ARRAY_SIZE(tas->supplies), tas->supplies);
1482 return ret;
1483 }
1484 }
1485
1486 if (tas->pd_gpio && tas->stby_gpio) {
1487 /*
1488 * Independent Pin Control
1489 * Deassert PD first to boot digital, then STBY for analog.
1490 */
1491 /* Min 4ms digital boot wait */
1492 gpiod_set_value_cansleep(tas->pd_gpio, 0);
1493 usleep_range(4000, 5000);
1494
1495 /* ~2ms analog stabilization */
1496 gpiod_set_value_cansleep(tas->stby_gpio, 0);
1497 usleep_range(2000, 3000);
1498 } else if (tas->pd_gpio) {
1499 /*
1500 * Simultaneous Pin Release
1501 * STBY tied to PD or hardwired HIGH.
1502 */
1503 /* 6ms wait for simultaneous release transition */
1504 gpiod_set_value_cansleep(tas->pd_gpio, 0);
1505 usleep_range(6000, 7000);
1506 } else {
1507 /*
1508 * PD hardwired, device in DEEP_SLEEP.
1509 * Digital core already booted, I2C active. Deassert STBY
1510 * to bring up the analog output stage.
1511 */
1512 /* ~2ms analog stabilization */
1513 gpiod_set_value_cansleep(tas->stby_gpio, 0);
1514 usleep_range(2000, 3000);
1515 }
1516
1517 return 0;
1518 }
1519
tas675x_hw_disable(struct tas675x_priv * tas)1520 static void tas675x_hw_disable(struct tas675x_priv *tas)
1521 {
1522 if (tas->stby_gpio)
1523 gpiod_set_value_cansleep(tas->stby_gpio, 1);
1524
1525 if (tas->pd_gpio)
1526 gpiod_set_value_cansleep(tas->pd_gpio, 1);
1527
1528 /*
1529 * Hold PD/STBY asserted for at least 10ms
1530 * before removing PVDD, VBAT or DVDD.
1531 */
1532 usleep_range(10000, 11000);
1533
1534 if (!IS_ERR(tas->vbat))
1535 regulator_disable(tas->vbat);
1536
1537 regulator_bulk_disable(ARRAY_SIZE(tas->supplies), tas->supplies);
1538 }
1539
1540 /*
1541 * Write device start-up defaults.
1542 * Must be called after tas675x_hw_enable() and after regcache is enabled.
1543 */
tas675x_init_device(struct tas675x_priv * tas)1544 static int tas675x_init_device(struct tas675x_priv *tas)
1545 {
1546 struct regmap *regmap = tas->regmap;
1547 unsigned int val;
1548 int ret, i;
1549
1550 /* Clear POR fault flag to prevent IRQ storm */
1551 regmap_read(regmap, TAS675X_POWER_FAULT_LATCHED_REG, &val);
1552
1553 /* Bypass DC Load Diagnostics for fast boot */
1554 if (tas->fast_boot)
1555 regmap_update_bits(regmap, TAS675X_DC_LDG_CTRL_REG,
1556 TAS675X_LDG_ABORT_BIT | TAS675X_LDG_BYPASS_BIT,
1557 TAS675X_LDG_ABORT_BIT | TAS675X_LDG_BYPASS_BIT);
1558
1559 tas675x_select_book(regmap, TAS675X_BOOK_DEFAULT);
1560
1561 /* Enter setup mode */
1562 ret = regmap_write(regmap, TAS675X_SETUP_REG1, TAS675X_SETUP_ENTER_VAL1);
1563 if (ret)
1564 goto err;
1565 ret = regmap_write(regmap, TAS675X_SETUP_REG2, TAS675X_SETUP_ENTER_VAL2);
1566 if (ret)
1567 goto err;
1568
1569 /* Set all channels to Sleep (required before Page 1 config) */
1570 tas675x_set_state_all(tas, TAS675X_STATE_SLEEP_BOTH);
1571
1572 /* Set DAC clock per TRM startup script */
1573 regmap_write(regmap, TAS675X_DAC_CLK_REG, 0x00);
1574
1575 /*
1576 * Switch to Page 1 for safety-critical OC/CBC configuration,
1577 * while bypassing regcache. (Page 1 not accessible post setup)
1578 */
1579 regcache_cache_bypass(regmap, true);
1580 ret = regmap_multi_reg_write(regmap, tas675x_page1_init,
1581 ARRAY_SIZE(tas675x_page1_init));
1582 regcache_cache_bypass(regmap, false);
1583 if (ret)
1584 goto err_setup;
1585
1586 /* Resync regmap's cached page selector */
1587 regmap_write(regmap, TAS675X_PAGE_CTRL_REG, 0x00);
1588
1589 /* Exit setup mode */
1590 regmap_write(regmap, TAS675X_SETUP_REG1, TAS675X_SETUP_EXIT_VAL);
1591 regmap_write(regmap, TAS675X_SETUP_REG2, TAS675X_SETUP_EXIT_VAL);
1592
1593 /* Write DSP parameters if cached */
1594 for (i = 0; i < ARRAY_SIZE(tas->dsp_params); i++) {
1595 if (tas->dsp_params[i].val)
1596 tas675x_dsp_mem_write(tas,
1597 tas->dsp_params[i].page,
1598 tas->dsp_params[i].reg,
1599 tas->dsp_params[i].val);
1600 }
1601
1602 /*
1603 * Configure fault and warning event routing:
1604 *
1605 * ROUTING_1: CP fault/UVLO latch, OUTM soft short latch
1606 * ROUTING_2: CBC latch, OTSD latch, OTSD, power fault
1607 * ROUTING_3: CBC latch, OTSD latch, power latch, DC LDG,
1608 * OTSD, power warnings
1609 * ROUTING_4: OC latch, DC latch, protection shutdown
1610 * OTW latch, OTW, clip latch
1611 * ROUTING_5: clock latch+non-latch, RTLDG latch
1612 * CBC warning, clip warning
1613 */
1614 regmap_write(regmap, TAS675X_REPORT_ROUTING_1_REG, 0x70);
1615 regmap_write(regmap, TAS675X_REPORT_ROUTING_2_REG, 0xA3);
1616 regmap_write(regmap, TAS675X_REPORT_ROUTING_3_REG, 0xBB);
1617 regmap_write(regmap, TAS675X_REPORT_ROUTING_4_REG, 0x7E);
1618 regmap_write(regmap, TAS675X_REPORT_ROUTING_5_REG, 0xF3);
1619
1620 /* Configure GPIO pins if specified in DT */
1621 if (tas->gpio1_func >= 0 || tas->gpio2_func >= 0) {
1622 unsigned int gpio_ctrl = TAS675X_GPIO_CTRL_RSTVAL;
1623
1624 tas675x_config_gpio_pin(regmap, tas->gpio1_func,
1625 TAS675X_GPIO1_OUTPUT_SEL_REG,
1626 0, &gpio_ctrl);
1627 tas675x_config_gpio_pin(regmap, tas->gpio2_func,
1628 TAS675X_GPIO2_OUTPUT_SEL_REG,
1629 1, &gpio_ctrl);
1630 regmap_write(regmap, TAS675X_GPIO_CTRL_REG, gpio_ctrl);
1631 }
1632
1633 /* Clear fast boot bits */
1634 if (tas->fast_boot)
1635 regmap_update_bits(regmap, TAS675X_DC_LDG_CTRL_REG,
1636 TAS675X_LDG_ABORT_BIT | TAS675X_LDG_BYPASS_BIT,
1637 0);
1638
1639 /* Clear any stale faults from the boot sequence */
1640 regmap_read(regmap, TAS675X_POWER_FAULT_STATUS_1_REG, &val);
1641 regmap_read(regmap, TAS675X_POWER_FAULT_LATCHED_REG, &val);
1642 regmap_read(regmap, TAS675X_CLK_FAULT_LATCHED_REG, &val);
1643 regmap_write(regmap, TAS675X_RESET_REG, TAS675X_FAULT_CLEAR);
1644
1645 return 0;
1646
1647 err_setup:
1648 regmap_write(regmap, TAS675X_SETUP_REG1, TAS675X_SETUP_EXIT_VAL);
1649 regmap_write(regmap, TAS675X_SETUP_REG2, TAS675X_SETUP_EXIT_VAL);
1650 err:
1651 dev_err(tas->dev, "Init device failed: %d\n", ret);
1652 return ret;
1653 }
1654
tas675x_power_off(struct tas675x_priv * tas)1655 static void tas675x_power_off(struct tas675x_priv *tas)
1656 {
1657 regcache_cache_only(tas->regmap, true);
1658 regcache_mark_dirty(tas->regmap);
1659 tas675x_hw_disable(tas);
1660 }
1661
tas675x_power_on(struct tas675x_priv * tas)1662 static int tas675x_power_on(struct tas675x_priv *tas)
1663 {
1664 int ret;
1665
1666 ret = tas675x_hw_enable(tas);
1667 if (ret)
1668 return ret;
1669
1670 regcache_cache_only(tas->regmap, false);
1671 regcache_mark_dirty(tas->regmap);
1672
1673 ret = tas675x_init_device(tas);
1674 if (ret)
1675 goto err_disable;
1676
1677 ret = regcache_sync(tas->regmap);
1678 if (ret) {
1679 dev_err(tas->dev, "Failed to sync regcache: %d\n", ret);
1680 goto err_disable;
1681 }
1682
1683 /* Reset fault tracking */
1684 memset(tas->last_status, 0, sizeof(tas->last_status));
1685
1686 return 0;
1687
1688 err_disable:
1689 tas675x_power_off(tas);
1690 return ret;
1691 }
1692
tas675x_runtime_suspend(struct device * dev)1693 static int tas675x_runtime_suspend(struct device *dev)
1694 {
1695 struct tas675x_priv *tas = dev_get_drvdata(dev);
1696
1697 disable_delayed_work_sync(&tas->fault_check_work);
1698 tas675x_set_state_all(tas, TAS675X_STATE_SLEEP_BOTH);
1699
1700 return 0;
1701 }
1702
tas675x_runtime_resume(struct device * dev)1703 static int tas675x_runtime_resume(struct device *dev)
1704 {
1705 struct tas675x_priv *tas = dev_get_drvdata(dev);
1706
1707 tas675x_set_state_all(tas, TAS675X_STATE_SLEEP_BOTH);
1708
1709 if (!to_i2c_client(dev)->irq) {
1710 enable_delayed_work(&tas->fault_check_work);
1711 schedule_delayed_work(&tas->fault_check_work,
1712 msecs_to_jiffies(TAS675X_FAULT_CHECK_INTERVAL_MS));
1713 }
1714
1715 return 0;
1716 }
1717
tas675x_system_suspend(struct device * dev)1718 static int tas675x_system_suspend(struct device *dev)
1719 {
1720 struct tas675x_priv *tas = dev_get_drvdata(dev);
1721 int ret;
1722
1723 ret = tas675x_runtime_suspend(dev);
1724 if (ret)
1725 return ret;
1726
1727 if (to_i2c_client(dev)->irq)
1728 disable_irq(to_i2c_client(dev)->irq);
1729
1730 tas675x_power_off(tas);
1731 return 0;
1732 }
1733
tas675x_system_resume(struct device * dev)1734 static int tas675x_system_resume(struct device *dev)
1735 {
1736 struct tas675x_priv *tas = dev_get_drvdata(dev);
1737 int ret;
1738
1739 ret = tas675x_power_on(tas);
1740 if (ret)
1741 return ret;
1742
1743 if (to_i2c_client(dev)->irq)
1744 enable_irq(to_i2c_client(dev)->irq);
1745
1746 return tas675x_runtime_resume(dev);
1747 }
1748
1749 static const struct snd_soc_component_driver soc_codec_dev_tas675x = {
1750 .controls = tas675x_snd_controls,
1751 .num_controls = ARRAY_SIZE(tas675x_snd_controls),
1752 .dapm_widgets = tas675x_dapm_widgets,
1753 .num_dapm_widgets = ARRAY_SIZE(tas675x_dapm_widgets),
1754 .dapm_routes = tas675x_dapm_routes,
1755 .num_dapm_routes = ARRAY_SIZE(tas675x_dapm_routes),
1756 .endianness = 1,
1757 };
1758
1759 /* Fault register flags */
1760 #define TAS675X_FAULT_CRITICAL BIT(0) /* causes FAULT state, FAULT_CLEAR required */
1761 #define TAS675X_FAULT_TRACK BIT(1) /* track last value, only log on change */
1762 #define TAS675X_FAULT_ACTIVE BIT(2) /* skip when no stream is active */
1763
1764 struct tas675x_fault_reg {
1765 unsigned int reg;
1766 unsigned int flags;
1767 const char *name;
1768 };
1769
1770 static const struct tas675x_fault_reg tas675x_fault_table[] = {
1771 /* Critical */
1772 { TAS675X_OTSD_LATCHED_REG, TAS675X_FAULT_CRITICAL | TAS675X_FAULT_TRACK,
1773 "Overtemperature Shutdown" },
1774 { TAS675X_OC_DC_FAULT_LATCHED_REG, TAS675X_FAULT_CRITICAL | TAS675X_FAULT_TRACK,
1775 "Overcurrent / DC Fault" },
1776 { TAS675X_RTLDG_OL_SL_FAULT_LATCHED_REG, TAS675X_FAULT_CRITICAL | TAS675X_FAULT_TRACK,
1777 "Real-Time Load Diagnostic Fault" },
1778 { TAS675X_CBC_FAULT_WARN_LATCHED_REG, TAS675X_FAULT_CRITICAL | TAS675X_FAULT_TRACK,
1779 "CBC Fault/Warning" },
1780 /* Warning */
1781 { TAS675X_POWER_FAULT_STATUS_1_REG, TAS675X_FAULT_TRACK,
1782 "CP / OUTM Fault" },
1783 { TAS675X_POWER_FAULT_LATCHED_REG, TAS675X_FAULT_TRACK,
1784 "Power Fault" },
1785 { TAS675X_CLK_FAULT_LATCHED_REG, TAS675X_FAULT_TRACK | TAS675X_FAULT_ACTIVE,
1786 "Clock Fault" },
1787 { TAS675X_OTW_LATCHED_REG, TAS675X_FAULT_TRACK,
1788 "Overtemperature Warning" },
1789 { TAS675X_CLIP_WARN_LATCHED_REG, TAS675X_FAULT_ACTIVE,
1790 "Clip Warning" },
1791 };
1792
1793 static_assert(ARRAY_SIZE(tas675x_fault_table) == TAS675X_FAULT_REGS_NUM);
1794
1795 /*
1796 * Read and log all latched fault registers.
1797 * Shared by both the polled fault_check_work and IRQ handler paths
1798 * (which are mutually exclusive, only one is active per device).
1799 * Returns true if any fault register needs to be cleared.
1800 *
1801 * For deciphering fault messages, see "Fault Monitoring" in
1802 * Documentation/sound/codecs/tas675x.rst
1803 */
tas675x_check_faults(struct tas675x_priv * tas)1804 static bool tas675x_check_faults(struct tas675x_priv *tas)
1805 {
1806 struct device *dev = tas->dev;
1807 bool needs_clear = false;
1808 unsigned int reg;
1809 int i, ret;
1810
1811 for (i = 0; i < ARRAY_SIZE(tas675x_fault_table); i++) {
1812 const struct tas675x_fault_reg *f = &tas675x_fault_table[i];
1813
1814 ret = regmap_read(tas->regmap, f->reg, ®);
1815 if (ret) {
1816 if (f->flags & TAS675X_FAULT_CRITICAL) {
1817 dev_err(dev, "failed to read %s: %d\n", f->name, ret);
1818 return needs_clear;
1819 }
1820 continue;
1821 }
1822
1823 if (reg)
1824 needs_clear = true;
1825
1826 /* Skip logging stream-dependent events when no stream is active */
1827 if ((f->flags & TAS675X_FAULT_ACTIVE) &&
1828 !READ_ONCE(tas->active_playback_dais) &&
1829 !READ_ONCE(tas->active_capture_dais))
1830 continue;
1831
1832 /* Log on change or on every non-zero read */
1833 if (reg && (!(f->flags & TAS675X_FAULT_TRACK) ||
1834 reg != tas->last_status[i])) {
1835 if (f->flags & TAS675X_FAULT_CRITICAL)
1836 dev_crit(dev, "%s Latched: 0x%02x\n", f->name, reg);
1837 else
1838 dev_warn(dev, "%s Latched: 0x%02x\n", f->name, reg);
1839 }
1840
1841 if (f->flags & TAS675X_FAULT_TRACK)
1842 tas->last_status[i] = reg;
1843 }
1844
1845 return needs_clear;
1846 }
1847
tas675x_fault_check_work(struct work_struct * work)1848 static void tas675x_fault_check_work(struct work_struct *work)
1849 {
1850 struct tas675x_priv *tas = container_of(work, struct tas675x_priv,
1851 fault_check_work.work);
1852
1853 if (tas675x_check_faults(tas))
1854 regmap_write(tas->regmap, TAS675X_RESET_REG, TAS675X_FAULT_CLEAR);
1855
1856 schedule_delayed_work(&tas->fault_check_work,
1857 msecs_to_jiffies(TAS675X_FAULT_CHECK_INTERVAL_MS));
1858 }
1859
tas675x_irq_handler(int irq,void * data)1860 static irqreturn_t tas675x_irq_handler(int irq, void *data)
1861 {
1862 struct tas675x_priv *tas = data;
1863 irqreturn_t ret = IRQ_NONE;
1864
1865 if (pm_runtime_resume_and_get(tas->dev) < 0)
1866 return IRQ_NONE;
1867
1868 if (tas675x_check_faults(tas)) {
1869 regmap_write(tas->regmap, TAS675X_RESET_REG, TAS675X_FAULT_CLEAR);
1870 ret = IRQ_HANDLED;
1871 }
1872
1873 pm_runtime_mark_last_busy(tas->dev);
1874 pm_runtime_put_autosuspend(tas->dev);
1875 return ret;
1876 }
1877
1878 static const struct reg_default tas675x_reg_defaults[] = {
1879 { TAS675X_PAGE_CTRL_REG, 0x00 },
1880 { TAS675X_OUTPUT_CTRL_REG, 0x00 },
1881 { TAS675X_STATE_CTRL_CH1_CH2_REG, TAS675X_STATE_SLEEP_BOTH },
1882 { TAS675X_STATE_CTRL_CH3_CH4_REG, TAS675X_STATE_SLEEP_BOTH },
1883 { TAS675X_ISENSE_CTRL_REG, 0x0F },
1884 { TAS675X_DC_DETECT_CTRL_REG, 0x00 },
1885 { TAS675X_SCLK_INV_CTRL_REG, 0x00 },
1886 { TAS675X_AUDIO_IF_CTRL_REG, 0x00 },
1887 { TAS675X_SDIN_CTRL_REG, 0x0A },
1888 { TAS675X_SDOUT_CTRL_REG, 0x1A },
1889 { TAS675X_SDIN_OFFSET_MSB_REG, 0x00 },
1890 { TAS675X_SDIN_AUDIO_OFFSET_REG, 0x00 },
1891 { TAS675X_SDIN_LL_OFFSET_REG, 0x60 },
1892 { TAS675X_SDIN_CH_SWAP_REG, 0x00 },
1893 { TAS675X_SDOUT_OFFSET_MSB_REG, 0xCF },
1894 { TAS675X_VPREDICT_OFFSET_REG, 0xFF },
1895 { TAS675X_ISENSE_OFFSET_REG, 0x00 },
1896 { TAS675X_SDOUT_EN_REG, 0x00 },
1897 { TAS675X_LL_EN_REG, 0x00 },
1898 { TAS675X_RTLDG_EN_REG, 0x10 },
1899 { TAS675X_DC_BLOCK_BYP_REG, 0x00 },
1900 { TAS675X_DSP_CTRL_REG, 0x00 },
1901 { TAS675X_PAGE_AUTO_INC_REG, 0x00 },
1902 { TAS675X_DIG_VOL_CH1_REG, 0x30 },
1903 { TAS675X_DIG_VOL_CH2_REG, 0x30 },
1904 { TAS675X_DIG_VOL_CH3_REG, 0x30 },
1905 { TAS675X_DIG_VOL_CH4_REG, 0x30 },
1906 { TAS675X_DIG_VOL_RAMP_CTRL_REG, 0x77 },
1907 { TAS675X_DIG_VOL_COMBINE_CTRL_REG, 0x00 },
1908 { TAS675X_AUTO_MUTE_EN_REG, 0x00 },
1909 { TAS675X_AUTO_MUTE_TIMING_CH1_CH2_REG, 0x00 },
1910 { TAS675X_AUTO_MUTE_TIMING_CH3_CH4_REG, 0x00 },
1911 { TAS675X_ANALOG_GAIN_CH1_CH2_REG, 0x00 },
1912 { TAS675X_ANALOG_GAIN_CH3_CH4_REG, 0x00 },
1913 { TAS675X_ANALOG_GAIN_RAMP_CTRL_REG, 0x00 },
1914 { TAS675X_PULSE_INJECTION_EN_REG, 0x03 },
1915 { TAS675X_CBC_CTRL_REG, 0x07 },
1916 { TAS675X_CURRENT_LIMIT_CTRL_REG, 0x00 },
1917 { TAS675X_ISENSE_CAL_REG, 0x00 },
1918 { TAS675X_PWM_PHASE_CTRL_REG, 0x00 },
1919 { TAS675X_SS_CTRL_REG, 0x00 },
1920 { TAS675X_SS_RANGE_CTRL_REG, 0x00 },
1921 { TAS675X_SS_DWELL_CTRL_REG, 0x00 },
1922 { TAS675X_RAMP_PHASE_CTRL_GPO_REG, 0x00 },
1923 { TAS675X_PWM_PHASE_M_CTRL_CH1_REG, 0x00 },
1924 { TAS675X_PWM_PHASE_M_CTRL_CH2_REG, 0x00 },
1925 { TAS675X_PWM_PHASE_M_CTRL_CH3_REG, 0x00 },
1926 { TAS675X_PWM_PHASE_M_CTRL_CH4_REG, 0x00 },
1927 { TAS675X_REPORT_ROUTING_1_REG, 0x00 },
1928 { TAS675X_OTSD_RECOVERY_EN_REG, 0x00 },
1929 { TAS675X_REPORT_ROUTING_2_REG, 0xA2 },
1930 { TAS675X_REPORT_ROUTING_3_REG, 0x00 },
1931 { TAS675X_REPORT_ROUTING_4_REG, 0x06 },
1932 { TAS675X_CLIP_DETECT_CTRL_REG, 0x00 },
1933 { TAS675X_REPORT_ROUTING_5_REG, 0x00 },
1934 { TAS675X_GPIO1_OUTPUT_SEL_REG, 0x00 },
1935 { TAS675X_GPIO2_OUTPUT_SEL_REG, 0x00 },
1936 { TAS675X_GPIO_CTRL_REG, TAS675X_GPIO_CTRL_RSTVAL },
1937 { TAS675X_DC_LDG_CTRL_REG, 0x00 },
1938 { TAS675X_DC_LDG_LO_CTRL_REG, 0x00 },
1939 { TAS675X_DC_LDG_TIME_CTRL_REG, 0x00 },
1940 { TAS675X_DC_LDG_SL_CH1_CH2_CTRL_REG, 0x11 },
1941 { TAS675X_DC_LDG_SL_CH3_CH4_CTRL_REG, 0x11 },
1942 { TAS675X_AC_LDG_CTRL_REG, 0x10 },
1943 { TAS675X_TWEETER_DETECT_CTRL_REG, 0x08 },
1944 { TAS675X_TWEETER_DETECT_THRESH_REG, 0x00 },
1945 { TAS675X_AC_LDG_FREQ_CTRL_REG, 0xC8 },
1946 { TAS675X_OTW_CTRL_CH1_CH2_REG, 0x11 },
1947 { TAS675X_OTW_CTRL_CH3_CH4_REG, 0x11 },
1948 };
1949
tas675x_is_readable_register(struct device * dev,unsigned int reg)1950 static bool tas675x_is_readable_register(struct device *dev, unsigned int reg)
1951 {
1952 switch (reg) {
1953 case TAS675X_RESET_REG:
1954 return false;
1955 default:
1956 return true;
1957 }
1958 }
1959
tas675x_is_volatile_register(struct device * dev,unsigned int reg)1960 static bool tas675x_is_volatile_register(struct device *dev, unsigned int reg)
1961 {
1962 switch (reg) {
1963 case TAS675X_RESET_REG:
1964 case TAS675X_BOOK_CTRL_REG:
1965 case TAS675X_AUTO_MUTE_STATUS_REG:
1966 case TAS675X_STATE_REPORT_CH1_CH2_REG:
1967 case TAS675X_STATE_REPORT_CH3_CH4_REG:
1968 case TAS675X_PVDD_SENSE_REG:
1969 case TAS675X_TEMP_GLOBAL_REG:
1970 case TAS675X_TEMP_CH1_CH2_REG:
1971 case TAS675X_TEMP_CH3_CH4_REG:
1972 case TAS675X_FS_MON_REG:
1973 case TAS675X_SCLK_MON_REG:
1974 case TAS675X_POWER_FAULT_STATUS_1_REG:
1975 case TAS675X_POWER_FAULT_STATUS_2_REG:
1976 case TAS675X_OT_FAULT_REG:
1977 case TAS675X_OTW_STATUS_REG:
1978 case TAS675X_CLIP_WARN_STATUS_REG:
1979 case TAS675X_CBC_WARNING_STATUS_REG:
1980 case TAS675X_POWER_FAULT_LATCHED_REG:
1981 case TAS675X_OTSD_LATCHED_REG:
1982 case TAS675X_OTW_LATCHED_REG:
1983 case TAS675X_CLIP_WARN_LATCHED_REG:
1984 case TAS675X_CLK_FAULT_LATCHED_REG:
1985 case TAS675X_RTLDG_OL_SL_FAULT_LATCHED_REG:
1986 case TAS675X_CBC_FAULT_WARN_LATCHED_REG:
1987 case TAS675X_OC_DC_FAULT_LATCHED_REG:
1988 case TAS675X_WARN_OT_MAX_FLAG_REG:
1989 case TAS675X_DC_LDG_REPORT_CH1_CH2_REG ... TAS675X_TWEETER_REPORT_REG:
1990 case TAS675X_CH1_RTLDG_IMP_MSB_REG ... TAS675X_CH4_DC_LDG_DCR_LSB_REG:
1991 return true;
1992 default:
1993 return false;
1994 }
1995 }
1996
1997 static const struct regmap_range_cfg tas675x_ranges[] = {
1998 {
1999 .name = "Pages",
2000 .range_min = 0,
2001 .range_max = TAS675X_PAGE_SIZE * TAS675X_PAGE_SIZE - 1,
2002 .selector_reg = TAS675X_PAGE_CTRL_REG,
2003 .selector_mask = 0xff,
2004 .selector_shift = 0,
2005 .window_start = 0,
2006 .window_len = TAS675X_PAGE_SIZE,
2007 },
2008 };
2009
tas675x_regmap_lock(void * lock_arg)2010 static void tas675x_regmap_lock(void *lock_arg)
2011 {
2012 struct tas675x_priv *tas = lock_arg;
2013
2014 mutex_lock(&tas->io_lock);
2015 }
2016
tas675x_regmap_unlock(void * lock_arg)2017 static void tas675x_regmap_unlock(void *lock_arg)
2018 {
2019 struct tas675x_priv *tas = lock_arg;
2020
2021 mutex_unlock(&tas->io_lock);
2022 }
2023
2024 static const struct regmap_config tas675x_regmap_config = {
2025 .reg_bits = 8,
2026 .val_bits = 8,
2027 .max_register = TAS675X_PAGE_SIZE * TAS675X_PAGE_SIZE - 1,
2028 .ranges = tas675x_ranges,
2029 .num_ranges = ARRAY_SIZE(tas675x_ranges),
2030 .cache_type = REGCACHE_MAPLE,
2031 .reg_defaults = tas675x_reg_defaults,
2032 .num_reg_defaults = ARRAY_SIZE(tas675x_reg_defaults),
2033 .readable_reg = tas675x_is_readable_register,
2034 .volatile_reg = tas675x_is_volatile_register,
2035 };
2036
tas675x_i2c_probe(struct i2c_client * client)2037 static int tas675x_i2c_probe(struct i2c_client *client)
2038 {
2039 struct regmap_config cfg = tas675x_regmap_config;
2040 struct tas675x_priv *tas;
2041 u32 val;
2042 int i, ret;
2043
2044 tas = devm_kzalloc(&client->dev, sizeof(*tas), GFP_KERNEL);
2045 if (!tas)
2046 return -ENOMEM;
2047
2048 tas->dev = &client->dev;
2049 i2c_set_clientdata(client, tas);
2050
2051 mutex_init(&tas->io_lock);
2052 cfg.lock = tas675x_regmap_lock;
2053 cfg.unlock = tas675x_regmap_unlock;
2054 cfg.lock_arg = tas;
2055
2056 memcpy(tas->dsp_params, tas675x_dsp_defaults, sizeof(tas->dsp_params));
2057 INIT_DELAYED_WORK(&tas->fault_check_work, tas675x_fault_check_work);
2058
2059 tas->regmap = devm_regmap_init_i2c(client, &cfg);
2060 if (IS_ERR(tas->regmap))
2061 return PTR_ERR(tas->regmap);
2062
2063 /* Keep regmap cache-only until hardware is powered on */
2064 regcache_cache_only(tas->regmap, true);
2065
2066 tas->dev_type = (enum tas675x_type)(unsigned long)device_get_match_data(tas->dev);
2067 tas->fast_boot = device_property_read_bool(tas->dev, "ti,fast-boot");
2068
2069 tas->audio_slot = -1;
2070 tas->llp_slot = -1;
2071 tas->vpredict_slot = -1;
2072 tas->isense_slot = -1;
2073 if (!device_property_read_u32(tas->dev, "ti,audio-slot-no", &val))
2074 tas->audio_slot = val;
2075 if (!device_property_read_u32(tas->dev, "ti,llp-slot-no", &val))
2076 tas->llp_slot = val;
2077 if (!device_property_read_u32(tas->dev, "ti,vpredict-slot-no", &val))
2078 tas->vpredict_slot = val;
2079 if (!device_property_read_u32(tas->dev, "ti,isense-slot-no", &val))
2080 tas->isense_slot = val;
2081
2082 tas->gpio1_func = tas675x_gpio_func_parse(tas->dev, "ti,gpio1-function");
2083 tas->gpio2_func = tas675x_gpio_func_parse(tas->dev, "ti,gpio2-function");
2084
2085 for (i = 0; i < ARRAY_SIZE(tas675x_supply_names); i++)
2086 tas->supplies[i].supply = tas675x_supply_names[i];
2087
2088 ret = devm_regulator_bulk_get(tas->dev, ARRAY_SIZE(tas->supplies), tas->supplies);
2089 if (ret)
2090 return dev_err_probe(tas->dev, ret, "Failed to request supplies\n");
2091
2092 tas->vbat = devm_regulator_get_optional(tas->dev, "vbat");
2093 if (IS_ERR(tas->vbat) && PTR_ERR(tas->vbat) != -ENODEV)
2094 return dev_err_probe(tas->dev, PTR_ERR(tas->vbat),
2095 "Failed to get vbat supply\n");
2096
2097 tas->pd_gpio = devm_gpiod_get_optional(tas->dev, "powerdown", GPIOD_OUT_HIGH);
2098 if (IS_ERR(tas->pd_gpio))
2099 return dev_err_probe(tas->dev, PTR_ERR(tas->pd_gpio), "Failed powerdown-gpios\n");
2100
2101 tas->stby_gpio = devm_gpiod_get_optional(tas->dev, "standby", GPIOD_OUT_HIGH);
2102 if (IS_ERR(tas->stby_gpio))
2103 return dev_err_probe(tas->dev, PTR_ERR(tas->stby_gpio), "Failed standby-gpios\n");
2104
2105 if (!tas->pd_gpio && !tas->stby_gpio)
2106 return dev_err_probe(tas->dev, -EINVAL,
2107 "At least one of powerdown-gpios or standby-gpios is required\n");
2108
2109 ret = tas675x_power_on(tas);
2110 if (ret)
2111 return ret;
2112
2113 if (client->irq) {
2114 ret = devm_request_threaded_irq(tas->dev, client->irq, NULL,
2115 tas675x_irq_handler,
2116 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
2117 "tas675x-fault", tas);
2118 if (ret) {
2119 tas675x_power_off(tas);
2120 return dev_err_probe(tas->dev, ret, "Failed to request IRQ\n");
2121 }
2122 } else {
2123 /* Schedule delayed work for fault checking at probe and runtime resume */
2124 schedule_delayed_work(&tas->fault_check_work,
2125 msecs_to_jiffies(TAS675X_FAULT_CHECK_INTERVAL_MS));
2126 }
2127
2128 /* Enable runtime PM with 2s autosuspend */
2129 pm_runtime_set_autosuspend_delay(tas->dev, 2000);
2130 pm_runtime_use_autosuspend(tas->dev);
2131 pm_runtime_set_active(tas->dev);
2132 pm_runtime_mark_last_busy(tas->dev);
2133 pm_runtime_enable(tas->dev);
2134
2135 ret = devm_snd_soc_register_component(tas->dev, &soc_codec_dev_tas675x,
2136 tas675x_dais, ARRAY_SIZE(tas675x_dais));
2137 if (ret)
2138 goto err_pm_disable;
2139
2140 return 0;
2141
2142 err_pm_disable:
2143 pm_runtime_force_suspend(tas->dev);
2144 pm_runtime_disable(tas->dev);
2145 tas675x_power_off(tas);
2146 return ret;
2147 }
2148
tas675x_i2c_remove(struct i2c_client * client)2149 static void tas675x_i2c_remove(struct i2c_client *client)
2150 {
2151 struct tas675x_priv *tas = dev_get_drvdata(&client->dev);
2152
2153 disable_delayed_work_sync(&tas->fault_check_work);
2154 if (client->irq)
2155 disable_irq(client->irq);
2156
2157 pm_runtime_force_suspend(&client->dev);
2158 pm_runtime_disable(&client->dev);
2159 tas675x_power_off(tas);
2160 }
2161
2162 static const struct dev_pm_ops tas675x_pm_ops = {
2163 SYSTEM_SLEEP_PM_OPS(tas675x_system_suspend, tas675x_system_resume)
2164 RUNTIME_PM_OPS(tas675x_runtime_suspend, tas675x_runtime_resume, NULL)
2165 };
2166
2167 static const struct of_device_id tas675x_of_match[] = {
2168 { .compatible = "ti,tas67524", .data = (void *)TAS67524 },
2169 { }
2170 };
2171 MODULE_DEVICE_TABLE(of, tas675x_of_match);
2172
2173 static const struct i2c_device_id tas675x_i2c_id[] = {
2174 { "tas67524", TAS67524 },
2175 { }
2176 };
2177 MODULE_DEVICE_TABLE(i2c, tas675x_i2c_id);
2178
2179 static struct i2c_driver tas675x_i2c_driver = {
2180 .driver = {
2181 .name = "tas675x",
2182 .of_match_table = tas675x_of_match,
2183 .pm = pm_ptr(&tas675x_pm_ops),
2184 },
2185 .probe = tas675x_i2c_probe,
2186 .remove = tas675x_i2c_remove,
2187 .id_table = tas675x_i2c_id,
2188 };
2189
2190 module_i2c_driver(tas675x_i2c_driver);
2191
2192 MODULE_AUTHOR("Sen Wang <sen@ti.com>");
2193 MODULE_DESCRIPTION("ASoC TAS675x Audio Amplifier Driver");
2194 MODULE_LICENSE("GPL");
2195