1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Codec driver for ST STA350 2.1-channel high-efficiency digital audio system 4 * 5 * Copyright: 2014 Raumfeld GmbH 6 * Author: Sven Brandau <info@brandau.biz> 7 * 8 * based on code from: 9 * Raumfeld GmbH 10 * Johannes Stezenbach <js@sig21.net> 11 * Wolfson Microelectronics PLC. 12 * Mark Brown <broonie@opensource.wolfsonmicro.com> 13 * Freescale Semiconductor, Inc. 14 * Timur Tabi <timur@freescale.com> 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d: " fmt, __func__, __LINE__ 18 19 #include <linux/cleanup.h> 20 #include <linux/module.h> 21 #include <linux/moduleparam.h> 22 #include <linux/init.h> 23 #include <linux/delay.h> 24 #include <linux/pm.h> 25 #include <linux/i2c.h> 26 #include <linux/of.h> 27 #include <linux/regmap.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/gpio/consumer.h> 30 #include <linux/slab.h> 31 #include <sound/core.h> 32 #include <sound/pcm.h> 33 #include <sound/pcm_params.h> 34 #include <sound/soc.h> 35 #include <sound/soc-dapm.h> 36 #include <sound/initval.h> 37 #include <sound/tlv.h> 38 39 #include <sound/sta350.h> 40 #include "sta350.h" 41 42 #define STA350_RATES (SNDRV_PCM_RATE_32000 | \ 43 SNDRV_PCM_RATE_44100 | \ 44 SNDRV_PCM_RATE_48000 | \ 45 SNDRV_PCM_RATE_88200 | \ 46 SNDRV_PCM_RATE_96000 | \ 47 SNDRV_PCM_RATE_176400 | \ 48 SNDRV_PCM_RATE_192000) 49 50 #define STA350_FORMATS \ 51 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \ 52 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_3LE | \ 53 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 54 55 /* Power-up register defaults */ 56 static const struct reg_default sta350_regs[] = { 57 { 0x0, 0x63 }, 58 { 0x1, 0x80 }, 59 { 0x2, 0xdf }, 60 { 0x3, 0x40 }, 61 { 0x4, 0xc2 }, 62 { 0x5, 0x5c }, 63 { 0x6, 0x00 }, 64 { 0x7, 0xff }, 65 { 0x8, 0x60 }, 66 { 0x9, 0x60 }, 67 { 0xa, 0x60 }, 68 { 0xb, 0x00 }, 69 { 0xc, 0x00 }, 70 { 0xd, 0x00 }, 71 { 0xe, 0x00 }, 72 { 0xf, 0x40 }, 73 { 0x10, 0x80 }, 74 { 0x11, 0x77 }, 75 { 0x12, 0x6a }, 76 { 0x13, 0x69 }, 77 { 0x14, 0x6a }, 78 { 0x15, 0x69 }, 79 { 0x16, 0x00 }, 80 { 0x17, 0x00 }, 81 { 0x18, 0x00 }, 82 { 0x19, 0x00 }, 83 { 0x1a, 0x00 }, 84 { 0x1b, 0x00 }, 85 { 0x1c, 0x00 }, 86 { 0x1d, 0x00 }, 87 { 0x1e, 0x00 }, 88 { 0x1f, 0x00 }, 89 { 0x20, 0x00 }, 90 { 0x21, 0x00 }, 91 { 0x22, 0x00 }, 92 { 0x23, 0x00 }, 93 { 0x24, 0x00 }, 94 { 0x25, 0x00 }, 95 { 0x26, 0x00 }, 96 { 0x27, 0x2a }, 97 { 0x28, 0xc0 }, 98 { 0x29, 0xf3 }, 99 { 0x2a, 0x33 }, 100 { 0x2b, 0x00 }, 101 { 0x2c, 0x0c }, 102 { 0x31, 0x00 }, 103 { 0x36, 0x00 }, 104 { 0x37, 0x00 }, 105 { 0x38, 0x00 }, 106 { 0x39, 0x01 }, 107 { 0x3a, 0xee }, 108 { 0x3b, 0xff }, 109 { 0x3c, 0x7e }, 110 { 0x3d, 0xc0 }, 111 { 0x3e, 0x26 }, 112 { 0x3f, 0x00 }, 113 { 0x48, 0x00 }, 114 { 0x49, 0x00 }, 115 { 0x4a, 0x00 }, 116 { 0x4b, 0x04 }, 117 { 0x4c, 0x00 }, 118 }; 119 120 static const struct regmap_range sta350_write_regs_range[] = { 121 regmap_reg_range(STA350_CONFA, STA350_AUTO2), 122 regmap_reg_range(STA350_C1CFG, STA350_FDRC2), 123 regmap_reg_range(STA350_EQCFG, STA350_EVOLRES), 124 regmap_reg_range(STA350_NSHAPE, STA350_MISC2), 125 }; 126 127 static const struct regmap_range sta350_read_regs_range[] = { 128 regmap_reg_range(STA350_CONFA, STA350_AUTO2), 129 regmap_reg_range(STA350_C1CFG, STA350_STATUS), 130 regmap_reg_range(STA350_EQCFG, STA350_EVOLRES), 131 regmap_reg_range(STA350_NSHAPE, STA350_MISC2), 132 }; 133 134 static const struct regmap_range sta350_volatile_regs_range[] = { 135 regmap_reg_range(STA350_CFADDR2, STA350_CFUD), 136 regmap_reg_range(STA350_STATUS, STA350_STATUS), 137 }; 138 139 static const struct regmap_access_table sta350_write_regs = { 140 .yes_ranges = sta350_write_regs_range, 141 .n_yes_ranges = ARRAY_SIZE(sta350_write_regs_range), 142 }; 143 144 static const struct regmap_access_table sta350_read_regs = { 145 .yes_ranges = sta350_read_regs_range, 146 .n_yes_ranges = ARRAY_SIZE(sta350_read_regs_range), 147 }; 148 149 static const struct regmap_access_table sta350_volatile_regs = { 150 .yes_ranges = sta350_volatile_regs_range, 151 .n_yes_ranges = ARRAY_SIZE(sta350_volatile_regs_range), 152 }; 153 154 /* regulator power supply names */ 155 static const char * const sta350_supply_names[] = { 156 "vdd-dig", /* digital supply, 3.3V */ 157 "vdd-pll", /* pll supply, 3.3V */ 158 "vcc" /* power amp supply, 5V - 26V */ 159 }; 160 161 /* codec private data */ 162 struct sta350_priv { 163 struct regmap *regmap; 164 struct regulator_bulk_data supplies[ARRAY_SIZE(sta350_supply_names)]; 165 struct sta350_platform_data *pdata; 166 167 unsigned int mclk; 168 unsigned int format; 169 170 u32 coef_shadow[STA350_COEF_COUNT]; 171 int shutdown; 172 173 struct gpio_desc *gpiod_nreset; 174 struct gpio_desc *gpiod_power_down; 175 176 struct mutex coeff_lock; 177 }; 178 179 static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12750, 50, 1); 180 static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1); 181 static const DECLARE_TLV_DB_SCALE(tone_tlv, -1200, 200, 0); 182 183 static const char * const sta350_drc_ac[] = { 184 "Anti-Clipping", "Dynamic Range Compression" 185 }; 186 static const char * const sta350_auto_gc_mode[] = { 187 "User", "AC no clipping", "AC limited clipping (10%)", 188 "DRC nighttime listening mode" 189 }; 190 static const char * const sta350_auto_xo_mode[] = { 191 "User", "80Hz", "100Hz", "120Hz", "140Hz", "160Hz", "180Hz", 192 "200Hz", "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", "320Hz", 193 "340Hz", "360Hz" 194 }; 195 static const char * const sta350_binary_output[] = { 196 "FFX 3-state output - normal operation", "Binary output" 197 }; 198 static const char * const sta350_limiter_select[] = { 199 "Limiter Disabled", "Limiter #1", "Limiter #2" 200 }; 201 static const char * const sta350_limiter_attack_rate[] = { 202 "3.1584", "2.7072", "2.2560", "1.8048", "1.3536", "0.9024", 203 "0.4512", "0.2256", "0.1504", "0.1123", "0.0902", "0.0752", 204 "0.0645", "0.0564", "0.0501", "0.0451" 205 }; 206 static const char * const sta350_limiter_release_rate[] = { 207 "0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299", 208 "0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137", 209 "0.0134", "0.0117", "0.0110", "0.0104" 210 }; 211 static const char * const sta350_noise_shaper_type[] = { 212 "Third order", "Fourth order" 213 }; 214 215 static DECLARE_TLV_DB_RANGE(sta350_limiter_ac_attack_tlv, 216 0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0), 217 8, 16, TLV_DB_SCALE_ITEM(300, 100, 0), 218 ); 219 220 static DECLARE_TLV_DB_RANGE(sta350_limiter_ac_release_tlv, 221 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0), 222 1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0), 223 2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0), 224 3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0), 225 8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0), 226 ); 227 228 static DECLARE_TLV_DB_RANGE(sta350_limiter_drc_attack_tlv, 229 0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0), 230 8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0), 231 14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0), 232 ); 233 234 static DECLARE_TLV_DB_RANGE(sta350_limiter_drc_release_tlv, 235 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0), 236 1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0), 237 3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0), 238 5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0), 239 13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0), 240 ); 241 242 static SOC_ENUM_SINGLE_DECL(sta350_drc_ac_enum, 243 STA350_CONFD, STA350_CONFD_DRC_SHIFT, 244 sta350_drc_ac); 245 static SOC_ENUM_SINGLE_DECL(sta350_noise_shaper_enum, 246 STA350_CONFE, STA350_CONFE_NSBW_SHIFT, 247 sta350_noise_shaper_type); 248 static SOC_ENUM_SINGLE_DECL(sta350_auto_gc_enum, 249 STA350_AUTO1, STA350_AUTO1_AMGC_SHIFT, 250 sta350_auto_gc_mode); 251 static SOC_ENUM_SINGLE_DECL(sta350_auto_xo_enum, 252 STA350_AUTO2, STA350_AUTO2_XO_SHIFT, 253 sta350_auto_xo_mode); 254 static SOC_ENUM_SINGLE_DECL(sta350_binary_output_ch1_enum, 255 STA350_C1CFG, STA350_CxCFG_BO_SHIFT, 256 sta350_binary_output); 257 static SOC_ENUM_SINGLE_DECL(sta350_binary_output_ch2_enum, 258 STA350_C2CFG, STA350_CxCFG_BO_SHIFT, 259 sta350_binary_output); 260 static SOC_ENUM_SINGLE_DECL(sta350_binary_output_ch3_enum, 261 STA350_C3CFG, STA350_CxCFG_BO_SHIFT, 262 sta350_binary_output); 263 static SOC_ENUM_SINGLE_DECL(sta350_limiter_ch1_enum, 264 STA350_C1CFG, STA350_CxCFG_LS_SHIFT, 265 sta350_limiter_select); 266 static SOC_ENUM_SINGLE_DECL(sta350_limiter_ch2_enum, 267 STA350_C2CFG, STA350_CxCFG_LS_SHIFT, 268 sta350_limiter_select); 269 static SOC_ENUM_SINGLE_DECL(sta350_limiter_ch3_enum, 270 STA350_C3CFG, STA350_CxCFG_LS_SHIFT, 271 sta350_limiter_select); 272 static SOC_ENUM_SINGLE_DECL(sta350_limiter1_attack_rate_enum, 273 STA350_L1AR, STA350_LxA_SHIFT, 274 sta350_limiter_attack_rate); 275 static SOC_ENUM_SINGLE_DECL(sta350_limiter2_attack_rate_enum, 276 STA350_L2AR, STA350_LxA_SHIFT, 277 sta350_limiter_attack_rate); 278 static SOC_ENUM_SINGLE_DECL(sta350_limiter1_release_rate_enum, 279 STA350_L1AR, STA350_LxR_SHIFT, 280 sta350_limiter_release_rate); 281 static SOC_ENUM_SINGLE_DECL(sta350_limiter2_release_rate_enum, 282 STA350_L2AR, STA350_LxR_SHIFT, 283 sta350_limiter_release_rate); 284 285 /* 286 * byte array controls for setting biquad, mixer, scaling coefficients; 287 * for biquads all five coefficients need to be set in one go, 288 * mixer and pre/postscale coefs can be set individually; 289 * each coef is 24bit, the bytes are ordered in the same way 290 * as given in the STA350 data sheet (big endian; b1, b2, a1, a2, b0) 291 */ 292 293 static int sta350_coefficient_info(struct snd_kcontrol *kcontrol, 294 struct snd_ctl_elem_info *uinfo) 295 { 296 int numcoef = kcontrol->private_value >> 16; 297 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 298 uinfo->count = 3 * numcoef; 299 return 0; 300 } 301 302 static int sta350_coefficient_get(struct snd_kcontrol *kcontrol, 303 struct snd_ctl_elem_value *ucontrol) 304 { 305 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 306 struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component); 307 int numcoef = kcontrol->private_value >> 16; 308 int index = kcontrol->private_value & 0xffff; 309 unsigned int cfud, val; 310 int i; 311 312 guard(mutex)(&sta350->coeff_lock); 313 314 /* preserve reserved bits in STA350_CFUD */ 315 regmap_read(sta350->regmap, STA350_CFUD, &cfud); 316 cfud &= 0xf0; 317 /* 318 * chip documentation does not say if the bits are self clearing, 319 * so do it explicitly 320 */ 321 regmap_write(sta350->regmap, STA350_CFUD, cfud); 322 323 regmap_write(sta350->regmap, STA350_CFADDR2, index); 324 if (numcoef == 1) 325 regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x04); 326 else if (numcoef == 5) 327 regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x08); 328 else 329 return -EINVAL; 330 331 for (i = 0; i < 3 * numcoef; i++) { 332 regmap_read(sta350->regmap, STA350_B1CF1 + i, &val); 333 ucontrol->value.bytes.data[i] = val; 334 } 335 336 return 0; 337 } 338 339 static int sta350_coefficient_put(struct snd_kcontrol *kcontrol, 340 struct snd_ctl_elem_value *ucontrol) 341 { 342 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 343 struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component); 344 int numcoef = kcontrol->private_value >> 16; 345 int index = kcontrol->private_value & 0xffff; 346 unsigned int cfud; 347 int i; 348 349 /* preserve reserved bits in STA350_CFUD */ 350 regmap_read(sta350->regmap, STA350_CFUD, &cfud); 351 cfud &= 0xf0; 352 /* 353 * chip documentation does not say if the bits are self clearing, 354 * so do it explicitly 355 */ 356 regmap_write(sta350->regmap, STA350_CFUD, cfud); 357 358 regmap_write(sta350->regmap, STA350_CFADDR2, index); 359 for (i = 0; i < numcoef && (index + i < STA350_COEF_COUNT); i++) 360 sta350->coef_shadow[index + i] = 361 (ucontrol->value.bytes.data[3 * i] << 16) 362 | (ucontrol->value.bytes.data[3 * i + 1] << 8) 363 | (ucontrol->value.bytes.data[3 * i + 2]); 364 for (i = 0; i < 3 * numcoef; i++) 365 regmap_write(sta350->regmap, STA350_B1CF1 + i, 366 ucontrol->value.bytes.data[i]); 367 if (numcoef == 1) 368 regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x01); 369 else if (numcoef == 5) 370 regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x02); 371 else 372 return -EINVAL; 373 374 return 0; 375 } 376 377 static int sta350_sync_coef_shadow(struct snd_soc_component *component) 378 { 379 struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component); 380 unsigned int cfud; 381 int i; 382 383 /* preserve reserved bits in STA350_CFUD */ 384 regmap_read(sta350->regmap, STA350_CFUD, &cfud); 385 cfud &= 0xf0; 386 387 for (i = 0; i < STA350_COEF_COUNT; i++) { 388 regmap_write(sta350->regmap, STA350_CFADDR2, i); 389 regmap_write(sta350->regmap, STA350_B1CF1, 390 (sta350->coef_shadow[i] >> 16) & 0xff); 391 regmap_write(sta350->regmap, STA350_B1CF2, 392 (sta350->coef_shadow[i] >> 8) & 0xff); 393 regmap_write(sta350->regmap, STA350_B1CF3, 394 (sta350->coef_shadow[i]) & 0xff); 395 /* 396 * chip documentation does not say if the bits are 397 * self-clearing, so do it explicitly 398 */ 399 regmap_write(sta350->regmap, STA350_CFUD, cfud); 400 regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x01); 401 } 402 return 0; 403 } 404 405 static int sta350_cache_sync(struct snd_soc_component *component) 406 { 407 struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component); 408 unsigned int mute; 409 int rc; 410 411 /* mute during register sync */ 412 regmap_read(sta350->regmap, STA350_CFUD, &mute); 413 regmap_write(sta350->regmap, STA350_MMUTE, mute | STA350_MMUTE_MMUTE); 414 sta350_sync_coef_shadow(component); 415 rc = regcache_sync(sta350->regmap); 416 regmap_write(sta350->regmap, STA350_MMUTE, mute); 417 return rc; 418 } 419 420 #define SINGLE_COEF(xname, index) \ 421 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 422 .info = sta350_coefficient_info, \ 423 .get = sta350_coefficient_get,\ 424 .put = sta350_coefficient_put, \ 425 .private_value = index | (1 << 16) } 426 427 #define BIQUAD_COEFS(xname, index) \ 428 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 429 .info = sta350_coefficient_info, \ 430 .get = sta350_coefficient_get,\ 431 .put = sta350_coefficient_put, \ 432 .private_value = index | (5 << 16) } 433 434 static const struct snd_kcontrol_new sta350_snd_controls[] = { 435 SOC_SINGLE_TLV("Master Volume", STA350_MVOL, 0, 0xff, 1, mvol_tlv), 436 /* VOL */ 437 SOC_SINGLE_TLV("Ch1 Volume", STA350_C1VOL, 0, 0xff, 1, chvol_tlv), 438 SOC_SINGLE_TLV("Ch2 Volume", STA350_C2VOL, 0, 0xff, 1, chvol_tlv), 439 SOC_SINGLE_TLV("Ch3 Volume", STA350_C3VOL, 0, 0xff, 1, chvol_tlv), 440 /* CONFD */ 441 SOC_SINGLE("High Pass Filter Bypass Switch", 442 STA350_CONFD, STA350_CONFD_HPB_SHIFT, 1, 1), 443 SOC_SINGLE("De-emphasis Filter Switch", 444 STA350_CONFD, STA350_CONFD_DEMP_SHIFT, 1, 0), 445 SOC_SINGLE("DSP Bypass Switch", 446 STA350_CONFD, STA350_CONFD_DSPB_SHIFT, 1, 0), 447 SOC_SINGLE("Post-scale Link Switch", 448 STA350_CONFD, STA350_CONFD_PSL_SHIFT, 1, 0), 449 SOC_SINGLE("Biquad Coefficient Link Switch", 450 STA350_CONFD, STA350_CONFD_BQL_SHIFT, 1, 0), 451 SOC_ENUM("Compressor/Limiter Switch", sta350_drc_ac_enum), 452 SOC_ENUM("Noise Shaper Bandwidth", sta350_noise_shaper_enum), 453 SOC_SINGLE("Zero-detect Mute Enable Switch", 454 STA350_CONFD, STA350_CONFD_ZDE_SHIFT, 1, 0), 455 SOC_SINGLE("Submix Mode Switch", 456 STA350_CONFD, STA350_CONFD_SME_SHIFT, 1, 0), 457 /* CONFE */ 458 SOC_SINGLE("Zero Cross Switch", STA350_CONFE, STA350_CONFE_ZCE_SHIFT, 1, 0), 459 SOC_SINGLE("Soft Ramp Switch", STA350_CONFE, STA350_CONFE_SVE_SHIFT, 1, 0), 460 /* MUTE */ 461 SOC_SINGLE("Master Switch", STA350_MMUTE, STA350_MMUTE_MMUTE_SHIFT, 1, 1), 462 SOC_SINGLE("Ch1 Switch", STA350_MMUTE, STA350_MMUTE_C1M_SHIFT, 1, 1), 463 SOC_SINGLE("Ch2 Switch", STA350_MMUTE, STA350_MMUTE_C2M_SHIFT, 1, 1), 464 SOC_SINGLE("Ch3 Switch", STA350_MMUTE, STA350_MMUTE_C3M_SHIFT, 1, 1), 465 /* AUTOx */ 466 SOC_ENUM("Automode GC", sta350_auto_gc_enum), 467 SOC_ENUM("Automode XO", sta350_auto_xo_enum), 468 /* CxCFG */ 469 SOC_SINGLE("Ch1 Tone Control Bypass Switch", 470 STA350_C1CFG, STA350_CxCFG_TCB_SHIFT, 1, 0), 471 SOC_SINGLE("Ch2 Tone Control Bypass Switch", 472 STA350_C2CFG, STA350_CxCFG_TCB_SHIFT, 1, 0), 473 SOC_SINGLE("Ch1 EQ Bypass Switch", 474 STA350_C1CFG, STA350_CxCFG_EQBP_SHIFT, 1, 0), 475 SOC_SINGLE("Ch2 EQ Bypass Switch", 476 STA350_C2CFG, STA350_CxCFG_EQBP_SHIFT, 1, 0), 477 SOC_SINGLE("Ch1 Master Volume Bypass Switch", 478 STA350_C1CFG, STA350_CxCFG_VBP_SHIFT, 1, 0), 479 SOC_SINGLE("Ch2 Master Volume Bypass Switch", 480 STA350_C1CFG, STA350_CxCFG_VBP_SHIFT, 1, 0), 481 SOC_SINGLE("Ch3 Master Volume Bypass Switch", 482 STA350_C1CFG, STA350_CxCFG_VBP_SHIFT, 1, 0), 483 SOC_ENUM("Ch1 Binary Output Select", sta350_binary_output_ch1_enum), 484 SOC_ENUM("Ch2 Binary Output Select", sta350_binary_output_ch2_enum), 485 SOC_ENUM("Ch3 Binary Output Select", sta350_binary_output_ch3_enum), 486 SOC_ENUM("Ch1 Limiter Select", sta350_limiter_ch1_enum), 487 SOC_ENUM("Ch2 Limiter Select", sta350_limiter_ch2_enum), 488 SOC_ENUM("Ch3 Limiter Select", sta350_limiter_ch3_enum), 489 /* TONE */ 490 SOC_SINGLE_RANGE_TLV("Bass Tone Control Volume", 491 STA350_TONE, STA350_TONE_BTC_SHIFT, 1, 13, 0, tone_tlv), 492 SOC_SINGLE_RANGE_TLV("Treble Tone Control Volume", 493 STA350_TONE, STA350_TONE_TTC_SHIFT, 1, 13, 0, tone_tlv), 494 SOC_ENUM("Limiter1 Attack Rate (dB/ms)", sta350_limiter1_attack_rate_enum), 495 SOC_ENUM("Limiter2 Attack Rate (dB/ms)", sta350_limiter2_attack_rate_enum), 496 SOC_ENUM("Limiter1 Release Rate (dB/ms)", sta350_limiter1_release_rate_enum), 497 SOC_ENUM("Limiter2 Release Rate (dB/ms)", sta350_limiter2_release_rate_enum), 498 499 /* 500 * depending on mode, the attack/release thresholds have 501 * two different enum definitions; provide both 502 */ 503 SOC_SINGLE_TLV("Limiter1 Attack Threshold (AC Mode)", 504 STA350_L1ATRT, STA350_LxA_SHIFT, 505 16, 0, sta350_limiter_ac_attack_tlv), 506 SOC_SINGLE_TLV("Limiter2 Attack Threshold (AC Mode)", 507 STA350_L2ATRT, STA350_LxA_SHIFT, 508 16, 0, sta350_limiter_ac_attack_tlv), 509 SOC_SINGLE_TLV("Limiter1 Release Threshold (AC Mode)", 510 STA350_L1ATRT, STA350_LxR_SHIFT, 511 16, 0, sta350_limiter_ac_release_tlv), 512 SOC_SINGLE_TLV("Limiter2 Release Threshold (AC Mode)", 513 STA350_L2ATRT, STA350_LxR_SHIFT, 514 16, 0, sta350_limiter_ac_release_tlv), 515 SOC_SINGLE_TLV("Limiter1 Attack Threshold (DRC Mode)", 516 STA350_L1ATRT, STA350_LxA_SHIFT, 517 16, 0, sta350_limiter_drc_attack_tlv), 518 SOC_SINGLE_TLV("Limiter2 Attack Threshold (DRC Mode)", 519 STA350_L2ATRT, STA350_LxA_SHIFT, 520 16, 0, sta350_limiter_drc_attack_tlv), 521 SOC_SINGLE_TLV("Limiter1 Release Threshold (DRC Mode)", 522 STA350_L1ATRT, STA350_LxR_SHIFT, 523 16, 0, sta350_limiter_drc_release_tlv), 524 SOC_SINGLE_TLV("Limiter2 Release Threshold (DRC Mode)", 525 STA350_L2ATRT, STA350_LxR_SHIFT, 526 16, 0, sta350_limiter_drc_release_tlv), 527 528 BIQUAD_COEFS("Ch1 - Biquad 1", 0), 529 BIQUAD_COEFS("Ch1 - Biquad 2", 5), 530 BIQUAD_COEFS("Ch1 - Biquad 3", 10), 531 BIQUAD_COEFS("Ch1 - Biquad 4", 15), 532 BIQUAD_COEFS("Ch2 - Biquad 1", 20), 533 BIQUAD_COEFS("Ch2 - Biquad 2", 25), 534 BIQUAD_COEFS("Ch2 - Biquad 3", 30), 535 BIQUAD_COEFS("Ch2 - Biquad 4", 35), 536 BIQUAD_COEFS("High-pass", 40), 537 BIQUAD_COEFS("Low-pass", 45), 538 SINGLE_COEF("Ch1 - Prescale", 50), 539 SINGLE_COEF("Ch2 - Prescale", 51), 540 SINGLE_COEF("Ch1 - Postscale", 52), 541 SINGLE_COEF("Ch2 - Postscale", 53), 542 SINGLE_COEF("Ch3 - Postscale", 54), 543 SINGLE_COEF("Thermal warning - Postscale", 55), 544 SINGLE_COEF("Ch1 - Mix 1", 56), 545 SINGLE_COEF("Ch1 - Mix 2", 57), 546 SINGLE_COEF("Ch2 - Mix 1", 58), 547 SINGLE_COEF("Ch2 - Mix 2", 59), 548 SINGLE_COEF("Ch3 - Mix 1", 60), 549 SINGLE_COEF("Ch3 - Mix 2", 61), 550 }; 551 552 static const struct snd_soc_dapm_widget sta350_dapm_widgets[] = { 553 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0), 554 SND_SOC_DAPM_OUTPUT("LEFT"), 555 SND_SOC_DAPM_OUTPUT("RIGHT"), 556 SND_SOC_DAPM_OUTPUT("SUB"), 557 }; 558 559 static const struct snd_soc_dapm_route sta350_dapm_routes[] = { 560 { "LEFT", NULL, "DAC" }, 561 { "RIGHT", NULL, "DAC" }, 562 { "SUB", NULL, "DAC" }, 563 { "DAC", NULL, "Playback" }, 564 }; 565 566 /* MCLK interpolation ratio per fs */ 567 static struct { 568 int fs; 569 int ir; 570 } interpolation_ratios[] = { 571 { 32000, 0 }, 572 { 44100, 0 }, 573 { 48000, 0 }, 574 { 88200, 1 }, 575 { 96000, 1 }, 576 { 176400, 2 }, 577 { 192000, 2 }, 578 }; 579 580 /* MCLK to fs clock ratios */ 581 static int mcs_ratio_table[3][6] = { 582 { 768, 512, 384, 256, 128, 576 }, 583 { 384, 256, 192, 128, 64, 0 }, 584 { 192, 128, 96, 64, 32, 0 }, 585 }; 586 587 /** 588 * sta350_set_dai_sysclk - configure MCLK 589 * @codec_dai: the codec DAI 590 * @clk_id: the clock ID (ignored) 591 * @freq: the MCLK input frequency 592 * @dir: the clock direction (ignored) 593 * 594 * The value of MCLK is used to determine which sample rates are supported 595 * by the STA350, based on the mcs_ratio_table. 596 * 597 * This function must be called by the machine driver's 'startup' function, 598 * otherwise the list of supported sample rates will not be available in 599 * time for ALSA. 600 */ 601 static int sta350_set_dai_sysclk(struct snd_soc_dai *codec_dai, 602 int clk_id, unsigned int freq, int dir) 603 { 604 struct snd_soc_component *component = codec_dai->component; 605 struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component); 606 607 dev_dbg(component->dev, "mclk=%u\n", freq); 608 sta350->mclk = freq; 609 610 return 0; 611 } 612 613 /** 614 * sta350_set_dai_fmt - configure the codec for the selected audio format 615 * @codec_dai: the codec DAI 616 * @fmt: a SND_SOC_DAIFMT_x value indicating the data format 617 * 618 * This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the 619 * codec accordingly. 620 */ 621 static int sta350_set_dai_fmt(struct snd_soc_dai *codec_dai, 622 unsigned int fmt) 623 { 624 struct snd_soc_component *component = codec_dai->component; 625 struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component); 626 unsigned int confb = 0; 627 628 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 629 case SND_SOC_DAIFMT_CBC_CFC: 630 break; 631 default: 632 return -EINVAL; 633 } 634 635 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 636 case SND_SOC_DAIFMT_I2S: 637 case SND_SOC_DAIFMT_RIGHT_J: 638 case SND_SOC_DAIFMT_LEFT_J: 639 sta350->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 640 break; 641 default: 642 return -EINVAL; 643 } 644 645 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 646 case SND_SOC_DAIFMT_NB_NF: 647 confb |= STA350_CONFB_C2IM; 648 break; 649 case SND_SOC_DAIFMT_NB_IF: 650 confb |= STA350_CONFB_C1IM; 651 break; 652 default: 653 return -EINVAL; 654 } 655 656 return regmap_update_bits(sta350->regmap, STA350_CONFB, 657 STA350_CONFB_C1IM | STA350_CONFB_C2IM, confb); 658 } 659 660 /** 661 * sta350_hw_params - program the STA350 with the given hardware parameters. 662 * @substream: the audio stream 663 * @params: the hardware parameters to set 664 * @dai: the SOC DAI (ignored) 665 * 666 * This function programs the hardware with the values provided. 667 * Specifically, the sample rate and the data format. 668 */ 669 static int sta350_hw_params(struct snd_pcm_substream *substream, 670 struct snd_pcm_hw_params *params, 671 struct snd_soc_dai *dai) 672 { 673 struct snd_soc_component *component = dai->component; 674 struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component); 675 int i, mcs = -EINVAL, ir = -EINVAL; 676 unsigned int confa, confb; 677 unsigned int rate, ratio; 678 int ret; 679 680 if (!sta350->mclk) { 681 dev_err(component->dev, 682 "sta350->mclk is unset. Unable to determine ratio\n"); 683 return -EIO; 684 } 685 686 rate = params_rate(params); 687 ratio = sta350->mclk / rate; 688 dev_dbg(component->dev, "rate: %u, ratio: %u\n", rate, ratio); 689 690 for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) { 691 if (interpolation_ratios[i].fs == rate) { 692 ir = interpolation_ratios[i].ir; 693 break; 694 } 695 } 696 697 if (ir < 0) { 698 dev_err(component->dev, "Unsupported samplerate: %u\n", rate); 699 return -EINVAL; 700 } 701 702 for (i = 0; i < 6; i++) { 703 if (mcs_ratio_table[ir][i] == ratio) { 704 mcs = i; 705 break; 706 } 707 } 708 709 if (mcs < 0) { 710 dev_err(component->dev, "Unresolvable ratio: %u\n", ratio); 711 return -EINVAL; 712 } 713 714 confa = (ir << STA350_CONFA_IR_SHIFT) | 715 (mcs << STA350_CONFA_MCS_SHIFT); 716 confb = 0; 717 718 switch (params_width(params)) { 719 case 24: 720 dev_dbg(component->dev, "24bit\n"); 721 fallthrough; 722 case 32: 723 dev_dbg(component->dev, "24bit or 32bit\n"); 724 switch (sta350->format) { 725 case SND_SOC_DAIFMT_I2S: 726 confb |= 0x0; 727 break; 728 case SND_SOC_DAIFMT_LEFT_J: 729 confb |= 0x1; 730 break; 731 case SND_SOC_DAIFMT_RIGHT_J: 732 confb |= 0x2; 733 break; 734 } 735 736 break; 737 case 20: 738 dev_dbg(component->dev, "20bit\n"); 739 switch (sta350->format) { 740 case SND_SOC_DAIFMT_I2S: 741 confb |= 0x4; 742 break; 743 case SND_SOC_DAIFMT_LEFT_J: 744 confb |= 0x5; 745 break; 746 case SND_SOC_DAIFMT_RIGHT_J: 747 confb |= 0x6; 748 break; 749 } 750 751 break; 752 case 18: 753 dev_dbg(component->dev, "18bit\n"); 754 switch (sta350->format) { 755 case SND_SOC_DAIFMT_I2S: 756 confb |= 0x8; 757 break; 758 case SND_SOC_DAIFMT_LEFT_J: 759 confb |= 0x9; 760 break; 761 case SND_SOC_DAIFMT_RIGHT_J: 762 confb |= 0xa; 763 break; 764 } 765 766 break; 767 case 16: 768 dev_dbg(component->dev, "16bit\n"); 769 switch (sta350->format) { 770 case SND_SOC_DAIFMT_I2S: 771 confb |= 0x0; 772 break; 773 case SND_SOC_DAIFMT_LEFT_J: 774 confb |= 0xd; 775 break; 776 case SND_SOC_DAIFMT_RIGHT_J: 777 confb |= 0xe; 778 break; 779 } 780 781 break; 782 default: 783 return -EINVAL; 784 } 785 786 ret = regmap_update_bits(sta350->regmap, STA350_CONFA, 787 STA350_CONFA_MCS_MASK | STA350_CONFA_IR_MASK, 788 confa); 789 if (ret < 0) 790 return ret; 791 792 ret = regmap_update_bits(sta350->regmap, STA350_CONFB, 793 STA350_CONFB_SAI_MASK | STA350_CONFB_SAIFB, 794 confb); 795 if (ret < 0) 796 return ret; 797 798 return 0; 799 } 800 801 static int sta350_startup_sequence(struct sta350_priv *sta350) 802 { 803 if (sta350->gpiod_power_down) 804 gpiod_set_value(sta350->gpiod_power_down, 1); 805 806 if (sta350->gpiod_nreset) { 807 gpiod_set_value(sta350->gpiod_nreset, 0); 808 mdelay(1); 809 gpiod_set_value(sta350->gpiod_nreset, 1); 810 mdelay(1); 811 } 812 813 return 0; 814 } 815 816 /** 817 * sta350_set_bias_level - DAPM callback 818 * @component: the component device 819 * @level: DAPM power level 820 * 821 * This is called by ALSA to put the component into low power mode 822 * or to wake it up. If the component is powered off completely 823 * all registers must be restored after power on. 824 */ 825 static int sta350_set_bias_level(struct snd_soc_component *component, 826 enum snd_soc_bias_level level) 827 { 828 struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component); 829 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 830 int ret; 831 832 dev_dbg(component->dev, "level = %d\n", level); 833 switch (level) { 834 case SND_SOC_BIAS_ON: 835 break; 836 837 case SND_SOC_BIAS_PREPARE: 838 /* Full power on */ 839 regmap_update_bits(sta350->regmap, STA350_CONFF, 840 STA350_CONFF_PWDN | STA350_CONFF_EAPD, 841 STA350_CONFF_PWDN | STA350_CONFF_EAPD); 842 break; 843 844 case SND_SOC_BIAS_STANDBY: 845 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) { 846 ret = regulator_bulk_enable( 847 ARRAY_SIZE(sta350->supplies), 848 sta350->supplies); 849 if (ret < 0) { 850 dev_err(component->dev, 851 "Failed to enable supplies: %d\n", 852 ret); 853 return ret; 854 } 855 sta350_startup_sequence(sta350); 856 sta350_cache_sync(component); 857 } 858 859 /* Power down */ 860 regmap_update_bits(sta350->regmap, STA350_CONFF, 861 STA350_CONFF_PWDN | STA350_CONFF_EAPD, 862 0); 863 864 break; 865 866 case SND_SOC_BIAS_OFF: 867 /* The chip runs through the power down sequence for us */ 868 regmap_update_bits(sta350->regmap, STA350_CONFF, 869 STA350_CONFF_PWDN | STA350_CONFF_EAPD, 0); 870 871 /* power down: low */ 872 if (sta350->gpiod_power_down) 873 gpiod_set_value(sta350->gpiod_power_down, 0); 874 875 if (sta350->gpiod_nreset) 876 gpiod_set_value(sta350->gpiod_nreset, 0); 877 878 regulator_bulk_disable(ARRAY_SIZE(sta350->supplies), 879 sta350->supplies); 880 break; 881 } 882 return 0; 883 } 884 885 static const struct snd_soc_dai_ops sta350_dai_ops = { 886 .hw_params = sta350_hw_params, 887 .set_sysclk = sta350_set_dai_sysclk, 888 .set_fmt = sta350_set_dai_fmt, 889 }; 890 891 static struct snd_soc_dai_driver sta350_dai = { 892 .name = "sta350-hifi", 893 .playback = { 894 .stream_name = "Playback", 895 .channels_min = 2, 896 .channels_max = 2, 897 .rates = STA350_RATES, 898 .formats = STA350_FORMATS, 899 }, 900 .ops = &sta350_dai_ops, 901 }; 902 903 static int sta350_probe(struct snd_soc_component *component) 904 { 905 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 906 struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component); 907 struct sta350_platform_data *pdata = sta350->pdata; 908 int i, ret = 0, thermal = 0; 909 910 ret = regulator_bulk_enable(ARRAY_SIZE(sta350->supplies), 911 sta350->supplies); 912 if (ret < 0) { 913 dev_err(component->dev, "Failed to enable supplies: %d\n", ret); 914 return ret; 915 } 916 917 ret = sta350_startup_sequence(sta350); 918 if (ret < 0) { 919 dev_err(component->dev, "Failed to startup device\n"); 920 return ret; 921 } 922 923 /* CONFA */ 924 if (!pdata->thermal_warning_recovery) 925 thermal |= STA350_CONFA_TWAB; 926 if (!pdata->thermal_warning_adjustment) 927 thermal |= STA350_CONFA_TWRB; 928 if (!pdata->fault_detect_recovery) 929 thermal |= STA350_CONFA_FDRB; 930 regmap_update_bits(sta350->regmap, STA350_CONFA, 931 STA350_CONFA_TWAB | STA350_CONFA_TWRB | 932 STA350_CONFA_FDRB, 933 thermal); 934 935 /* CONFC */ 936 regmap_update_bits(sta350->regmap, STA350_CONFC, 937 STA350_CONFC_OM_MASK, 938 pdata->ffx_power_output_mode 939 << STA350_CONFC_OM_SHIFT); 940 regmap_update_bits(sta350->regmap, STA350_CONFC, 941 STA350_CONFC_CSZ_MASK, 942 pdata->drop_compensation_ns 943 << STA350_CONFC_CSZ_SHIFT); 944 regmap_update_bits(sta350->regmap, 945 STA350_CONFC, 946 STA350_CONFC_OCRB, 947 pdata->oc_warning_adjustment ? 948 STA350_CONFC_OCRB : 0); 949 950 /* CONFE */ 951 regmap_update_bits(sta350->regmap, STA350_CONFE, 952 STA350_CONFE_MPCV, 953 pdata->max_power_use_mpcc ? 954 STA350_CONFE_MPCV : 0); 955 regmap_update_bits(sta350->regmap, STA350_CONFE, 956 STA350_CONFE_MPC, 957 pdata->max_power_correction ? 958 STA350_CONFE_MPC : 0); 959 regmap_update_bits(sta350->regmap, STA350_CONFE, 960 STA350_CONFE_AME, 961 pdata->am_reduction_mode ? 962 STA350_CONFE_AME : 0); 963 regmap_update_bits(sta350->regmap, STA350_CONFE, 964 STA350_CONFE_PWMS, 965 pdata->odd_pwm_speed_mode ? 966 STA350_CONFE_PWMS : 0); 967 regmap_update_bits(sta350->regmap, STA350_CONFE, 968 STA350_CONFE_DCCV, 969 pdata->distortion_compensation ? 970 STA350_CONFE_DCCV : 0); 971 /* CONFF */ 972 regmap_update_bits(sta350->regmap, STA350_CONFF, 973 STA350_CONFF_IDE, 974 pdata->invalid_input_detect_mute ? 975 STA350_CONFF_IDE : 0); 976 regmap_update_bits(sta350->regmap, STA350_CONFF, 977 STA350_CONFF_OCFG_MASK, 978 pdata->output_conf 979 << STA350_CONFF_OCFG_SHIFT); 980 981 /* channel to output mapping */ 982 regmap_update_bits(sta350->regmap, STA350_C1CFG, 983 STA350_CxCFG_OM_MASK, 984 pdata->ch1_output_mapping 985 << STA350_CxCFG_OM_SHIFT); 986 regmap_update_bits(sta350->regmap, STA350_C2CFG, 987 STA350_CxCFG_OM_MASK, 988 pdata->ch2_output_mapping 989 << STA350_CxCFG_OM_SHIFT); 990 regmap_update_bits(sta350->regmap, STA350_C3CFG, 991 STA350_CxCFG_OM_MASK, 992 pdata->ch3_output_mapping 993 << STA350_CxCFG_OM_SHIFT); 994 995 /* miscellaneous registers */ 996 regmap_update_bits(sta350->regmap, STA350_MISC1, 997 STA350_MISC1_CPWMEN, 998 pdata->activate_mute_output ? 999 STA350_MISC1_CPWMEN : 0); 1000 regmap_update_bits(sta350->regmap, STA350_MISC1, 1001 STA350_MISC1_BRIDGOFF, 1002 pdata->bridge_immediate_off ? 1003 STA350_MISC1_BRIDGOFF : 0); 1004 regmap_update_bits(sta350->regmap, STA350_MISC1, 1005 STA350_MISC1_NSHHPEN, 1006 pdata->noise_shape_dc_cut ? 1007 STA350_MISC1_NSHHPEN : 0); 1008 regmap_update_bits(sta350->regmap, STA350_MISC1, 1009 STA350_MISC1_RPDNEN, 1010 pdata->powerdown_master_vol ? 1011 STA350_MISC1_RPDNEN: 0); 1012 1013 regmap_update_bits(sta350->regmap, STA350_MISC2, 1014 STA350_MISC2_PNDLSL_MASK, 1015 pdata->powerdown_delay_divider 1016 << STA350_MISC2_PNDLSL_SHIFT); 1017 1018 /* initialize coefficient shadow RAM with reset values */ 1019 for (i = 4; i <= 49; i += 5) 1020 sta350->coef_shadow[i] = 0x400000; 1021 for (i = 50; i <= 54; i++) 1022 sta350->coef_shadow[i] = 0x7fffff; 1023 sta350->coef_shadow[55] = 0x5a9df7; 1024 sta350->coef_shadow[56] = 0x7fffff; 1025 sta350->coef_shadow[59] = 0x7fffff; 1026 sta350->coef_shadow[60] = 0x400000; 1027 sta350->coef_shadow[61] = 0x400000; 1028 1029 snd_soc_dapm_force_bias_level(dapm, SND_SOC_BIAS_STANDBY); 1030 /* Bias level configuration will have done an extra enable */ 1031 regulator_bulk_disable(ARRAY_SIZE(sta350->supplies), sta350->supplies); 1032 1033 return 0; 1034 } 1035 1036 static void sta350_remove(struct snd_soc_component *component) 1037 { 1038 struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component); 1039 1040 regulator_bulk_disable(ARRAY_SIZE(sta350->supplies), sta350->supplies); 1041 } 1042 1043 static const struct snd_soc_component_driver sta350_component = { 1044 .probe = sta350_probe, 1045 .remove = sta350_remove, 1046 .set_bias_level = sta350_set_bias_level, 1047 .controls = sta350_snd_controls, 1048 .num_controls = ARRAY_SIZE(sta350_snd_controls), 1049 .dapm_widgets = sta350_dapm_widgets, 1050 .num_dapm_widgets = ARRAY_SIZE(sta350_dapm_widgets), 1051 .dapm_routes = sta350_dapm_routes, 1052 .num_dapm_routes = ARRAY_SIZE(sta350_dapm_routes), 1053 .suspend_bias_off = 1, 1054 .idle_bias_on = 1, 1055 .use_pmdown_time = 1, 1056 .endianness = 1, 1057 }; 1058 1059 static const struct regmap_config sta350_regmap = { 1060 .reg_bits = 8, 1061 .val_bits = 8, 1062 .max_register = STA350_MISC2, 1063 .reg_defaults = sta350_regs, 1064 .num_reg_defaults = ARRAY_SIZE(sta350_regs), 1065 .cache_type = REGCACHE_MAPLE, 1066 .wr_table = &sta350_write_regs, 1067 .rd_table = &sta350_read_regs, 1068 .volatile_table = &sta350_volatile_regs, 1069 }; 1070 1071 #ifdef CONFIG_OF 1072 static const struct of_device_id st350_dt_ids[] = { 1073 { .compatible = "st,sta350", }, 1074 { } 1075 }; 1076 MODULE_DEVICE_TABLE(of, st350_dt_ids); 1077 1078 static const char * const sta350_ffx_modes[] = { 1079 [STA350_FFX_PM_DROP_COMP] = "drop-compensation", 1080 [STA350_FFX_PM_TAPERED_COMP] = "tapered-compensation", 1081 [STA350_FFX_PM_FULL_POWER] = "full-power-mode", 1082 [STA350_FFX_PM_VARIABLE_DROP_COMP] = "variable-drop-compensation", 1083 }; 1084 1085 static int sta350_probe_dt(struct device *dev, struct sta350_priv *sta350) 1086 { 1087 struct device_node *np = dev->of_node; 1088 struct sta350_platform_data *pdata; 1089 const char *ffx_power_mode; 1090 u16 tmp; 1091 u8 tmp8; 1092 1093 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 1094 if (!pdata) 1095 return -ENOMEM; 1096 1097 of_property_read_u8(np, "st,output-conf", 1098 &pdata->output_conf); 1099 of_property_read_u8(np, "st,ch1-output-mapping", 1100 &pdata->ch1_output_mapping); 1101 of_property_read_u8(np, "st,ch2-output-mapping", 1102 &pdata->ch2_output_mapping); 1103 of_property_read_u8(np, "st,ch3-output-mapping", 1104 &pdata->ch3_output_mapping); 1105 1106 pdata->thermal_warning_recovery = 1107 of_property_read_bool(np, "st,thermal-warning-recovery"); 1108 pdata->thermal_warning_adjustment = 1109 of_property_read_bool(np, "st,thermal-warning-adjustment"); 1110 pdata->fault_detect_recovery = 1111 of_property_read_bool(np, "st,fault-detect-recovery"); 1112 1113 pdata->ffx_power_output_mode = STA350_FFX_PM_VARIABLE_DROP_COMP; 1114 if (!of_property_read_string(np, "st,ffx-power-output-mode", 1115 &ffx_power_mode)) { 1116 int i, mode = -EINVAL; 1117 1118 for (i = 0; i < ARRAY_SIZE(sta350_ffx_modes); i++) 1119 if (!strcasecmp(ffx_power_mode, sta350_ffx_modes[i])) 1120 mode = i; 1121 1122 if (mode < 0) 1123 dev_warn(dev, "Unsupported ffx output mode: %s\n", 1124 ffx_power_mode); 1125 else 1126 pdata->ffx_power_output_mode = mode; 1127 } 1128 1129 tmp = 140; 1130 of_property_read_u16(np, "st,drop-compensation-ns", &tmp); 1131 pdata->drop_compensation_ns = clamp_t(u16, tmp, 0, 300) / 20; 1132 1133 pdata->oc_warning_adjustment = 1134 of_property_read_bool(np, "st,overcurrent-warning-adjustment"); 1135 1136 /* CONFE */ 1137 pdata->max_power_use_mpcc = 1138 of_property_read_bool(np, "st,max-power-use-mpcc"); 1139 pdata->max_power_correction = 1140 of_property_read_bool(np, "st,max-power-correction"); 1141 pdata->am_reduction_mode = 1142 of_property_read_bool(np, "st,am-reduction-mode"); 1143 pdata->odd_pwm_speed_mode = 1144 of_property_read_bool(np, "st,odd-pwm-speed-mode"); 1145 pdata->distortion_compensation = 1146 of_property_read_bool(np, "st,distortion-compensation"); 1147 1148 /* CONFF */ 1149 pdata->invalid_input_detect_mute = 1150 of_property_read_bool(np, "st,invalid-input-detect-mute"); 1151 1152 /* MISC */ 1153 pdata->activate_mute_output = 1154 of_property_read_bool(np, "st,activate-mute-output"); 1155 pdata->bridge_immediate_off = 1156 of_property_read_bool(np, "st,bridge-immediate-off"); 1157 pdata->noise_shape_dc_cut = 1158 of_property_read_bool(np, "st,noise-shape-dc-cut"); 1159 pdata->powerdown_master_vol = 1160 of_property_read_bool(np, "st,powerdown-master-volume"); 1161 1162 if (!of_property_read_u8(np, "st,powerdown-delay-divider", &tmp8)) { 1163 if (is_power_of_2(tmp8) && tmp8 >= 1 && tmp8 <= 128) 1164 pdata->powerdown_delay_divider = ilog2(tmp8); 1165 else 1166 dev_warn(dev, "Unsupported powerdown delay divider %d\n", 1167 tmp8); 1168 } 1169 1170 sta350->pdata = pdata; 1171 1172 return 0; 1173 } 1174 #endif 1175 1176 static int sta350_i2c_probe(struct i2c_client *i2c) 1177 { 1178 struct device *dev = &i2c->dev; 1179 struct sta350_priv *sta350; 1180 int ret, i; 1181 1182 sta350 = devm_kzalloc(dev, sizeof(struct sta350_priv), GFP_KERNEL); 1183 if (!sta350) 1184 return -ENOMEM; 1185 1186 mutex_init(&sta350->coeff_lock); 1187 sta350->pdata = dev_get_platdata(dev); 1188 1189 #ifdef CONFIG_OF 1190 if (dev->of_node) { 1191 ret = sta350_probe_dt(dev, sta350); 1192 if (ret < 0) 1193 return ret; 1194 } 1195 #endif 1196 1197 /* GPIOs */ 1198 sta350->gpiod_nreset = devm_gpiod_get_optional(dev, "reset", 1199 GPIOD_OUT_LOW); 1200 if (IS_ERR(sta350->gpiod_nreset)) 1201 return PTR_ERR(sta350->gpiod_nreset); 1202 1203 sta350->gpiod_power_down = devm_gpiod_get_optional(dev, "power-down", 1204 GPIOD_OUT_LOW); 1205 if (IS_ERR(sta350->gpiod_power_down)) 1206 return PTR_ERR(sta350->gpiod_power_down); 1207 1208 /* regulators */ 1209 for (i = 0; i < ARRAY_SIZE(sta350->supplies); i++) 1210 sta350->supplies[i].supply = sta350_supply_names[i]; 1211 1212 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(sta350->supplies), 1213 sta350->supplies); 1214 if (ret < 0) { 1215 dev_err(dev, "Failed to request supplies: %d\n", ret); 1216 return ret; 1217 } 1218 1219 sta350->regmap = devm_regmap_init_i2c(i2c, &sta350_regmap); 1220 if (IS_ERR(sta350->regmap)) { 1221 ret = PTR_ERR(sta350->regmap); 1222 dev_err(dev, "Failed to init regmap: %d\n", ret); 1223 return ret; 1224 } 1225 1226 i2c_set_clientdata(i2c, sta350); 1227 1228 ret = devm_snd_soc_register_component(dev, &sta350_component, &sta350_dai, 1); 1229 if (ret < 0) 1230 dev_err(dev, "Failed to register component (%d)\n", ret); 1231 1232 return ret; 1233 } 1234 1235 static const struct i2c_device_id sta350_i2c_id[] = { 1236 { .name = "sta350" }, 1237 { } 1238 }; 1239 MODULE_DEVICE_TABLE(i2c, sta350_i2c_id); 1240 1241 static struct i2c_driver sta350_i2c_driver = { 1242 .driver = { 1243 .name = "sta350", 1244 .of_match_table = of_match_ptr(st350_dt_ids), 1245 }, 1246 .probe = sta350_i2c_probe, 1247 .id_table = sta350_i2c_id, 1248 }; 1249 1250 module_i2c_driver(sta350_i2c_driver); 1251 1252 MODULE_DESCRIPTION("ASoC STA350 driver"); 1253 MODULE_AUTHOR("Sven Brandau <info@brandau.biz>"); 1254 MODULE_LICENSE("GPL"); 1255