1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * Creative Labs, Inc. 5 * Routines for control of EMU10K1 chips 6 * 7 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk> 8 * Added support for Audigy 2 Value. 9 * Added EMU 1010 support. 10 * General bug fixes and enhancements. 11 * 12 * BUGS: 13 * -- 14 * 15 * TODO: 16 * -- 17 */ 18 19 #include <linux/sched.h> 20 #include <linux/delay.h> 21 #include <linux/init.h> 22 #include <linux/module.h> 23 #include <linux/interrupt.h> 24 #include <linux/iommu.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include <linux/vmalloc.h> 28 #include <linux/mutex.h> 29 30 31 #include <sound/core.h> 32 #include <sound/emu10k1.h> 33 #include <linux/firmware.h> 34 #include "p16v.h" 35 #include "tina2.h" 36 #include "p17v.h" 37 38 39 #define HANA_FILENAME "emu/hana.fw" 40 #define DOCK_FILENAME "emu/audio_dock.fw" 41 #define EMU1010B_FILENAME "emu/emu1010b.fw" 42 #define MICRO_DOCK_FILENAME "emu/micro_dock.fw" 43 #define EMU0404_FILENAME "emu/emu0404.fw" 44 #define EMU1010_NOTEBOOK_FILENAME "emu/emu1010_notebook.fw" 45 46 MODULE_FIRMWARE(HANA_FILENAME); 47 MODULE_FIRMWARE(DOCK_FILENAME); 48 MODULE_FIRMWARE(EMU1010B_FILENAME); 49 MODULE_FIRMWARE(MICRO_DOCK_FILENAME); 50 MODULE_FIRMWARE(EMU0404_FILENAME); 51 MODULE_FIRMWARE(EMU1010_NOTEBOOK_FILENAME); 52 53 54 /************************************************************************* 55 * EMU10K1 init / done 56 *************************************************************************/ 57 58 void snd_emu10k1_voice_init(struct snd_emu10k1 *emu, int ch) 59 { 60 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0); 61 snd_emu10k1_ptr_write(emu, VTFT, ch, VTFT_FILTERTARGET_MASK); 62 snd_emu10k1_ptr_write(emu, CVCF, ch, CVCF_CURRENTFILTER_MASK); 63 snd_emu10k1_ptr_write(emu, PTRX, ch, 0); 64 snd_emu10k1_ptr_write(emu, CPF, ch, 0); 65 snd_emu10k1_ptr_write(emu, CCR, ch, 0); 66 67 snd_emu10k1_ptr_write(emu, PSST, ch, 0); 68 snd_emu10k1_ptr_write(emu, DSL, ch, 0x10); 69 snd_emu10k1_ptr_write(emu, CCCA, ch, 0); 70 snd_emu10k1_ptr_write(emu, Z1, ch, 0); 71 snd_emu10k1_ptr_write(emu, Z2, ch, 0); 72 snd_emu10k1_ptr_write(emu, FXRT, ch, 0x32100000); 73 74 // The rest is meaningless as long as DCYSUSV_CHANNELENABLE_MASK is zero 75 snd_emu10k1_ptr_write(emu, DCYSUSM, ch, 0); 76 snd_emu10k1_ptr_write(emu, ATKHLDV, ch, 0); 77 snd_emu10k1_ptr_write(emu, ATKHLDM, ch, 0); 78 snd_emu10k1_ptr_write(emu, IP, ch, 0); 79 snd_emu10k1_ptr_write(emu, IFATN, ch, IFATN_FILTERCUTOFF_MASK | IFATN_ATTENUATION_MASK); 80 snd_emu10k1_ptr_write(emu, PEFE, ch, 0); 81 snd_emu10k1_ptr_write(emu, FMMOD, ch, 0); 82 snd_emu10k1_ptr_write(emu, TREMFRQ, ch, 24); /* 1 Hz */ 83 snd_emu10k1_ptr_write(emu, FM2FRQ2, ch, 24); /* 1 Hz */ 84 snd_emu10k1_ptr_write(emu, LFOVAL2, ch, 0); 85 snd_emu10k1_ptr_write(emu, LFOVAL1, ch, 0); 86 snd_emu10k1_ptr_write(emu, ENVVOL, ch, 0); 87 snd_emu10k1_ptr_write(emu, ENVVAL, ch, 0); 88 89 /* Audigy extra stuffs */ 90 if (emu->audigy) { 91 snd_emu10k1_ptr_write(emu, A_CSBA, ch, 0); 92 snd_emu10k1_ptr_write(emu, A_CSDC, ch, 0); 93 snd_emu10k1_ptr_write(emu, A_CSFE, ch, 0); 94 snd_emu10k1_ptr_write(emu, A_CSHG, ch, 0); 95 snd_emu10k1_ptr_write(emu, A_FXRT1, ch, 0x03020100); 96 snd_emu10k1_ptr_write(emu, A_FXRT2, ch, 0x07060504); 97 snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, ch, 0); 98 } 99 } 100 101 static const unsigned int spi_dac_init[] = { 102 0x00ff, 103 0x02ff, 104 0x0400, 105 0x0520, 106 0x0600, 107 0x08ff, 108 0x0aff, 109 0x0cff, 110 0x0eff, 111 0x10ff, 112 0x1200, 113 0x1400, 114 0x1480, 115 0x1800, 116 0x1aff, 117 0x1cff, 118 0x1e00, 119 0x0530, 120 0x0602, 121 0x0622, 122 0x1400, 123 }; 124 125 static const unsigned int i2c_adc_init[][2] = { 126 { 0x17, 0x00 }, /* Reset */ 127 { 0x07, 0x00 }, /* Timeout */ 128 { 0x0b, 0x22 }, /* Interface control */ 129 { 0x0c, 0x22 }, /* Master mode control */ 130 { 0x0d, 0x08 }, /* Powerdown control */ 131 { 0x0e, 0xcf }, /* Attenuation Left 0x01 = -103dB, 0xff = 24dB */ 132 { 0x0f, 0xcf }, /* Attenuation Right 0.5dB steps */ 133 { 0x10, 0x7b }, /* ALC Control 1 */ 134 { 0x11, 0x00 }, /* ALC Control 2 */ 135 { 0x12, 0x32 }, /* ALC Control 3 */ 136 { 0x13, 0x00 }, /* Noise gate control */ 137 { 0x14, 0xa6 }, /* Limiter control */ 138 { 0x15, ADC_MUX_2 }, /* ADC Mixer control. Mic for A2ZS Notebook */ 139 }; 140 141 static int snd_emu10k1_init(struct snd_emu10k1 *emu, int enable_ir) 142 { 143 unsigned int silent_page; 144 int ch; 145 u32 tmp; 146 147 /* disable audio and lock cache */ 148 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | 149 HCFG_MUTEBUTTONENABLE, emu->port + HCFG); 150 151 /* reset recording buffers */ 152 snd_emu10k1_ptr_write(emu, MICBS, 0, ADCBS_BUFSIZE_NONE); 153 snd_emu10k1_ptr_write(emu, MICBA, 0, 0); 154 snd_emu10k1_ptr_write(emu, FXBS, 0, ADCBS_BUFSIZE_NONE); 155 snd_emu10k1_ptr_write(emu, FXBA, 0, 0); 156 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE); 157 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0); 158 159 /* disable channel interrupt */ 160 outl(0, emu->port + INTE); 161 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0); 162 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0); 163 164 /* disable stop on loop end */ 165 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0); 166 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0); 167 168 if (emu->audigy) { 169 /* set SPDIF bypass mode */ 170 snd_emu10k1_ptr_write(emu, SPBYPASS, 0, SPBYPASS_FORMAT); 171 /* enable rear left + rear right AC97 slots */ 172 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_REAR_RIGHT | 173 AC97SLOT_REAR_LEFT); 174 } 175 176 /* init envelope engine */ 177 for (ch = 0; ch < NUM_G; ch++) 178 snd_emu10k1_voice_init(emu, ch); 179 180 snd_emu10k1_ptr_write(emu, SPCS0, 0, emu->spdif_bits[0]); 181 snd_emu10k1_ptr_write(emu, SPCS1, 0, emu->spdif_bits[1]); 182 snd_emu10k1_ptr_write(emu, SPCS2, 0, emu->spdif_bits[2]); 183 184 if (emu->card_capabilities->emu_model) { 185 } else if (emu->card_capabilities->ca0151_chip) { /* audigy2 */ 186 /* Hacks for Alice3 to work independent of haP16V driver */ 187 /* Setup SRCMulti_I2S SamplingRate */ 188 snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, 0, A_I2S_CAPTURE_96000); 189 190 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */ 191 snd_emu10k1_ptr20_write(emu, SRCSel, 0, 0x14); 192 /* Setup SRCMulti Input Audio Enable */ 193 /* Use 0xFFFFFFFF to enable P16V sounds. */ 194 snd_emu10k1_ptr20_write(emu, SRCMULTI_ENABLE, 0, 0xFFFFFFFF); 195 196 /* Enabled Phased (8-channel) P16V playback */ 197 outl(0x0201, emu->port + HCFG2); 198 /* Set playback routing. */ 199 snd_emu10k1_ptr20_write(emu, CAPTURE_P16V_SOURCE, 0, 0x78e4); 200 } else if (emu->card_capabilities->ca0108_chip) { /* audigy2 Value */ 201 /* Hacks for Alice3 to work independent of haP16V driver */ 202 dev_info(emu->card->dev, "Audigy2 value: Special config.\n"); 203 /* Setup SRCMulti_I2S SamplingRate */ 204 snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, 0, A_I2S_CAPTURE_96000); 205 206 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */ 207 snd_emu10k1_ptr20_write(emu, P17V_SRCSel, 0, 0x14); 208 209 /* Setup SRCMulti Input Audio Enable */ 210 snd_emu10k1_ptr20_write(emu, P17V_MIXER_I2S_ENABLE, 0, 0xFF000000); 211 212 /* Setup SPDIF Out Audio Enable */ 213 /* The Audigy 2 Value has a separate SPDIF out, 214 * so no need for a mixer switch 215 */ 216 snd_emu10k1_ptr20_write(emu, P17V_MIXER_SPDIF_ENABLE, 0, 0xFF000000); 217 218 tmp = inw(emu->port + A_IOCFG) & ~0x8; /* Clear bit 3 */ 219 outw(tmp, emu->port + A_IOCFG); 220 } 221 if (emu->card_capabilities->spi_dac) { /* Audigy 2 ZS Notebook with DAC Wolfson WM8768/WM8568 */ 222 int size, n; 223 224 size = ARRAY_SIZE(spi_dac_init); 225 for (n = 0; n < size; n++) 226 snd_emu10k1_spi_write(emu, spi_dac_init[n]); 227 228 snd_emu10k1_ptr20_write(emu, 0x60, 0, 0x10); 229 /* Enable GPIOs 230 * GPIO0: Unknown 231 * GPIO1: Speakers-enabled. 232 * GPIO2: Unknown 233 * GPIO3: Unknown 234 * GPIO4: IEC958 Output on. 235 * GPIO5: Unknown 236 * GPIO6: Unknown 237 * GPIO7: Unknown 238 */ 239 outw(0x76, emu->port + A_IOCFG); /* Windows uses 0x3f76 */ 240 } 241 if (emu->card_capabilities->i2c_adc) { /* Audigy 2 ZS Notebook with ADC Wolfson WM8775 */ 242 int size, n; 243 244 snd_emu10k1_ptr20_write(emu, P17V_I2S_SRC_SEL, 0, 0x2020205f); 245 tmp = inw(emu->port + A_IOCFG); 246 outw(tmp | 0x4, emu->port + A_IOCFG); /* Set bit 2 for mic input */ 247 tmp = inw(emu->port + A_IOCFG); 248 size = ARRAY_SIZE(i2c_adc_init); 249 for (n = 0; n < size; n++) 250 snd_emu10k1_i2c_write(emu, i2c_adc_init[n][0], i2c_adc_init[n][1]); 251 for (n = 0; n < 4; n++) { 252 emu->i2c_capture_volume[n][0] = 0xcf; 253 emu->i2c_capture_volume[n][1] = 0xcf; 254 } 255 } 256 257 258 snd_emu10k1_ptr_write(emu, PTB, 0, emu->ptb_pages.addr); 259 snd_emu10k1_ptr_write(emu, TCB, 0, 0); /* taken from original driver */ 260 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_256K); /* taken from original driver */ 261 262 silent_page = (emu->silent_page.addr << emu->address_mode) | (emu->address_mode ? MAP_PTI_MASK1 : MAP_PTI_MASK0); 263 for (ch = 0; ch < NUM_G; ch++) { 264 snd_emu10k1_ptr_write(emu, MAPA, ch, silent_page); 265 snd_emu10k1_ptr_write(emu, MAPB, ch, silent_page); 266 } 267 268 if (emu->card_capabilities->emu_model) { 269 outl(HCFG_AUTOMUTE_ASYNC | 270 HCFG_EMU32_SLAVE | 271 HCFG_AUDIOENABLE, emu->port + HCFG); 272 /* 273 * Hokay, setup HCFG 274 * Mute Disable Audio = 0 275 * Lock Tank Memory = 1 276 * Lock Sound Memory = 0 277 * Auto Mute = 1 278 */ 279 } else if (emu->audigy) { 280 if (emu->revision == 4) /* audigy2 */ 281 outl(HCFG_AUDIOENABLE | 282 HCFG_AC3ENABLE_CDSPDIF | 283 HCFG_AC3ENABLE_GPSPDIF | 284 HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG); 285 else 286 outl(HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG); 287 /* FIXME: Remove all these emu->model and replace it with a card recognition parameter, 288 * e.g. card_capabilities->joystick */ 289 } else if (emu->model == 0x20 || 290 emu->model == 0xc400 || 291 (emu->model == 0x21 && emu->revision < 6)) 292 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE, emu->port + HCFG); 293 else 294 /* With on-chip joystick */ 295 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG); 296 297 if (enable_ir) { /* enable IR for SB Live */ 298 if (emu->card_capabilities->emu_model) { 299 ; /* Disable all access to A_IOCFG for the emu1010 */ 300 } else if (emu->card_capabilities->i2c_adc) { 301 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */ 302 } else if (emu->audigy) { 303 u16 reg = inw(emu->port + A_IOCFG); 304 outw(reg | A_IOCFG_GPOUT2, emu->port + A_IOCFG); 305 udelay(500); 306 outw(reg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, emu->port + A_IOCFG); 307 udelay(100); 308 outw(reg, emu->port + A_IOCFG); 309 } else { 310 unsigned int reg = inl(emu->port + HCFG); 311 outl(reg | HCFG_GPOUT2, emu->port + HCFG); 312 udelay(500); 313 outl(reg | HCFG_GPOUT1 | HCFG_GPOUT2, emu->port + HCFG); 314 udelay(100); 315 outl(reg, emu->port + HCFG); 316 } 317 } 318 319 if (emu->card_capabilities->emu_model) { 320 ; /* Disable all access to A_IOCFG for the emu1010 */ 321 } else if (emu->card_capabilities->i2c_adc) { 322 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */ 323 } else if (emu->audigy) { /* enable analog output */ 324 u16 reg = inw(emu->port + A_IOCFG); 325 outw(reg | A_IOCFG_GPOUT0, emu->port + A_IOCFG); 326 } 327 328 if (emu->address_mode == 0) { 329 /* use 16M in 4G */ 330 outl(inl(emu->port + HCFG) | HCFG_EXPANDED_MEM, emu->port + HCFG); 331 } 332 333 return 0; 334 } 335 336 static void snd_emu10k1_audio_enable(struct snd_emu10k1 *emu) 337 { 338 /* 339 * Enable the audio bit 340 */ 341 outl(inl(emu->port + HCFG) | HCFG_AUDIOENABLE, emu->port + HCFG); 342 343 /* Enable analog/digital outs on audigy */ 344 if (emu->card_capabilities->emu_model) { 345 ; /* Disable all access to A_IOCFG for the emu1010 */ 346 } else if (emu->card_capabilities->i2c_adc) { 347 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */ 348 } else if (emu->audigy) { 349 outw(inw(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG); 350 351 if (emu->card_capabilities->ca0151_chip) { /* audigy2 */ 352 /* Unmute Analog now. Set GPO6 to 1 for Apollo. 353 * This has to be done after init ALice3 I2SOut beyond 48KHz. 354 * So, sequence is important. */ 355 outw(inw(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG); 356 } else if (emu->card_capabilities->ca0108_chip) { /* audigy2 value */ 357 /* Unmute Analog now. */ 358 outw(inw(emu->port + A_IOCFG) | 0x0060, emu->port + A_IOCFG); 359 } else { 360 /* Disable routing from AC97 line out to Front speakers */ 361 outw(inw(emu->port + A_IOCFG) | 0x0080, emu->port + A_IOCFG); 362 } 363 } 364 365 #if 0 366 { 367 unsigned int tmp; 368 /* FIXME: the following routine disables LiveDrive-II !! */ 369 /* TOSLink detection */ 370 emu->tos_link = 0; 371 tmp = inl(emu->port + HCFG); 372 if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) { 373 outl(tmp|0x800, emu->port + HCFG); 374 udelay(50); 375 if (tmp != (inl(emu->port + HCFG) & ~0x800)) { 376 emu->tos_link = 1; 377 outl(tmp, emu->port + HCFG); 378 } 379 } 380 } 381 #endif 382 383 snd_emu10k1_intr_enable(emu, INTE_PCIERRORENABLE); 384 } 385 386 int snd_emu10k1_done(struct snd_emu10k1 *emu) 387 { 388 int ch; 389 390 outl(0, emu->port + INTE); 391 392 /* 393 * Shutdown the chip 394 */ 395 for (ch = 0; ch < NUM_G; ch++) 396 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0); 397 for (ch = 0; ch < NUM_G; ch++) { 398 snd_emu10k1_ptr_write(emu, VTFT, ch, 0); 399 snd_emu10k1_ptr_write(emu, CVCF, ch, 0); 400 snd_emu10k1_ptr_write(emu, PTRX, ch, 0); 401 snd_emu10k1_ptr_write(emu, CPF, ch, 0); 402 } 403 404 /* reset recording buffers */ 405 snd_emu10k1_ptr_write(emu, MICBS, 0, 0); 406 snd_emu10k1_ptr_write(emu, MICBA, 0, 0); 407 snd_emu10k1_ptr_write(emu, FXBS, 0, 0); 408 snd_emu10k1_ptr_write(emu, FXBA, 0, 0); 409 snd_emu10k1_ptr_write(emu, FXWC, 0, 0); 410 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE); 411 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0); 412 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K); 413 snd_emu10k1_ptr_write(emu, TCB, 0, 0); 414 if (emu->audigy) 415 snd_emu10k1_ptr_write(emu, A_DBG, 0, A_DBG_SINGLE_STEP); 416 else 417 snd_emu10k1_ptr_write(emu, DBG, 0, EMU10K1_DBG_SINGLE_STEP); 418 419 /* disable channel interrupt */ 420 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0); 421 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0); 422 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0); 423 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0); 424 425 /* disable audio and lock cache */ 426 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG); 427 snd_emu10k1_ptr_write(emu, PTB, 0, 0); 428 429 return 0; 430 } 431 432 /************************************************************************* 433 * ECARD functional implementation 434 *************************************************************************/ 435 436 /* In A1 Silicon, these bits are in the HC register */ 437 #define HOOKN_BIT (1L << 12) 438 #define HANDN_BIT (1L << 11) 439 #define PULSEN_BIT (1L << 10) 440 441 #define EC_GDI1 (1 << 13) 442 #define EC_GDI0 (1 << 14) 443 444 #define EC_NUM_CONTROL_BITS 20 445 446 #define EC_AC3_DATA_SELN 0x0001L 447 #define EC_EE_DATA_SEL 0x0002L 448 #define EC_EE_CNTRL_SELN 0x0004L 449 #define EC_EECLK 0x0008L 450 #define EC_EECS 0x0010L 451 #define EC_EESDO 0x0020L 452 #define EC_TRIM_CSN 0x0040L 453 #define EC_TRIM_SCLK 0x0080L 454 #define EC_TRIM_SDATA 0x0100L 455 #define EC_TRIM_MUTEN 0x0200L 456 #define EC_ADCCAL 0x0400L 457 #define EC_ADCRSTN 0x0800L 458 #define EC_DACCAL 0x1000L 459 #define EC_DACMUTEN 0x2000L 460 #define EC_LEDN 0x4000L 461 462 #define EC_SPDIF0_SEL_SHIFT 15 463 #define EC_SPDIF1_SEL_SHIFT 17 464 #define EC_SPDIF0_SEL_MASK (0x3L << EC_SPDIF0_SEL_SHIFT) 465 #define EC_SPDIF1_SEL_MASK (0x7L << EC_SPDIF1_SEL_SHIFT) 466 #define EC_SPDIF0_SELECT(_x) (((_x) << EC_SPDIF0_SEL_SHIFT) & EC_SPDIF0_SEL_MASK) 467 #define EC_SPDIF1_SELECT(_x) (((_x) << EC_SPDIF1_SEL_SHIFT) & EC_SPDIF1_SEL_MASK) 468 #define EC_CURRENT_PROM_VERSION 0x01 /* Self-explanatory. This should 469 * be incremented any time the EEPROM's 470 * format is changed. */ 471 472 #define EC_EEPROM_SIZE 0x40 /* ECARD EEPROM has 64 16-bit words */ 473 474 /* Addresses for special values stored in to EEPROM */ 475 #define EC_PROM_VERSION_ADDR 0x20 /* Address of the current prom version */ 476 #define EC_BOARDREV0_ADDR 0x21 /* LSW of board rev */ 477 #define EC_BOARDREV1_ADDR 0x22 /* MSW of board rev */ 478 479 #define EC_LAST_PROMFILE_ADDR 0x2f 480 481 #define EC_SERIALNUM_ADDR 0x30 /* First word of serial number. The 482 * can be up to 30 characters in length 483 * and is stored as a NULL-terminated 484 * ASCII string. Any unused bytes must be 485 * filled with zeros */ 486 #define EC_CHECKSUM_ADDR 0x3f /* Location at which checksum is stored */ 487 488 489 /* Most of this stuff is pretty self-evident. According to the hardware 490 * dudes, we need to leave the ADCCAL bit low in order to avoid a DC 491 * offset problem. Weird. 492 */ 493 #define EC_RAW_RUN_MODE (EC_DACMUTEN | EC_ADCRSTN | EC_TRIM_MUTEN | \ 494 EC_TRIM_CSN) 495 496 497 #define EC_DEFAULT_ADC_GAIN 0xC4C4 498 #define EC_DEFAULT_SPDIF0_SEL 0x0 499 #define EC_DEFAULT_SPDIF1_SEL 0x4 500 501 /************************************************************************** 502 * @func Clock bits into the Ecard's control latch. The Ecard uses a 503 * control latch will is loaded bit-serially by toggling the Modem control 504 * lines from function 2 on the E8010. This function hides these details 505 * and presents the illusion that we are actually writing to a distinct 506 * register. 507 */ 508 509 static void snd_emu10k1_ecard_write(struct snd_emu10k1 *emu, unsigned int value) 510 { 511 unsigned short count; 512 unsigned int data; 513 unsigned long hc_port; 514 unsigned int hc_value; 515 516 hc_port = emu->port + HCFG; 517 hc_value = inl(hc_port) & ~(HOOKN_BIT | HANDN_BIT | PULSEN_BIT); 518 outl(hc_value, hc_port); 519 520 for (count = 0; count < EC_NUM_CONTROL_BITS; count++) { 521 522 /* Set up the value */ 523 data = ((value & 0x1) ? PULSEN_BIT : 0); 524 value >>= 1; 525 526 outl(hc_value | data, hc_port); 527 528 /* Clock the shift register */ 529 outl(hc_value | data | HANDN_BIT, hc_port); 530 outl(hc_value | data, hc_port); 531 } 532 533 /* Latch the bits */ 534 outl(hc_value | HOOKN_BIT, hc_port); 535 outl(hc_value, hc_port); 536 } 537 538 /************************************************************************** 539 * @func Set the gain of the ECARD's CS3310 Trim/gain controller. The 540 * trim value consists of a 16bit value which is composed of two 541 * 8 bit gain/trim values, one for the left channel and one for the 542 * right channel. The following table maps from the Gain/Attenuation 543 * value in decibels into the corresponding bit pattern for a single 544 * channel. 545 */ 546 547 static void snd_emu10k1_ecard_setadcgain(struct snd_emu10k1 *emu, 548 unsigned short gain) 549 { 550 unsigned int bit; 551 552 /* Enable writing to the TRIM registers */ 553 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN); 554 555 /* Do it again to insure that we meet hold time requirements */ 556 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN); 557 558 for (bit = (1 << 15); bit; bit >>= 1) { 559 unsigned int value; 560 561 value = emu->ecard_ctrl & ~(EC_TRIM_CSN | EC_TRIM_SDATA); 562 563 if (gain & bit) 564 value |= EC_TRIM_SDATA; 565 566 /* Clock the bit */ 567 snd_emu10k1_ecard_write(emu, value); 568 snd_emu10k1_ecard_write(emu, value | EC_TRIM_SCLK); 569 snd_emu10k1_ecard_write(emu, value); 570 } 571 572 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl); 573 } 574 575 static int snd_emu10k1_ecard_init(struct snd_emu10k1 *emu) 576 { 577 unsigned int hc_value; 578 579 /* Set up the initial settings */ 580 emu->ecard_ctrl = EC_RAW_RUN_MODE | 581 EC_SPDIF0_SELECT(EC_DEFAULT_SPDIF0_SEL) | 582 EC_SPDIF1_SELECT(EC_DEFAULT_SPDIF1_SEL); 583 584 /* Step 0: Set the codec type in the hardware control register 585 * and enable audio output */ 586 hc_value = inl(emu->port + HCFG); 587 outl(hc_value | HCFG_AUDIOENABLE | HCFG_CODECFORMAT_I2S, emu->port + HCFG); 588 inl(emu->port + HCFG); 589 590 /* Step 1: Turn off the led and deassert TRIM_CS */ 591 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN); 592 593 /* Step 2: Calibrate the ADC and DAC */ 594 snd_emu10k1_ecard_write(emu, EC_DACCAL | EC_LEDN | EC_TRIM_CSN); 595 596 /* Step 3: Wait for awhile; XXX We can't get away with this 597 * under a real operating system; we'll need to block and wait that 598 * way. */ 599 snd_emu10k1_wait(emu, 48000); 600 601 /* Step 4: Switch off the DAC and ADC calibration. Note 602 * That ADC_CAL is actually an inverted signal, so we assert 603 * it here to stop calibration. */ 604 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN); 605 606 /* Step 4: Switch into run mode */ 607 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl); 608 609 /* Step 5: Set the analog input gain */ 610 snd_emu10k1_ecard_setadcgain(emu, EC_DEFAULT_ADC_GAIN); 611 612 return 0; 613 } 614 615 static int snd_emu10k1_cardbus_init(struct snd_emu10k1 *emu) 616 { 617 unsigned long special_port; 618 __always_unused unsigned int value; 619 620 /* Special initialisation routine 621 * before the rest of the IO-Ports become active. 622 */ 623 special_port = emu->port + 0x38; 624 value = inl(special_port); 625 outl(0x00d00000, special_port); 626 value = inl(special_port); 627 outl(0x00d00001, special_port); 628 value = inl(special_port); 629 outl(0x00d0005f, special_port); 630 value = inl(special_port); 631 outl(0x00d0007f, special_port); 632 value = inl(special_port); 633 outl(0x0090007f, special_port); 634 value = inl(special_port); 635 636 snd_emu10k1_ptr20_write(emu, TINA2_VOLUME, 0, 0xfefefefe); /* Defaults to 0x30303030 */ 637 /* Delay to give time for ADC chip to switch on. It needs 113ms */ 638 msleep(200); 639 return 0; 640 } 641 642 static int snd_emu1010_load_firmware_entry(struct snd_emu10k1 *emu, 643 const struct firmware *fw_entry) 644 { 645 int n, i; 646 u16 reg; 647 u8 value; 648 __always_unused u16 write_post; 649 unsigned long flags; 650 651 if (!fw_entry) 652 return -EIO; 653 654 /* The FPGA is a Xilinx Spartan IIE XC2S50E */ 655 /* On E-MU 0404b it is a Xilinx Spartan III XC3S50 */ 656 /* GPIO7 -> FPGA PGMN 657 * GPIO6 -> FPGA CCLK 658 * GPIO5 -> FPGA DIN 659 * FPGA CONFIG OFF -> FPGA PGMN 660 */ 661 spin_lock_irqsave(&emu->emu_lock, flags); 662 outw(0x00, emu->port + A_GPIO); /* Set PGMN low for 100uS. */ 663 write_post = inw(emu->port + A_GPIO); 664 udelay(100); 665 outw(0x80, emu->port + A_GPIO); /* Leave bit 7 set during netlist setup. */ 666 write_post = inw(emu->port + A_GPIO); 667 udelay(100); /* Allow FPGA memory to clean */ 668 for (n = 0; n < fw_entry->size; n++) { 669 value = fw_entry->data[n]; 670 for (i = 0; i < 8; i++) { 671 reg = 0x80; 672 if (value & 0x1) 673 reg = reg | 0x20; 674 value = value >> 1; 675 outw(reg, emu->port + A_GPIO); 676 write_post = inw(emu->port + A_GPIO); 677 outw(reg | 0x40, emu->port + A_GPIO); 678 write_post = inw(emu->port + A_GPIO); 679 } 680 } 681 /* After programming, set GPIO bit 4 high again. */ 682 outw(0x10, emu->port + A_GPIO); 683 write_post = inw(emu->port + A_GPIO); 684 spin_unlock_irqrestore(&emu->emu_lock, flags); 685 686 return 0; 687 } 688 689 /* firmware file names, per model, init-fw and dock-fw (optional) */ 690 static const char * const firmware_names[5][2] = { 691 [EMU_MODEL_EMU1010] = { 692 HANA_FILENAME, DOCK_FILENAME 693 }, 694 [EMU_MODEL_EMU1010B] = { 695 EMU1010B_FILENAME, MICRO_DOCK_FILENAME 696 }, 697 [EMU_MODEL_EMU1616] = { 698 EMU1010_NOTEBOOK_FILENAME, MICRO_DOCK_FILENAME 699 }, 700 [EMU_MODEL_EMU0404] = { 701 EMU0404_FILENAME, NULL 702 }, 703 }; 704 705 static int snd_emu1010_load_firmware(struct snd_emu10k1 *emu, int dock, 706 const struct firmware **fw) 707 { 708 const char *filename; 709 int err; 710 711 if (!*fw) { 712 filename = firmware_names[emu->card_capabilities->emu_model][dock]; 713 if (!filename) 714 return 0; 715 err = request_firmware(fw, filename, &emu->pci->dev); 716 if (err) 717 return err; 718 } 719 720 return snd_emu1010_load_firmware_entry(emu, *fw); 721 } 722 723 static void emu1010_firmware_work(struct work_struct *work) 724 { 725 struct snd_emu10k1 *emu; 726 u32 tmp, tmp2, reg; 727 int err; 728 729 emu = container_of(work, struct snd_emu10k1, 730 emu1010.firmware_work.work); 731 if (emu->card->shutdown) 732 return; 733 #ifdef CONFIG_PM_SLEEP 734 if (emu->suspend) 735 return; 736 #endif 737 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &tmp); /* IRQ Status */ 738 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®); /* OPTIONS: Which cards are attached to the EMU */ 739 if (reg & EMU_HANA_OPTION_DOCK_OFFLINE) { 740 /* Audio Dock attached */ 741 /* Return to Audio Dock programming mode */ 742 dev_info(emu->card->dev, 743 "emu1010: Loading Audio Dock Firmware\n"); 744 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 745 EMU_HANA_FPGA_CONFIG_AUDIODOCK); 746 err = snd_emu1010_load_firmware(emu, 1, &emu->dock_fw); 747 if (err < 0) 748 goto next; 749 750 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0); 751 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &tmp); 752 dev_info(emu->card->dev, 753 "emu1010: EMU_HANA+DOCK_IRQ_STATUS = 0x%x\n", tmp); 754 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */ 755 snd_emu1010_fpga_read(emu, EMU_HANA_ID, &tmp); 756 dev_info(emu->card->dev, 757 "emu1010: EMU_HANA+DOCK_ID = 0x%x\n", tmp); 758 if ((tmp & 0x1f) != 0x15) { 759 /* FPGA failed to be programmed */ 760 dev_info(emu->card->dev, 761 "emu1010: Loading Audio Dock Firmware file failed, reg = 0x%x\n", 762 tmp); 763 goto next; 764 } 765 dev_info(emu->card->dev, 766 "emu1010: Audio Dock Firmware loaded\n"); 767 snd_emu1010_fpga_read(emu, EMU_DOCK_MAJOR_REV, &tmp); 768 snd_emu1010_fpga_read(emu, EMU_DOCK_MINOR_REV, &tmp2); 769 dev_info(emu->card->dev, "Audio Dock ver: %u.%u\n", tmp, tmp2); 770 /* Sync clocking between 1010 and Dock */ 771 /* Allow DLL to settle */ 772 msleep(10); 773 /* Unmute all. Default is muted after a firmware load */ 774 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE); 775 } else if (!reg && emu->emu1010.last_reg) { 776 /* Audio Dock removed */ 777 dev_info(emu->card->dev, "emu1010: Audio Dock detached\n"); 778 /* The hardware auto-mutes all, so we unmute again */ 779 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE); 780 } 781 782 next: 783 emu->emu1010.last_reg = reg; 784 if (!emu->card->shutdown) 785 schedule_delayed_work(&emu->emu1010.firmware_work, 786 msecs_to_jiffies(1000)); 787 } 788 789 /* 790 * Current status of the driver: 791 * ---------------------------- 792 * * only 44.1/48kHz supported (the MS Win driver supports up to 192 kHz) 793 * * PCM device nb. 2: 794 * 16 x 16-bit playback - snd_emu10k1_fx8010_playback_ops 795 * 16 x 32-bit capture - snd_emu10k1_capture_efx_ops 796 */ 797 static int snd_emu10k1_emu1010_init(struct snd_emu10k1 *emu) 798 { 799 unsigned int i; 800 u32 tmp, tmp2, reg; 801 int err; 802 803 dev_info(emu->card->dev, "emu1010: Special config.\n"); 804 805 /* Mute, and disable audio and lock cache, just in case. 806 * Proper init follows in snd_emu10k1_init(). */ 807 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG); 808 809 /* Disable 48Volt power to Audio Dock */ 810 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0); 811 812 /* ID, should read & 0x7f = 0x55. (Bit 7 is the IRQ bit) */ 813 snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®); 814 dev_dbg(emu->card->dev, "reg1 = 0x%x\n", reg); 815 if ((reg & 0x3f) == 0x15) { 816 /* FPGA netlist already present so clear it */ 817 /* Return to programming mode */ 818 819 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, EMU_HANA_FPGA_CONFIG_HANA); 820 } 821 snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®); 822 dev_dbg(emu->card->dev, "reg2 = 0x%x\n", reg); 823 if ((reg & 0x3f) == 0x15) { 824 /* FPGA failed to return to programming mode */ 825 dev_info(emu->card->dev, 826 "emu1010: FPGA failed to return to programming mode\n"); 827 return -ENODEV; 828 } 829 dev_info(emu->card->dev, "emu1010: EMU_HANA_ID = 0x%x\n", reg); 830 831 err = snd_emu1010_load_firmware(emu, 0, &emu->firmware); 832 if (err < 0) { 833 dev_info(emu->card->dev, "emu1010: Loading Firmware failed\n"); 834 return err; 835 } 836 837 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */ 838 snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®); 839 if ((reg & 0x3f) != 0x15) { 840 /* FPGA failed to be programmed */ 841 dev_info(emu->card->dev, 842 "emu1010: Loading Hana Firmware file failed, reg = 0x%x\n", 843 reg); 844 return -ENODEV; 845 } 846 847 dev_info(emu->card->dev, "emu1010: Hana Firmware loaded\n"); 848 snd_emu1010_fpga_read(emu, EMU_HANA_MAJOR_REV, &tmp); 849 snd_emu1010_fpga_read(emu, EMU_HANA_MINOR_REV, &tmp2); 850 dev_info(emu->card->dev, "emu1010: Hana version: %u.%u\n", tmp, tmp2); 851 /* Enable 48Volt power to Audio Dock */ 852 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, EMU_HANA_DOCK_PWR_ON); 853 854 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®); 855 dev_info(emu->card->dev, "emu1010: Card options = 0x%x\n", reg); 856 /* Optical -> ADAT I/O */ 857 emu->emu1010.optical_in = 1; /* IN_ADAT */ 858 emu->emu1010.optical_out = 1; /* OUT_ADAT */ 859 tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : EMU_HANA_OPTICAL_IN_SPDIF) | 860 (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : EMU_HANA_OPTICAL_OUT_SPDIF); 861 snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp); 862 /* Set no attenuation on Audio Dock pads. */ 863 emu->emu1010.adc_pads = 0x00; 864 snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, emu->emu1010.adc_pads); 865 /* Unmute Audio dock DACs, Headphone source DAC-4. */ 866 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, EMU_HANA_DOCK_PHONES_192_DAC4); 867 /* DAC PADs. */ 868 emu->emu1010.dac_pads = EMU_HANA_DOCK_DAC_PAD1 | EMU_HANA_DOCK_DAC_PAD2 | 869 EMU_HANA_DOCK_DAC_PAD3 | EMU_HANA_DOCK_DAC_PAD4; 870 snd_emu1010_fpga_write(emu, EMU_HANA_DAC_PADS, emu->emu1010.dac_pads); 871 /* SPDIF Format. Set Consumer mode, 24bit, copy enable */ 872 snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, EMU_HANA_SPDIF_MODE_RX_INVALID); 873 /* MIDI routing */ 874 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, EMU_HANA_MIDI_INA_FROM_HAMOA | EMU_HANA_MIDI_INB_FROM_DOCK2); 875 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, EMU_HANA_MIDI_OUT_DOCK2 | EMU_HANA_MIDI_OUT_SYNC2); 876 /* IRQ Enable: All on */ 877 /* snd_emu1010_fpga_write(emu, EMU_HANA_IRQ_ENABLE, 0x0f); */ 878 /* IRQ Enable: All off */ 879 snd_emu1010_fpga_write(emu, EMU_HANA_IRQ_ENABLE, 0x00); 880 881 emu->emu1010.internal_clock = 1; /* 48000 */ 882 /* Default WCLK set to 48kHz. */ 883 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, EMU_HANA_DEFCLOCK_48K); 884 /* Word Clock source, Internal 48kHz x1 */ 885 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K); 886 /* snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X); */ 887 /* Audio Dock LEDs. */ 888 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, EMU_HANA_DOCK_LEDS_2_LOCK | EMU_HANA_DOCK_LEDS_2_48K); 889 890 #if 0 891 /* For 96kHz */ 892 snd_emu1010_fpga_link_dst_src_write(emu, 893 EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1); 894 snd_emu1010_fpga_link_dst_src_write(emu, 895 EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1); 896 snd_emu1010_fpga_link_dst_src_write(emu, 897 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT2); 898 snd_emu1010_fpga_link_dst_src_write(emu, 899 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT2); 900 #endif 901 #if 0 902 /* For 192kHz */ 903 snd_emu1010_fpga_link_dst_src_write(emu, 904 EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1); 905 snd_emu1010_fpga_link_dst_src_write(emu, 906 EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1); 907 snd_emu1010_fpga_link_dst_src_write(emu, 908 EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2); 909 snd_emu1010_fpga_link_dst_src_write(emu, 910 EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_RIGHT2); 911 snd_emu1010_fpga_link_dst_src_write(emu, 912 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT3); 913 snd_emu1010_fpga_link_dst_src_write(emu, 914 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT3); 915 snd_emu1010_fpga_link_dst_src_write(emu, 916 EMU_DST_ALICE2_EMU32_6, EMU_SRC_HAMOA_ADC_LEFT4); 917 snd_emu1010_fpga_link_dst_src_write(emu, 918 EMU_DST_ALICE2_EMU32_7, EMU_SRC_HAMOA_ADC_RIGHT4); 919 #endif 920 #if 1 921 /* For 48kHz */ 922 snd_emu1010_fpga_link_dst_src_write(emu, 923 EMU_DST_ALICE2_EMU32_0, EMU_SRC_DOCK_MIC_A1); 924 snd_emu1010_fpga_link_dst_src_write(emu, 925 EMU_DST_ALICE2_EMU32_1, EMU_SRC_DOCK_MIC_B1); 926 snd_emu1010_fpga_link_dst_src_write(emu, 927 EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2); 928 snd_emu1010_fpga_link_dst_src_write(emu, 929 EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_LEFT2); 930 snd_emu1010_fpga_link_dst_src_write(emu, 931 EMU_DST_ALICE2_EMU32_4, EMU_SRC_DOCK_ADC1_LEFT1); 932 snd_emu1010_fpga_link_dst_src_write(emu, 933 EMU_DST_ALICE2_EMU32_5, EMU_SRC_DOCK_ADC1_RIGHT1); 934 snd_emu1010_fpga_link_dst_src_write(emu, 935 EMU_DST_ALICE2_EMU32_6, EMU_SRC_DOCK_ADC2_LEFT1); 936 snd_emu1010_fpga_link_dst_src_write(emu, 937 EMU_DST_ALICE2_EMU32_7, EMU_SRC_DOCK_ADC2_RIGHT1); 938 /* Pavel Hofman - setting defaults for 8 more capture channels 939 * Defaults only, users will set their own values anyways, let's 940 * just copy/paste. 941 */ 942 943 snd_emu1010_fpga_link_dst_src_write(emu, 944 EMU_DST_ALICE2_EMU32_8, EMU_SRC_DOCK_MIC_A1); 945 snd_emu1010_fpga_link_dst_src_write(emu, 946 EMU_DST_ALICE2_EMU32_9, EMU_SRC_DOCK_MIC_B1); 947 snd_emu1010_fpga_link_dst_src_write(emu, 948 EMU_DST_ALICE2_EMU32_A, EMU_SRC_HAMOA_ADC_LEFT2); 949 snd_emu1010_fpga_link_dst_src_write(emu, 950 EMU_DST_ALICE2_EMU32_B, EMU_SRC_HAMOA_ADC_LEFT2); 951 snd_emu1010_fpga_link_dst_src_write(emu, 952 EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_ADC1_LEFT1); 953 snd_emu1010_fpga_link_dst_src_write(emu, 954 EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_ADC1_RIGHT1); 955 snd_emu1010_fpga_link_dst_src_write(emu, 956 EMU_DST_ALICE2_EMU32_E, EMU_SRC_DOCK_ADC2_LEFT1); 957 snd_emu1010_fpga_link_dst_src_write(emu, 958 EMU_DST_ALICE2_EMU32_F, EMU_SRC_DOCK_ADC2_RIGHT1); 959 #endif 960 #if 0 961 /* Original */ 962 snd_emu1010_fpga_link_dst_src_write(emu, 963 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HANA_ADAT); 964 snd_emu1010_fpga_link_dst_src_write(emu, 965 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HANA_ADAT + 1); 966 snd_emu1010_fpga_link_dst_src_write(emu, 967 EMU_DST_ALICE2_EMU32_6, EMU_SRC_HANA_ADAT + 2); 968 snd_emu1010_fpga_link_dst_src_write(emu, 969 EMU_DST_ALICE2_EMU32_7, EMU_SRC_HANA_ADAT + 3); 970 snd_emu1010_fpga_link_dst_src_write(emu, 971 EMU_DST_ALICE2_EMU32_8, EMU_SRC_HANA_ADAT + 4); 972 snd_emu1010_fpga_link_dst_src_write(emu, 973 EMU_DST_ALICE2_EMU32_9, EMU_SRC_HANA_ADAT + 5); 974 snd_emu1010_fpga_link_dst_src_write(emu, 975 EMU_DST_ALICE2_EMU32_A, EMU_SRC_HANA_ADAT + 6); 976 snd_emu1010_fpga_link_dst_src_write(emu, 977 EMU_DST_ALICE2_EMU32_B, EMU_SRC_HANA_ADAT + 7); 978 snd_emu1010_fpga_link_dst_src_write(emu, 979 EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_MIC_A1); 980 snd_emu1010_fpga_link_dst_src_write(emu, 981 EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_MIC_B1); 982 snd_emu1010_fpga_link_dst_src_write(emu, 983 EMU_DST_ALICE2_EMU32_E, EMU_SRC_HAMOA_ADC_LEFT2); 984 snd_emu1010_fpga_link_dst_src_write(emu, 985 EMU_DST_ALICE2_EMU32_F, EMU_SRC_HAMOA_ADC_LEFT2); 986 #endif 987 for (i = 0; i < 0x20; i++) { 988 /* AudioDock Elink <- Silence */ 989 snd_emu1010_fpga_link_dst_src_write(emu, 0x0100 + i, EMU_SRC_SILENCE); 990 } 991 for (i = 0; i < 4; i++) { 992 /* Hana SPDIF Out <- Silence */ 993 snd_emu1010_fpga_link_dst_src_write(emu, 0x0200 + i, EMU_SRC_SILENCE); 994 } 995 for (i = 0; i < 7; i++) { 996 /* Hamoa DAC <- Silence */ 997 snd_emu1010_fpga_link_dst_src_write(emu, 0x0300 + i, EMU_SRC_SILENCE); 998 } 999 for (i = 0; i < 7; i++) { 1000 /* Hana ADAT Out <- Silence */ 1001 snd_emu1010_fpga_link_dst_src_write(emu, EMU_DST_HANA_ADAT + i, EMU_SRC_SILENCE); 1002 } 1003 snd_emu1010_fpga_link_dst_src_write(emu, 1004 EMU_DST_ALICE_I2S0_LEFT, EMU_SRC_DOCK_ADC1_LEFT1); 1005 snd_emu1010_fpga_link_dst_src_write(emu, 1006 EMU_DST_ALICE_I2S0_RIGHT, EMU_SRC_DOCK_ADC1_RIGHT1); 1007 snd_emu1010_fpga_link_dst_src_write(emu, 1008 EMU_DST_ALICE_I2S1_LEFT, EMU_SRC_DOCK_ADC2_LEFT1); 1009 snd_emu1010_fpga_link_dst_src_write(emu, 1010 EMU_DST_ALICE_I2S1_RIGHT, EMU_SRC_DOCK_ADC2_RIGHT1); 1011 snd_emu1010_fpga_link_dst_src_write(emu, 1012 EMU_DST_ALICE_I2S2_LEFT, EMU_SRC_DOCK_ADC3_LEFT1); 1013 snd_emu1010_fpga_link_dst_src_write(emu, 1014 EMU_DST_ALICE_I2S2_RIGHT, EMU_SRC_DOCK_ADC3_RIGHT1); 1015 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE); 1016 1017 #if 0 1018 snd_emu1010_fpga_link_dst_src_write(emu, 1019 EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32B + 2); /* ALICE2 bus 0xa2 */ 1020 snd_emu1010_fpga_link_dst_src_write(emu, 1021 EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32B + 3); /* ALICE2 bus 0xa3 */ 1022 snd_emu1010_fpga_link_dst_src_write(emu, 1023 EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 2); /* ALICE2 bus 0xb2 */ 1024 snd_emu1010_fpga_link_dst_src_write(emu, 1025 EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 3); /* ALICE2 bus 0xb3 */ 1026 #endif 1027 /* Default outputs */ 1028 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616) { 1029 /* 1616(M) cardbus default outputs */ 1030 /* ALICE2 bus 0xa0 */ 1031 snd_emu1010_fpga_link_dst_src_write(emu, 1032 EMU_DST_DOCK_DAC1_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1033 emu->emu1010.output_source[0] = 17; 1034 snd_emu1010_fpga_link_dst_src_write(emu, 1035 EMU_DST_DOCK_DAC1_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1036 emu->emu1010.output_source[1] = 18; 1037 snd_emu1010_fpga_link_dst_src_write(emu, 1038 EMU_DST_DOCK_DAC2_LEFT1, EMU_SRC_ALICE_EMU32A + 2); 1039 emu->emu1010.output_source[2] = 19; 1040 snd_emu1010_fpga_link_dst_src_write(emu, 1041 EMU_DST_DOCK_DAC2_RIGHT1, EMU_SRC_ALICE_EMU32A + 3); 1042 emu->emu1010.output_source[3] = 20; 1043 snd_emu1010_fpga_link_dst_src_write(emu, 1044 EMU_DST_DOCK_DAC3_LEFT1, EMU_SRC_ALICE_EMU32A + 4); 1045 emu->emu1010.output_source[4] = 21; 1046 snd_emu1010_fpga_link_dst_src_write(emu, 1047 EMU_DST_DOCK_DAC3_RIGHT1, EMU_SRC_ALICE_EMU32A + 5); 1048 emu->emu1010.output_source[5] = 22; 1049 /* ALICE2 bus 0xa0 */ 1050 snd_emu1010_fpga_link_dst_src_write(emu, 1051 EMU_DST_MANA_DAC_LEFT, EMU_SRC_ALICE_EMU32A + 0); 1052 emu->emu1010.output_source[16] = 17; 1053 snd_emu1010_fpga_link_dst_src_write(emu, 1054 EMU_DST_MANA_DAC_RIGHT, EMU_SRC_ALICE_EMU32A + 1); 1055 emu->emu1010.output_source[17] = 18; 1056 } else { 1057 /* ALICE2 bus 0xa0 */ 1058 snd_emu1010_fpga_link_dst_src_write(emu, 1059 EMU_DST_DOCK_DAC1_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1060 emu->emu1010.output_source[0] = 21; 1061 snd_emu1010_fpga_link_dst_src_write(emu, 1062 EMU_DST_DOCK_DAC1_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1063 emu->emu1010.output_source[1] = 22; 1064 snd_emu1010_fpga_link_dst_src_write(emu, 1065 EMU_DST_DOCK_DAC2_LEFT1, EMU_SRC_ALICE_EMU32A + 2); 1066 emu->emu1010.output_source[2] = 23; 1067 snd_emu1010_fpga_link_dst_src_write(emu, 1068 EMU_DST_DOCK_DAC2_RIGHT1, EMU_SRC_ALICE_EMU32A + 3); 1069 emu->emu1010.output_source[3] = 24; 1070 snd_emu1010_fpga_link_dst_src_write(emu, 1071 EMU_DST_DOCK_DAC3_LEFT1, EMU_SRC_ALICE_EMU32A + 4); 1072 emu->emu1010.output_source[4] = 25; 1073 snd_emu1010_fpga_link_dst_src_write(emu, 1074 EMU_DST_DOCK_DAC3_RIGHT1, EMU_SRC_ALICE_EMU32A + 5); 1075 emu->emu1010.output_source[5] = 26; 1076 snd_emu1010_fpga_link_dst_src_write(emu, 1077 EMU_DST_DOCK_DAC4_LEFT1, EMU_SRC_ALICE_EMU32A + 6); 1078 emu->emu1010.output_source[6] = 27; 1079 snd_emu1010_fpga_link_dst_src_write(emu, 1080 EMU_DST_DOCK_DAC4_RIGHT1, EMU_SRC_ALICE_EMU32A + 7); 1081 emu->emu1010.output_source[7] = 28; 1082 /* ALICE2 bus 0xa0 */ 1083 snd_emu1010_fpga_link_dst_src_write(emu, 1084 EMU_DST_DOCK_PHONES_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1085 emu->emu1010.output_source[8] = 21; 1086 snd_emu1010_fpga_link_dst_src_write(emu, 1087 EMU_DST_DOCK_PHONES_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1088 emu->emu1010.output_source[9] = 22; 1089 /* ALICE2 bus 0xa0 */ 1090 snd_emu1010_fpga_link_dst_src_write(emu, 1091 EMU_DST_DOCK_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1092 emu->emu1010.output_source[10] = 21; 1093 snd_emu1010_fpga_link_dst_src_write(emu, 1094 EMU_DST_DOCK_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1095 emu->emu1010.output_source[11] = 22; 1096 /* ALICE2 bus 0xa0 */ 1097 snd_emu1010_fpga_link_dst_src_write(emu, 1098 EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1099 emu->emu1010.output_source[12] = 21; 1100 snd_emu1010_fpga_link_dst_src_write(emu, 1101 EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1102 emu->emu1010.output_source[13] = 22; 1103 /* ALICE2 bus 0xa0 */ 1104 snd_emu1010_fpga_link_dst_src_write(emu, 1105 EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1106 emu->emu1010.output_source[14] = 21; 1107 snd_emu1010_fpga_link_dst_src_write(emu, 1108 EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1109 emu->emu1010.output_source[15] = 22; 1110 /* ALICE2 bus 0xa0 */ 1111 snd_emu1010_fpga_link_dst_src_write(emu, 1112 EMU_DST_HANA_ADAT, EMU_SRC_ALICE_EMU32A + 0); 1113 emu->emu1010.output_source[16] = 21; 1114 snd_emu1010_fpga_link_dst_src_write(emu, 1115 EMU_DST_HANA_ADAT + 1, EMU_SRC_ALICE_EMU32A + 1); 1116 emu->emu1010.output_source[17] = 22; 1117 snd_emu1010_fpga_link_dst_src_write(emu, 1118 EMU_DST_HANA_ADAT + 2, EMU_SRC_ALICE_EMU32A + 2); 1119 emu->emu1010.output_source[18] = 23; 1120 snd_emu1010_fpga_link_dst_src_write(emu, 1121 EMU_DST_HANA_ADAT + 3, EMU_SRC_ALICE_EMU32A + 3); 1122 emu->emu1010.output_source[19] = 24; 1123 snd_emu1010_fpga_link_dst_src_write(emu, 1124 EMU_DST_HANA_ADAT + 4, EMU_SRC_ALICE_EMU32A + 4); 1125 emu->emu1010.output_source[20] = 25; 1126 snd_emu1010_fpga_link_dst_src_write(emu, 1127 EMU_DST_HANA_ADAT + 5, EMU_SRC_ALICE_EMU32A + 5); 1128 emu->emu1010.output_source[21] = 26; 1129 snd_emu1010_fpga_link_dst_src_write(emu, 1130 EMU_DST_HANA_ADAT + 6, EMU_SRC_ALICE_EMU32A + 6); 1131 emu->emu1010.output_source[22] = 27; 1132 snd_emu1010_fpga_link_dst_src_write(emu, 1133 EMU_DST_HANA_ADAT + 7, EMU_SRC_ALICE_EMU32A + 7); 1134 emu->emu1010.output_source[23] = 28; 1135 } 1136 1137 return 0; 1138 } 1139 /* 1140 * Create the EMU10K1 instance 1141 */ 1142 1143 #ifdef CONFIG_PM_SLEEP 1144 static int alloc_pm_buffer(struct snd_emu10k1 *emu); 1145 static void free_pm_buffer(struct snd_emu10k1 *emu); 1146 #endif 1147 1148 static void snd_emu10k1_free(struct snd_card *card) 1149 { 1150 struct snd_emu10k1 *emu = card->private_data; 1151 1152 if (emu->port) { /* avoid access to already used hardware */ 1153 snd_emu10k1_fx8010_tram_setup(emu, 0); 1154 snd_emu10k1_done(emu); 1155 snd_emu10k1_free_efx(emu); 1156 } 1157 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1010) { 1158 /* Disable 48Volt power to Audio Dock */ 1159 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0); 1160 } 1161 cancel_delayed_work_sync(&emu->emu1010.firmware_work); 1162 release_firmware(emu->firmware); 1163 release_firmware(emu->dock_fw); 1164 snd_util_memhdr_free(emu->memhdr); 1165 if (emu->silent_page.area) 1166 snd_dma_free_pages(&emu->silent_page); 1167 if (emu->ptb_pages.area) 1168 snd_dma_free_pages(&emu->ptb_pages); 1169 vfree(emu->page_ptr_table); 1170 vfree(emu->page_addr_table); 1171 #ifdef CONFIG_PM_SLEEP 1172 free_pm_buffer(emu); 1173 #endif 1174 } 1175 1176 static const struct snd_emu_chip_details emu_chip_details[] = { 1177 /* Audigy 5/Rx SB1550 */ 1178 /* Tested by michael@gernoth.net 28 Mar 2015 */ 1179 /* DSP: CA10300-IAT LF 1180 * DAC: Cirrus Logic CS4382-KQZ 1181 * ADC: Philips 1361T 1182 * AC97: Sigmatel STAC9750 1183 * CA0151: None 1184 */ 1185 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10241102, 1186 .driver = "Audigy2", .name = "SB Audigy 5/Rx [SB1550]", 1187 .id = "Audigy2", 1188 .emu10k2_chip = 1, 1189 .ca0108_chip = 1, 1190 .spk71 = 1, 1191 .adc_1361t = 1, /* 24 bit capture instead of 16bit */ 1192 .ac97_chip = 1}, 1193 /* Audigy4 (Not PRO) SB0610 */ 1194 /* Tested by James@superbug.co.uk 4th April 2006 */ 1195 /* A_IOCFG bits 1196 * Output 1197 * 0: ? 1198 * 1: ? 1199 * 2: ? 1200 * 3: 0 - Digital Out, 1 - Line in 1201 * 4: ? 1202 * 5: ? 1203 * 6: ? 1204 * 7: ? 1205 * Input 1206 * 8: ? 1207 * 9: ? 1208 * A: Green jack sense (Front) 1209 * B: ? 1210 * C: Black jack sense (Rear/Side Right) 1211 * D: Yellow jack sense (Center/LFE/Side Left) 1212 * E: ? 1213 * F: ? 1214 * 1215 * Digital Out/Line in switch using A_IOCFG bit 3 (0x08) 1216 * 0 - Digital Out 1217 * 1 - Line in 1218 */ 1219 /* Mic input not tested. 1220 * Analog CD input not tested 1221 * Digital Out not tested. 1222 * Line in working. 1223 * Audio output 5.1 working. Side outputs not working. 1224 */ 1225 /* DSP: CA10300-IAT LF 1226 * DAC: Cirrus Logic CS4382-KQZ 1227 * ADC: Philips 1361T 1228 * AC97: Sigmatel STAC9750 1229 * CA0151: None 1230 */ 1231 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10211102, 1232 .driver = "Audigy2", .name = "SB Audigy 4 [SB0610]", 1233 .id = "Audigy2", 1234 .emu10k2_chip = 1, 1235 .ca0108_chip = 1, 1236 .spk71 = 1, 1237 .adc_1361t = 1, /* 24 bit capture instead of 16bit */ 1238 .ac97_chip = 1} , 1239 /* Audigy 2 Value AC3 out does not work yet. 1240 * Need to find out how to turn off interpolators. 1241 */ 1242 /* Tested by James@superbug.co.uk 3rd July 2005 */ 1243 /* DSP: CA0108-IAT 1244 * DAC: CS4382-KQ 1245 * ADC: Philips 1361T 1246 * AC97: STAC9750 1247 * CA0151: None 1248 */ 1249 /* 1250 * A_IOCFG Input (GPIO) 1251 * 0x400 = Front analog jack plugged in. (Green socket) 1252 * 0x1000 = Rear analog jack plugged in. (Black socket) 1253 * 0x2000 = Center/LFE analog jack plugged in. (Orange socket) 1254 * A_IOCFG Output (GPIO) 1255 * 0x60 = Sound out of front Left. 1256 * Win sets it to 0xXX61 1257 */ 1258 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10011102, 1259 .driver = "Audigy2", .name = "SB Audigy 2 Value [SB0400]", 1260 .id = "Audigy2", 1261 .emu10k2_chip = 1, 1262 .ca0108_chip = 1, 1263 .spk71 = 1, 1264 .ac97_chip = 1} , 1265 /* Audigy 2 ZS Notebook Cardbus card.*/ 1266 /* Tested by James@superbug.co.uk 6th November 2006 */ 1267 /* Audio output 7.1/Headphones working. 1268 * Digital output working. (AC3 not checked, only PCM) 1269 * Audio Mic/Line inputs working. 1270 * Digital input not tested. 1271 */ 1272 /* DSP: Tina2 1273 * DAC: Wolfson WM8768/WM8568 1274 * ADC: Wolfson WM8775 1275 * AC97: None 1276 * CA0151: None 1277 */ 1278 /* Tested by James@superbug.co.uk 4th April 2006 */ 1279 /* A_IOCFG bits 1280 * Output 1281 * 0: Not Used 1282 * 1: 0 = Mute all the 7.1 channel out. 1 = unmute. 1283 * 2: Analog input 0 = line in, 1 = mic in 1284 * 3: Not Used 1285 * 4: Digital output 0 = off, 1 = on. 1286 * 5: Not Used 1287 * 6: Not Used 1288 * 7: Not Used 1289 * Input 1290 * All bits 1 (0x3fxx) means nothing plugged in. 1291 * 8-9: 0 = Line in/Mic, 2 = Optical in, 3 = Nothing. 1292 * A-B: 0 = Headphones, 2 = Optical out, 3 = Nothing. 1293 * C-D: 2 = Front/Rear/etc, 3 = nothing. 1294 * E-F: Always 0 1295 * 1296 */ 1297 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x20011102, 1298 .driver = "Audigy2", .name = "Audigy 2 ZS Notebook [SB0530]", 1299 .id = "Audigy2", 1300 .emu10k2_chip = 1, 1301 .ca0108_chip = 1, 1302 .ca_cardbus_chip = 1, 1303 .spi_dac = 1, 1304 .i2c_adc = 1, 1305 .spk71 = 1} , 1306 /* This is MAEM8950 "Mana" */ 1307 /* Attach MicroDock[M] to make it an E-MU 1616[m]. */ 1308 /* Does NOT support sync daughter card (obviously). */ 1309 /* Tested by James@superbug.co.uk 4th Nov 2007. */ 1310 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x42011102, 1311 .driver = "Audigy2", .name = "E-MU 02 CardBus [MAEM8950]", 1312 .id = "EMU1010", 1313 .emu10k2_chip = 1, 1314 .ca0108_chip = 1, 1315 .ca_cardbus_chip = 1, 1316 .spk71 = 1 , 1317 .emu_model = EMU_MODEL_EMU1616}, 1318 /* Tested by James@superbug.co.uk 4th Nov 2007. */ 1319 /* This is MAEM8960 "Hana3", 0202 is MAEM8980 */ 1320 /* Attach 0202 daughter card to make it an E-MU 1212m, OR a 1321 * MicroDock[M] to make it an E-MU 1616[m]. */ 1322 /* Does NOT support sync daughter card. */ 1323 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40041102, 1324 .driver = "Audigy2", .name = "E-MU 1010b PCI [MAEM8960]", 1325 .id = "EMU1010", 1326 .emu10k2_chip = 1, 1327 .ca0108_chip = 1, 1328 .spk71 = 1, 1329 .emu_model = EMU_MODEL_EMU1010B}, /* EMU 1010 new revision */ 1330 /* Tested by Maxim Kachur <mcdebugger@duganet.ru> 17th Oct 2012. */ 1331 /* This is MAEM8986, 0202 is MAEM8980 */ 1332 /* Attach 0202 daughter card to make it an E-MU 1212m, OR a 1333 * MicroDockM to make it an E-MU 1616m. The non-m 1334 * version was never sold with this card, but should 1335 * still work. */ 1336 /* Does NOT support sync daughter card. */ 1337 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40071102, 1338 .driver = "Audigy2", .name = "E-MU 1010 PCIe [MAEM8986]", 1339 .id = "EMU1010", 1340 .emu10k2_chip = 1, 1341 .ca0108_chip = 1, 1342 .spk71 = 1, 1343 .emu_model = EMU_MODEL_EMU1010B}, /* EMU 1010 PCIe */ 1344 /* Tested by James@superbug.co.uk 8th July 2005. */ 1345 /* This is MAEM8810 "Hana", 0202 is MAEM8820 "Hamoa" */ 1346 /* Attach 0202 daughter card to make it an E-MU 1212m, OR an 1347 * AudioDock[M] to make it an E-MU 1820[m]. */ 1348 /* Supports sync daughter card. */ 1349 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40011102, 1350 .driver = "Audigy2", .name = "E-MU 1010 [MAEM8810]", 1351 .id = "EMU1010", 1352 .emu10k2_chip = 1, 1353 .ca0102_chip = 1, 1354 .spk71 = 1, 1355 .emu_model = EMU_MODEL_EMU1010}, /* EMU 1010 old revision */ 1356 /* This is MAEM8852 "HanaLiteLite" */ 1357 /* Supports sync daughter card. */ 1358 /* Tested by oswald.buddenhagen@gmx.de Mar 2023. */ 1359 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40021102, 1360 .driver = "Audigy2", .name = "E-MU 0404b PCI [MAEM8852]", 1361 .id = "EMU0404", 1362 .emu10k2_chip = 1, 1363 .ca0108_chip = 1, 1364 .spk71 = 1, 1365 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 new revision */ 1366 /* This is MAEM8850 "HanaLite" */ 1367 /* Supports sync daughter card. */ 1368 /* Tested by James@superbug.co.uk 20-3-2007. */ 1369 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40021102, 1370 .driver = "Audigy2", .name = "E-MU 0404 [MAEM8850]", 1371 .id = "EMU0404", 1372 .emu10k2_chip = 1, 1373 .ca0102_chip = 1, 1374 .spk71 = 1, 1375 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 */ 1376 /* EMU0404 PCIe */ 1377 /* Does NOT support sync daughter card. */ 1378 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40051102, 1379 .driver = "Audigy2", .name = "E-MU 0404 PCIe [MAEM8984]", 1380 .id = "EMU0404", 1381 .emu10k2_chip = 1, 1382 .ca0108_chip = 1, 1383 .spk71 = 1, 1384 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 PCIe ver_03 */ 1385 {.vendor = 0x1102, .device = 0x0008, 1386 .driver = "Audigy2", .name = "SB Audigy 2 Value [Unknown]", 1387 .id = "Audigy2", 1388 .emu10k2_chip = 1, 1389 .ca0108_chip = 1, 1390 .ac97_chip = 1} , 1391 /* Tested by James@superbug.co.uk 3rd July 2005 */ 1392 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20071102, 1393 .driver = "Audigy2", .name = "SB Audigy 4 PRO [SB0380]", 1394 .id = "Audigy2", 1395 .emu10k2_chip = 1, 1396 .ca0102_chip = 1, 1397 .ca0151_chip = 1, 1398 .spk71 = 1, 1399 .spdif_bug = 1, 1400 .ac97_chip = 1} , 1401 /* Tested by shane-alsa@cm.nu 5th Nov 2005 */ 1402 /* The 0x20061102 does have SB0350 written on it 1403 * Just like 0x20021102 1404 */ 1405 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20061102, 1406 .driver = "Audigy2", .name = "SB Audigy 2 [SB0350b]", 1407 .id = "Audigy2", 1408 .emu10k2_chip = 1, 1409 .ca0102_chip = 1, 1410 .ca0151_chip = 1, 1411 .spk71 = 1, 1412 .spdif_bug = 1, 1413 .invert_shared_spdif = 1, /* digital/analog switch swapped */ 1414 .ac97_chip = 1} , 1415 /* 0x20051102 also has SB0350 written on it, treated as Audigy 2 ZS by 1416 Creative's Windows driver */ 1417 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20051102, 1418 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0350a]", 1419 .id = "Audigy2", 1420 .emu10k2_chip = 1, 1421 .ca0102_chip = 1, 1422 .ca0151_chip = 1, 1423 .spk71 = 1, 1424 .spdif_bug = 1, 1425 .invert_shared_spdif = 1, /* digital/analog switch swapped */ 1426 .ac97_chip = 1} , 1427 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20021102, 1428 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0350]", 1429 .id = "Audigy2", 1430 .emu10k2_chip = 1, 1431 .ca0102_chip = 1, 1432 .ca0151_chip = 1, 1433 .spk71 = 1, 1434 .spdif_bug = 1, 1435 .invert_shared_spdif = 1, /* digital/analog switch swapped */ 1436 .ac97_chip = 1} , 1437 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20011102, 1438 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0360]", 1439 .id = "Audigy2", 1440 .emu10k2_chip = 1, 1441 .ca0102_chip = 1, 1442 .ca0151_chip = 1, 1443 .spk71 = 1, 1444 .spdif_bug = 1, 1445 .invert_shared_spdif = 1, /* digital/analog switch swapped */ 1446 .ac97_chip = 1} , 1447 /* Audigy 2 */ 1448 /* Tested by James@superbug.co.uk 3rd July 2005 */ 1449 /* DSP: CA0102-IAT 1450 * DAC: CS4382-KQ 1451 * ADC: Philips 1361T 1452 * AC97: STAC9721 1453 * CA0151: Yes 1454 */ 1455 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10071102, 1456 .driver = "Audigy2", .name = "SB Audigy 2 [SB0240]", 1457 .id = "Audigy2", 1458 .emu10k2_chip = 1, 1459 .ca0102_chip = 1, 1460 .ca0151_chip = 1, 1461 .spk71 = 1, 1462 .spdif_bug = 1, 1463 .adc_1361t = 1, /* 24 bit capture instead of 16bit */ 1464 .ac97_chip = 1} , 1465 /* Audigy 2 Platinum EX */ 1466 /* Win driver sets A_IOCFG output to 0x1c00 */ 1467 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10051102, 1468 .driver = "Audigy2", .name = "Audigy 2 Platinum EX [SB0280]", 1469 .id = "Audigy2", 1470 .emu10k2_chip = 1, 1471 .ca0102_chip = 1, 1472 .ca0151_chip = 1, 1473 .spk71 = 1, 1474 .spdif_bug = 1} , 1475 /* Dell OEM/Creative Labs Audigy 2 ZS */ 1476 /* See ALSA bug#1365 */ 1477 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10031102, 1478 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0353]", 1479 .id = "Audigy2", 1480 .emu10k2_chip = 1, 1481 .ca0102_chip = 1, 1482 .ca0151_chip = 1, 1483 .spk71 = 1, 1484 .spdif_bug = 1, 1485 .invert_shared_spdif = 1, /* digital/analog switch swapped */ 1486 .ac97_chip = 1} , 1487 /* Audigy 2 Platinum */ 1488 /* Win driver sets A_IOCFG output to 0xa00 */ 1489 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10021102, 1490 .driver = "Audigy2", .name = "SB Audigy 2 Platinum [SB0240P]", 1491 .id = "Audigy2", 1492 .emu10k2_chip = 1, 1493 .ca0102_chip = 1, 1494 .ca0151_chip = 1, 1495 .spk71 = 1, 1496 .spdif_bug = 1, 1497 .invert_shared_spdif = 1, /* digital/analog switch swapped */ 1498 .adc_1361t = 1, /* 24 bit capture instead of 16bit. Fixes ALSA bug#324 */ 1499 .ac97_chip = 1} , 1500 {.vendor = 0x1102, .device = 0x0004, .revision = 0x04, 1501 .driver = "Audigy2", .name = "SB Audigy 2 [Unknown]", 1502 .id = "Audigy2", 1503 .emu10k2_chip = 1, 1504 .ca0102_chip = 1, 1505 .ca0151_chip = 1, 1506 .spdif_bug = 1, 1507 .ac97_chip = 1} , 1508 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00531102, 1509 .driver = "Audigy", .name = "SB Audigy 1 [SB0092]", 1510 .id = "Audigy", 1511 .emu10k2_chip = 1, 1512 .ca0102_chip = 1, 1513 .ac97_chip = 1} , 1514 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00521102, 1515 .driver = "Audigy", .name = "SB Audigy 1 ES [SB0160]", 1516 .id = "Audigy", 1517 .emu10k2_chip = 1, 1518 .ca0102_chip = 1, 1519 .spdif_bug = 1, 1520 .ac97_chip = 1} , 1521 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00511102, 1522 .driver = "Audigy", .name = "SB Audigy 1 [SB0090]", 1523 .id = "Audigy", 1524 .emu10k2_chip = 1, 1525 .ca0102_chip = 1, 1526 .ac97_chip = 1} , 1527 {.vendor = 0x1102, .device = 0x0004, 1528 .driver = "Audigy", .name = "Audigy 1 [Unknown]", 1529 .id = "Audigy", 1530 .emu10k2_chip = 1, 1531 .ca0102_chip = 1, 1532 .ac97_chip = 1} , 1533 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x100a1102, 1534 .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0220]", 1535 .id = "Live", 1536 .emu10k1_chip = 1, 1537 .ac97_chip = 1, 1538 .sblive51 = 1} , 1539 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806b1102, 1540 .driver = "EMU10K1", .name = "SB Live! [SB0105]", 1541 .id = "Live", 1542 .emu10k1_chip = 1, 1543 .ac97_chip = 1, 1544 .sblive51 = 1} , 1545 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806a1102, 1546 .driver = "EMU10K1", .name = "SB Live! Value [SB0103]", 1547 .id = "Live", 1548 .emu10k1_chip = 1, 1549 .ac97_chip = 1, 1550 .sblive51 = 1} , 1551 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80691102, 1552 .driver = "EMU10K1", .name = "SB Live! Value [SB0101]", 1553 .id = "Live", 1554 .emu10k1_chip = 1, 1555 .ac97_chip = 1, 1556 .sblive51 = 1} , 1557 /* Tested by ALSA bug#1680 26th December 2005 */ 1558 /* note: It really has SB0220 written on the card, */ 1559 /* but it's SB0228 according to kx.inf */ 1560 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80661102, 1561 .driver = "EMU10K1", .name = "SB Live! 5.1 Dell OEM [SB0228]", 1562 .id = "Live", 1563 .emu10k1_chip = 1, 1564 .ac97_chip = 1, 1565 .sblive51 = 1} , 1566 /* Tested by Thomas Zehetbauer 27th Aug 2005 */ 1567 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80651102, 1568 .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0220]", 1569 .id = "Live", 1570 .emu10k1_chip = 1, 1571 .ac97_chip = 1, 1572 .sblive51 = 1} , 1573 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80641102, 1574 .driver = "EMU10K1", .name = "SB Live! 5.1", 1575 .id = "Live", 1576 .emu10k1_chip = 1, 1577 .ac97_chip = 1, 1578 .sblive51 = 1} , 1579 /* Tested by alsa bugtrack user "hus" bug #1297 12th Aug 2005 */ 1580 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80611102, 1581 .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0060]", 1582 .id = "Live", 1583 .emu10k1_chip = 1, 1584 .ac97_chip = 2, /* ac97 is optional; both SBLive 5.1 and platinum 1585 * share the same IDs! 1586 */ 1587 .sblive51 = 1} , 1588 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80511102, 1589 .driver = "EMU10K1", .name = "SB Live! Value [CT4850]", 1590 .id = "Live", 1591 .emu10k1_chip = 1, 1592 .ac97_chip = 1, 1593 .sblive51 = 1} , 1594 /* SB Live! Platinum */ 1595 /* Win driver sets A_IOCFG output to 0 */ 1596 /* Tested by Jonathan Dowland <jon@dow.land> Apr 2023. */ 1597 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80401102, 1598 .driver = "EMU10K1", .name = "SB Live! Platinum [CT4760P]", 1599 .id = "Live", 1600 .emu10k1_chip = 1, 1601 .ac97_chip = 1} , 1602 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80321102, 1603 .driver = "EMU10K1", .name = "SB Live! Value [CT4871]", 1604 .id = "Live", 1605 .emu10k1_chip = 1, 1606 .ac97_chip = 1, 1607 .sblive51 = 1} , 1608 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80311102, 1609 .driver = "EMU10K1", .name = "SB Live! Value [CT4831]", 1610 .id = "Live", 1611 .emu10k1_chip = 1, 1612 .ac97_chip = 1, 1613 .sblive51 = 1} , 1614 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80281102, 1615 .driver = "EMU10K1", .name = "SB Live! Value [CT4870]", 1616 .id = "Live", 1617 .emu10k1_chip = 1, 1618 .ac97_chip = 1, 1619 .sblive51 = 1} , 1620 /* Tested by James@superbug.co.uk 3rd July 2005 */ 1621 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80271102, 1622 .driver = "EMU10K1", .name = "SB Live! Value [CT4832]", 1623 .id = "Live", 1624 .emu10k1_chip = 1, 1625 .ac97_chip = 1, 1626 .sblive51 = 1} , 1627 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80261102, 1628 .driver = "EMU10K1", .name = "SB Live! Value [CT4830]", 1629 .id = "Live", 1630 .emu10k1_chip = 1, 1631 .ac97_chip = 1, 1632 .sblive51 = 1} , 1633 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80231102, 1634 .driver = "EMU10K1", .name = "SB PCI512 [CT4790]", 1635 .id = "Live", 1636 .emu10k1_chip = 1, 1637 .ac97_chip = 1, 1638 .sblive51 = 1} , 1639 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80221102, 1640 .driver = "EMU10K1", .name = "SB Live! Value [CT4780]", 1641 .id = "Live", 1642 .emu10k1_chip = 1, 1643 .ac97_chip = 1, 1644 .sblive51 = 1} , 1645 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x40011102, 1646 .driver = "EMU10K1", .name = "E-MU APS [PC545]", 1647 .id = "APS", 1648 .emu10k1_chip = 1, 1649 .ecard = 1} , 1650 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00211102, 1651 .driver = "EMU10K1", .name = "SB Live! [CT4620]", 1652 .id = "Live", 1653 .emu10k1_chip = 1, 1654 .ac97_chip = 1, 1655 .sblive51 = 1} , 1656 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00201102, 1657 .driver = "EMU10K1", .name = "SB Live! Value [CT4670]", 1658 .id = "Live", 1659 .emu10k1_chip = 1, 1660 .ac97_chip = 1, 1661 .sblive51 = 1} , 1662 {.vendor = 0x1102, .device = 0x0002, 1663 .driver = "EMU10K1", .name = "SB Live! [Unknown]", 1664 .id = "Live", 1665 .emu10k1_chip = 1, 1666 .ac97_chip = 1, 1667 .sblive51 = 1} , 1668 { } /* terminator */ 1669 }; 1670 1671 /* 1672 * The chip (at least the Audigy 2 CA0102 chip, but most likely others, too) 1673 * has a problem that from time to time it likes to do few DMA reads a bit 1674 * beyond its normal allocation and gets very confused if these reads get 1675 * blocked by a IOMMU. 1676 * 1677 * This behaviour has been observed for the first (reserved) page 1678 * (for which it happens multiple times at every playback), often for various 1679 * synth pages and sometimes for PCM playback buffers and the page table 1680 * memory itself. 1681 * 1682 * As a workaround let's widen these DMA allocations by an extra page if we 1683 * detect that the device is behind a non-passthrough IOMMU. 1684 */ 1685 static void snd_emu10k1_detect_iommu(struct snd_emu10k1 *emu) 1686 { 1687 struct iommu_domain *domain; 1688 1689 emu->iommu_workaround = false; 1690 1691 domain = iommu_get_domain_for_dev(emu->card->dev); 1692 if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY) 1693 return; 1694 1695 dev_notice(emu->card->dev, 1696 "non-passthrough IOMMU detected, widening DMA allocations"); 1697 emu->iommu_workaround = true; 1698 } 1699 1700 int snd_emu10k1_create(struct snd_card *card, 1701 struct pci_dev *pci, 1702 unsigned short extin_mask, 1703 unsigned short extout_mask, 1704 long max_cache_bytes, 1705 int enable_ir, 1706 uint subsystem) 1707 { 1708 struct snd_emu10k1 *emu = card->private_data; 1709 int idx, err; 1710 int is_audigy; 1711 size_t page_table_size; 1712 __le32 *pgtbl; 1713 unsigned int silent_page; 1714 const struct snd_emu_chip_details *c; 1715 1716 /* enable PCI device */ 1717 err = pcim_enable_device(pci); 1718 if (err < 0) 1719 return err; 1720 1721 card->private_free = snd_emu10k1_free; 1722 emu->card = card; 1723 spin_lock_init(&emu->reg_lock); 1724 spin_lock_init(&emu->emu_lock); 1725 spin_lock_init(&emu->spi_lock); 1726 spin_lock_init(&emu->i2c_lock); 1727 spin_lock_init(&emu->voice_lock); 1728 spin_lock_init(&emu->synth_lock); 1729 spin_lock_init(&emu->memblk_lock); 1730 mutex_init(&emu->fx8010.lock); 1731 INIT_LIST_HEAD(&emu->mapped_link_head); 1732 INIT_LIST_HEAD(&emu->mapped_order_link_head); 1733 emu->pci = pci; 1734 emu->irq = -1; 1735 emu->synth = NULL; 1736 emu->get_synth_voice = NULL; 1737 INIT_DELAYED_WORK(&emu->emu1010.firmware_work, emu1010_firmware_work); 1738 /* read revision & serial */ 1739 emu->revision = pci->revision; 1740 pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &emu->serial); 1741 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &emu->model); 1742 dev_dbg(card->dev, 1743 "vendor = 0x%x, device = 0x%x, subsystem_vendor_id = 0x%x, subsystem_id = 0x%x\n", 1744 pci->vendor, pci->device, emu->serial, emu->model); 1745 1746 for (c = emu_chip_details; c->vendor; c++) { 1747 if (c->vendor == pci->vendor && c->device == pci->device) { 1748 if (subsystem) { 1749 if (c->subsystem && (c->subsystem == subsystem)) 1750 break; 1751 else 1752 continue; 1753 } else { 1754 if (c->subsystem && (c->subsystem != emu->serial)) 1755 continue; 1756 if (c->revision && c->revision != emu->revision) 1757 continue; 1758 } 1759 break; 1760 } 1761 } 1762 if (c->vendor == 0) { 1763 dev_err(card->dev, "emu10k1: Card not recognised\n"); 1764 return -ENOENT; 1765 } 1766 emu->card_capabilities = c; 1767 if (c->subsystem && !subsystem) 1768 dev_dbg(card->dev, "Sound card name = %s\n", c->name); 1769 else if (subsystem) 1770 dev_dbg(card->dev, "Sound card name = %s, " 1771 "vendor = 0x%x, device = 0x%x, subsystem = 0x%x. " 1772 "Forced to subsystem = 0x%x\n", c->name, 1773 pci->vendor, pci->device, emu->serial, c->subsystem); 1774 else 1775 dev_dbg(card->dev, "Sound card name = %s, " 1776 "vendor = 0x%x, device = 0x%x, subsystem = 0x%x.\n", 1777 c->name, pci->vendor, pci->device, 1778 emu->serial); 1779 1780 if (!*card->id && c->id) 1781 strscpy(card->id, c->id, sizeof(card->id)); 1782 1783 is_audigy = emu->audigy = c->emu10k2_chip; 1784 1785 snd_emu10k1_detect_iommu(emu); 1786 1787 /* set addressing mode */ 1788 emu->address_mode = is_audigy ? 0 : 1; 1789 /* set the DMA transfer mask */ 1790 emu->dma_mask = emu->address_mode ? EMU10K1_DMA_MASK : AUDIGY_DMA_MASK; 1791 if (dma_set_mask_and_coherent(&pci->dev, emu->dma_mask) < 0) { 1792 dev_err(card->dev, 1793 "architecture does not support PCI busmaster DMA with mask 0x%lx\n", 1794 emu->dma_mask); 1795 return -ENXIO; 1796 } 1797 if (is_audigy) 1798 emu->gpr_base = A_FXGPREGBASE; 1799 else 1800 emu->gpr_base = FXGPREGBASE; 1801 1802 err = pci_request_regions(pci, "EMU10K1"); 1803 if (err < 0) 1804 return err; 1805 emu->port = pci_resource_start(pci, 0); 1806 1807 emu->max_cache_pages = max_cache_bytes >> PAGE_SHIFT; 1808 1809 page_table_size = sizeof(u32) * (emu->address_mode ? MAXPAGES1 : 1810 MAXPAGES0); 1811 if (snd_emu10k1_alloc_pages_maybe_wider(emu, page_table_size, 1812 &emu->ptb_pages) < 0) 1813 return -ENOMEM; 1814 dev_dbg(card->dev, "page table address range is %.8lx:%.8lx\n", 1815 (unsigned long)emu->ptb_pages.addr, 1816 (unsigned long)(emu->ptb_pages.addr + emu->ptb_pages.bytes)); 1817 1818 emu->page_ptr_table = vmalloc(array_size(sizeof(void *), 1819 emu->max_cache_pages)); 1820 emu->page_addr_table = vmalloc(array_size(sizeof(unsigned long), 1821 emu->max_cache_pages)); 1822 if (!emu->page_ptr_table || !emu->page_addr_table) 1823 return -ENOMEM; 1824 1825 if (snd_emu10k1_alloc_pages_maybe_wider(emu, EMUPAGESIZE, 1826 &emu->silent_page) < 0) 1827 return -ENOMEM; 1828 dev_dbg(card->dev, "silent page range is %.8lx:%.8lx\n", 1829 (unsigned long)emu->silent_page.addr, 1830 (unsigned long)(emu->silent_page.addr + 1831 emu->silent_page.bytes)); 1832 1833 emu->memhdr = snd_util_memhdr_new(emu->max_cache_pages * PAGE_SIZE); 1834 if (!emu->memhdr) 1835 return -ENOMEM; 1836 emu->memhdr->block_extra_size = sizeof(struct snd_emu10k1_memblk) - 1837 sizeof(struct snd_util_memblk); 1838 1839 pci_set_master(pci); 1840 1841 // The masks are not used for Audigy. 1842 // FIXME: these should come from the card_capabilites table. 1843 if (extin_mask == 0) 1844 extin_mask = 0x3fcf; // EXTIN_* 1845 if (extout_mask == 0) 1846 extout_mask = 0x7fff; // EXTOUT_* 1847 emu->fx8010.extin_mask = extin_mask; 1848 emu->fx8010.extout_mask = extout_mask; 1849 emu->enable_ir = enable_ir; 1850 1851 if (emu->card_capabilities->ca_cardbus_chip) { 1852 err = snd_emu10k1_cardbus_init(emu); 1853 if (err < 0) 1854 return err; 1855 } 1856 if (emu->card_capabilities->ecard) { 1857 err = snd_emu10k1_ecard_init(emu); 1858 if (err < 0) 1859 return err; 1860 } else if (emu->card_capabilities->emu_model) { 1861 err = snd_emu10k1_emu1010_init(emu); 1862 if (err < 0) 1863 return err; 1864 } else { 1865 /* 5.1: Enable the additional AC97 Slots. If the emu10k1 version 1866 does not support this, it shouldn't do any harm */ 1867 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, 1868 AC97SLOT_CNTR|AC97SLOT_LFE); 1869 } 1870 1871 /* initialize TRAM setup */ 1872 emu->fx8010.itram_size = (16 * 1024)/2; 1873 emu->fx8010.etram_pages.area = NULL; 1874 emu->fx8010.etram_pages.bytes = 0; 1875 1876 /* irq handler must be registered after I/O ports are activated */ 1877 if (devm_request_irq(&pci->dev, pci->irq, snd_emu10k1_interrupt, 1878 IRQF_SHARED, KBUILD_MODNAME, emu)) 1879 return -EBUSY; 1880 emu->irq = pci->irq; 1881 card->sync_irq = emu->irq; 1882 1883 /* 1884 * Init to 0x02109204 : 1885 * Clock accuracy = 0 (1000ppm) 1886 * Sample Rate = 2 (48kHz) 1887 * Audio Channel = 1 (Left of 2) 1888 * Source Number = 0 (Unspecified) 1889 * Generation Status = 1 (Original for Cat Code 12) 1890 * Cat Code = 12 (Digital Signal Mixer) 1891 * Mode = 0 (Mode 0) 1892 * Emphasis = 0 (None) 1893 * CP = 1 (Copyright unasserted) 1894 * AN = 0 (Audio data) 1895 * P = 0 (Consumer) 1896 */ 1897 emu->spdif_bits[0] = emu->spdif_bits[1] = 1898 emu->spdif_bits[2] = SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 | 1899 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC | 1900 SPCS_GENERATIONSTATUS | 0x00001200 | 1901 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT; 1902 1903 /* Clear silent pages and set up pointers */ 1904 memset(emu->silent_page.area, 0, emu->silent_page.bytes); 1905 silent_page = emu->silent_page.addr << emu->address_mode; 1906 pgtbl = (__le32 *)emu->ptb_pages.area; 1907 for (idx = 0; idx < (emu->address_mode ? MAXPAGES1 : MAXPAGES0); idx++) 1908 pgtbl[idx] = cpu_to_le32(silent_page | idx); 1909 1910 /* set up voice indices */ 1911 for (idx = 0; idx < NUM_G; idx++) 1912 emu->voices[idx].number = idx; 1913 1914 err = snd_emu10k1_init(emu, enable_ir); 1915 if (err < 0) 1916 return err; 1917 #ifdef CONFIG_PM_SLEEP 1918 err = alloc_pm_buffer(emu); 1919 if (err < 0) 1920 return err; 1921 #endif 1922 1923 /* Initialize the effect engine */ 1924 err = snd_emu10k1_init_efx(emu); 1925 if (err < 0) 1926 return err; 1927 snd_emu10k1_audio_enable(emu); 1928 1929 #ifdef CONFIG_SND_PROC_FS 1930 snd_emu10k1_proc_init(emu); 1931 #endif 1932 return 0; 1933 } 1934 1935 #ifdef CONFIG_PM_SLEEP 1936 static const unsigned char saved_regs[] = { 1937 CPF, PTRX, CVCF, VTFT, Z1, Z2, PSST, DSL, CCCA, CCR, CLP, 1938 FXRT, MAPA, MAPB, ENVVOL, ATKHLDV, DCYSUSV, LFOVAL1, ENVVAL, 1939 ATKHLDM, DCYSUSM, LFOVAL2, IP, IFATN, PEFE, FMMOD, TREMFRQ, FM2FRQ2, 1940 TEMPENV, ADCCR, FXWC, MICBA, ADCBA, FXBA, 1941 MICBS, ADCBS, FXBS, CDCS, GPSCS, SPCS0, SPCS1, SPCS2, 1942 SPBYPASS, AC97SLOT, CDSRCS, GPSRCS, ZVSRCS, MICIDX, ADCIDX, FXIDX, 1943 0xff /* end */ 1944 }; 1945 static const unsigned char saved_regs_audigy[] = { 1946 A_ADCIDX, A_MICIDX, A_FXWC1, A_FXWC2, A_EHC, 1947 A_FXRT2, A_SENDAMOUNTS, A_FXRT1, 1948 0xff /* end */ 1949 }; 1950 1951 static int alloc_pm_buffer(struct snd_emu10k1 *emu) 1952 { 1953 int size; 1954 1955 size = ARRAY_SIZE(saved_regs); 1956 if (emu->audigy) 1957 size += ARRAY_SIZE(saved_regs_audigy); 1958 emu->saved_ptr = vmalloc(array3_size(4, NUM_G, size)); 1959 if (!emu->saved_ptr) 1960 return -ENOMEM; 1961 if (snd_emu10k1_efx_alloc_pm_buffer(emu) < 0) 1962 return -ENOMEM; 1963 if (emu->card_capabilities->ca0151_chip && 1964 snd_p16v_alloc_pm_buffer(emu) < 0) 1965 return -ENOMEM; 1966 return 0; 1967 } 1968 1969 static void free_pm_buffer(struct snd_emu10k1 *emu) 1970 { 1971 vfree(emu->saved_ptr); 1972 snd_emu10k1_efx_free_pm_buffer(emu); 1973 if (emu->card_capabilities->ca0151_chip) 1974 snd_p16v_free_pm_buffer(emu); 1975 } 1976 1977 void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu) 1978 { 1979 int i; 1980 const unsigned char *reg; 1981 unsigned int *val; 1982 1983 val = emu->saved_ptr; 1984 for (reg = saved_regs; *reg != 0xff; reg++) 1985 for (i = 0; i < NUM_G; i++, val++) 1986 *val = snd_emu10k1_ptr_read(emu, *reg, i); 1987 if (emu->audigy) { 1988 for (reg = saved_regs_audigy; *reg != 0xff; reg++) 1989 for (i = 0; i < NUM_G; i++, val++) 1990 *val = snd_emu10k1_ptr_read(emu, *reg, i); 1991 } 1992 if (emu->audigy) 1993 emu->saved_a_iocfg = inw(emu->port + A_IOCFG); 1994 emu->saved_hcfg = inl(emu->port + HCFG); 1995 } 1996 1997 void snd_emu10k1_resume_init(struct snd_emu10k1 *emu) 1998 { 1999 if (emu->card_capabilities->ca_cardbus_chip) 2000 snd_emu10k1_cardbus_init(emu); 2001 if (emu->card_capabilities->ecard) 2002 snd_emu10k1_ecard_init(emu); 2003 else if (emu->card_capabilities->emu_model) 2004 snd_emu10k1_emu1010_init(emu); 2005 else 2006 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_CNTR|AC97SLOT_LFE); 2007 snd_emu10k1_init(emu, emu->enable_ir); 2008 } 2009 2010 void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu) 2011 { 2012 int i; 2013 const unsigned char *reg; 2014 unsigned int *val; 2015 2016 snd_emu10k1_audio_enable(emu); 2017 2018 /* resore for spdif */ 2019 if (emu->audigy) 2020 outw(emu->saved_a_iocfg, emu->port + A_IOCFG); 2021 outl(emu->saved_hcfg, emu->port + HCFG); 2022 2023 val = emu->saved_ptr; 2024 for (reg = saved_regs; *reg != 0xff; reg++) 2025 for (i = 0; i < NUM_G; i++, val++) 2026 snd_emu10k1_ptr_write(emu, *reg, i, *val); 2027 if (emu->audigy) { 2028 for (reg = saved_regs_audigy; *reg != 0xff; reg++) 2029 for (i = 0; i < NUM_G; i++, val++) 2030 snd_emu10k1_ptr_write(emu, *reg, i, *val); 2031 } 2032 } 2033 #endif 2034