1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * Creative Labs, Inc. 5 * Routines for control of EMU10K1 chips 6 * 7 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk> 8 * Added support for Audigy 2 Value. 9 * Added EMU 1010 support. 10 * General bug fixes and enhancements. 11 * 12 * BUGS: 13 * -- 14 * 15 * TODO: 16 * -- 17 */ 18 19 #include <linux/sched.h> 20 #include <linux/delay.h> 21 #include <linux/init.h> 22 #include <linux/module.h> 23 #include <linux/interrupt.h> 24 #include <linux/iommu.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include <linux/vmalloc.h> 28 #include <linux/mutex.h> 29 30 31 #include <sound/core.h> 32 #include <sound/emu10k1.h> 33 #include <linux/firmware.h> 34 #include "p16v.h" 35 #include "tina2.h" 36 #include "p17v.h" 37 38 39 #define HANA_FILENAME "emu/hana.fw" 40 #define DOCK_FILENAME "emu/audio_dock.fw" 41 #define EMU1010B_FILENAME "emu/emu1010b.fw" 42 #define MICRO_DOCK_FILENAME "emu/micro_dock.fw" 43 #define EMU0404_FILENAME "emu/emu0404.fw" 44 #define EMU1010_NOTEBOOK_FILENAME "emu/emu1010_notebook.fw" 45 46 MODULE_FIRMWARE(HANA_FILENAME); 47 MODULE_FIRMWARE(DOCK_FILENAME); 48 MODULE_FIRMWARE(EMU1010B_FILENAME); 49 MODULE_FIRMWARE(MICRO_DOCK_FILENAME); 50 MODULE_FIRMWARE(EMU0404_FILENAME); 51 MODULE_FIRMWARE(EMU1010_NOTEBOOK_FILENAME); 52 53 54 /************************************************************************* 55 * EMU10K1 init / done 56 *************************************************************************/ 57 58 void snd_emu10k1_voice_init(struct snd_emu10k1 *emu, int ch) 59 { 60 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0); 61 snd_emu10k1_ptr_write(emu, IP, ch, 0); 62 snd_emu10k1_ptr_write(emu, VTFT, ch, VTFT_FILTERTARGET_MASK); 63 snd_emu10k1_ptr_write(emu, CVCF, ch, CVCF_CURRENTFILTER_MASK); 64 snd_emu10k1_ptr_write(emu, PTRX, ch, 0); 65 snd_emu10k1_ptr_write(emu, CPF, ch, 0); 66 snd_emu10k1_ptr_write(emu, CCR, ch, 0); 67 68 snd_emu10k1_ptr_write(emu, PSST, ch, 0); 69 snd_emu10k1_ptr_write(emu, DSL, ch, 0x10); 70 snd_emu10k1_ptr_write(emu, CCCA, ch, 0); 71 snd_emu10k1_ptr_write(emu, Z1, ch, 0); 72 snd_emu10k1_ptr_write(emu, Z2, ch, 0); 73 snd_emu10k1_ptr_write(emu, FXRT, ch, 0x32100000); 74 75 snd_emu10k1_ptr_write(emu, ATKHLDM, ch, 0); 76 snd_emu10k1_ptr_write(emu, DCYSUSM, ch, 0); 77 snd_emu10k1_ptr_write(emu, IFATN, ch, IFATN_FILTERCUTOFF_MASK | IFATN_ATTENUATION_MASK); 78 snd_emu10k1_ptr_write(emu, PEFE, ch, 0); 79 snd_emu10k1_ptr_write(emu, FMMOD, ch, 0); 80 snd_emu10k1_ptr_write(emu, TREMFRQ, ch, 24); /* 1 Hz */ 81 snd_emu10k1_ptr_write(emu, FM2FRQ2, ch, 24); /* 1 Hz */ 82 snd_emu10k1_ptr_write(emu, TEMPENV, ch, 0); 83 84 /*** these are last so OFF prevents writing ***/ 85 snd_emu10k1_ptr_write(emu, LFOVAL2, ch, 0); 86 snd_emu10k1_ptr_write(emu, LFOVAL1, ch, 0); 87 snd_emu10k1_ptr_write(emu, ATKHLDV, ch, 0); 88 snd_emu10k1_ptr_write(emu, ENVVOL, ch, 0); 89 snd_emu10k1_ptr_write(emu, ENVVAL, ch, 0); 90 91 /* Audigy extra stuffs */ 92 if (emu->audigy) { 93 snd_emu10k1_ptr_write(emu, A_CSBA, ch, 0); 94 snd_emu10k1_ptr_write(emu, A_CSDC, ch, 0); 95 snd_emu10k1_ptr_write(emu, A_CSFE, ch, 0); 96 snd_emu10k1_ptr_write(emu, A_CSHG, ch, 0); 97 snd_emu10k1_ptr_write(emu, A_FXRT1, ch, 0x03020100); 98 snd_emu10k1_ptr_write(emu, A_FXRT2, ch, 0x3f3f3f3f); 99 snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, ch, 0); 100 } 101 } 102 103 static const unsigned int spi_dac_init[] = { 104 0x00ff, 105 0x02ff, 106 0x0400, 107 0x0520, 108 0x0600, 109 0x08ff, 110 0x0aff, 111 0x0cff, 112 0x0eff, 113 0x10ff, 114 0x1200, 115 0x1400, 116 0x1480, 117 0x1800, 118 0x1aff, 119 0x1cff, 120 0x1e00, 121 0x0530, 122 0x0602, 123 0x0622, 124 0x1400, 125 }; 126 127 static const unsigned int i2c_adc_init[][2] = { 128 { 0x17, 0x00 }, /* Reset */ 129 { 0x07, 0x00 }, /* Timeout */ 130 { 0x0b, 0x22 }, /* Interface control */ 131 { 0x0c, 0x22 }, /* Master mode control */ 132 { 0x0d, 0x08 }, /* Powerdown control */ 133 { 0x0e, 0xcf }, /* Attenuation Left 0x01 = -103dB, 0xff = 24dB */ 134 { 0x0f, 0xcf }, /* Attenuation Right 0.5dB steps */ 135 { 0x10, 0x7b }, /* ALC Control 1 */ 136 { 0x11, 0x00 }, /* ALC Control 2 */ 137 { 0x12, 0x32 }, /* ALC Control 3 */ 138 { 0x13, 0x00 }, /* Noise gate control */ 139 { 0x14, 0xa6 }, /* Limiter control */ 140 { 0x15, ADC_MUX_2 }, /* ADC Mixer control. Mic for A2ZS Notebook */ 141 }; 142 143 static int snd_emu10k1_init(struct snd_emu10k1 *emu, int enable_ir) 144 { 145 unsigned int silent_page; 146 int ch; 147 u32 tmp; 148 149 /* disable audio and lock cache */ 150 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | 151 HCFG_MUTEBUTTONENABLE, emu->port + HCFG); 152 153 /* reset recording buffers */ 154 snd_emu10k1_ptr_write(emu, MICBS, 0, ADCBS_BUFSIZE_NONE); 155 snd_emu10k1_ptr_write(emu, MICBA, 0, 0); 156 snd_emu10k1_ptr_write(emu, FXBS, 0, ADCBS_BUFSIZE_NONE); 157 snd_emu10k1_ptr_write(emu, FXBA, 0, 0); 158 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE); 159 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0); 160 161 /* disable channel interrupt */ 162 outl(0, emu->port + INTE); 163 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0); 164 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0); 165 166 /* disable stop on loop end */ 167 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0); 168 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0); 169 170 if (emu->audigy) { 171 /* set SPDIF bypass mode */ 172 snd_emu10k1_ptr_write(emu, SPBYPASS, 0, SPBYPASS_FORMAT); 173 /* enable rear left + rear right AC97 slots */ 174 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_REAR_RIGHT | 175 AC97SLOT_REAR_LEFT); 176 } 177 178 /* init envelope engine */ 179 for (ch = 0; ch < NUM_G; ch++) 180 snd_emu10k1_voice_init(emu, ch); 181 182 snd_emu10k1_ptr_write(emu, SPCS0, 0, emu->spdif_bits[0]); 183 snd_emu10k1_ptr_write(emu, SPCS1, 0, emu->spdif_bits[1]); 184 snd_emu10k1_ptr_write(emu, SPCS2, 0, emu->spdif_bits[2]); 185 186 if (emu->card_capabilities->emu_model) { 187 } else if (emu->card_capabilities->ca0151_chip) { /* audigy2 */ 188 /* Hacks for Alice3 to work independent of haP16V driver */ 189 /* Setup SRCMulti_I2S SamplingRate */ 190 snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, 0, A_I2S_CAPTURE_96000); 191 192 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */ 193 snd_emu10k1_ptr20_write(emu, SRCSel, 0, 0x14); 194 /* Setup SRCMulti Input Audio Enable */ 195 /* Use 0xFFFFFFFF to enable P16V sounds. */ 196 snd_emu10k1_ptr20_write(emu, SRCMULTI_ENABLE, 0, 0xFFFFFFFF); 197 198 /* Enabled Phased (8-channel) P16V playback */ 199 outl(0x0201, emu->port + HCFG2); 200 /* Set playback routing. */ 201 snd_emu10k1_ptr20_write(emu, CAPTURE_P16V_SOURCE, 0, 0x78e4); 202 } else if (emu->card_capabilities->ca0108_chip) { /* audigy2 Value */ 203 /* Hacks for Alice3 to work independent of haP16V driver */ 204 dev_info(emu->card->dev, "Audigy2 value: Special config.\n"); 205 /* Setup SRCMulti_I2S SamplingRate */ 206 snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, 0, A_I2S_CAPTURE_96000); 207 208 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */ 209 snd_emu10k1_ptr20_write(emu, P17V_SRCSel, 0, 0x14); 210 211 /* Setup SRCMulti Input Audio Enable */ 212 snd_emu10k1_ptr20_write(emu, P17V_MIXER_I2S_ENABLE, 0, 0xFF000000); 213 214 /* Setup SPDIF Out Audio Enable */ 215 /* The Audigy 2 Value has a separate SPDIF out, 216 * so no need for a mixer switch 217 */ 218 snd_emu10k1_ptr20_write(emu, P17V_MIXER_SPDIF_ENABLE, 0, 0xFF000000); 219 220 tmp = inw(emu->port + A_IOCFG) & ~0x8; /* Clear bit 3 */ 221 outw(tmp, emu->port + A_IOCFG); 222 } 223 if (emu->card_capabilities->spi_dac) { /* Audigy 2 ZS Notebook with DAC Wolfson WM8768/WM8568 */ 224 int size, n; 225 226 size = ARRAY_SIZE(spi_dac_init); 227 for (n = 0; n < size; n++) 228 snd_emu10k1_spi_write(emu, spi_dac_init[n]); 229 230 snd_emu10k1_ptr20_write(emu, 0x60, 0, 0x10); 231 /* Enable GPIOs 232 * GPIO0: Unknown 233 * GPIO1: Speakers-enabled. 234 * GPIO2: Unknown 235 * GPIO3: Unknown 236 * GPIO4: IEC958 Output on. 237 * GPIO5: Unknown 238 * GPIO6: Unknown 239 * GPIO7: Unknown 240 */ 241 outw(0x76, emu->port + A_IOCFG); /* Windows uses 0x3f76 */ 242 } 243 if (emu->card_capabilities->i2c_adc) { /* Audigy 2 ZS Notebook with ADC Wolfson WM8775 */ 244 int size, n; 245 246 snd_emu10k1_ptr20_write(emu, P17V_I2S_SRC_SEL, 0, 0x2020205f); 247 tmp = inw(emu->port + A_IOCFG); 248 outw(tmp | 0x4, emu->port + A_IOCFG); /* Set bit 2 for mic input */ 249 tmp = inw(emu->port + A_IOCFG); 250 size = ARRAY_SIZE(i2c_adc_init); 251 for (n = 0; n < size; n++) 252 snd_emu10k1_i2c_write(emu, i2c_adc_init[n][0], i2c_adc_init[n][1]); 253 for (n = 0; n < 4; n++) { 254 emu->i2c_capture_volume[n][0] = 0xcf; 255 emu->i2c_capture_volume[n][1] = 0xcf; 256 } 257 } 258 259 260 snd_emu10k1_ptr_write(emu, PTB, 0, emu->ptb_pages.addr); 261 snd_emu10k1_ptr_write(emu, TCB, 0, 0); /* taken from original driver */ 262 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_256K); /* taken from original driver */ 263 264 silent_page = (emu->silent_page.addr << emu->address_mode) | (emu->address_mode ? MAP_PTI_MASK1 : MAP_PTI_MASK0); 265 for (ch = 0; ch < NUM_G; ch++) { 266 snd_emu10k1_ptr_write(emu, MAPA, ch, silent_page); 267 snd_emu10k1_ptr_write(emu, MAPB, ch, silent_page); 268 } 269 270 if (emu->card_capabilities->emu_model) { 271 outl(HCFG_AUTOMUTE_ASYNC | 272 HCFG_EMU32_SLAVE | 273 HCFG_AUDIOENABLE, emu->port + HCFG); 274 /* 275 * Hokay, setup HCFG 276 * Mute Disable Audio = 0 277 * Lock Tank Memory = 1 278 * Lock Sound Memory = 0 279 * Auto Mute = 1 280 */ 281 } else if (emu->audigy) { 282 if (emu->revision == 4) /* audigy2 */ 283 outl(HCFG_AUDIOENABLE | 284 HCFG_AC3ENABLE_CDSPDIF | 285 HCFG_AC3ENABLE_GPSPDIF | 286 HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG); 287 else 288 outl(HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG); 289 /* FIXME: Remove all these emu->model and replace it with a card recognition parameter, 290 * e.g. card_capabilities->joystick */ 291 } else if (emu->model == 0x20 || 292 emu->model == 0xc400 || 293 (emu->model == 0x21 && emu->revision < 6)) 294 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE, emu->port + HCFG); 295 else 296 /* With on-chip joystick */ 297 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG); 298 299 if (enable_ir) { /* enable IR for SB Live */ 300 if (emu->card_capabilities->emu_model) { 301 ; /* Disable all access to A_IOCFG for the emu1010 */ 302 } else if (emu->card_capabilities->i2c_adc) { 303 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */ 304 } else if (emu->audigy) { 305 u16 reg = inw(emu->port + A_IOCFG); 306 outw(reg | A_IOCFG_GPOUT2, emu->port + A_IOCFG); 307 udelay(500); 308 outw(reg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, emu->port + A_IOCFG); 309 udelay(100); 310 outw(reg, emu->port + A_IOCFG); 311 } else { 312 unsigned int reg = inl(emu->port + HCFG); 313 outl(reg | HCFG_GPOUT2, emu->port + HCFG); 314 udelay(500); 315 outl(reg | HCFG_GPOUT1 | HCFG_GPOUT2, emu->port + HCFG); 316 udelay(100); 317 outl(reg, emu->port + HCFG); 318 } 319 } 320 321 if (emu->card_capabilities->emu_model) { 322 ; /* Disable all access to A_IOCFG for the emu1010 */ 323 } else if (emu->card_capabilities->i2c_adc) { 324 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */ 325 } else if (emu->audigy) { /* enable analog output */ 326 u16 reg = inw(emu->port + A_IOCFG); 327 outw(reg | A_IOCFG_GPOUT0, emu->port + A_IOCFG); 328 } 329 330 if (emu->address_mode == 0) { 331 /* use 16M in 4G */ 332 outl(inl(emu->port + HCFG) | HCFG_EXPANDED_MEM, emu->port + HCFG); 333 } 334 335 return 0; 336 } 337 338 static void snd_emu10k1_audio_enable(struct snd_emu10k1 *emu) 339 { 340 /* 341 * Enable the audio bit 342 */ 343 outl(inl(emu->port + HCFG) | HCFG_AUDIOENABLE, emu->port + HCFG); 344 345 /* Enable analog/digital outs on audigy */ 346 if (emu->card_capabilities->emu_model) { 347 ; /* Disable all access to A_IOCFG for the emu1010 */ 348 } else if (emu->card_capabilities->i2c_adc) { 349 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */ 350 } else if (emu->audigy) { 351 outw(inw(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG); 352 353 if (emu->card_capabilities->ca0151_chip) { /* audigy2 */ 354 /* Unmute Analog now. Set GPO6 to 1 for Apollo. 355 * This has to be done after init ALice3 I2SOut beyond 48KHz. 356 * So, sequence is important. */ 357 outw(inw(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG); 358 } else if (emu->card_capabilities->ca0108_chip) { /* audigy2 value */ 359 /* Unmute Analog now. */ 360 outw(inw(emu->port + A_IOCFG) | 0x0060, emu->port + A_IOCFG); 361 } else { 362 /* Disable routing from AC97 line out to Front speakers */ 363 outw(inw(emu->port + A_IOCFG) | 0x0080, emu->port + A_IOCFG); 364 } 365 } 366 367 #if 0 368 { 369 unsigned int tmp; 370 /* FIXME: the following routine disables LiveDrive-II !! */ 371 /* TOSLink detection */ 372 emu->tos_link = 0; 373 tmp = inl(emu->port + HCFG); 374 if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) { 375 outl(tmp|0x800, emu->port + HCFG); 376 udelay(50); 377 if (tmp != (inl(emu->port + HCFG) & ~0x800)) { 378 emu->tos_link = 1; 379 outl(tmp, emu->port + HCFG); 380 } 381 } 382 } 383 #endif 384 385 snd_emu10k1_intr_enable(emu, INTE_PCIERRORENABLE); 386 } 387 388 int snd_emu10k1_done(struct snd_emu10k1 *emu) 389 { 390 int ch; 391 392 outl(0, emu->port + INTE); 393 394 /* 395 * Shutdown the chip 396 */ 397 for (ch = 0; ch < NUM_G; ch++) 398 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0); 399 for (ch = 0; ch < NUM_G; ch++) { 400 snd_emu10k1_ptr_write(emu, VTFT, ch, 0); 401 snd_emu10k1_ptr_write(emu, CVCF, ch, 0); 402 snd_emu10k1_ptr_write(emu, PTRX, ch, 0); 403 snd_emu10k1_ptr_write(emu, CPF, ch, 0); 404 } 405 406 /* reset recording buffers */ 407 snd_emu10k1_ptr_write(emu, MICBS, 0, 0); 408 snd_emu10k1_ptr_write(emu, MICBA, 0, 0); 409 snd_emu10k1_ptr_write(emu, FXBS, 0, 0); 410 snd_emu10k1_ptr_write(emu, FXBA, 0, 0); 411 snd_emu10k1_ptr_write(emu, FXWC, 0, 0); 412 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE); 413 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0); 414 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K); 415 snd_emu10k1_ptr_write(emu, TCB, 0, 0); 416 if (emu->audigy) 417 snd_emu10k1_ptr_write(emu, A_DBG, 0, A_DBG_SINGLE_STEP); 418 else 419 snd_emu10k1_ptr_write(emu, DBG, 0, EMU10K1_DBG_SINGLE_STEP); 420 421 /* disable channel interrupt */ 422 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0); 423 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0); 424 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0); 425 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0); 426 427 /* disable audio and lock cache */ 428 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG); 429 snd_emu10k1_ptr_write(emu, PTB, 0, 0); 430 431 return 0; 432 } 433 434 /************************************************************************* 435 * ECARD functional implementation 436 *************************************************************************/ 437 438 /* In A1 Silicon, these bits are in the HC register */ 439 #define HOOKN_BIT (1L << 12) 440 #define HANDN_BIT (1L << 11) 441 #define PULSEN_BIT (1L << 10) 442 443 #define EC_GDI1 (1 << 13) 444 #define EC_GDI0 (1 << 14) 445 446 #define EC_NUM_CONTROL_BITS 20 447 448 #define EC_AC3_DATA_SELN 0x0001L 449 #define EC_EE_DATA_SEL 0x0002L 450 #define EC_EE_CNTRL_SELN 0x0004L 451 #define EC_EECLK 0x0008L 452 #define EC_EECS 0x0010L 453 #define EC_EESDO 0x0020L 454 #define EC_TRIM_CSN 0x0040L 455 #define EC_TRIM_SCLK 0x0080L 456 #define EC_TRIM_SDATA 0x0100L 457 #define EC_TRIM_MUTEN 0x0200L 458 #define EC_ADCCAL 0x0400L 459 #define EC_ADCRSTN 0x0800L 460 #define EC_DACCAL 0x1000L 461 #define EC_DACMUTEN 0x2000L 462 #define EC_LEDN 0x4000L 463 464 #define EC_SPDIF0_SEL_SHIFT 15 465 #define EC_SPDIF1_SEL_SHIFT 17 466 #define EC_SPDIF0_SEL_MASK (0x3L << EC_SPDIF0_SEL_SHIFT) 467 #define EC_SPDIF1_SEL_MASK (0x7L << EC_SPDIF1_SEL_SHIFT) 468 #define EC_SPDIF0_SELECT(_x) (((_x) << EC_SPDIF0_SEL_SHIFT) & EC_SPDIF0_SEL_MASK) 469 #define EC_SPDIF1_SELECT(_x) (((_x) << EC_SPDIF1_SEL_SHIFT) & EC_SPDIF1_SEL_MASK) 470 #define EC_CURRENT_PROM_VERSION 0x01 /* Self-explanatory. This should 471 * be incremented any time the EEPROM's 472 * format is changed. */ 473 474 #define EC_EEPROM_SIZE 0x40 /* ECARD EEPROM has 64 16-bit words */ 475 476 /* Addresses for special values stored in to EEPROM */ 477 #define EC_PROM_VERSION_ADDR 0x20 /* Address of the current prom version */ 478 #define EC_BOARDREV0_ADDR 0x21 /* LSW of board rev */ 479 #define EC_BOARDREV1_ADDR 0x22 /* MSW of board rev */ 480 481 #define EC_LAST_PROMFILE_ADDR 0x2f 482 483 #define EC_SERIALNUM_ADDR 0x30 /* First word of serial number. The 484 * can be up to 30 characters in length 485 * and is stored as a NULL-terminated 486 * ASCII string. Any unused bytes must be 487 * filled with zeros */ 488 #define EC_CHECKSUM_ADDR 0x3f /* Location at which checksum is stored */ 489 490 491 /* Most of this stuff is pretty self-evident. According to the hardware 492 * dudes, we need to leave the ADCCAL bit low in order to avoid a DC 493 * offset problem. Weird. 494 */ 495 #define EC_RAW_RUN_MODE (EC_DACMUTEN | EC_ADCRSTN | EC_TRIM_MUTEN | \ 496 EC_TRIM_CSN) 497 498 499 #define EC_DEFAULT_ADC_GAIN 0xC4C4 500 #define EC_DEFAULT_SPDIF0_SEL 0x0 501 #define EC_DEFAULT_SPDIF1_SEL 0x4 502 503 /************************************************************************** 504 * @func Clock bits into the Ecard's control latch. The Ecard uses a 505 * control latch will is loaded bit-serially by toggling the Modem control 506 * lines from function 2 on the E8010. This function hides these details 507 * and presents the illusion that we are actually writing to a distinct 508 * register. 509 */ 510 511 static void snd_emu10k1_ecard_write(struct snd_emu10k1 *emu, unsigned int value) 512 { 513 unsigned short count; 514 unsigned int data; 515 unsigned long hc_port; 516 unsigned int hc_value; 517 518 hc_port = emu->port + HCFG; 519 hc_value = inl(hc_port) & ~(HOOKN_BIT | HANDN_BIT | PULSEN_BIT); 520 outl(hc_value, hc_port); 521 522 for (count = 0; count < EC_NUM_CONTROL_BITS; count++) { 523 524 /* Set up the value */ 525 data = ((value & 0x1) ? PULSEN_BIT : 0); 526 value >>= 1; 527 528 outl(hc_value | data, hc_port); 529 530 /* Clock the shift register */ 531 outl(hc_value | data | HANDN_BIT, hc_port); 532 outl(hc_value | data, hc_port); 533 } 534 535 /* Latch the bits */ 536 outl(hc_value | HOOKN_BIT, hc_port); 537 outl(hc_value, hc_port); 538 } 539 540 /************************************************************************** 541 * @func Set the gain of the ECARD's CS3310 Trim/gain controller. The 542 * trim value consists of a 16bit value which is composed of two 543 * 8 bit gain/trim values, one for the left channel and one for the 544 * right channel. The following table maps from the Gain/Attenuation 545 * value in decibels into the corresponding bit pattern for a single 546 * channel. 547 */ 548 549 static void snd_emu10k1_ecard_setadcgain(struct snd_emu10k1 *emu, 550 unsigned short gain) 551 { 552 unsigned int bit; 553 554 /* Enable writing to the TRIM registers */ 555 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN); 556 557 /* Do it again to insure that we meet hold time requirements */ 558 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN); 559 560 for (bit = (1 << 15); bit; bit >>= 1) { 561 unsigned int value; 562 563 value = emu->ecard_ctrl & ~(EC_TRIM_CSN | EC_TRIM_SDATA); 564 565 if (gain & bit) 566 value |= EC_TRIM_SDATA; 567 568 /* Clock the bit */ 569 snd_emu10k1_ecard_write(emu, value); 570 snd_emu10k1_ecard_write(emu, value | EC_TRIM_SCLK); 571 snd_emu10k1_ecard_write(emu, value); 572 } 573 574 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl); 575 } 576 577 static int snd_emu10k1_ecard_init(struct snd_emu10k1 *emu) 578 { 579 unsigned int hc_value; 580 581 /* Set up the initial settings */ 582 emu->ecard_ctrl = EC_RAW_RUN_MODE | 583 EC_SPDIF0_SELECT(EC_DEFAULT_SPDIF0_SEL) | 584 EC_SPDIF1_SELECT(EC_DEFAULT_SPDIF1_SEL); 585 586 /* Step 0: Set the codec type in the hardware control register 587 * and enable audio output */ 588 hc_value = inl(emu->port + HCFG); 589 outl(hc_value | HCFG_AUDIOENABLE | HCFG_CODECFORMAT_I2S, emu->port + HCFG); 590 inl(emu->port + HCFG); 591 592 /* Step 1: Turn off the led and deassert TRIM_CS */ 593 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN); 594 595 /* Step 2: Calibrate the ADC and DAC */ 596 snd_emu10k1_ecard_write(emu, EC_DACCAL | EC_LEDN | EC_TRIM_CSN); 597 598 /* Step 3: Wait for awhile; XXX We can't get away with this 599 * under a real operating system; we'll need to block and wait that 600 * way. */ 601 snd_emu10k1_wait(emu, 48000); 602 603 /* Step 4: Switch off the DAC and ADC calibration. Note 604 * That ADC_CAL is actually an inverted signal, so we assert 605 * it here to stop calibration. */ 606 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN); 607 608 /* Step 4: Switch into run mode */ 609 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl); 610 611 /* Step 5: Set the analog input gain */ 612 snd_emu10k1_ecard_setadcgain(emu, EC_DEFAULT_ADC_GAIN); 613 614 return 0; 615 } 616 617 static int snd_emu10k1_cardbus_init(struct snd_emu10k1 *emu) 618 { 619 unsigned long special_port; 620 __always_unused unsigned int value; 621 622 /* Special initialisation routine 623 * before the rest of the IO-Ports become active. 624 */ 625 special_port = emu->port + 0x38; 626 value = inl(special_port); 627 outl(0x00d00000, special_port); 628 value = inl(special_port); 629 outl(0x00d00001, special_port); 630 value = inl(special_port); 631 outl(0x00d0005f, special_port); 632 value = inl(special_port); 633 outl(0x00d0007f, special_port); 634 value = inl(special_port); 635 outl(0x0090007f, special_port); 636 value = inl(special_port); 637 638 snd_emu10k1_ptr20_write(emu, TINA2_VOLUME, 0, 0xfefefefe); /* Defaults to 0x30303030 */ 639 /* Delay to give time for ADC chip to switch on. It needs 113ms */ 640 msleep(200); 641 return 0; 642 } 643 644 static int snd_emu1010_load_firmware_entry(struct snd_emu10k1 *emu, 645 const struct firmware *fw_entry) 646 { 647 int n, i; 648 u16 reg; 649 u8 value; 650 __always_unused u16 write_post; 651 unsigned long flags; 652 653 if (!fw_entry) 654 return -EIO; 655 656 /* The FPGA is a Xilinx Spartan IIE XC2S50E */ 657 /* On E-MU 0404b it is a Xilinx Spartan III XC3S50 */ 658 /* GPIO7 -> FPGA PGMN 659 * GPIO6 -> FPGA CCLK 660 * GPIO5 -> FPGA DIN 661 * FPGA CONFIG OFF -> FPGA PGMN 662 */ 663 spin_lock_irqsave(&emu->emu_lock, flags); 664 outw(0x00, emu->port + A_GPIO); /* Set PGMN low for 100uS. */ 665 write_post = inw(emu->port + A_GPIO); 666 udelay(100); 667 outw(0x80, emu->port + A_GPIO); /* Leave bit 7 set during netlist setup. */ 668 write_post = inw(emu->port + A_GPIO); 669 udelay(100); /* Allow FPGA memory to clean */ 670 for (n = 0; n < fw_entry->size; n++) { 671 value = fw_entry->data[n]; 672 for (i = 0; i < 8; i++) { 673 reg = 0x80; 674 if (value & 0x1) 675 reg = reg | 0x20; 676 value = value >> 1; 677 outw(reg, emu->port + A_GPIO); 678 write_post = inw(emu->port + A_GPIO); 679 outw(reg | 0x40, emu->port + A_GPIO); 680 write_post = inw(emu->port + A_GPIO); 681 } 682 } 683 /* After programming, set GPIO bit 4 high again. */ 684 outw(0x10, emu->port + A_GPIO); 685 write_post = inw(emu->port + A_GPIO); 686 spin_unlock_irqrestore(&emu->emu_lock, flags); 687 688 return 0; 689 } 690 691 /* firmware file names, per model, init-fw and dock-fw (optional) */ 692 static const char * const firmware_names[5][2] = { 693 [EMU_MODEL_EMU1010] = { 694 HANA_FILENAME, DOCK_FILENAME 695 }, 696 [EMU_MODEL_EMU1010B] = { 697 EMU1010B_FILENAME, MICRO_DOCK_FILENAME 698 }, 699 [EMU_MODEL_EMU1616] = { 700 EMU1010_NOTEBOOK_FILENAME, MICRO_DOCK_FILENAME 701 }, 702 [EMU_MODEL_EMU0404] = { 703 EMU0404_FILENAME, NULL 704 }, 705 }; 706 707 static int snd_emu1010_load_firmware(struct snd_emu10k1 *emu, int dock, 708 const struct firmware **fw) 709 { 710 const char *filename; 711 int err; 712 713 if (!*fw) { 714 filename = firmware_names[emu->card_capabilities->emu_model][dock]; 715 if (!filename) 716 return 0; 717 err = request_firmware(fw, filename, &emu->pci->dev); 718 if (err) 719 return err; 720 } 721 722 return snd_emu1010_load_firmware_entry(emu, *fw); 723 } 724 725 static void emu1010_firmware_work(struct work_struct *work) 726 { 727 struct snd_emu10k1 *emu; 728 u32 tmp, tmp2, reg; 729 int err; 730 731 emu = container_of(work, struct snd_emu10k1, 732 emu1010.firmware_work.work); 733 if (emu->card->shutdown) 734 return; 735 #ifdef CONFIG_PM_SLEEP 736 if (emu->suspend) 737 return; 738 #endif 739 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &tmp); /* IRQ Status */ 740 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®); /* OPTIONS: Which cards are attached to the EMU */ 741 if (reg & EMU_HANA_OPTION_DOCK_OFFLINE) { 742 /* Audio Dock attached */ 743 /* Return to Audio Dock programming mode */ 744 dev_info(emu->card->dev, 745 "emu1010: Loading Audio Dock Firmware\n"); 746 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 747 EMU_HANA_FPGA_CONFIG_AUDIODOCK); 748 err = snd_emu1010_load_firmware(emu, 1, &emu->dock_fw); 749 if (err < 0) 750 goto next; 751 752 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0); 753 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &tmp); 754 dev_info(emu->card->dev, 755 "emu1010: EMU_HANA+DOCK_IRQ_STATUS = 0x%x\n", tmp); 756 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */ 757 snd_emu1010_fpga_read(emu, EMU_HANA_ID, &tmp); 758 dev_info(emu->card->dev, 759 "emu1010: EMU_HANA+DOCK_ID = 0x%x\n", tmp); 760 if ((tmp & 0x1f) != 0x15) { 761 /* FPGA failed to be programmed */ 762 dev_info(emu->card->dev, 763 "emu1010: Loading Audio Dock Firmware file failed, reg = 0x%x\n", 764 tmp); 765 goto next; 766 } 767 dev_info(emu->card->dev, 768 "emu1010: Audio Dock Firmware loaded\n"); 769 snd_emu1010_fpga_read(emu, EMU_DOCK_MAJOR_REV, &tmp); 770 snd_emu1010_fpga_read(emu, EMU_DOCK_MINOR_REV, &tmp2); 771 dev_info(emu->card->dev, "Audio Dock ver: %u.%u\n", tmp, tmp2); 772 /* Sync clocking between 1010 and Dock */ 773 /* Allow DLL to settle */ 774 msleep(10); 775 /* Unmute all. Default is muted after a firmware load */ 776 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE); 777 } else if (!reg && emu->emu1010.last_reg) { 778 /* Audio Dock removed */ 779 dev_info(emu->card->dev, "emu1010: Audio Dock detached\n"); 780 /* The hardware auto-mutes all, so we unmute again */ 781 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE); 782 } 783 784 next: 785 emu->emu1010.last_reg = reg; 786 if (!emu->card->shutdown) 787 schedule_delayed_work(&emu->emu1010.firmware_work, 788 msecs_to_jiffies(1000)); 789 } 790 791 /* 792 * Current status of the driver: 793 * ---------------------------- 794 * * only 44.1/48kHz supported (the MS Win driver supports up to 192 kHz) 795 * * PCM device nb. 2: 796 * 16 x 16-bit playback - snd_emu10k1_fx8010_playback_ops 797 * 16 x 32-bit capture - snd_emu10k1_capture_efx_ops 798 */ 799 static int snd_emu10k1_emu1010_init(struct snd_emu10k1 *emu) 800 { 801 unsigned int i; 802 u32 tmp, tmp2, reg; 803 int err; 804 805 dev_info(emu->card->dev, "emu1010: Special config.\n"); 806 807 /* Mute, and disable audio and lock cache, just in case. 808 * Proper init follows in snd_emu10k1_init(). */ 809 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG); 810 811 /* Disable 48Volt power to Audio Dock */ 812 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0); 813 814 /* ID, should read & 0x7f = 0x55. (Bit 7 is the IRQ bit) */ 815 snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®); 816 dev_dbg(emu->card->dev, "reg1 = 0x%x\n", reg); 817 if ((reg & 0x3f) == 0x15) { 818 /* FPGA netlist already present so clear it */ 819 /* Return to programming mode */ 820 821 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, EMU_HANA_FPGA_CONFIG_HANA); 822 } 823 snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®); 824 dev_dbg(emu->card->dev, "reg2 = 0x%x\n", reg); 825 if ((reg & 0x3f) == 0x15) { 826 /* FPGA failed to return to programming mode */ 827 dev_info(emu->card->dev, 828 "emu1010: FPGA failed to return to programming mode\n"); 829 return -ENODEV; 830 } 831 dev_info(emu->card->dev, "emu1010: EMU_HANA_ID = 0x%x\n", reg); 832 833 err = snd_emu1010_load_firmware(emu, 0, &emu->firmware); 834 if (err < 0) { 835 dev_info(emu->card->dev, "emu1010: Loading Firmware failed\n"); 836 return err; 837 } 838 839 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */ 840 snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®); 841 if ((reg & 0x3f) != 0x15) { 842 /* FPGA failed to be programmed */ 843 dev_info(emu->card->dev, 844 "emu1010: Loading Hana Firmware file failed, reg = 0x%x\n", 845 reg); 846 return -ENODEV; 847 } 848 849 dev_info(emu->card->dev, "emu1010: Hana Firmware loaded\n"); 850 snd_emu1010_fpga_read(emu, EMU_HANA_MAJOR_REV, &tmp); 851 snd_emu1010_fpga_read(emu, EMU_HANA_MINOR_REV, &tmp2); 852 dev_info(emu->card->dev, "emu1010: Hana version: %u.%u\n", tmp, tmp2); 853 /* Enable 48Volt power to Audio Dock */ 854 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, EMU_HANA_DOCK_PWR_ON); 855 856 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®); 857 dev_info(emu->card->dev, "emu1010: Card options = 0x%x\n", reg); 858 /* Optical -> ADAT I/O */ 859 emu->emu1010.optical_in = 1; /* IN_ADAT */ 860 emu->emu1010.optical_out = 1; /* OUT_ADAT */ 861 tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : EMU_HANA_OPTICAL_IN_SPDIF) | 862 (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : EMU_HANA_OPTICAL_OUT_SPDIF); 863 snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp); 864 /* Set no attenuation on Audio Dock pads. */ 865 emu->emu1010.adc_pads = 0x00; 866 snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, emu->emu1010.adc_pads); 867 /* Unmute Audio dock DACs, Headphone source DAC-4. */ 868 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, EMU_HANA_DOCK_PHONES_192_DAC4); 869 /* DAC PADs. */ 870 emu->emu1010.dac_pads = EMU_HANA_DOCK_DAC_PAD1 | EMU_HANA_DOCK_DAC_PAD2 | 871 EMU_HANA_DOCK_DAC_PAD3 | EMU_HANA_DOCK_DAC_PAD4; 872 snd_emu1010_fpga_write(emu, EMU_HANA_DAC_PADS, emu->emu1010.dac_pads); 873 /* SPDIF Format. Set Consumer mode, 24bit, copy enable */ 874 snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, EMU_HANA_SPDIF_MODE_RX_INVALID); 875 /* MIDI routing */ 876 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, EMU_HANA_MIDI_INA_FROM_HAMOA | EMU_HANA_MIDI_INB_FROM_DOCK2); 877 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, EMU_HANA_MIDI_OUT_DOCK2 | EMU_HANA_MIDI_OUT_SYNC2); 878 /* IRQ Enable: All on */ 879 /* snd_emu1010_fpga_write(emu, EMU_HANA_IRQ_ENABLE, 0x0f); */ 880 /* IRQ Enable: All off */ 881 snd_emu1010_fpga_write(emu, EMU_HANA_IRQ_ENABLE, 0x00); 882 883 emu->emu1010.internal_clock = 1; /* 48000 */ 884 /* Default WCLK set to 48kHz. */ 885 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, EMU_HANA_DEFCLOCK_48K); 886 /* Word Clock source, Internal 48kHz x1 */ 887 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K); 888 /* snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X); */ 889 /* Audio Dock LEDs. */ 890 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, EMU_HANA_DOCK_LEDS_2_LOCK | EMU_HANA_DOCK_LEDS_2_48K); 891 892 #if 0 893 /* For 96kHz */ 894 snd_emu1010_fpga_link_dst_src_write(emu, 895 EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1); 896 snd_emu1010_fpga_link_dst_src_write(emu, 897 EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1); 898 snd_emu1010_fpga_link_dst_src_write(emu, 899 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT2); 900 snd_emu1010_fpga_link_dst_src_write(emu, 901 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT2); 902 #endif 903 #if 0 904 /* For 192kHz */ 905 snd_emu1010_fpga_link_dst_src_write(emu, 906 EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1); 907 snd_emu1010_fpga_link_dst_src_write(emu, 908 EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1); 909 snd_emu1010_fpga_link_dst_src_write(emu, 910 EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2); 911 snd_emu1010_fpga_link_dst_src_write(emu, 912 EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_RIGHT2); 913 snd_emu1010_fpga_link_dst_src_write(emu, 914 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT3); 915 snd_emu1010_fpga_link_dst_src_write(emu, 916 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT3); 917 snd_emu1010_fpga_link_dst_src_write(emu, 918 EMU_DST_ALICE2_EMU32_6, EMU_SRC_HAMOA_ADC_LEFT4); 919 snd_emu1010_fpga_link_dst_src_write(emu, 920 EMU_DST_ALICE2_EMU32_7, EMU_SRC_HAMOA_ADC_RIGHT4); 921 #endif 922 #if 1 923 /* For 48kHz */ 924 snd_emu1010_fpga_link_dst_src_write(emu, 925 EMU_DST_ALICE2_EMU32_0, EMU_SRC_DOCK_MIC_A1); 926 snd_emu1010_fpga_link_dst_src_write(emu, 927 EMU_DST_ALICE2_EMU32_1, EMU_SRC_DOCK_MIC_B1); 928 snd_emu1010_fpga_link_dst_src_write(emu, 929 EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2); 930 snd_emu1010_fpga_link_dst_src_write(emu, 931 EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_LEFT2); 932 snd_emu1010_fpga_link_dst_src_write(emu, 933 EMU_DST_ALICE2_EMU32_4, EMU_SRC_DOCK_ADC1_LEFT1); 934 snd_emu1010_fpga_link_dst_src_write(emu, 935 EMU_DST_ALICE2_EMU32_5, EMU_SRC_DOCK_ADC1_RIGHT1); 936 snd_emu1010_fpga_link_dst_src_write(emu, 937 EMU_DST_ALICE2_EMU32_6, EMU_SRC_DOCK_ADC2_LEFT1); 938 snd_emu1010_fpga_link_dst_src_write(emu, 939 EMU_DST_ALICE2_EMU32_7, EMU_SRC_DOCK_ADC2_RIGHT1); 940 /* Pavel Hofman - setting defaults for 8 more capture channels 941 * Defaults only, users will set their own values anyways, let's 942 * just copy/paste. 943 */ 944 945 snd_emu1010_fpga_link_dst_src_write(emu, 946 EMU_DST_ALICE2_EMU32_8, EMU_SRC_DOCK_MIC_A1); 947 snd_emu1010_fpga_link_dst_src_write(emu, 948 EMU_DST_ALICE2_EMU32_9, EMU_SRC_DOCK_MIC_B1); 949 snd_emu1010_fpga_link_dst_src_write(emu, 950 EMU_DST_ALICE2_EMU32_A, EMU_SRC_HAMOA_ADC_LEFT2); 951 snd_emu1010_fpga_link_dst_src_write(emu, 952 EMU_DST_ALICE2_EMU32_B, EMU_SRC_HAMOA_ADC_LEFT2); 953 snd_emu1010_fpga_link_dst_src_write(emu, 954 EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_ADC1_LEFT1); 955 snd_emu1010_fpga_link_dst_src_write(emu, 956 EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_ADC1_RIGHT1); 957 snd_emu1010_fpga_link_dst_src_write(emu, 958 EMU_DST_ALICE2_EMU32_E, EMU_SRC_DOCK_ADC2_LEFT1); 959 snd_emu1010_fpga_link_dst_src_write(emu, 960 EMU_DST_ALICE2_EMU32_F, EMU_SRC_DOCK_ADC2_RIGHT1); 961 #endif 962 #if 0 963 /* Original */ 964 snd_emu1010_fpga_link_dst_src_write(emu, 965 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HANA_ADAT); 966 snd_emu1010_fpga_link_dst_src_write(emu, 967 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HANA_ADAT + 1); 968 snd_emu1010_fpga_link_dst_src_write(emu, 969 EMU_DST_ALICE2_EMU32_6, EMU_SRC_HANA_ADAT + 2); 970 snd_emu1010_fpga_link_dst_src_write(emu, 971 EMU_DST_ALICE2_EMU32_7, EMU_SRC_HANA_ADAT + 3); 972 snd_emu1010_fpga_link_dst_src_write(emu, 973 EMU_DST_ALICE2_EMU32_8, EMU_SRC_HANA_ADAT + 4); 974 snd_emu1010_fpga_link_dst_src_write(emu, 975 EMU_DST_ALICE2_EMU32_9, EMU_SRC_HANA_ADAT + 5); 976 snd_emu1010_fpga_link_dst_src_write(emu, 977 EMU_DST_ALICE2_EMU32_A, EMU_SRC_HANA_ADAT + 6); 978 snd_emu1010_fpga_link_dst_src_write(emu, 979 EMU_DST_ALICE2_EMU32_B, EMU_SRC_HANA_ADAT + 7); 980 snd_emu1010_fpga_link_dst_src_write(emu, 981 EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_MIC_A1); 982 snd_emu1010_fpga_link_dst_src_write(emu, 983 EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_MIC_B1); 984 snd_emu1010_fpga_link_dst_src_write(emu, 985 EMU_DST_ALICE2_EMU32_E, EMU_SRC_HAMOA_ADC_LEFT2); 986 snd_emu1010_fpga_link_dst_src_write(emu, 987 EMU_DST_ALICE2_EMU32_F, EMU_SRC_HAMOA_ADC_LEFT2); 988 #endif 989 for (i = 0; i < 0x20; i++) { 990 /* AudioDock Elink <- Silence */ 991 snd_emu1010_fpga_link_dst_src_write(emu, 0x0100 + i, EMU_SRC_SILENCE); 992 } 993 for (i = 0; i < 4; i++) { 994 /* Hana SPDIF Out <- Silence */ 995 snd_emu1010_fpga_link_dst_src_write(emu, 0x0200 + i, EMU_SRC_SILENCE); 996 } 997 for (i = 0; i < 7; i++) { 998 /* Hamoa DAC <- Silence */ 999 snd_emu1010_fpga_link_dst_src_write(emu, 0x0300 + i, EMU_SRC_SILENCE); 1000 } 1001 for (i = 0; i < 7; i++) { 1002 /* Hana ADAT Out <- Silence */ 1003 snd_emu1010_fpga_link_dst_src_write(emu, EMU_DST_HANA_ADAT + i, EMU_SRC_SILENCE); 1004 } 1005 snd_emu1010_fpga_link_dst_src_write(emu, 1006 EMU_DST_ALICE_I2S0_LEFT, EMU_SRC_DOCK_ADC1_LEFT1); 1007 snd_emu1010_fpga_link_dst_src_write(emu, 1008 EMU_DST_ALICE_I2S0_RIGHT, EMU_SRC_DOCK_ADC1_RIGHT1); 1009 snd_emu1010_fpga_link_dst_src_write(emu, 1010 EMU_DST_ALICE_I2S1_LEFT, EMU_SRC_DOCK_ADC2_LEFT1); 1011 snd_emu1010_fpga_link_dst_src_write(emu, 1012 EMU_DST_ALICE_I2S1_RIGHT, EMU_SRC_DOCK_ADC2_RIGHT1); 1013 snd_emu1010_fpga_link_dst_src_write(emu, 1014 EMU_DST_ALICE_I2S2_LEFT, EMU_SRC_DOCK_ADC3_LEFT1); 1015 snd_emu1010_fpga_link_dst_src_write(emu, 1016 EMU_DST_ALICE_I2S2_RIGHT, EMU_SRC_DOCK_ADC3_RIGHT1); 1017 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE); 1018 1019 #if 0 1020 snd_emu1010_fpga_link_dst_src_write(emu, 1021 EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32B + 2); /* ALICE2 bus 0xa2 */ 1022 snd_emu1010_fpga_link_dst_src_write(emu, 1023 EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32B + 3); /* ALICE2 bus 0xa3 */ 1024 snd_emu1010_fpga_link_dst_src_write(emu, 1025 EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 2); /* ALICE2 bus 0xb2 */ 1026 snd_emu1010_fpga_link_dst_src_write(emu, 1027 EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 3); /* ALICE2 bus 0xb3 */ 1028 #endif 1029 /* Default outputs */ 1030 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616) { 1031 /* 1616(M) cardbus default outputs */ 1032 /* ALICE2 bus 0xa0 */ 1033 snd_emu1010_fpga_link_dst_src_write(emu, 1034 EMU_DST_DOCK_DAC1_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1035 emu->emu1010.output_source[0] = 17; 1036 snd_emu1010_fpga_link_dst_src_write(emu, 1037 EMU_DST_DOCK_DAC1_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1038 emu->emu1010.output_source[1] = 18; 1039 snd_emu1010_fpga_link_dst_src_write(emu, 1040 EMU_DST_DOCK_DAC2_LEFT1, EMU_SRC_ALICE_EMU32A + 2); 1041 emu->emu1010.output_source[2] = 19; 1042 snd_emu1010_fpga_link_dst_src_write(emu, 1043 EMU_DST_DOCK_DAC2_RIGHT1, EMU_SRC_ALICE_EMU32A + 3); 1044 emu->emu1010.output_source[3] = 20; 1045 snd_emu1010_fpga_link_dst_src_write(emu, 1046 EMU_DST_DOCK_DAC3_LEFT1, EMU_SRC_ALICE_EMU32A + 4); 1047 emu->emu1010.output_source[4] = 21; 1048 snd_emu1010_fpga_link_dst_src_write(emu, 1049 EMU_DST_DOCK_DAC3_RIGHT1, EMU_SRC_ALICE_EMU32A + 5); 1050 emu->emu1010.output_source[5] = 22; 1051 /* ALICE2 bus 0xa0 */ 1052 snd_emu1010_fpga_link_dst_src_write(emu, 1053 EMU_DST_MANA_DAC_LEFT, EMU_SRC_ALICE_EMU32A + 0); 1054 emu->emu1010.output_source[16] = 17; 1055 snd_emu1010_fpga_link_dst_src_write(emu, 1056 EMU_DST_MANA_DAC_RIGHT, EMU_SRC_ALICE_EMU32A + 1); 1057 emu->emu1010.output_source[17] = 18; 1058 } else { 1059 /* ALICE2 bus 0xa0 */ 1060 snd_emu1010_fpga_link_dst_src_write(emu, 1061 EMU_DST_DOCK_DAC1_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1062 emu->emu1010.output_source[0] = 21; 1063 snd_emu1010_fpga_link_dst_src_write(emu, 1064 EMU_DST_DOCK_DAC1_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1065 emu->emu1010.output_source[1] = 22; 1066 snd_emu1010_fpga_link_dst_src_write(emu, 1067 EMU_DST_DOCK_DAC2_LEFT1, EMU_SRC_ALICE_EMU32A + 2); 1068 emu->emu1010.output_source[2] = 23; 1069 snd_emu1010_fpga_link_dst_src_write(emu, 1070 EMU_DST_DOCK_DAC2_RIGHT1, EMU_SRC_ALICE_EMU32A + 3); 1071 emu->emu1010.output_source[3] = 24; 1072 snd_emu1010_fpga_link_dst_src_write(emu, 1073 EMU_DST_DOCK_DAC3_LEFT1, EMU_SRC_ALICE_EMU32A + 4); 1074 emu->emu1010.output_source[4] = 25; 1075 snd_emu1010_fpga_link_dst_src_write(emu, 1076 EMU_DST_DOCK_DAC3_RIGHT1, EMU_SRC_ALICE_EMU32A + 5); 1077 emu->emu1010.output_source[5] = 26; 1078 snd_emu1010_fpga_link_dst_src_write(emu, 1079 EMU_DST_DOCK_DAC4_LEFT1, EMU_SRC_ALICE_EMU32A + 6); 1080 emu->emu1010.output_source[6] = 27; 1081 snd_emu1010_fpga_link_dst_src_write(emu, 1082 EMU_DST_DOCK_DAC4_RIGHT1, EMU_SRC_ALICE_EMU32A + 7); 1083 emu->emu1010.output_source[7] = 28; 1084 /* ALICE2 bus 0xa0 */ 1085 snd_emu1010_fpga_link_dst_src_write(emu, 1086 EMU_DST_DOCK_PHONES_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1087 emu->emu1010.output_source[8] = 21; 1088 snd_emu1010_fpga_link_dst_src_write(emu, 1089 EMU_DST_DOCK_PHONES_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1090 emu->emu1010.output_source[9] = 22; 1091 /* ALICE2 bus 0xa0 */ 1092 snd_emu1010_fpga_link_dst_src_write(emu, 1093 EMU_DST_DOCK_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1094 emu->emu1010.output_source[10] = 21; 1095 snd_emu1010_fpga_link_dst_src_write(emu, 1096 EMU_DST_DOCK_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1097 emu->emu1010.output_source[11] = 22; 1098 /* ALICE2 bus 0xa0 */ 1099 snd_emu1010_fpga_link_dst_src_write(emu, 1100 EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1101 emu->emu1010.output_source[12] = 21; 1102 snd_emu1010_fpga_link_dst_src_write(emu, 1103 EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1104 emu->emu1010.output_source[13] = 22; 1105 /* ALICE2 bus 0xa0 */ 1106 snd_emu1010_fpga_link_dst_src_write(emu, 1107 EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1108 emu->emu1010.output_source[14] = 21; 1109 snd_emu1010_fpga_link_dst_src_write(emu, 1110 EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1111 emu->emu1010.output_source[15] = 22; 1112 /* ALICE2 bus 0xa0 */ 1113 snd_emu1010_fpga_link_dst_src_write(emu, 1114 EMU_DST_HANA_ADAT, EMU_SRC_ALICE_EMU32A + 0); 1115 emu->emu1010.output_source[16] = 21; 1116 snd_emu1010_fpga_link_dst_src_write(emu, 1117 EMU_DST_HANA_ADAT + 1, EMU_SRC_ALICE_EMU32A + 1); 1118 emu->emu1010.output_source[17] = 22; 1119 snd_emu1010_fpga_link_dst_src_write(emu, 1120 EMU_DST_HANA_ADAT + 2, EMU_SRC_ALICE_EMU32A + 2); 1121 emu->emu1010.output_source[18] = 23; 1122 snd_emu1010_fpga_link_dst_src_write(emu, 1123 EMU_DST_HANA_ADAT + 3, EMU_SRC_ALICE_EMU32A + 3); 1124 emu->emu1010.output_source[19] = 24; 1125 snd_emu1010_fpga_link_dst_src_write(emu, 1126 EMU_DST_HANA_ADAT + 4, EMU_SRC_ALICE_EMU32A + 4); 1127 emu->emu1010.output_source[20] = 25; 1128 snd_emu1010_fpga_link_dst_src_write(emu, 1129 EMU_DST_HANA_ADAT + 5, EMU_SRC_ALICE_EMU32A + 5); 1130 emu->emu1010.output_source[21] = 26; 1131 snd_emu1010_fpga_link_dst_src_write(emu, 1132 EMU_DST_HANA_ADAT + 6, EMU_SRC_ALICE_EMU32A + 6); 1133 emu->emu1010.output_source[22] = 27; 1134 snd_emu1010_fpga_link_dst_src_write(emu, 1135 EMU_DST_HANA_ADAT + 7, EMU_SRC_ALICE_EMU32A + 7); 1136 emu->emu1010.output_source[23] = 28; 1137 } 1138 1139 return 0; 1140 } 1141 /* 1142 * Create the EMU10K1 instance 1143 */ 1144 1145 #ifdef CONFIG_PM_SLEEP 1146 static int alloc_pm_buffer(struct snd_emu10k1 *emu); 1147 static void free_pm_buffer(struct snd_emu10k1 *emu); 1148 #endif 1149 1150 static void snd_emu10k1_free(struct snd_card *card) 1151 { 1152 struct snd_emu10k1 *emu = card->private_data; 1153 1154 if (emu->port) { /* avoid access to already used hardware */ 1155 snd_emu10k1_fx8010_tram_setup(emu, 0); 1156 snd_emu10k1_done(emu); 1157 snd_emu10k1_free_efx(emu); 1158 } 1159 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1010) { 1160 /* Disable 48Volt power to Audio Dock */ 1161 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0); 1162 } 1163 cancel_delayed_work_sync(&emu->emu1010.firmware_work); 1164 release_firmware(emu->firmware); 1165 release_firmware(emu->dock_fw); 1166 snd_util_memhdr_free(emu->memhdr); 1167 if (emu->silent_page.area) 1168 snd_dma_free_pages(&emu->silent_page); 1169 if (emu->ptb_pages.area) 1170 snd_dma_free_pages(&emu->ptb_pages); 1171 vfree(emu->page_ptr_table); 1172 vfree(emu->page_addr_table); 1173 #ifdef CONFIG_PM_SLEEP 1174 free_pm_buffer(emu); 1175 #endif 1176 } 1177 1178 static const struct snd_emu_chip_details emu_chip_details[] = { 1179 /* Audigy 5/Rx SB1550 */ 1180 /* Tested by michael@gernoth.net 28 Mar 2015 */ 1181 /* DSP: CA10300-IAT LF 1182 * DAC: Cirrus Logic CS4382-KQZ 1183 * ADC: Philips 1361T 1184 * AC97: Sigmatel STAC9750 1185 * CA0151: None 1186 */ 1187 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10241102, 1188 .driver = "Audigy2", .name = "SB Audigy 5/Rx [SB1550]", 1189 .id = "Audigy2", 1190 .emu10k2_chip = 1, 1191 .ca0108_chip = 1, 1192 .spk71 = 1, 1193 .adc_1361t = 1, /* 24 bit capture instead of 16bit */ 1194 .ac97_chip = 1}, 1195 /* Audigy4 (Not PRO) SB0610 */ 1196 /* Tested by James@superbug.co.uk 4th April 2006 */ 1197 /* A_IOCFG bits 1198 * Output 1199 * 0: ? 1200 * 1: ? 1201 * 2: ? 1202 * 3: 0 - Digital Out, 1 - Line in 1203 * 4: ? 1204 * 5: ? 1205 * 6: ? 1206 * 7: ? 1207 * Input 1208 * 8: ? 1209 * 9: ? 1210 * A: Green jack sense (Front) 1211 * B: ? 1212 * C: Black jack sense (Rear/Side Right) 1213 * D: Yellow jack sense (Center/LFE/Side Left) 1214 * E: ? 1215 * F: ? 1216 * 1217 * Digital Out/Line in switch using A_IOCFG bit 3 (0x08) 1218 * 0 - Digital Out 1219 * 1 - Line in 1220 */ 1221 /* Mic input not tested. 1222 * Analog CD input not tested 1223 * Digital Out not tested. 1224 * Line in working. 1225 * Audio output 5.1 working. Side outputs not working. 1226 */ 1227 /* DSP: CA10300-IAT LF 1228 * DAC: Cirrus Logic CS4382-KQZ 1229 * ADC: Philips 1361T 1230 * AC97: Sigmatel STAC9750 1231 * CA0151: None 1232 */ 1233 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10211102, 1234 .driver = "Audigy2", .name = "SB Audigy 4 [SB0610]", 1235 .id = "Audigy2", 1236 .emu10k2_chip = 1, 1237 .ca0108_chip = 1, 1238 .spk71 = 1, 1239 .adc_1361t = 1, /* 24 bit capture instead of 16bit */ 1240 .ac97_chip = 1} , 1241 /* Audigy 2 Value AC3 out does not work yet. 1242 * Need to find out how to turn off interpolators. 1243 */ 1244 /* Tested by James@superbug.co.uk 3rd July 2005 */ 1245 /* DSP: CA0108-IAT 1246 * DAC: CS4382-KQ 1247 * ADC: Philips 1361T 1248 * AC97: STAC9750 1249 * CA0151: None 1250 */ 1251 /* 1252 * A_IOCFG Input (GPIO) 1253 * 0x400 = Front analog jack plugged in. (Green socket) 1254 * 0x1000 = Rear analog jack plugged in. (Black socket) 1255 * 0x2000 = Center/LFE analog jack plugged in. (Orange socket) 1256 * A_IOCFG Output (GPIO) 1257 * 0x60 = Sound out of front Left. 1258 * Win sets it to 0xXX61 1259 */ 1260 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10011102, 1261 .driver = "Audigy2", .name = "SB Audigy 2 Value [SB0400]", 1262 .id = "Audigy2", 1263 .emu10k2_chip = 1, 1264 .ca0108_chip = 1, 1265 .spk71 = 1, 1266 .ac97_chip = 1} , 1267 /* Audigy 2 ZS Notebook Cardbus card.*/ 1268 /* Tested by James@superbug.co.uk 6th November 2006 */ 1269 /* Audio output 7.1/Headphones working. 1270 * Digital output working. (AC3 not checked, only PCM) 1271 * Audio Mic/Line inputs working. 1272 * Digital input not tested. 1273 */ 1274 /* DSP: Tina2 1275 * DAC: Wolfson WM8768/WM8568 1276 * ADC: Wolfson WM8775 1277 * AC97: None 1278 * CA0151: None 1279 */ 1280 /* Tested by James@superbug.co.uk 4th April 2006 */ 1281 /* A_IOCFG bits 1282 * Output 1283 * 0: Not Used 1284 * 1: 0 = Mute all the 7.1 channel out. 1 = unmute. 1285 * 2: Analog input 0 = line in, 1 = mic in 1286 * 3: Not Used 1287 * 4: Digital output 0 = off, 1 = on. 1288 * 5: Not Used 1289 * 6: Not Used 1290 * 7: Not Used 1291 * Input 1292 * All bits 1 (0x3fxx) means nothing plugged in. 1293 * 8-9: 0 = Line in/Mic, 2 = Optical in, 3 = Nothing. 1294 * A-B: 0 = Headphones, 2 = Optical out, 3 = Nothing. 1295 * C-D: 2 = Front/Rear/etc, 3 = nothing. 1296 * E-F: Always 0 1297 * 1298 */ 1299 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x20011102, 1300 .driver = "Audigy2", .name = "Audigy 2 ZS Notebook [SB0530]", 1301 .id = "Audigy2", 1302 .emu10k2_chip = 1, 1303 .ca0108_chip = 1, 1304 .ca_cardbus_chip = 1, 1305 .spi_dac = 1, 1306 .i2c_adc = 1, 1307 .spk71 = 1} , 1308 /* This is MAEM8950 "Mana" */ 1309 /* Attach MicroDock[M] to make it an E-MU 1616[m]. */ 1310 /* Does NOT support sync daughter card (obviously). */ 1311 /* Tested by James@superbug.co.uk 4th Nov 2007. */ 1312 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x42011102, 1313 .driver = "Audigy2", .name = "E-mu 1010 Notebook [MAEM8950]", 1314 .id = "EMU1010", 1315 .emu10k2_chip = 1, 1316 .ca0108_chip = 1, 1317 .ca_cardbus_chip = 1, 1318 .spk71 = 1 , 1319 .emu_model = EMU_MODEL_EMU1616}, 1320 /* Tested by James@superbug.co.uk 4th Nov 2007. */ 1321 /* This is MAEM8960 "Hana3", 0202 is MAEM8980 */ 1322 /* Attach 0202 daughter card to make it an E-MU 1212m, OR a 1323 * MicroDock[M] to make it an E-MU 1616[m]. */ 1324 /* Does NOT support sync daughter card. */ 1325 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40041102, 1326 .driver = "Audigy2", .name = "E-mu 1010b PCI [MAEM8960]", 1327 .id = "EMU1010", 1328 .emu10k2_chip = 1, 1329 .ca0108_chip = 1, 1330 .spk71 = 1, 1331 .emu_model = EMU_MODEL_EMU1010B}, /* EMU 1010 new revision */ 1332 /* Tested by Maxim Kachur <mcdebugger@duganet.ru> 17th Oct 2012. */ 1333 /* This is MAEM8986, 0202 is MAEM8980 */ 1334 /* Attach 0202 daughter card to make it an E-MU 1212m, OR a 1335 * MicroDockM to make it an E-MU 1616m. The non-m 1336 * version was never sold with this card, but should 1337 * still work. */ 1338 /* Does NOT support sync daughter card. */ 1339 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40071102, 1340 .driver = "Audigy2", .name = "E-mu 1010 PCIe [MAEM8986]", 1341 .id = "EMU1010", 1342 .emu10k2_chip = 1, 1343 .ca0108_chip = 1, 1344 .spk71 = 1, 1345 .emu_model = EMU_MODEL_EMU1010B}, /* EMU 1010 PCIe */ 1346 /* Tested by James@superbug.co.uk 8th July 2005. */ 1347 /* This is MAEM8810 "Hana", 0202 is MAEM8820 "Hamoa" */ 1348 /* Attach 0202 daughter card to make it an E-MU 1212m, OR an 1349 * AudioDock[M] to make it an E-MU 1820[m]. */ 1350 /* Supports sync daughter card. */ 1351 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40011102, 1352 .driver = "Audigy2", .name = "E-mu 1010 [MAEM8810]", 1353 .id = "EMU1010", 1354 .emu10k2_chip = 1, 1355 .ca0102_chip = 1, 1356 .spk71 = 1, 1357 .emu_model = EMU_MODEL_EMU1010}, /* EMU 1010 old revision */ 1358 /* This is MAEM8852 "HanaLiteLite" */ 1359 /* Supports sync daughter card. */ 1360 /* Tested by oswald.buddenhagen@gmx.de Mar 2023. */ 1361 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40021102, 1362 .driver = "Audigy2", .name = "E-mu 0404b PCI [MAEM8852]", 1363 .id = "EMU0404", 1364 .emu10k2_chip = 1, 1365 .ca0108_chip = 1, 1366 .spk71 = 1, 1367 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 new revision */ 1368 /* This is MAEM8850 "HanaLite" */ 1369 /* Supports sync daughter card. */ 1370 /* Tested by James@superbug.co.uk 20-3-2007. */ 1371 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40021102, 1372 .driver = "Audigy2", .name = "E-mu 0404 [MAEM8850]", 1373 .id = "EMU0404", 1374 .emu10k2_chip = 1, 1375 .ca0102_chip = 1, 1376 .spk71 = 1, 1377 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 */ 1378 /* EMU0404 PCIe */ 1379 /* Does NOT support sync daughter card. */ 1380 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40051102, 1381 .driver = "Audigy2", .name = "E-mu 0404 PCIe [MAEM8984]", 1382 .id = "EMU0404", 1383 .emu10k2_chip = 1, 1384 .ca0108_chip = 1, 1385 .spk71 = 1, 1386 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 PCIe ver_03 */ 1387 {.vendor = 0x1102, .device = 0x0008, 1388 .driver = "Audigy2", .name = "SB Audigy 2 Value [Unknown]", 1389 .id = "Audigy2", 1390 .emu10k2_chip = 1, 1391 .ca0108_chip = 1, 1392 .ac97_chip = 1} , 1393 /* Tested by James@superbug.co.uk 3rd July 2005 */ 1394 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20071102, 1395 .driver = "Audigy2", .name = "SB Audigy 4 PRO [SB0380]", 1396 .id = "Audigy2", 1397 .emu10k2_chip = 1, 1398 .ca0102_chip = 1, 1399 .ca0151_chip = 1, 1400 .spk71 = 1, 1401 .spdif_bug = 1, 1402 .ac97_chip = 1} , 1403 /* Tested by shane-alsa@cm.nu 5th Nov 2005 */ 1404 /* The 0x20061102 does have SB0350 written on it 1405 * Just like 0x20021102 1406 */ 1407 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20061102, 1408 .driver = "Audigy2", .name = "SB Audigy 2 [SB0350b]", 1409 .id = "Audigy2", 1410 .emu10k2_chip = 1, 1411 .ca0102_chip = 1, 1412 .ca0151_chip = 1, 1413 .spk71 = 1, 1414 .spdif_bug = 1, 1415 .invert_shared_spdif = 1, /* digital/analog switch swapped */ 1416 .ac97_chip = 1} , 1417 /* 0x20051102 also has SB0350 written on it, treated as Audigy 2 ZS by 1418 Creative's Windows driver */ 1419 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20051102, 1420 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0350a]", 1421 .id = "Audigy2", 1422 .emu10k2_chip = 1, 1423 .ca0102_chip = 1, 1424 .ca0151_chip = 1, 1425 .spk71 = 1, 1426 .spdif_bug = 1, 1427 .invert_shared_spdif = 1, /* digital/analog switch swapped */ 1428 .ac97_chip = 1} , 1429 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20021102, 1430 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0350]", 1431 .id = "Audigy2", 1432 .emu10k2_chip = 1, 1433 .ca0102_chip = 1, 1434 .ca0151_chip = 1, 1435 .spk71 = 1, 1436 .spdif_bug = 1, 1437 .invert_shared_spdif = 1, /* digital/analog switch swapped */ 1438 .ac97_chip = 1} , 1439 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20011102, 1440 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0360]", 1441 .id = "Audigy2", 1442 .emu10k2_chip = 1, 1443 .ca0102_chip = 1, 1444 .ca0151_chip = 1, 1445 .spk71 = 1, 1446 .spdif_bug = 1, 1447 .invert_shared_spdif = 1, /* digital/analog switch swapped */ 1448 .ac97_chip = 1} , 1449 /* Audigy 2 */ 1450 /* Tested by James@superbug.co.uk 3rd July 2005 */ 1451 /* DSP: CA0102-IAT 1452 * DAC: CS4382-KQ 1453 * ADC: Philips 1361T 1454 * AC97: STAC9721 1455 * CA0151: Yes 1456 */ 1457 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10071102, 1458 .driver = "Audigy2", .name = "SB Audigy 2 [SB0240]", 1459 .id = "Audigy2", 1460 .emu10k2_chip = 1, 1461 .ca0102_chip = 1, 1462 .ca0151_chip = 1, 1463 .spk71 = 1, 1464 .spdif_bug = 1, 1465 .adc_1361t = 1, /* 24 bit capture instead of 16bit */ 1466 .ac97_chip = 1} , 1467 /* Audigy 2 Platinum EX */ 1468 /* Win driver sets A_IOCFG output to 0x1c00 */ 1469 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10051102, 1470 .driver = "Audigy2", .name = "Audigy 2 Platinum EX [SB0280]", 1471 .id = "Audigy2", 1472 .emu10k2_chip = 1, 1473 .ca0102_chip = 1, 1474 .ca0151_chip = 1, 1475 .spk71 = 1, 1476 .spdif_bug = 1} , 1477 /* Dell OEM/Creative Labs Audigy 2 ZS */ 1478 /* See ALSA bug#1365 */ 1479 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10031102, 1480 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0353]", 1481 .id = "Audigy2", 1482 .emu10k2_chip = 1, 1483 .ca0102_chip = 1, 1484 .ca0151_chip = 1, 1485 .spk71 = 1, 1486 .spdif_bug = 1, 1487 .invert_shared_spdif = 1, /* digital/analog switch swapped */ 1488 .ac97_chip = 1} , 1489 /* Audigy 2 Platinum */ 1490 /* Win driver sets A_IOCFG output to 0xa00 */ 1491 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10021102, 1492 .driver = "Audigy2", .name = "SB Audigy 2 Platinum [SB0240P]", 1493 .id = "Audigy2", 1494 .emu10k2_chip = 1, 1495 .ca0102_chip = 1, 1496 .ca0151_chip = 1, 1497 .spk71 = 1, 1498 .spdif_bug = 1, 1499 .invert_shared_spdif = 1, /* digital/analog switch swapped */ 1500 .adc_1361t = 1, /* 24 bit capture instead of 16bit. Fixes ALSA bug#324 */ 1501 .ac97_chip = 1} , 1502 {.vendor = 0x1102, .device = 0x0004, .revision = 0x04, 1503 .driver = "Audigy2", .name = "SB Audigy 2 [Unknown]", 1504 .id = "Audigy2", 1505 .emu10k2_chip = 1, 1506 .ca0102_chip = 1, 1507 .ca0151_chip = 1, 1508 .spdif_bug = 1, 1509 .ac97_chip = 1} , 1510 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00531102, 1511 .driver = "Audigy", .name = "SB Audigy 1 [SB0092]", 1512 .id = "Audigy", 1513 .emu10k2_chip = 1, 1514 .ca0102_chip = 1, 1515 .ac97_chip = 1} , 1516 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00521102, 1517 .driver = "Audigy", .name = "SB Audigy 1 ES [SB0160]", 1518 .id = "Audigy", 1519 .emu10k2_chip = 1, 1520 .ca0102_chip = 1, 1521 .spdif_bug = 1, 1522 .ac97_chip = 1} , 1523 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00511102, 1524 .driver = "Audigy", .name = "SB Audigy 1 [SB0090]", 1525 .id = "Audigy", 1526 .emu10k2_chip = 1, 1527 .ca0102_chip = 1, 1528 .ac97_chip = 1} , 1529 {.vendor = 0x1102, .device = 0x0004, 1530 .driver = "Audigy", .name = "Audigy 1 [Unknown]", 1531 .id = "Audigy", 1532 .emu10k2_chip = 1, 1533 .ca0102_chip = 1, 1534 .ac97_chip = 1} , 1535 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x100a1102, 1536 .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0220]", 1537 .id = "Live", 1538 .emu10k1_chip = 1, 1539 .ac97_chip = 1, 1540 .sblive51 = 1} , 1541 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806b1102, 1542 .driver = "EMU10K1", .name = "SB Live! [SB0105]", 1543 .id = "Live", 1544 .emu10k1_chip = 1, 1545 .ac97_chip = 1, 1546 .sblive51 = 1} , 1547 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806a1102, 1548 .driver = "EMU10K1", .name = "SB Live! Value [SB0103]", 1549 .id = "Live", 1550 .emu10k1_chip = 1, 1551 .ac97_chip = 1, 1552 .sblive51 = 1} , 1553 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80691102, 1554 .driver = "EMU10K1", .name = "SB Live! Value [SB0101]", 1555 .id = "Live", 1556 .emu10k1_chip = 1, 1557 .ac97_chip = 1, 1558 .sblive51 = 1} , 1559 /* Tested by ALSA bug#1680 26th December 2005 */ 1560 /* note: It really has SB0220 written on the card, */ 1561 /* but it's SB0228 according to kx.inf */ 1562 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80661102, 1563 .driver = "EMU10K1", .name = "SB Live! 5.1 Dell OEM [SB0228]", 1564 .id = "Live", 1565 .emu10k1_chip = 1, 1566 .ac97_chip = 1, 1567 .sblive51 = 1} , 1568 /* Tested by Thomas Zehetbauer 27th Aug 2005 */ 1569 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80651102, 1570 .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0220]", 1571 .id = "Live", 1572 .emu10k1_chip = 1, 1573 .ac97_chip = 1, 1574 .sblive51 = 1} , 1575 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80641102, 1576 .driver = "EMU10K1", .name = "SB Live! 5.1", 1577 .id = "Live", 1578 .emu10k1_chip = 1, 1579 .ac97_chip = 1, 1580 .sblive51 = 1} , 1581 /* Tested by alsa bugtrack user "hus" bug #1297 12th Aug 2005 */ 1582 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80611102, 1583 .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0060]", 1584 .id = "Live", 1585 .emu10k1_chip = 1, 1586 .ac97_chip = 2, /* ac97 is optional; both SBLive 5.1 and platinum 1587 * share the same IDs! 1588 */ 1589 .sblive51 = 1} , 1590 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80511102, 1591 .driver = "EMU10K1", .name = "SB Live! Value [CT4850]", 1592 .id = "Live", 1593 .emu10k1_chip = 1, 1594 .ac97_chip = 1, 1595 .sblive51 = 1} , 1596 /* SB Live! Platinum */ 1597 /* Win driver sets A_IOCFG output to 0 */ 1598 /* Tested by Jonathan Dowland <jon@dow.land> Apr 2023. */ 1599 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80401102, 1600 .driver = "EMU10K1", .name = "SB Live! Platinum [CT4760P]", 1601 .id = "Live", 1602 .emu10k1_chip = 1, 1603 .ac97_chip = 1} , 1604 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80321102, 1605 .driver = "EMU10K1", .name = "SB Live! Value [CT4871]", 1606 .id = "Live", 1607 .emu10k1_chip = 1, 1608 .ac97_chip = 1, 1609 .sblive51 = 1} , 1610 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80311102, 1611 .driver = "EMU10K1", .name = "SB Live! Value [CT4831]", 1612 .id = "Live", 1613 .emu10k1_chip = 1, 1614 .ac97_chip = 1, 1615 .sblive51 = 1} , 1616 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80281102, 1617 .driver = "EMU10K1", .name = "SB Live! Value [CT4870]", 1618 .id = "Live", 1619 .emu10k1_chip = 1, 1620 .ac97_chip = 1, 1621 .sblive51 = 1} , 1622 /* Tested by James@superbug.co.uk 3rd July 2005 */ 1623 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80271102, 1624 .driver = "EMU10K1", .name = "SB Live! Value [CT4832]", 1625 .id = "Live", 1626 .emu10k1_chip = 1, 1627 .ac97_chip = 1, 1628 .sblive51 = 1} , 1629 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80261102, 1630 .driver = "EMU10K1", .name = "SB Live! Value [CT4830]", 1631 .id = "Live", 1632 .emu10k1_chip = 1, 1633 .ac97_chip = 1, 1634 .sblive51 = 1} , 1635 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80231102, 1636 .driver = "EMU10K1", .name = "SB PCI512 [CT4790]", 1637 .id = "Live", 1638 .emu10k1_chip = 1, 1639 .ac97_chip = 1, 1640 .sblive51 = 1} , 1641 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80221102, 1642 .driver = "EMU10K1", .name = "SB Live! Value [CT4780]", 1643 .id = "Live", 1644 .emu10k1_chip = 1, 1645 .ac97_chip = 1, 1646 .sblive51 = 1} , 1647 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x40011102, 1648 .driver = "EMU10K1", .name = "E-mu APS [PC545]", 1649 .id = "APS", 1650 .emu10k1_chip = 1, 1651 .ecard = 1} , 1652 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00211102, 1653 .driver = "EMU10K1", .name = "SB Live! [CT4620]", 1654 .id = "Live", 1655 .emu10k1_chip = 1, 1656 .ac97_chip = 1, 1657 .sblive51 = 1} , 1658 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00201102, 1659 .driver = "EMU10K1", .name = "SB Live! Value [CT4670]", 1660 .id = "Live", 1661 .emu10k1_chip = 1, 1662 .ac97_chip = 1, 1663 .sblive51 = 1} , 1664 {.vendor = 0x1102, .device = 0x0002, 1665 .driver = "EMU10K1", .name = "SB Live! [Unknown]", 1666 .id = "Live", 1667 .emu10k1_chip = 1, 1668 .ac97_chip = 1, 1669 .sblive51 = 1} , 1670 { } /* terminator */ 1671 }; 1672 1673 /* 1674 * The chip (at least the Audigy 2 CA0102 chip, but most likely others, too) 1675 * has a problem that from time to time it likes to do few DMA reads a bit 1676 * beyond its normal allocation and gets very confused if these reads get 1677 * blocked by a IOMMU. 1678 * 1679 * This behaviour has been observed for the first (reserved) page 1680 * (for which it happens multiple times at every playback), often for various 1681 * synth pages and sometimes for PCM playback buffers and the page table 1682 * memory itself. 1683 * 1684 * As a workaround let's widen these DMA allocations by an extra page if we 1685 * detect that the device is behind a non-passthrough IOMMU. 1686 */ 1687 static void snd_emu10k1_detect_iommu(struct snd_emu10k1 *emu) 1688 { 1689 struct iommu_domain *domain; 1690 1691 emu->iommu_workaround = false; 1692 1693 domain = iommu_get_domain_for_dev(emu->card->dev); 1694 if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY) 1695 return; 1696 1697 dev_notice(emu->card->dev, 1698 "non-passthrough IOMMU detected, widening DMA allocations"); 1699 emu->iommu_workaround = true; 1700 } 1701 1702 int snd_emu10k1_create(struct snd_card *card, 1703 struct pci_dev *pci, 1704 unsigned short extin_mask, 1705 unsigned short extout_mask, 1706 long max_cache_bytes, 1707 int enable_ir, 1708 uint subsystem) 1709 { 1710 struct snd_emu10k1 *emu = card->private_data; 1711 int idx, err; 1712 int is_audigy; 1713 size_t page_table_size; 1714 __le32 *pgtbl; 1715 unsigned int silent_page; 1716 const struct snd_emu_chip_details *c; 1717 1718 /* enable PCI device */ 1719 err = pcim_enable_device(pci); 1720 if (err < 0) 1721 return err; 1722 1723 card->private_free = snd_emu10k1_free; 1724 emu->card = card; 1725 spin_lock_init(&emu->reg_lock); 1726 spin_lock_init(&emu->emu_lock); 1727 spin_lock_init(&emu->spi_lock); 1728 spin_lock_init(&emu->i2c_lock); 1729 spin_lock_init(&emu->voice_lock); 1730 spin_lock_init(&emu->synth_lock); 1731 spin_lock_init(&emu->memblk_lock); 1732 mutex_init(&emu->fx8010.lock); 1733 INIT_LIST_HEAD(&emu->mapped_link_head); 1734 INIT_LIST_HEAD(&emu->mapped_order_link_head); 1735 emu->pci = pci; 1736 emu->irq = -1; 1737 emu->synth = NULL; 1738 emu->get_synth_voice = NULL; 1739 INIT_DELAYED_WORK(&emu->emu1010.firmware_work, emu1010_firmware_work); 1740 /* read revision & serial */ 1741 emu->revision = pci->revision; 1742 pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &emu->serial); 1743 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &emu->model); 1744 dev_dbg(card->dev, 1745 "vendor = 0x%x, device = 0x%x, subsystem_vendor_id = 0x%x, subsystem_id = 0x%x\n", 1746 pci->vendor, pci->device, emu->serial, emu->model); 1747 1748 for (c = emu_chip_details; c->vendor; c++) { 1749 if (c->vendor == pci->vendor && c->device == pci->device) { 1750 if (subsystem) { 1751 if (c->subsystem && (c->subsystem == subsystem)) 1752 break; 1753 else 1754 continue; 1755 } else { 1756 if (c->subsystem && (c->subsystem != emu->serial)) 1757 continue; 1758 if (c->revision && c->revision != emu->revision) 1759 continue; 1760 } 1761 break; 1762 } 1763 } 1764 if (c->vendor == 0) { 1765 dev_err(card->dev, "emu10k1: Card not recognised\n"); 1766 return -ENOENT; 1767 } 1768 emu->card_capabilities = c; 1769 if (c->subsystem && !subsystem) 1770 dev_dbg(card->dev, "Sound card name = %s\n", c->name); 1771 else if (subsystem) 1772 dev_dbg(card->dev, "Sound card name = %s, " 1773 "vendor = 0x%x, device = 0x%x, subsystem = 0x%x. " 1774 "Forced to subsystem = 0x%x\n", c->name, 1775 pci->vendor, pci->device, emu->serial, c->subsystem); 1776 else 1777 dev_dbg(card->dev, "Sound card name = %s, " 1778 "vendor = 0x%x, device = 0x%x, subsystem = 0x%x.\n", 1779 c->name, pci->vendor, pci->device, 1780 emu->serial); 1781 1782 if (!*card->id && c->id) 1783 strscpy(card->id, c->id, sizeof(card->id)); 1784 1785 is_audigy = emu->audigy = c->emu10k2_chip; 1786 1787 snd_emu10k1_detect_iommu(emu); 1788 1789 /* set addressing mode */ 1790 emu->address_mode = is_audigy ? 0 : 1; 1791 /* set the DMA transfer mask */ 1792 emu->dma_mask = emu->address_mode ? EMU10K1_DMA_MASK : AUDIGY_DMA_MASK; 1793 if (dma_set_mask_and_coherent(&pci->dev, emu->dma_mask) < 0) { 1794 dev_err(card->dev, 1795 "architecture does not support PCI busmaster DMA with mask 0x%lx\n", 1796 emu->dma_mask); 1797 return -ENXIO; 1798 } 1799 if (is_audigy) 1800 emu->gpr_base = A_FXGPREGBASE; 1801 else 1802 emu->gpr_base = FXGPREGBASE; 1803 1804 err = pci_request_regions(pci, "EMU10K1"); 1805 if (err < 0) 1806 return err; 1807 emu->port = pci_resource_start(pci, 0); 1808 1809 emu->max_cache_pages = max_cache_bytes >> PAGE_SHIFT; 1810 1811 page_table_size = sizeof(u32) * (emu->address_mode ? MAXPAGES1 : 1812 MAXPAGES0); 1813 if (snd_emu10k1_alloc_pages_maybe_wider(emu, page_table_size, 1814 &emu->ptb_pages) < 0) 1815 return -ENOMEM; 1816 dev_dbg(card->dev, "page table address range is %.8lx:%.8lx\n", 1817 (unsigned long)emu->ptb_pages.addr, 1818 (unsigned long)(emu->ptb_pages.addr + emu->ptb_pages.bytes)); 1819 1820 emu->page_ptr_table = vmalloc(array_size(sizeof(void *), 1821 emu->max_cache_pages)); 1822 emu->page_addr_table = vmalloc(array_size(sizeof(unsigned long), 1823 emu->max_cache_pages)); 1824 if (!emu->page_ptr_table || !emu->page_addr_table) 1825 return -ENOMEM; 1826 1827 if (snd_emu10k1_alloc_pages_maybe_wider(emu, EMUPAGESIZE, 1828 &emu->silent_page) < 0) 1829 return -ENOMEM; 1830 dev_dbg(card->dev, "silent page range is %.8lx:%.8lx\n", 1831 (unsigned long)emu->silent_page.addr, 1832 (unsigned long)(emu->silent_page.addr + 1833 emu->silent_page.bytes)); 1834 1835 emu->memhdr = snd_util_memhdr_new(emu->max_cache_pages * PAGE_SIZE); 1836 if (!emu->memhdr) 1837 return -ENOMEM; 1838 emu->memhdr->block_extra_size = sizeof(struct snd_emu10k1_memblk) - 1839 sizeof(struct snd_util_memblk); 1840 1841 pci_set_master(pci); 1842 1843 // The masks are not used for Audigy. 1844 // FIXME: these should come from the card_capabilites table. 1845 if (extin_mask == 0) 1846 extin_mask = 0x3fcf; // EXTIN_* 1847 if (extout_mask == 0) 1848 extout_mask = 0x7fff; // EXTOUT_* 1849 emu->fx8010.extin_mask = extin_mask; 1850 emu->fx8010.extout_mask = extout_mask; 1851 emu->enable_ir = enable_ir; 1852 1853 if (emu->card_capabilities->ca_cardbus_chip) { 1854 err = snd_emu10k1_cardbus_init(emu); 1855 if (err < 0) 1856 return err; 1857 } 1858 if (emu->card_capabilities->ecard) { 1859 err = snd_emu10k1_ecard_init(emu); 1860 if (err < 0) 1861 return err; 1862 } else if (emu->card_capabilities->emu_model) { 1863 err = snd_emu10k1_emu1010_init(emu); 1864 if (err < 0) 1865 return err; 1866 } else { 1867 /* 5.1: Enable the additional AC97 Slots. If the emu10k1 version 1868 does not support this, it shouldn't do any harm */ 1869 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, 1870 AC97SLOT_CNTR|AC97SLOT_LFE); 1871 } 1872 1873 /* initialize TRAM setup */ 1874 emu->fx8010.itram_size = (16 * 1024)/2; 1875 emu->fx8010.etram_pages.area = NULL; 1876 emu->fx8010.etram_pages.bytes = 0; 1877 1878 /* irq handler must be registered after I/O ports are activated */ 1879 if (devm_request_irq(&pci->dev, pci->irq, snd_emu10k1_interrupt, 1880 IRQF_SHARED, KBUILD_MODNAME, emu)) 1881 return -EBUSY; 1882 emu->irq = pci->irq; 1883 card->sync_irq = emu->irq; 1884 1885 /* 1886 * Init to 0x02109204 : 1887 * Clock accuracy = 0 (1000ppm) 1888 * Sample Rate = 2 (48kHz) 1889 * Audio Channel = 1 (Left of 2) 1890 * Source Number = 0 (Unspecified) 1891 * Generation Status = 1 (Original for Cat Code 12) 1892 * Cat Code = 12 (Digital Signal Mixer) 1893 * Mode = 0 (Mode 0) 1894 * Emphasis = 0 (None) 1895 * CP = 1 (Copyright unasserted) 1896 * AN = 0 (Audio data) 1897 * P = 0 (Consumer) 1898 */ 1899 emu->spdif_bits[0] = emu->spdif_bits[1] = 1900 emu->spdif_bits[2] = SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 | 1901 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC | 1902 SPCS_GENERATIONSTATUS | 0x00001200 | 1903 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT; 1904 1905 /* Clear silent pages and set up pointers */ 1906 memset(emu->silent_page.area, 0, emu->silent_page.bytes); 1907 silent_page = emu->silent_page.addr << emu->address_mode; 1908 pgtbl = (__le32 *)emu->ptb_pages.area; 1909 for (idx = 0; idx < (emu->address_mode ? MAXPAGES1 : MAXPAGES0); idx++) 1910 pgtbl[idx] = cpu_to_le32(silent_page | idx); 1911 1912 /* set up voice indices */ 1913 for (idx = 0; idx < NUM_G; idx++) 1914 emu->voices[idx].number = idx; 1915 1916 err = snd_emu10k1_init(emu, enable_ir); 1917 if (err < 0) 1918 return err; 1919 #ifdef CONFIG_PM_SLEEP 1920 err = alloc_pm_buffer(emu); 1921 if (err < 0) 1922 return err; 1923 #endif 1924 1925 /* Initialize the effect engine */ 1926 err = snd_emu10k1_init_efx(emu); 1927 if (err < 0) 1928 return err; 1929 snd_emu10k1_audio_enable(emu); 1930 1931 #ifdef CONFIG_SND_PROC_FS 1932 snd_emu10k1_proc_init(emu); 1933 #endif 1934 return 0; 1935 } 1936 1937 #ifdef CONFIG_PM_SLEEP 1938 static const unsigned char saved_regs[] = { 1939 CPF, PTRX, CVCF, VTFT, Z1, Z2, PSST, DSL, CCCA, CCR, CLP, 1940 FXRT, MAPA, MAPB, ENVVOL, ATKHLDV, DCYSUSV, LFOVAL1, ENVVAL, 1941 ATKHLDM, DCYSUSM, LFOVAL2, IP, IFATN, PEFE, FMMOD, TREMFRQ, FM2FRQ2, 1942 TEMPENV, ADCCR, FXWC, MICBA, ADCBA, FXBA, 1943 MICBS, ADCBS, FXBS, CDCS, GPSCS, SPCS0, SPCS1, SPCS2, 1944 SPBYPASS, AC97SLOT, CDSRCS, GPSRCS, ZVSRCS, MICIDX, ADCIDX, FXIDX, 1945 0xff /* end */ 1946 }; 1947 static const unsigned char saved_regs_audigy[] = { 1948 A_ADCIDX, A_MICIDX, A_FXWC1, A_FXWC2, A_EHC, 1949 A_FXRT2, A_SENDAMOUNTS, A_FXRT1, 1950 0xff /* end */ 1951 }; 1952 1953 static int alloc_pm_buffer(struct snd_emu10k1 *emu) 1954 { 1955 int size; 1956 1957 size = ARRAY_SIZE(saved_regs); 1958 if (emu->audigy) 1959 size += ARRAY_SIZE(saved_regs_audigy); 1960 emu->saved_ptr = vmalloc(array3_size(4, NUM_G, size)); 1961 if (!emu->saved_ptr) 1962 return -ENOMEM; 1963 if (snd_emu10k1_efx_alloc_pm_buffer(emu) < 0) 1964 return -ENOMEM; 1965 if (emu->card_capabilities->ca0151_chip && 1966 snd_p16v_alloc_pm_buffer(emu) < 0) 1967 return -ENOMEM; 1968 return 0; 1969 } 1970 1971 static void free_pm_buffer(struct snd_emu10k1 *emu) 1972 { 1973 vfree(emu->saved_ptr); 1974 snd_emu10k1_efx_free_pm_buffer(emu); 1975 if (emu->card_capabilities->ca0151_chip) 1976 snd_p16v_free_pm_buffer(emu); 1977 } 1978 1979 void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu) 1980 { 1981 int i; 1982 const unsigned char *reg; 1983 unsigned int *val; 1984 1985 val = emu->saved_ptr; 1986 for (reg = saved_regs; *reg != 0xff; reg++) 1987 for (i = 0; i < NUM_G; i++, val++) 1988 *val = snd_emu10k1_ptr_read(emu, *reg, i); 1989 if (emu->audigy) { 1990 for (reg = saved_regs_audigy; *reg != 0xff; reg++) 1991 for (i = 0; i < NUM_G; i++, val++) 1992 *val = snd_emu10k1_ptr_read(emu, *reg, i); 1993 } 1994 if (emu->audigy) 1995 emu->saved_a_iocfg = inw(emu->port + A_IOCFG); 1996 emu->saved_hcfg = inl(emu->port + HCFG); 1997 } 1998 1999 void snd_emu10k1_resume_init(struct snd_emu10k1 *emu) 2000 { 2001 if (emu->card_capabilities->ca_cardbus_chip) 2002 snd_emu10k1_cardbus_init(emu); 2003 if (emu->card_capabilities->ecard) 2004 snd_emu10k1_ecard_init(emu); 2005 else if (emu->card_capabilities->emu_model) 2006 snd_emu10k1_emu1010_init(emu); 2007 else 2008 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_CNTR|AC97SLOT_LFE); 2009 snd_emu10k1_init(emu, emu->enable_ir); 2010 } 2011 2012 void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu) 2013 { 2014 int i; 2015 const unsigned char *reg; 2016 unsigned int *val; 2017 2018 snd_emu10k1_audio_enable(emu); 2019 2020 /* resore for spdif */ 2021 if (emu->audigy) 2022 outw(emu->saved_a_iocfg, emu->port + A_IOCFG); 2023 outl(emu->saved_hcfg, emu->port + HCFG); 2024 2025 val = emu->saved_ptr; 2026 for (reg = saved_regs; *reg != 0xff; reg++) 2027 for (i = 0; i < NUM_G; i++, val++) 2028 snd_emu10k1_ptr_write(emu, *reg, i, *val); 2029 if (emu->audigy) { 2030 for (reg = saved_regs_audigy; *reg != 0xff; reg++) 2031 for (i = 0; i < NUM_G; i++, val++) 2032 snd_emu10k1_ptr_write(emu, *reg, i, *val); 2033 } 2034 } 2035 #endif 2036