1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * Creative Labs, Inc. 5 * Routines for control of EMU10K1 chips 6 * 7 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk> 8 * Added support for Audigy 2 Value. 9 * Added EMU 1010 support. 10 * General bug fixes and enhancements. 11 * 12 * BUGS: 13 * -- 14 * 15 * TODO: 16 * -- 17 */ 18 19 #include <linux/sched.h> 20 #include <linux/delay.h> 21 #include <linux/init.h> 22 #include <linux/module.h> 23 #include <linux/interrupt.h> 24 #include <linux/iommu.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include <linux/vmalloc.h> 28 #include <linux/mutex.h> 29 30 31 #include <sound/core.h> 32 #include <sound/emu10k1.h> 33 #include <linux/firmware.h> 34 #include "p16v.h" 35 #include "tina2.h" 36 #include "p17v.h" 37 38 39 #define HANA_FILENAME "emu/hana.fw" 40 #define DOCK_FILENAME "emu/audio_dock.fw" 41 #define EMU1010B_FILENAME "emu/emu1010b.fw" 42 #define MICRO_DOCK_FILENAME "emu/micro_dock.fw" 43 #define EMU0404_FILENAME "emu/emu0404.fw" 44 #define EMU1010_NOTEBOOK_FILENAME "emu/emu1010_notebook.fw" 45 46 MODULE_FIRMWARE(HANA_FILENAME); 47 MODULE_FIRMWARE(DOCK_FILENAME); 48 MODULE_FIRMWARE(EMU1010B_FILENAME); 49 MODULE_FIRMWARE(MICRO_DOCK_FILENAME); 50 MODULE_FIRMWARE(EMU0404_FILENAME); 51 MODULE_FIRMWARE(EMU1010_NOTEBOOK_FILENAME); 52 53 54 /************************************************************************* 55 * EMU10K1 init / done 56 *************************************************************************/ 57 58 void snd_emu10k1_voice_init(struct snd_emu10k1 *emu, int ch) 59 { 60 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0); 61 snd_emu10k1_ptr_write(emu, IP, ch, 0); 62 snd_emu10k1_ptr_write(emu, VTFT, ch, 0xffff); 63 snd_emu10k1_ptr_write(emu, CVCF, ch, 0xffff); 64 snd_emu10k1_ptr_write(emu, PTRX, ch, 0); 65 snd_emu10k1_ptr_write(emu, CPF, ch, 0); 66 snd_emu10k1_ptr_write(emu, CCR, ch, 0); 67 68 snd_emu10k1_ptr_write(emu, PSST, ch, 0); 69 snd_emu10k1_ptr_write(emu, DSL, ch, 0x10); 70 snd_emu10k1_ptr_write(emu, CCCA, ch, 0); 71 snd_emu10k1_ptr_write(emu, Z1, ch, 0); 72 snd_emu10k1_ptr_write(emu, Z2, ch, 0); 73 snd_emu10k1_ptr_write(emu, FXRT, ch, 0x32100000); 74 75 snd_emu10k1_ptr_write(emu, ATKHLDM, ch, 0); 76 snd_emu10k1_ptr_write(emu, DCYSUSM, ch, 0); 77 snd_emu10k1_ptr_write(emu, IFATN, ch, 0xffff); 78 snd_emu10k1_ptr_write(emu, PEFE, ch, 0); 79 snd_emu10k1_ptr_write(emu, FMMOD, ch, 0); 80 snd_emu10k1_ptr_write(emu, TREMFRQ, ch, 24); /* 1 Hz */ 81 snd_emu10k1_ptr_write(emu, FM2FRQ2, ch, 24); /* 1 Hz */ 82 snd_emu10k1_ptr_write(emu, TEMPENV, ch, 0); 83 84 /*** these are last so OFF prevents writing ***/ 85 snd_emu10k1_ptr_write(emu, LFOVAL2, ch, 0); 86 snd_emu10k1_ptr_write(emu, LFOVAL1, ch, 0); 87 snd_emu10k1_ptr_write(emu, ATKHLDV, ch, 0); 88 snd_emu10k1_ptr_write(emu, ENVVOL, ch, 0); 89 snd_emu10k1_ptr_write(emu, ENVVAL, ch, 0); 90 91 /* Audigy extra stuffs */ 92 if (emu->audigy) { 93 snd_emu10k1_ptr_write(emu, 0x4c, ch, 0); /* ?? */ 94 snd_emu10k1_ptr_write(emu, 0x4d, ch, 0); /* ?? */ 95 snd_emu10k1_ptr_write(emu, 0x4e, ch, 0); /* ?? */ 96 snd_emu10k1_ptr_write(emu, 0x4f, ch, 0); /* ?? */ 97 snd_emu10k1_ptr_write(emu, A_FXRT1, ch, 0x03020100); 98 snd_emu10k1_ptr_write(emu, A_FXRT2, ch, 0x3f3f3f3f); 99 snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, ch, 0); 100 } 101 } 102 103 static const unsigned int spi_dac_init[] = { 104 0x00ff, 105 0x02ff, 106 0x0400, 107 0x0520, 108 0x0600, 109 0x08ff, 110 0x0aff, 111 0x0cff, 112 0x0eff, 113 0x10ff, 114 0x1200, 115 0x1400, 116 0x1480, 117 0x1800, 118 0x1aff, 119 0x1cff, 120 0x1e00, 121 0x0530, 122 0x0602, 123 0x0622, 124 0x1400, 125 }; 126 127 static const unsigned int i2c_adc_init[][2] = { 128 { 0x17, 0x00 }, /* Reset */ 129 { 0x07, 0x00 }, /* Timeout */ 130 { 0x0b, 0x22 }, /* Interface control */ 131 { 0x0c, 0x22 }, /* Master mode control */ 132 { 0x0d, 0x08 }, /* Powerdown control */ 133 { 0x0e, 0xcf }, /* Attenuation Left 0x01 = -103dB, 0xff = 24dB */ 134 { 0x0f, 0xcf }, /* Attenuation Right 0.5dB steps */ 135 { 0x10, 0x7b }, /* ALC Control 1 */ 136 { 0x11, 0x00 }, /* ALC Control 2 */ 137 { 0x12, 0x32 }, /* ALC Control 3 */ 138 { 0x13, 0x00 }, /* Noise gate control */ 139 { 0x14, 0xa6 }, /* Limiter control */ 140 { 0x15, ADC_MUX_2 }, /* ADC Mixer control. Mic for A2ZS Notebook */ 141 }; 142 143 static int snd_emu10k1_init(struct snd_emu10k1 *emu, int enable_ir, int resume) 144 { 145 unsigned int silent_page; 146 int ch; 147 u32 tmp; 148 149 /* disable audio and lock cache */ 150 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | 151 HCFG_MUTEBUTTONENABLE, emu->port + HCFG); 152 153 /* reset recording buffers */ 154 snd_emu10k1_ptr_write(emu, MICBS, 0, ADCBS_BUFSIZE_NONE); 155 snd_emu10k1_ptr_write(emu, MICBA, 0, 0); 156 snd_emu10k1_ptr_write(emu, FXBS, 0, ADCBS_BUFSIZE_NONE); 157 snd_emu10k1_ptr_write(emu, FXBA, 0, 0); 158 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE); 159 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0); 160 161 /* disable channel interrupt */ 162 outl(0, emu->port + INTE); 163 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0); 164 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0); 165 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0); 166 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0); 167 168 if (emu->audigy) { 169 /* set SPDIF bypass mode */ 170 snd_emu10k1_ptr_write(emu, SPBYPASS, 0, SPBYPASS_FORMAT); 171 /* enable rear left + rear right AC97 slots */ 172 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_REAR_RIGHT | 173 AC97SLOT_REAR_LEFT); 174 } 175 176 /* init envelope engine */ 177 for (ch = 0; ch < NUM_G; ch++) 178 snd_emu10k1_voice_init(emu, ch); 179 180 snd_emu10k1_ptr_write(emu, SPCS0, 0, emu->spdif_bits[0]); 181 snd_emu10k1_ptr_write(emu, SPCS1, 0, emu->spdif_bits[1]); 182 snd_emu10k1_ptr_write(emu, SPCS2, 0, emu->spdif_bits[2]); 183 184 if (emu->card_capabilities->ca0151_chip) { /* audigy2 */ 185 /* Hacks for Alice3 to work independent of haP16V driver */ 186 /* Setup SRCMulti_I2S SamplingRate */ 187 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0); 188 tmp &= 0xfffff1ff; 189 tmp |= (0x2<<9); 190 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp); 191 192 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */ 193 snd_emu10k1_ptr20_write(emu, SRCSel, 0, 0x14); 194 /* Setup SRCMulti Input Audio Enable */ 195 /* Use 0xFFFFFFFF to enable P16V sounds. */ 196 snd_emu10k1_ptr20_write(emu, SRCMULTI_ENABLE, 0, 0xFFFFFFFF); 197 198 /* Enabled Phased (8-channel) P16V playback */ 199 outl(0x0201, emu->port + HCFG2); 200 /* Set playback routing. */ 201 snd_emu10k1_ptr20_write(emu, CAPTURE_P16V_SOURCE, 0, 0x78e4); 202 } 203 if (emu->card_capabilities->ca0108_chip) { /* audigy2 Value */ 204 /* Hacks for Alice3 to work independent of haP16V driver */ 205 dev_info(emu->card->dev, "Audigy2 value: Special config.\n"); 206 /* Setup SRCMulti_I2S SamplingRate */ 207 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0); 208 tmp &= 0xfffff1ff; 209 tmp |= (0x2<<9); 210 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp); 211 212 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */ 213 outl(0x600000, emu->port + 0x20); 214 outl(0x14, emu->port + 0x24); 215 216 /* Setup SRCMulti Input Audio Enable */ 217 outl(0x7b0000, emu->port + 0x20); 218 outl(0xFF000000, emu->port + 0x24); 219 220 /* Setup SPDIF Out Audio Enable */ 221 /* The Audigy 2 Value has a separate SPDIF out, 222 * so no need for a mixer switch 223 */ 224 outl(0x7a0000, emu->port + 0x20); 225 outl(0xFF000000, emu->port + 0x24); 226 tmp = inw(emu->port + A_IOCFG) & ~0x8; /* Clear bit 3 */ 227 outw(tmp, emu->port + A_IOCFG); 228 } 229 if (emu->card_capabilities->spi_dac) { /* Audigy 2 ZS Notebook with DAC Wolfson WM8768/WM8568 */ 230 int size, n; 231 232 size = ARRAY_SIZE(spi_dac_init); 233 for (n = 0; n < size; n++) 234 snd_emu10k1_spi_write(emu, spi_dac_init[n]); 235 236 snd_emu10k1_ptr20_write(emu, 0x60, 0, 0x10); 237 /* Enable GPIOs 238 * GPIO0: Unknown 239 * GPIO1: Speakers-enabled. 240 * GPIO2: Unknown 241 * GPIO3: Unknown 242 * GPIO4: IEC958 Output on. 243 * GPIO5: Unknown 244 * GPIO6: Unknown 245 * GPIO7: Unknown 246 */ 247 outw(0x76, emu->port + A_IOCFG); /* Windows uses 0x3f76 */ 248 } 249 if (emu->card_capabilities->i2c_adc) { /* Audigy 2 ZS Notebook with ADC Wolfson WM8775 */ 250 int size, n; 251 252 snd_emu10k1_ptr20_write(emu, P17V_I2S_SRC_SEL, 0, 0x2020205f); 253 tmp = inw(emu->port + A_IOCFG); 254 outw(tmp | 0x4, emu->port + A_IOCFG); /* Set bit 2 for mic input */ 255 tmp = inw(emu->port + A_IOCFG); 256 size = ARRAY_SIZE(i2c_adc_init); 257 for (n = 0; n < size; n++) 258 snd_emu10k1_i2c_write(emu, i2c_adc_init[n][0], i2c_adc_init[n][1]); 259 for (n = 0; n < 4; n++) { 260 emu->i2c_capture_volume[n][0] = 0xcf; 261 emu->i2c_capture_volume[n][1] = 0xcf; 262 } 263 } 264 265 266 snd_emu10k1_ptr_write(emu, PTB, 0, emu->ptb_pages.addr); 267 snd_emu10k1_ptr_write(emu, TCB, 0, 0); /* taken from original driver */ 268 snd_emu10k1_ptr_write(emu, TCBS, 0, 4); /* taken from original driver */ 269 270 silent_page = (emu->silent_page.addr << emu->address_mode) | (emu->address_mode ? MAP_PTI_MASK1 : MAP_PTI_MASK0); 271 for (ch = 0; ch < NUM_G; ch++) { 272 snd_emu10k1_ptr_write(emu, MAPA, ch, silent_page); 273 snd_emu10k1_ptr_write(emu, MAPB, ch, silent_page); 274 } 275 276 if (emu->card_capabilities->emu_model) { 277 outl(HCFG_AUTOMUTE_ASYNC | 278 HCFG_EMU32_SLAVE | 279 HCFG_AUDIOENABLE, emu->port + HCFG); 280 /* 281 * Hokay, setup HCFG 282 * Mute Disable Audio = 0 283 * Lock Tank Memory = 1 284 * Lock Sound Memory = 0 285 * Auto Mute = 1 286 */ 287 } else if (emu->audigy) { 288 if (emu->revision == 4) /* audigy2 */ 289 outl(HCFG_AUDIOENABLE | 290 HCFG_AC3ENABLE_CDSPDIF | 291 HCFG_AC3ENABLE_GPSPDIF | 292 HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG); 293 else 294 outl(HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG); 295 /* FIXME: Remove all these emu->model and replace it with a card recognition parameter, 296 * e.g. card_capabilities->joystick */ 297 } else if (emu->model == 0x20 || 298 emu->model == 0xc400 || 299 (emu->model == 0x21 && emu->revision < 6)) 300 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE, emu->port + HCFG); 301 else 302 /* With on-chip joystick */ 303 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG); 304 305 if (enable_ir) { /* enable IR for SB Live */ 306 if (emu->card_capabilities->emu_model) { 307 ; /* Disable all access to A_IOCFG for the emu1010 */ 308 } else if (emu->card_capabilities->i2c_adc) { 309 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */ 310 } else if (emu->audigy) { 311 u16 reg = inw(emu->port + A_IOCFG); 312 outw(reg | A_IOCFG_GPOUT2, emu->port + A_IOCFG); 313 udelay(500); 314 outw(reg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, emu->port + A_IOCFG); 315 udelay(100); 316 outw(reg, emu->port + A_IOCFG); 317 } else { 318 unsigned int reg = inl(emu->port + HCFG); 319 outl(reg | HCFG_GPOUT2, emu->port + HCFG); 320 udelay(500); 321 outl(reg | HCFG_GPOUT1 | HCFG_GPOUT2, emu->port + HCFG); 322 udelay(100); 323 outl(reg, emu->port + HCFG); 324 } 325 } 326 327 if (emu->card_capabilities->emu_model) { 328 ; /* Disable all access to A_IOCFG for the emu1010 */ 329 } else if (emu->card_capabilities->i2c_adc) { 330 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */ 331 } else if (emu->audigy) { /* enable analog output */ 332 u16 reg = inw(emu->port + A_IOCFG); 333 outw(reg | A_IOCFG_GPOUT0, emu->port + A_IOCFG); 334 } 335 336 if (emu->address_mode == 0) { 337 /* use 16M in 4G */ 338 outl(inl(emu->port + HCFG) | HCFG_EXPANDED_MEM, emu->port + HCFG); 339 } 340 341 return 0; 342 } 343 344 static void snd_emu10k1_audio_enable(struct snd_emu10k1 *emu) 345 { 346 /* 347 * Enable the audio bit 348 */ 349 outl(inl(emu->port + HCFG) | HCFG_AUDIOENABLE, emu->port + HCFG); 350 351 /* Enable analog/digital outs on audigy */ 352 if (emu->card_capabilities->emu_model) { 353 ; /* Disable all access to A_IOCFG for the emu1010 */ 354 } else if (emu->card_capabilities->i2c_adc) { 355 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */ 356 } else if (emu->audigy) { 357 outw(inw(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG); 358 359 if (emu->card_capabilities->ca0151_chip) { /* audigy2 */ 360 /* Unmute Analog now. Set GPO6 to 1 for Apollo. 361 * This has to be done after init ALice3 I2SOut beyond 48KHz. 362 * So, sequence is important. */ 363 outw(inw(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG); 364 } else if (emu->card_capabilities->ca0108_chip) { /* audigy2 value */ 365 /* Unmute Analog now. */ 366 outw(inw(emu->port + A_IOCFG) | 0x0060, emu->port + A_IOCFG); 367 } else { 368 /* Disable routing from AC97 line out to Front speakers */ 369 outw(inw(emu->port + A_IOCFG) | 0x0080, emu->port + A_IOCFG); 370 } 371 } 372 373 #if 0 374 { 375 unsigned int tmp; 376 /* FIXME: the following routine disables LiveDrive-II !! */ 377 /* TOSLink detection */ 378 emu->tos_link = 0; 379 tmp = inl(emu->port + HCFG); 380 if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) { 381 outl(tmp|0x800, emu->port + HCFG); 382 udelay(50); 383 if (tmp != (inl(emu->port + HCFG) & ~0x800)) { 384 emu->tos_link = 1; 385 outl(tmp, emu->port + HCFG); 386 } 387 } 388 } 389 #endif 390 391 snd_emu10k1_intr_enable(emu, INTE_PCIERRORENABLE); 392 } 393 394 int snd_emu10k1_done(struct snd_emu10k1 *emu) 395 { 396 int ch; 397 398 outl(0, emu->port + INTE); 399 400 /* 401 * Shutdown the chip 402 */ 403 for (ch = 0; ch < NUM_G; ch++) 404 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0); 405 for (ch = 0; ch < NUM_G; ch++) { 406 snd_emu10k1_ptr_write(emu, VTFT, ch, 0); 407 snd_emu10k1_ptr_write(emu, CVCF, ch, 0); 408 snd_emu10k1_ptr_write(emu, PTRX, ch, 0); 409 snd_emu10k1_ptr_write(emu, CPF, ch, 0); 410 } 411 412 /* reset recording buffers */ 413 snd_emu10k1_ptr_write(emu, MICBS, 0, 0); 414 snd_emu10k1_ptr_write(emu, MICBA, 0, 0); 415 snd_emu10k1_ptr_write(emu, FXBS, 0, 0); 416 snd_emu10k1_ptr_write(emu, FXBA, 0, 0); 417 snd_emu10k1_ptr_write(emu, FXWC, 0, 0); 418 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE); 419 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0); 420 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K); 421 snd_emu10k1_ptr_write(emu, TCB, 0, 0); 422 if (emu->audigy) 423 snd_emu10k1_ptr_write(emu, A_DBG, 0, A_DBG_SINGLE_STEP); 424 else 425 snd_emu10k1_ptr_write(emu, DBG, 0, EMU10K1_DBG_SINGLE_STEP); 426 427 /* disable channel interrupt */ 428 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0); 429 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0); 430 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0); 431 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0); 432 433 /* disable audio and lock cache */ 434 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG); 435 snd_emu10k1_ptr_write(emu, PTB, 0, 0); 436 437 return 0; 438 } 439 440 /************************************************************************* 441 * ECARD functional implementation 442 *************************************************************************/ 443 444 /* In A1 Silicon, these bits are in the HC register */ 445 #define HOOKN_BIT (1L << 12) 446 #define HANDN_BIT (1L << 11) 447 #define PULSEN_BIT (1L << 10) 448 449 #define EC_GDI1 (1 << 13) 450 #define EC_GDI0 (1 << 14) 451 452 #define EC_NUM_CONTROL_BITS 20 453 454 #define EC_AC3_DATA_SELN 0x0001L 455 #define EC_EE_DATA_SEL 0x0002L 456 #define EC_EE_CNTRL_SELN 0x0004L 457 #define EC_EECLK 0x0008L 458 #define EC_EECS 0x0010L 459 #define EC_EESDO 0x0020L 460 #define EC_TRIM_CSN 0x0040L 461 #define EC_TRIM_SCLK 0x0080L 462 #define EC_TRIM_SDATA 0x0100L 463 #define EC_TRIM_MUTEN 0x0200L 464 #define EC_ADCCAL 0x0400L 465 #define EC_ADCRSTN 0x0800L 466 #define EC_DACCAL 0x1000L 467 #define EC_DACMUTEN 0x2000L 468 #define EC_LEDN 0x4000L 469 470 #define EC_SPDIF0_SEL_SHIFT 15 471 #define EC_SPDIF1_SEL_SHIFT 17 472 #define EC_SPDIF0_SEL_MASK (0x3L << EC_SPDIF0_SEL_SHIFT) 473 #define EC_SPDIF1_SEL_MASK (0x7L << EC_SPDIF1_SEL_SHIFT) 474 #define EC_SPDIF0_SELECT(_x) (((_x) << EC_SPDIF0_SEL_SHIFT) & EC_SPDIF0_SEL_MASK) 475 #define EC_SPDIF1_SELECT(_x) (((_x) << EC_SPDIF1_SEL_SHIFT) & EC_SPDIF1_SEL_MASK) 476 #define EC_CURRENT_PROM_VERSION 0x01 /* Self-explanatory. This should 477 * be incremented any time the EEPROM's 478 * format is changed. */ 479 480 #define EC_EEPROM_SIZE 0x40 /* ECARD EEPROM has 64 16-bit words */ 481 482 /* Addresses for special values stored in to EEPROM */ 483 #define EC_PROM_VERSION_ADDR 0x20 /* Address of the current prom version */ 484 #define EC_BOARDREV0_ADDR 0x21 /* LSW of board rev */ 485 #define EC_BOARDREV1_ADDR 0x22 /* MSW of board rev */ 486 487 #define EC_LAST_PROMFILE_ADDR 0x2f 488 489 #define EC_SERIALNUM_ADDR 0x30 /* First word of serial number. The 490 * can be up to 30 characters in length 491 * and is stored as a NULL-terminated 492 * ASCII string. Any unused bytes must be 493 * filled with zeros */ 494 #define EC_CHECKSUM_ADDR 0x3f /* Location at which checksum is stored */ 495 496 497 /* Most of this stuff is pretty self-evident. According to the hardware 498 * dudes, we need to leave the ADCCAL bit low in order to avoid a DC 499 * offset problem. Weird. 500 */ 501 #define EC_RAW_RUN_MODE (EC_DACMUTEN | EC_ADCRSTN | EC_TRIM_MUTEN | \ 502 EC_TRIM_CSN) 503 504 505 #define EC_DEFAULT_ADC_GAIN 0xC4C4 506 #define EC_DEFAULT_SPDIF0_SEL 0x0 507 #define EC_DEFAULT_SPDIF1_SEL 0x4 508 509 /************************************************************************** 510 * @func Clock bits into the Ecard's control latch. The Ecard uses a 511 * control latch will is loaded bit-serially by toggling the Modem control 512 * lines from function 2 on the E8010. This function hides these details 513 * and presents the illusion that we are actually writing to a distinct 514 * register. 515 */ 516 517 static void snd_emu10k1_ecard_write(struct snd_emu10k1 *emu, unsigned int value) 518 { 519 unsigned short count; 520 unsigned int data; 521 unsigned long hc_port; 522 unsigned int hc_value; 523 524 hc_port = emu->port + HCFG; 525 hc_value = inl(hc_port) & ~(HOOKN_BIT | HANDN_BIT | PULSEN_BIT); 526 outl(hc_value, hc_port); 527 528 for (count = 0; count < EC_NUM_CONTROL_BITS; count++) { 529 530 /* Set up the value */ 531 data = ((value & 0x1) ? PULSEN_BIT : 0); 532 value >>= 1; 533 534 outl(hc_value | data, hc_port); 535 536 /* Clock the shift register */ 537 outl(hc_value | data | HANDN_BIT, hc_port); 538 outl(hc_value | data, hc_port); 539 } 540 541 /* Latch the bits */ 542 outl(hc_value | HOOKN_BIT, hc_port); 543 outl(hc_value, hc_port); 544 } 545 546 /************************************************************************** 547 * @func Set the gain of the ECARD's CS3310 Trim/gain controller. The 548 * trim value consists of a 16bit value which is composed of two 549 * 8 bit gain/trim values, one for the left channel and one for the 550 * right channel. The following table maps from the Gain/Attenuation 551 * value in decibels into the corresponding bit pattern for a single 552 * channel. 553 */ 554 555 static void snd_emu10k1_ecard_setadcgain(struct snd_emu10k1 *emu, 556 unsigned short gain) 557 { 558 unsigned int bit; 559 560 /* Enable writing to the TRIM registers */ 561 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN); 562 563 /* Do it again to insure that we meet hold time requirements */ 564 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN); 565 566 for (bit = (1 << 15); bit; bit >>= 1) { 567 unsigned int value; 568 569 value = emu->ecard_ctrl & ~(EC_TRIM_CSN | EC_TRIM_SDATA); 570 571 if (gain & bit) 572 value |= EC_TRIM_SDATA; 573 574 /* Clock the bit */ 575 snd_emu10k1_ecard_write(emu, value); 576 snd_emu10k1_ecard_write(emu, value | EC_TRIM_SCLK); 577 snd_emu10k1_ecard_write(emu, value); 578 } 579 580 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl); 581 } 582 583 static int snd_emu10k1_ecard_init(struct snd_emu10k1 *emu) 584 { 585 unsigned int hc_value; 586 587 /* Set up the initial settings */ 588 emu->ecard_ctrl = EC_RAW_RUN_MODE | 589 EC_SPDIF0_SELECT(EC_DEFAULT_SPDIF0_SEL) | 590 EC_SPDIF1_SELECT(EC_DEFAULT_SPDIF1_SEL); 591 592 /* Step 0: Set the codec type in the hardware control register 593 * and enable audio output */ 594 hc_value = inl(emu->port + HCFG); 595 outl(hc_value | HCFG_AUDIOENABLE | HCFG_CODECFORMAT_I2S, emu->port + HCFG); 596 inl(emu->port + HCFG); 597 598 /* Step 1: Turn off the led and deassert TRIM_CS */ 599 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN); 600 601 /* Step 2: Calibrate the ADC and DAC */ 602 snd_emu10k1_ecard_write(emu, EC_DACCAL | EC_LEDN | EC_TRIM_CSN); 603 604 /* Step 3: Wait for awhile; XXX We can't get away with this 605 * under a real operating system; we'll need to block and wait that 606 * way. */ 607 snd_emu10k1_wait(emu, 48000); 608 609 /* Step 4: Switch off the DAC and ADC calibration. Note 610 * That ADC_CAL is actually an inverted signal, so we assert 611 * it here to stop calibration. */ 612 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN); 613 614 /* Step 4: Switch into run mode */ 615 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl); 616 617 /* Step 5: Set the analog input gain */ 618 snd_emu10k1_ecard_setadcgain(emu, EC_DEFAULT_ADC_GAIN); 619 620 return 0; 621 } 622 623 static int snd_emu10k1_cardbus_init(struct snd_emu10k1 *emu) 624 { 625 unsigned long special_port; 626 __always_unused unsigned int value; 627 628 /* Special initialisation routine 629 * before the rest of the IO-Ports become active. 630 */ 631 special_port = emu->port + 0x38; 632 value = inl(special_port); 633 outl(0x00d00000, special_port); 634 value = inl(special_port); 635 outl(0x00d00001, special_port); 636 value = inl(special_port); 637 outl(0x00d0005f, special_port); 638 value = inl(special_port); 639 outl(0x00d0007f, special_port); 640 value = inl(special_port); 641 outl(0x0090007f, special_port); 642 value = inl(special_port); 643 644 snd_emu10k1_ptr20_write(emu, TINA2_VOLUME, 0, 0xfefefefe); /* Defaults to 0x30303030 */ 645 /* Delay to give time for ADC chip to switch on. It needs 113ms */ 646 msleep(200); 647 return 0; 648 } 649 650 static int snd_emu1010_load_firmware_entry(struct snd_emu10k1 *emu, 651 const struct firmware *fw_entry) 652 { 653 int n, i; 654 u16 reg; 655 u8 value; 656 __always_unused u16 write_post; 657 unsigned long flags; 658 659 if (!fw_entry) 660 return -EIO; 661 662 /* The FPGA is a Xilinx Spartan IIE XC2S50E */ 663 /* GPIO7 -> FPGA PGMN 664 * GPIO6 -> FPGA CCLK 665 * GPIO5 -> FPGA DIN 666 * FPGA CONFIG OFF -> FPGA PGMN 667 */ 668 spin_lock_irqsave(&emu->emu_lock, flags); 669 outw(0x00, emu->port + A_GPIO); /* Set PGMN low for 1uS. */ 670 write_post = inw(emu->port + A_GPIO); 671 udelay(100); 672 outw(0x80, emu->port + A_GPIO); /* Leave bit 7 set during netlist setup. */ 673 write_post = inw(emu->port + A_GPIO); 674 udelay(100); /* Allow FPGA memory to clean */ 675 for (n = 0; n < fw_entry->size; n++) { 676 value = fw_entry->data[n]; 677 for (i = 0; i < 8; i++) { 678 reg = 0x80; 679 if (value & 0x1) 680 reg = reg | 0x20; 681 value = value >> 1; 682 outw(reg, emu->port + A_GPIO); 683 write_post = inw(emu->port + A_GPIO); 684 outw(reg | 0x40, emu->port + A_GPIO); 685 write_post = inw(emu->port + A_GPIO); 686 } 687 } 688 /* After programming, set GPIO bit 4 high again. */ 689 outw(0x10, emu->port + A_GPIO); 690 write_post = inw(emu->port + A_GPIO); 691 spin_unlock_irqrestore(&emu->emu_lock, flags); 692 693 return 0; 694 } 695 696 /* firmware file names, per model, init-fw and dock-fw (optional) */ 697 static const char * const firmware_names[5][2] = { 698 [EMU_MODEL_EMU1010] = { 699 HANA_FILENAME, DOCK_FILENAME 700 }, 701 [EMU_MODEL_EMU1010B] = { 702 EMU1010B_FILENAME, MICRO_DOCK_FILENAME 703 }, 704 [EMU_MODEL_EMU1616] = { 705 EMU1010_NOTEBOOK_FILENAME, MICRO_DOCK_FILENAME 706 }, 707 [EMU_MODEL_EMU0404] = { 708 EMU0404_FILENAME, NULL 709 }, 710 }; 711 712 static int snd_emu1010_load_firmware(struct snd_emu10k1 *emu, int dock, 713 const struct firmware **fw) 714 { 715 const char *filename; 716 int err; 717 718 if (!*fw) { 719 filename = firmware_names[emu->card_capabilities->emu_model][dock]; 720 if (!filename) 721 return 0; 722 err = request_firmware(fw, filename, &emu->pci->dev); 723 if (err) 724 return err; 725 } 726 727 return snd_emu1010_load_firmware_entry(emu, *fw); 728 } 729 730 static void emu1010_firmware_work(struct work_struct *work) 731 { 732 struct snd_emu10k1 *emu; 733 u32 tmp, tmp2, reg; 734 int err; 735 736 emu = container_of(work, struct snd_emu10k1, 737 emu1010.firmware_work.work); 738 if (emu->card->shutdown) 739 return; 740 #ifdef CONFIG_PM_SLEEP 741 if (emu->suspend) 742 return; 743 #endif 744 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &tmp); /* IRQ Status */ 745 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®); /* OPTIONS: Which cards are attached to the EMU */ 746 if (reg & EMU_HANA_OPTION_DOCK_OFFLINE) { 747 /* Audio Dock attached */ 748 /* Return to Audio Dock programming mode */ 749 dev_info(emu->card->dev, 750 "emu1010: Loading Audio Dock Firmware\n"); 751 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 752 EMU_HANA_FPGA_CONFIG_AUDIODOCK); 753 err = snd_emu1010_load_firmware(emu, 1, &emu->dock_fw); 754 if (err < 0) 755 goto next; 756 757 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0); 758 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &tmp); 759 dev_info(emu->card->dev, 760 "emu1010: EMU_HANA+DOCK_IRQ_STATUS = 0x%x\n", tmp); 761 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */ 762 snd_emu1010_fpga_read(emu, EMU_HANA_ID, &tmp); 763 dev_info(emu->card->dev, 764 "emu1010: EMU_HANA+DOCK_ID = 0x%x\n", tmp); 765 if ((tmp & 0x1f) != 0x15) { 766 /* FPGA failed to be programmed */ 767 dev_info(emu->card->dev, 768 "emu1010: Loading Audio Dock Firmware file failed, reg = 0x%x\n", 769 tmp); 770 goto next; 771 } 772 dev_info(emu->card->dev, 773 "emu1010: Audio Dock Firmware loaded\n"); 774 snd_emu1010_fpga_read(emu, EMU_DOCK_MAJOR_REV, &tmp); 775 snd_emu1010_fpga_read(emu, EMU_DOCK_MINOR_REV, &tmp2); 776 dev_info(emu->card->dev, "Audio Dock ver: %u.%u\n", tmp, tmp2); 777 /* Sync clocking between 1010 and Dock */ 778 /* Allow DLL to settle */ 779 msleep(10); 780 /* Unmute all. Default is muted after a firmware load */ 781 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE); 782 } else if (!reg && emu->emu1010.last_reg) { 783 /* Audio Dock removed */ 784 dev_info(emu->card->dev, "emu1010: Audio Dock detached\n"); 785 /* Unmute all */ 786 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE); 787 } 788 789 next: 790 emu->emu1010.last_reg = reg; 791 if (!emu->card->shutdown) 792 schedule_delayed_work(&emu->emu1010.firmware_work, 793 msecs_to_jiffies(1000)); 794 } 795 796 /* 797 * EMU-1010 - details found out from this driver, official MS Win drivers, 798 * testing the card: 799 * 800 * Audigy2 (aka Alice2): 801 * --------------------- 802 * * communication over PCI 803 * * conversion of 32-bit data coming over EMU32 links from HANA FPGA 804 * to 2 x 16-bit, using internal DSP instructions 805 * * slave mode, clock supplied by HANA 806 * * linked to HANA using: 807 * 32 x 32-bit serial EMU32 output channels 808 * 16 x EMU32 input channels 809 * (?) x I2S I/O channels (?) 810 * 811 * FPGA (aka HANA): 812 * --------------- 813 * * provides all (?) physical inputs and outputs of the card 814 * (ADC, DAC, SPDIF I/O, ADAT I/O, etc.) 815 * * provides clock signal for the card and Alice2 816 * * two crystals - for 44.1kHz and 48kHz multiples 817 * * provides internal routing of signal sources to signal destinations 818 * * inputs/outputs to Alice2 - see above 819 * 820 * Current status of the driver: 821 * ---------------------------- 822 * * only 44.1/48kHz supported (the MS Win driver supports up to 192 kHz) 823 * * PCM device nb. 2: 824 * 16 x 16-bit playback - snd_emu10k1_fx8010_playback_ops 825 * 16 x 32-bit capture - snd_emu10k1_capture_efx_ops 826 */ 827 static int snd_emu10k1_emu1010_init(struct snd_emu10k1 *emu) 828 { 829 unsigned int i; 830 u32 tmp, tmp2, reg; 831 int err; 832 833 dev_info(emu->card->dev, "emu1010: Special config.\n"); 834 835 /* Mute, and disable audio and lock cache, just in case. 836 * Proper init follows in snd_emu10k1_init(). */ 837 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG); 838 839 /* Disable 48Volt power to Audio Dock */ 840 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0); 841 842 /* ID, should read & 0x7f = 0x55. (Bit 7 is the IRQ bit) */ 843 snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®); 844 dev_dbg(emu->card->dev, "reg1 = 0x%x\n", reg); 845 if ((reg & 0x3f) == 0x15) { 846 /* FPGA netlist already present so clear it */ 847 /* Return to programming mode */ 848 849 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0x02); 850 } 851 snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®); 852 dev_dbg(emu->card->dev, "reg2 = 0x%x\n", reg); 853 if ((reg & 0x3f) == 0x15) { 854 /* FPGA failed to return to programming mode */ 855 dev_info(emu->card->dev, 856 "emu1010: FPGA failed to return to programming mode\n"); 857 return -ENODEV; 858 } 859 dev_info(emu->card->dev, "emu1010: EMU_HANA_ID = 0x%x\n", reg); 860 861 err = snd_emu1010_load_firmware(emu, 0, &emu->firmware); 862 if (err < 0) { 863 dev_info(emu->card->dev, "emu1010: Loading Firmware failed\n"); 864 return err; 865 } 866 867 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */ 868 snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®); 869 if ((reg & 0x3f) != 0x15) { 870 /* FPGA failed to be programmed */ 871 dev_info(emu->card->dev, 872 "emu1010: Loading Hana Firmware file failed, reg = 0x%x\n", 873 reg); 874 return -ENODEV; 875 } 876 877 dev_info(emu->card->dev, "emu1010: Hana Firmware loaded\n"); 878 snd_emu1010_fpga_read(emu, EMU_HANA_MAJOR_REV, &tmp); 879 snd_emu1010_fpga_read(emu, EMU_HANA_MINOR_REV, &tmp2); 880 dev_info(emu->card->dev, "emu1010: Hana version: %u.%u\n", tmp, tmp2); 881 /* Enable 48Volt power to Audio Dock */ 882 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, EMU_HANA_DOCK_PWR_ON); 883 884 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®); 885 dev_info(emu->card->dev, "emu1010: Card options = 0x%x\n", reg); 886 /* Optical -> ADAT I/O */ 887 /* 0 : SPDIF 888 * 1 : ADAT 889 */ 890 emu->emu1010.optical_in = 1; /* IN_ADAT */ 891 emu->emu1010.optical_out = 1; /* IN_ADAT */ 892 tmp = 0; 893 tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : 0) | 894 (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : 0); 895 snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp); 896 /* Set no attenuation on Audio Dock pads. */ 897 snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, 0x00); 898 emu->emu1010.adc_pads = 0x00; 899 /* Unmute Audio dock DACs, Headphone source DAC-4. */ 900 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, 0x30); 901 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12); 902 /* DAC PADs. */ 903 snd_emu1010_fpga_write(emu, EMU_HANA_DAC_PADS, 0x0f); 904 emu->emu1010.dac_pads = 0x0f; 905 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, 0x30); 906 /* SPDIF Format. Set Consumer mode, 24bit, copy enable */ 907 snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, 0x10); 908 /* MIDI routing */ 909 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19); 910 /* Unknown. */ 911 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c); 912 /* IRQ Enable: All on */ 913 /* snd_emu1010_fpga_write(emu, 0x09, 0x0f ); */ 914 /* IRQ Enable: All off */ 915 snd_emu1010_fpga_write(emu, EMU_HANA_IRQ_ENABLE, 0x00); 916 917 /* Default WCLK set to 48kHz. */ 918 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 0x00); 919 /* Word Clock source, Internal 48kHz x1 */ 920 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K); 921 /* snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X); */ 922 /* Audio Dock LEDs. */ 923 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12); 924 925 #if 0 926 /* For 96kHz */ 927 snd_emu1010_fpga_link_dst_src_write(emu, 928 EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1); 929 snd_emu1010_fpga_link_dst_src_write(emu, 930 EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1); 931 snd_emu1010_fpga_link_dst_src_write(emu, 932 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT2); 933 snd_emu1010_fpga_link_dst_src_write(emu, 934 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT2); 935 #endif 936 #if 0 937 /* For 192kHz */ 938 snd_emu1010_fpga_link_dst_src_write(emu, 939 EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1); 940 snd_emu1010_fpga_link_dst_src_write(emu, 941 EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1); 942 snd_emu1010_fpga_link_dst_src_write(emu, 943 EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2); 944 snd_emu1010_fpga_link_dst_src_write(emu, 945 EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_RIGHT2); 946 snd_emu1010_fpga_link_dst_src_write(emu, 947 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT3); 948 snd_emu1010_fpga_link_dst_src_write(emu, 949 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT3); 950 snd_emu1010_fpga_link_dst_src_write(emu, 951 EMU_DST_ALICE2_EMU32_6, EMU_SRC_HAMOA_ADC_LEFT4); 952 snd_emu1010_fpga_link_dst_src_write(emu, 953 EMU_DST_ALICE2_EMU32_7, EMU_SRC_HAMOA_ADC_RIGHT4); 954 #endif 955 #if 1 956 /* For 48kHz */ 957 snd_emu1010_fpga_link_dst_src_write(emu, 958 EMU_DST_ALICE2_EMU32_0, EMU_SRC_DOCK_MIC_A1); 959 snd_emu1010_fpga_link_dst_src_write(emu, 960 EMU_DST_ALICE2_EMU32_1, EMU_SRC_DOCK_MIC_B1); 961 snd_emu1010_fpga_link_dst_src_write(emu, 962 EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2); 963 snd_emu1010_fpga_link_dst_src_write(emu, 964 EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_LEFT2); 965 snd_emu1010_fpga_link_dst_src_write(emu, 966 EMU_DST_ALICE2_EMU32_4, EMU_SRC_DOCK_ADC1_LEFT1); 967 snd_emu1010_fpga_link_dst_src_write(emu, 968 EMU_DST_ALICE2_EMU32_5, EMU_SRC_DOCK_ADC1_RIGHT1); 969 snd_emu1010_fpga_link_dst_src_write(emu, 970 EMU_DST_ALICE2_EMU32_6, EMU_SRC_DOCK_ADC2_LEFT1); 971 snd_emu1010_fpga_link_dst_src_write(emu, 972 EMU_DST_ALICE2_EMU32_7, EMU_SRC_DOCK_ADC2_RIGHT1); 973 /* Pavel Hofman - setting defaults for 8 more capture channels 974 * Defaults only, users will set their own values anyways, let's 975 * just copy/paste. 976 */ 977 978 snd_emu1010_fpga_link_dst_src_write(emu, 979 EMU_DST_ALICE2_EMU32_8, EMU_SRC_DOCK_MIC_A1); 980 snd_emu1010_fpga_link_dst_src_write(emu, 981 EMU_DST_ALICE2_EMU32_9, EMU_SRC_DOCK_MIC_B1); 982 snd_emu1010_fpga_link_dst_src_write(emu, 983 EMU_DST_ALICE2_EMU32_A, EMU_SRC_HAMOA_ADC_LEFT2); 984 snd_emu1010_fpga_link_dst_src_write(emu, 985 EMU_DST_ALICE2_EMU32_B, EMU_SRC_HAMOA_ADC_LEFT2); 986 snd_emu1010_fpga_link_dst_src_write(emu, 987 EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_ADC1_LEFT1); 988 snd_emu1010_fpga_link_dst_src_write(emu, 989 EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_ADC1_RIGHT1); 990 snd_emu1010_fpga_link_dst_src_write(emu, 991 EMU_DST_ALICE2_EMU32_E, EMU_SRC_DOCK_ADC2_LEFT1); 992 snd_emu1010_fpga_link_dst_src_write(emu, 993 EMU_DST_ALICE2_EMU32_F, EMU_SRC_DOCK_ADC2_RIGHT1); 994 #endif 995 #if 0 996 /* Original */ 997 snd_emu1010_fpga_link_dst_src_write(emu, 998 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HANA_ADAT); 999 snd_emu1010_fpga_link_dst_src_write(emu, 1000 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HANA_ADAT + 1); 1001 snd_emu1010_fpga_link_dst_src_write(emu, 1002 EMU_DST_ALICE2_EMU32_6, EMU_SRC_HANA_ADAT + 2); 1003 snd_emu1010_fpga_link_dst_src_write(emu, 1004 EMU_DST_ALICE2_EMU32_7, EMU_SRC_HANA_ADAT + 3); 1005 snd_emu1010_fpga_link_dst_src_write(emu, 1006 EMU_DST_ALICE2_EMU32_8, EMU_SRC_HANA_ADAT + 4); 1007 snd_emu1010_fpga_link_dst_src_write(emu, 1008 EMU_DST_ALICE2_EMU32_9, EMU_SRC_HANA_ADAT + 5); 1009 snd_emu1010_fpga_link_dst_src_write(emu, 1010 EMU_DST_ALICE2_EMU32_A, EMU_SRC_HANA_ADAT + 6); 1011 snd_emu1010_fpga_link_dst_src_write(emu, 1012 EMU_DST_ALICE2_EMU32_B, EMU_SRC_HANA_ADAT + 7); 1013 snd_emu1010_fpga_link_dst_src_write(emu, 1014 EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_MIC_A1); 1015 snd_emu1010_fpga_link_dst_src_write(emu, 1016 EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_MIC_B1); 1017 snd_emu1010_fpga_link_dst_src_write(emu, 1018 EMU_DST_ALICE2_EMU32_E, EMU_SRC_HAMOA_ADC_LEFT2); 1019 snd_emu1010_fpga_link_dst_src_write(emu, 1020 EMU_DST_ALICE2_EMU32_F, EMU_SRC_HAMOA_ADC_LEFT2); 1021 #endif 1022 for (i = 0; i < 0x20; i++) { 1023 /* AudioDock Elink <- Silence */ 1024 snd_emu1010_fpga_link_dst_src_write(emu, 0x0100 + i, EMU_SRC_SILENCE); 1025 } 1026 for (i = 0; i < 4; i++) { 1027 /* Hana SPDIF Out <- Silence */ 1028 snd_emu1010_fpga_link_dst_src_write(emu, 0x0200 + i, EMU_SRC_SILENCE); 1029 } 1030 for (i = 0; i < 7; i++) { 1031 /* Hamoa DAC <- Silence */ 1032 snd_emu1010_fpga_link_dst_src_write(emu, 0x0300 + i, EMU_SRC_SILENCE); 1033 } 1034 for (i = 0; i < 7; i++) { 1035 /* Hana ADAT Out <- Silence */ 1036 snd_emu1010_fpga_link_dst_src_write(emu, EMU_DST_HANA_ADAT + i, EMU_SRC_SILENCE); 1037 } 1038 snd_emu1010_fpga_link_dst_src_write(emu, 1039 EMU_DST_ALICE_I2S0_LEFT, EMU_SRC_DOCK_ADC1_LEFT1); 1040 snd_emu1010_fpga_link_dst_src_write(emu, 1041 EMU_DST_ALICE_I2S0_RIGHT, EMU_SRC_DOCK_ADC1_RIGHT1); 1042 snd_emu1010_fpga_link_dst_src_write(emu, 1043 EMU_DST_ALICE_I2S1_LEFT, EMU_SRC_DOCK_ADC2_LEFT1); 1044 snd_emu1010_fpga_link_dst_src_write(emu, 1045 EMU_DST_ALICE_I2S1_RIGHT, EMU_SRC_DOCK_ADC2_RIGHT1); 1046 snd_emu1010_fpga_link_dst_src_write(emu, 1047 EMU_DST_ALICE_I2S2_LEFT, EMU_SRC_DOCK_ADC3_LEFT1); 1048 snd_emu1010_fpga_link_dst_src_write(emu, 1049 EMU_DST_ALICE_I2S2_RIGHT, EMU_SRC_DOCK_ADC3_RIGHT1); 1050 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x01); /* Unmute all */ 1051 1052 /* Initial boot complete. Now patches */ 1053 1054 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19); /* MIDI Route */ 1055 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c); /* Unknown */ 1056 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19); /* MIDI Route */ 1057 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c); /* Unknown */ 1058 snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, 0x10); /* SPDIF Format spdif (or 0x11 for aes/ebu) */ 1059 1060 #if 0 1061 snd_emu1010_fpga_link_dst_src_write(emu, 1062 EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32B + 2); /* ALICE2 bus 0xa2 */ 1063 snd_emu1010_fpga_link_dst_src_write(emu, 1064 EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32B + 3); /* ALICE2 bus 0xa3 */ 1065 snd_emu1010_fpga_link_dst_src_write(emu, 1066 EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 2); /* ALICE2 bus 0xb2 */ 1067 snd_emu1010_fpga_link_dst_src_write(emu, 1068 EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 3); /* ALICE2 bus 0xb3 */ 1069 #endif 1070 /* Default outputs */ 1071 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616) { 1072 /* 1616(M) cardbus default outputs */ 1073 /* ALICE2 bus 0xa0 */ 1074 snd_emu1010_fpga_link_dst_src_write(emu, 1075 EMU_DST_DOCK_DAC1_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1076 emu->emu1010.output_source[0] = 17; 1077 snd_emu1010_fpga_link_dst_src_write(emu, 1078 EMU_DST_DOCK_DAC1_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1079 emu->emu1010.output_source[1] = 18; 1080 snd_emu1010_fpga_link_dst_src_write(emu, 1081 EMU_DST_DOCK_DAC2_LEFT1, EMU_SRC_ALICE_EMU32A + 2); 1082 emu->emu1010.output_source[2] = 19; 1083 snd_emu1010_fpga_link_dst_src_write(emu, 1084 EMU_DST_DOCK_DAC2_RIGHT1, EMU_SRC_ALICE_EMU32A + 3); 1085 emu->emu1010.output_source[3] = 20; 1086 snd_emu1010_fpga_link_dst_src_write(emu, 1087 EMU_DST_DOCK_DAC3_LEFT1, EMU_SRC_ALICE_EMU32A + 4); 1088 emu->emu1010.output_source[4] = 21; 1089 snd_emu1010_fpga_link_dst_src_write(emu, 1090 EMU_DST_DOCK_DAC3_RIGHT1, EMU_SRC_ALICE_EMU32A + 5); 1091 emu->emu1010.output_source[5] = 22; 1092 /* ALICE2 bus 0xa0 */ 1093 snd_emu1010_fpga_link_dst_src_write(emu, 1094 EMU_DST_MANA_DAC_LEFT, EMU_SRC_ALICE_EMU32A + 0); 1095 emu->emu1010.output_source[16] = 17; 1096 snd_emu1010_fpga_link_dst_src_write(emu, 1097 EMU_DST_MANA_DAC_RIGHT, EMU_SRC_ALICE_EMU32A + 1); 1098 emu->emu1010.output_source[17] = 18; 1099 } else { 1100 /* ALICE2 bus 0xa0 */ 1101 snd_emu1010_fpga_link_dst_src_write(emu, 1102 EMU_DST_DOCK_DAC1_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1103 emu->emu1010.output_source[0] = 21; 1104 snd_emu1010_fpga_link_dst_src_write(emu, 1105 EMU_DST_DOCK_DAC1_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1106 emu->emu1010.output_source[1] = 22; 1107 snd_emu1010_fpga_link_dst_src_write(emu, 1108 EMU_DST_DOCK_DAC2_LEFT1, EMU_SRC_ALICE_EMU32A + 2); 1109 emu->emu1010.output_source[2] = 23; 1110 snd_emu1010_fpga_link_dst_src_write(emu, 1111 EMU_DST_DOCK_DAC2_RIGHT1, EMU_SRC_ALICE_EMU32A + 3); 1112 emu->emu1010.output_source[3] = 24; 1113 snd_emu1010_fpga_link_dst_src_write(emu, 1114 EMU_DST_DOCK_DAC3_LEFT1, EMU_SRC_ALICE_EMU32A + 4); 1115 emu->emu1010.output_source[4] = 25; 1116 snd_emu1010_fpga_link_dst_src_write(emu, 1117 EMU_DST_DOCK_DAC3_RIGHT1, EMU_SRC_ALICE_EMU32A + 5); 1118 emu->emu1010.output_source[5] = 26; 1119 snd_emu1010_fpga_link_dst_src_write(emu, 1120 EMU_DST_DOCK_DAC4_LEFT1, EMU_SRC_ALICE_EMU32A + 6); 1121 emu->emu1010.output_source[6] = 27; 1122 snd_emu1010_fpga_link_dst_src_write(emu, 1123 EMU_DST_DOCK_DAC4_RIGHT1, EMU_SRC_ALICE_EMU32A + 7); 1124 emu->emu1010.output_source[7] = 28; 1125 /* ALICE2 bus 0xa0 */ 1126 snd_emu1010_fpga_link_dst_src_write(emu, 1127 EMU_DST_DOCK_PHONES_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1128 emu->emu1010.output_source[8] = 21; 1129 snd_emu1010_fpga_link_dst_src_write(emu, 1130 EMU_DST_DOCK_PHONES_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1131 emu->emu1010.output_source[9] = 22; 1132 /* ALICE2 bus 0xa0 */ 1133 snd_emu1010_fpga_link_dst_src_write(emu, 1134 EMU_DST_DOCK_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1135 emu->emu1010.output_source[10] = 21; 1136 snd_emu1010_fpga_link_dst_src_write(emu, 1137 EMU_DST_DOCK_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1138 emu->emu1010.output_source[11] = 22; 1139 /* ALICE2 bus 0xa0 */ 1140 snd_emu1010_fpga_link_dst_src_write(emu, 1141 EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1142 emu->emu1010.output_source[12] = 21; 1143 snd_emu1010_fpga_link_dst_src_write(emu, 1144 EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1145 emu->emu1010.output_source[13] = 22; 1146 /* ALICE2 bus 0xa0 */ 1147 snd_emu1010_fpga_link_dst_src_write(emu, 1148 EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32A + 0); 1149 emu->emu1010.output_source[14] = 21; 1150 snd_emu1010_fpga_link_dst_src_write(emu, 1151 EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32A + 1); 1152 emu->emu1010.output_source[15] = 22; 1153 /* ALICE2 bus 0xa0 */ 1154 snd_emu1010_fpga_link_dst_src_write(emu, 1155 EMU_DST_HANA_ADAT, EMU_SRC_ALICE_EMU32A + 0); 1156 emu->emu1010.output_source[16] = 21; 1157 snd_emu1010_fpga_link_dst_src_write(emu, 1158 EMU_DST_HANA_ADAT + 1, EMU_SRC_ALICE_EMU32A + 1); 1159 emu->emu1010.output_source[17] = 22; 1160 snd_emu1010_fpga_link_dst_src_write(emu, 1161 EMU_DST_HANA_ADAT + 2, EMU_SRC_ALICE_EMU32A + 2); 1162 emu->emu1010.output_source[18] = 23; 1163 snd_emu1010_fpga_link_dst_src_write(emu, 1164 EMU_DST_HANA_ADAT + 3, EMU_SRC_ALICE_EMU32A + 3); 1165 emu->emu1010.output_source[19] = 24; 1166 snd_emu1010_fpga_link_dst_src_write(emu, 1167 EMU_DST_HANA_ADAT + 4, EMU_SRC_ALICE_EMU32A + 4); 1168 emu->emu1010.output_source[20] = 25; 1169 snd_emu1010_fpga_link_dst_src_write(emu, 1170 EMU_DST_HANA_ADAT + 5, EMU_SRC_ALICE_EMU32A + 5); 1171 emu->emu1010.output_source[21] = 26; 1172 snd_emu1010_fpga_link_dst_src_write(emu, 1173 EMU_DST_HANA_ADAT + 6, EMU_SRC_ALICE_EMU32A + 6); 1174 emu->emu1010.output_source[22] = 27; 1175 snd_emu1010_fpga_link_dst_src_write(emu, 1176 EMU_DST_HANA_ADAT + 7, EMU_SRC_ALICE_EMU32A + 7); 1177 emu->emu1010.output_source[23] = 28; 1178 } 1179 /* TEMP: Select SPDIF in/out */ 1180 /* snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, 0x0); */ /* Output spdif */ 1181 1182 /* TEMP: Select 48kHz SPDIF out */ 1183 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x0); /* Mute all */ 1184 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 0x0); /* Default fallback clock 48kHz */ 1185 /* Word Clock source, Internal 48kHz x1 */ 1186 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K); 1187 /* snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X); */ 1188 emu->emu1010.internal_clock = 1; /* 48000 */ 1189 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12); /* Set LEDs on Audio Dock */ 1190 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x1); /* Unmute all */ 1191 /* snd_emu1010_fpga_write(emu, 0x7, 0x0); */ /* Mute all */ 1192 /* snd_emu1010_fpga_write(emu, 0x7, 0x1); */ /* Unmute all */ 1193 /* snd_emu1010_fpga_write(emu, 0xe, 0x12); */ /* Set LEDs on Audio Dock */ 1194 1195 return 0; 1196 } 1197 /* 1198 * Create the EMU10K1 instance 1199 */ 1200 1201 #ifdef CONFIG_PM_SLEEP 1202 static int alloc_pm_buffer(struct snd_emu10k1 *emu); 1203 static void free_pm_buffer(struct snd_emu10k1 *emu); 1204 #endif 1205 1206 static void snd_emu10k1_free(struct snd_card *card) 1207 { 1208 struct snd_emu10k1 *emu = card->private_data; 1209 1210 if (emu->port) { /* avoid access to already used hardware */ 1211 snd_emu10k1_fx8010_tram_setup(emu, 0); 1212 snd_emu10k1_done(emu); 1213 snd_emu10k1_free_efx(emu); 1214 } 1215 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1010) { 1216 /* Disable 48Volt power to Audio Dock */ 1217 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0); 1218 } 1219 cancel_delayed_work_sync(&emu->emu1010.firmware_work); 1220 release_firmware(emu->firmware); 1221 release_firmware(emu->dock_fw); 1222 snd_util_memhdr_free(emu->memhdr); 1223 if (emu->silent_page.area) 1224 snd_dma_free_pages(&emu->silent_page); 1225 if (emu->ptb_pages.area) 1226 snd_dma_free_pages(&emu->ptb_pages); 1227 vfree(emu->page_ptr_table); 1228 vfree(emu->page_addr_table); 1229 #ifdef CONFIG_PM_SLEEP 1230 free_pm_buffer(emu); 1231 #endif 1232 } 1233 1234 static const struct snd_emu_chip_details emu_chip_details[] = { 1235 /* Audigy 5/Rx SB1550 */ 1236 /* Tested by michael@gernoth.net 28 Mar 2015 */ 1237 /* DSP: CA10300-IAT LF 1238 * DAC: Cirrus Logic CS4382-KQZ 1239 * ADC: Philips 1361T 1240 * AC97: Sigmatel STAC9750 1241 * CA0151: None 1242 */ 1243 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10241102, 1244 .driver = "Audigy2", .name = "SB Audigy 5/Rx [SB1550]", 1245 .id = "Audigy2", 1246 .emu10k2_chip = 1, 1247 .ca0108_chip = 1, 1248 .spk71 = 1, 1249 .adc_1361t = 1, /* 24 bit capture instead of 16bit */ 1250 .ac97_chip = 1}, 1251 /* Audigy4 (Not PRO) SB0610 */ 1252 /* Tested by James@superbug.co.uk 4th April 2006 */ 1253 /* A_IOCFG bits 1254 * Output 1255 * 0: ? 1256 * 1: ? 1257 * 2: ? 1258 * 3: 0 - Digital Out, 1 - Line in 1259 * 4: ? 1260 * 5: ? 1261 * 6: ? 1262 * 7: ? 1263 * Input 1264 * 8: ? 1265 * 9: ? 1266 * A: Green jack sense (Front) 1267 * B: ? 1268 * C: Black jack sense (Rear/Side Right) 1269 * D: Yellow jack sense (Center/LFE/Side Left) 1270 * E: ? 1271 * F: ? 1272 * 1273 * Digital Out/Line in switch using A_IOCFG bit 3 (0x08) 1274 * 0 - Digital Out 1275 * 1 - Line in 1276 */ 1277 /* Mic input not tested. 1278 * Analog CD input not tested 1279 * Digital Out not tested. 1280 * Line in working. 1281 * Audio output 5.1 working. Side outputs not working. 1282 */ 1283 /* DSP: CA10300-IAT LF 1284 * DAC: Cirrus Logic CS4382-KQZ 1285 * ADC: Philips 1361T 1286 * AC97: Sigmatel STAC9750 1287 * CA0151: None 1288 */ 1289 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10211102, 1290 .driver = "Audigy2", .name = "SB Audigy 4 [SB0610]", 1291 .id = "Audigy2", 1292 .emu10k2_chip = 1, 1293 .ca0108_chip = 1, 1294 .spk71 = 1, 1295 .adc_1361t = 1, /* 24 bit capture instead of 16bit */ 1296 .ac97_chip = 1} , 1297 /* Audigy 2 Value AC3 out does not work yet. 1298 * Need to find out how to turn off interpolators. 1299 */ 1300 /* Tested by James@superbug.co.uk 3rd July 2005 */ 1301 /* DSP: CA0108-IAT 1302 * DAC: CS4382-KQ 1303 * ADC: Philips 1361T 1304 * AC97: STAC9750 1305 * CA0151: None 1306 */ 1307 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10011102, 1308 .driver = "Audigy2", .name = "SB Audigy 2 Value [SB0400]", 1309 .id = "Audigy2", 1310 .emu10k2_chip = 1, 1311 .ca0108_chip = 1, 1312 .spk71 = 1, 1313 .ac97_chip = 1} , 1314 /* Audigy 2 ZS Notebook Cardbus card.*/ 1315 /* Tested by James@superbug.co.uk 6th November 2006 */ 1316 /* Audio output 7.1/Headphones working. 1317 * Digital output working. (AC3 not checked, only PCM) 1318 * Audio Mic/Line inputs working. 1319 * Digital input not tested. 1320 */ 1321 /* DSP: Tina2 1322 * DAC: Wolfson WM8768/WM8568 1323 * ADC: Wolfson WM8775 1324 * AC97: None 1325 * CA0151: None 1326 */ 1327 /* Tested by James@superbug.co.uk 4th April 2006 */ 1328 /* A_IOCFG bits 1329 * Output 1330 * 0: Not Used 1331 * 1: 0 = Mute all the 7.1 channel out. 1 = unmute. 1332 * 2: Analog input 0 = line in, 1 = mic in 1333 * 3: Not Used 1334 * 4: Digital output 0 = off, 1 = on. 1335 * 5: Not Used 1336 * 6: Not Used 1337 * 7: Not Used 1338 * Input 1339 * All bits 1 (0x3fxx) means nothing plugged in. 1340 * 8-9: 0 = Line in/Mic, 2 = Optical in, 3 = Nothing. 1341 * A-B: 0 = Headphones, 2 = Optical out, 3 = Nothing. 1342 * C-D: 2 = Front/Rear/etc, 3 = nothing. 1343 * E-F: Always 0 1344 * 1345 */ 1346 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x20011102, 1347 .driver = "Audigy2", .name = "Audigy 2 ZS Notebook [SB0530]", 1348 .id = "Audigy2", 1349 .emu10k2_chip = 1, 1350 .ca0108_chip = 1, 1351 .ca_cardbus_chip = 1, 1352 .spi_dac = 1, 1353 .i2c_adc = 1, 1354 .spk71 = 1} , 1355 /* Tested by James@superbug.co.uk 4th Nov 2007. */ 1356 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x42011102, 1357 .driver = "Audigy2", .name = "E-mu 1010 Notebook [MAEM8950]", 1358 .id = "EMU1010", 1359 .emu10k2_chip = 1, 1360 .ca0108_chip = 1, 1361 .ca_cardbus_chip = 1, 1362 .spk71 = 1 , 1363 .emu_model = EMU_MODEL_EMU1616}, 1364 /* Tested by James@superbug.co.uk 4th Nov 2007. */ 1365 /* This is MAEM8960, 0202 is MAEM 8980 */ 1366 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40041102, 1367 .driver = "Audigy2", .name = "E-mu 1010b PCI [MAEM8960]", 1368 .id = "EMU1010", 1369 .emu10k2_chip = 1, 1370 .ca0108_chip = 1, 1371 .spk71 = 1, 1372 .emu_model = EMU_MODEL_EMU1010B}, /* EMU 1010 new revision */ 1373 /* Tested by Maxim Kachur <mcdebugger@duganet.ru> 17th Oct 2012. */ 1374 /* This is MAEM8986, 0202 is MAEM8980 */ 1375 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40071102, 1376 .driver = "Audigy2", .name = "E-mu 1010 PCIe [MAEM8986]", 1377 .id = "EMU1010", 1378 .emu10k2_chip = 1, 1379 .ca0108_chip = 1, 1380 .spk71 = 1, 1381 .emu_model = EMU_MODEL_EMU1010B}, /* EMU 1010 PCIe */ 1382 /* Tested by James@superbug.co.uk 8th July 2005. */ 1383 /* This is MAEM8810, 0202 is MAEM8820 */ 1384 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40011102, 1385 .driver = "Audigy2", .name = "E-mu 1010 [MAEM8810]", 1386 .id = "EMU1010", 1387 .emu10k2_chip = 1, 1388 .ca0102_chip = 1, 1389 .spk71 = 1, 1390 .emu_model = EMU_MODEL_EMU1010}, /* EMU 1010 old revision */ 1391 /* EMU0404b */ 1392 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40021102, 1393 .driver = "Audigy2", .name = "E-mu 0404b PCI [MAEM8852]", 1394 .id = "EMU0404", 1395 .emu10k2_chip = 1, 1396 .ca0108_chip = 1, 1397 .spk71 = 1, 1398 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 new revision */ 1399 /* Tested by James@superbug.co.uk 20-3-2007. */ 1400 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40021102, 1401 .driver = "Audigy2", .name = "E-mu 0404 [MAEM8850]", 1402 .id = "EMU0404", 1403 .emu10k2_chip = 1, 1404 .ca0102_chip = 1, 1405 .spk71 = 1, 1406 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 */ 1407 /* EMU0404 PCIe */ 1408 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40051102, 1409 .driver = "Audigy2", .name = "E-mu 0404 PCIe [MAEM8984]", 1410 .id = "EMU0404", 1411 .emu10k2_chip = 1, 1412 .ca0108_chip = 1, 1413 .spk71 = 1, 1414 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 PCIe ver_03 */ 1415 /* Note that all E-mu cards require kernel 2.6 or newer. */ 1416 {.vendor = 0x1102, .device = 0x0008, 1417 .driver = "Audigy2", .name = "SB Audigy 2 Value [Unknown]", 1418 .id = "Audigy2", 1419 .emu10k2_chip = 1, 1420 .ca0108_chip = 1, 1421 .ac97_chip = 1} , 1422 /* Tested by James@superbug.co.uk 3rd July 2005 */ 1423 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20071102, 1424 .driver = "Audigy2", .name = "SB Audigy 4 PRO [SB0380]", 1425 .id = "Audigy2", 1426 .emu10k2_chip = 1, 1427 .ca0102_chip = 1, 1428 .ca0151_chip = 1, 1429 .spk71 = 1, 1430 .spdif_bug = 1, 1431 .ac97_chip = 1} , 1432 /* Tested by shane-alsa@cm.nu 5th Nov 2005 */ 1433 /* The 0x20061102 does have SB0350 written on it 1434 * Just like 0x20021102 1435 */ 1436 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20061102, 1437 .driver = "Audigy2", .name = "SB Audigy 2 [SB0350b]", 1438 .id = "Audigy2", 1439 .emu10k2_chip = 1, 1440 .ca0102_chip = 1, 1441 .ca0151_chip = 1, 1442 .spk71 = 1, 1443 .spdif_bug = 1, 1444 .invert_shared_spdif = 1, /* digital/analog switch swapped */ 1445 .ac97_chip = 1} , 1446 /* 0x20051102 also has SB0350 written on it, treated as Audigy 2 ZS by 1447 Creative's Windows driver */ 1448 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20051102, 1449 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0350a]", 1450 .id = "Audigy2", 1451 .emu10k2_chip = 1, 1452 .ca0102_chip = 1, 1453 .ca0151_chip = 1, 1454 .spk71 = 1, 1455 .spdif_bug = 1, 1456 .invert_shared_spdif = 1, /* digital/analog switch swapped */ 1457 .ac97_chip = 1} , 1458 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20021102, 1459 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0350]", 1460 .id = "Audigy2", 1461 .emu10k2_chip = 1, 1462 .ca0102_chip = 1, 1463 .ca0151_chip = 1, 1464 .spk71 = 1, 1465 .spdif_bug = 1, 1466 .invert_shared_spdif = 1, /* digital/analog switch swapped */ 1467 .ac97_chip = 1} , 1468 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20011102, 1469 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0360]", 1470 .id = "Audigy2", 1471 .emu10k2_chip = 1, 1472 .ca0102_chip = 1, 1473 .ca0151_chip = 1, 1474 .spk71 = 1, 1475 .spdif_bug = 1, 1476 .invert_shared_spdif = 1, /* digital/analog switch swapped */ 1477 .ac97_chip = 1} , 1478 /* Audigy 2 */ 1479 /* Tested by James@superbug.co.uk 3rd July 2005 */ 1480 /* DSP: CA0102-IAT 1481 * DAC: CS4382-KQ 1482 * ADC: Philips 1361T 1483 * AC97: STAC9721 1484 * CA0151: Yes 1485 */ 1486 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10071102, 1487 .driver = "Audigy2", .name = "SB Audigy 2 [SB0240]", 1488 .id = "Audigy2", 1489 .emu10k2_chip = 1, 1490 .ca0102_chip = 1, 1491 .ca0151_chip = 1, 1492 .spk71 = 1, 1493 .spdif_bug = 1, 1494 .adc_1361t = 1, /* 24 bit capture instead of 16bit */ 1495 .ac97_chip = 1} , 1496 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10051102, 1497 .driver = "Audigy2", .name = "Audigy 2 Platinum EX [SB0280]", 1498 .id = "Audigy2", 1499 .emu10k2_chip = 1, 1500 .ca0102_chip = 1, 1501 .ca0151_chip = 1, 1502 .spk71 = 1, 1503 .spdif_bug = 1} , 1504 /* Dell OEM/Creative Labs Audigy 2 ZS */ 1505 /* See ALSA bug#1365 */ 1506 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10031102, 1507 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0353]", 1508 .id = "Audigy2", 1509 .emu10k2_chip = 1, 1510 .ca0102_chip = 1, 1511 .ca0151_chip = 1, 1512 .spk71 = 1, 1513 .spdif_bug = 1, 1514 .invert_shared_spdif = 1, /* digital/analog switch swapped */ 1515 .ac97_chip = 1} , 1516 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10021102, 1517 .driver = "Audigy2", .name = "SB Audigy 2 Platinum [SB0240P]", 1518 .id = "Audigy2", 1519 .emu10k2_chip = 1, 1520 .ca0102_chip = 1, 1521 .ca0151_chip = 1, 1522 .spk71 = 1, 1523 .spdif_bug = 1, 1524 .invert_shared_spdif = 1, /* digital/analog switch swapped */ 1525 .adc_1361t = 1, /* 24 bit capture instead of 16bit. Fixes ALSA bug#324 */ 1526 .ac97_chip = 1} , 1527 {.vendor = 0x1102, .device = 0x0004, .revision = 0x04, 1528 .driver = "Audigy2", .name = "SB Audigy 2 [Unknown]", 1529 .id = "Audigy2", 1530 .emu10k2_chip = 1, 1531 .ca0102_chip = 1, 1532 .ca0151_chip = 1, 1533 .spdif_bug = 1, 1534 .ac97_chip = 1} , 1535 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00531102, 1536 .driver = "Audigy", .name = "SB Audigy 1 [SB0092]", 1537 .id = "Audigy", 1538 .emu10k2_chip = 1, 1539 .ca0102_chip = 1, 1540 .ac97_chip = 1} , 1541 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00521102, 1542 .driver = "Audigy", .name = "SB Audigy 1 ES [SB0160]", 1543 .id = "Audigy", 1544 .emu10k2_chip = 1, 1545 .ca0102_chip = 1, 1546 .spdif_bug = 1, 1547 .ac97_chip = 1} , 1548 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00511102, 1549 .driver = "Audigy", .name = "SB Audigy 1 [SB0090]", 1550 .id = "Audigy", 1551 .emu10k2_chip = 1, 1552 .ca0102_chip = 1, 1553 .ac97_chip = 1} , 1554 {.vendor = 0x1102, .device = 0x0004, 1555 .driver = "Audigy", .name = "Audigy 1 [Unknown]", 1556 .id = "Audigy", 1557 .emu10k2_chip = 1, 1558 .ca0102_chip = 1, 1559 .ac97_chip = 1} , 1560 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x100a1102, 1561 .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0220]", 1562 .id = "Live", 1563 .emu10k1_chip = 1, 1564 .ac97_chip = 1, 1565 .sblive51 = 1} , 1566 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806b1102, 1567 .driver = "EMU10K1", .name = "SB Live! [SB0105]", 1568 .id = "Live", 1569 .emu10k1_chip = 1, 1570 .ac97_chip = 1, 1571 .sblive51 = 1} , 1572 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806a1102, 1573 .driver = "EMU10K1", .name = "SB Live! Value [SB0103]", 1574 .id = "Live", 1575 .emu10k1_chip = 1, 1576 .ac97_chip = 1, 1577 .sblive51 = 1} , 1578 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80691102, 1579 .driver = "EMU10K1", .name = "SB Live! Value [SB0101]", 1580 .id = "Live", 1581 .emu10k1_chip = 1, 1582 .ac97_chip = 1, 1583 .sblive51 = 1} , 1584 /* Tested by ALSA bug#1680 26th December 2005 */ 1585 /* note: It really has SB0220 written on the card, */ 1586 /* but it's SB0228 according to kx.inf */ 1587 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80661102, 1588 .driver = "EMU10K1", .name = "SB Live! 5.1 Dell OEM [SB0228]", 1589 .id = "Live", 1590 .emu10k1_chip = 1, 1591 .ac97_chip = 1, 1592 .sblive51 = 1} , 1593 /* Tested by Thomas Zehetbauer 27th Aug 2005 */ 1594 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80651102, 1595 .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0220]", 1596 .id = "Live", 1597 .emu10k1_chip = 1, 1598 .ac97_chip = 1, 1599 .sblive51 = 1} , 1600 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80641102, 1601 .driver = "EMU10K1", .name = "SB Live! 5.1", 1602 .id = "Live", 1603 .emu10k1_chip = 1, 1604 .ac97_chip = 1, 1605 .sblive51 = 1} , 1606 /* Tested by alsa bugtrack user "hus" bug #1297 12th Aug 2005 */ 1607 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80611102, 1608 .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0060]", 1609 .id = "Live", 1610 .emu10k1_chip = 1, 1611 .ac97_chip = 2, /* ac97 is optional; both SBLive 5.1 and platinum 1612 * share the same IDs! 1613 */ 1614 .sblive51 = 1} , 1615 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80511102, 1616 .driver = "EMU10K1", .name = "SB Live! Value [CT4850]", 1617 .id = "Live", 1618 .emu10k1_chip = 1, 1619 .ac97_chip = 1, 1620 .sblive51 = 1} , 1621 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80401102, 1622 .driver = "EMU10K1", .name = "SB Live! Platinum [CT4760P]", 1623 .id = "Live", 1624 .emu10k1_chip = 1, 1625 .ac97_chip = 1} , 1626 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80321102, 1627 .driver = "EMU10K1", .name = "SB Live! Value [CT4871]", 1628 .id = "Live", 1629 .emu10k1_chip = 1, 1630 .ac97_chip = 1, 1631 .sblive51 = 1} , 1632 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80311102, 1633 .driver = "EMU10K1", .name = "SB Live! Value [CT4831]", 1634 .id = "Live", 1635 .emu10k1_chip = 1, 1636 .ac97_chip = 1, 1637 .sblive51 = 1} , 1638 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80281102, 1639 .driver = "EMU10K1", .name = "SB Live! Value [CT4870]", 1640 .id = "Live", 1641 .emu10k1_chip = 1, 1642 .ac97_chip = 1, 1643 .sblive51 = 1} , 1644 /* Tested by James@superbug.co.uk 3rd July 2005 */ 1645 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80271102, 1646 .driver = "EMU10K1", .name = "SB Live! Value [CT4832]", 1647 .id = "Live", 1648 .emu10k1_chip = 1, 1649 .ac97_chip = 1, 1650 .sblive51 = 1} , 1651 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80261102, 1652 .driver = "EMU10K1", .name = "SB Live! Value [CT4830]", 1653 .id = "Live", 1654 .emu10k1_chip = 1, 1655 .ac97_chip = 1, 1656 .sblive51 = 1} , 1657 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80231102, 1658 .driver = "EMU10K1", .name = "SB PCI512 [CT4790]", 1659 .id = "Live", 1660 .emu10k1_chip = 1, 1661 .ac97_chip = 1, 1662 .sblive51 = 1} , 1663 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80221102, 1664 .driver = "EMU10K1", .name = "SB Live! Value [CT4780]", 1665 .id = "Live", 1666 .emu10k1_chip = 1, 1667 .ac97_chip = 1, 1668 .sblive51 = 1} , 1669 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x40011102, 1670 .driver = "EMU10K1", .name = "E-mu APS [PC545]", 1671 .id = "APS", 1672 .emu10k1_chip = 1, 1673 .ecard = 1} , 1674 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00211102, 1675 .driver = "EMU10K1", .name = "SB Live! [CT4620]", 1676 .id = "Live", 1677 .emu10k1_chip = 1, 1678 .ac97_chip = 1, 1679 .sblive51 = 1} , 1680 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00201102, 1681 .driver = "EMU10K1", .name = "SB Live! Value [CT4670]", 1682 .id = "Live", 1683 .emu10k1_chip = 1, 1684 .ac97_chip = 1, 1685 .sblive51 = 1} , 1686 {.vendor = 0x1102, .device = 0x0002, 1687 .driver = "EMU10K1", .name = "SB Live! [Unknown]", 1688 .id = "Live", 1689 .emu10k1_chip = 1, 1690 .ac97_chip = 1, 1691 .sblive51 = 1} , 1692 { } /* terminator */ 1693 }; 1694 1695 /* 1696 * The chip (at least the Audigy 2 CA0102 chip, but most likely others, too) 1697 * has a problem that from time to time it likes to do few DMA reads a bit 1698 * beyond its normal allocation and gets very confused if these reads get 1699 * blocked by a IOMMU. 1700 * 1701 * This behaviour has been observed for the first (reserved) page 1702 * (for which it happens multiple times at every playback), often for various 1703 * synth pages and sometimes for PCM playback buffers and the page table 1704 * memory itself. 1705 * 1706 * As a workaround let's widen these DMA allocations by an extra page if we 1707 * detect that the device is behind a non-passthrough IOMMU. 1708 */ 1709 static void snd_emu10k1_detect_iommu(struct snd_emu10k1 *emu) 1710 { 1711 struct iommu_domain *domain; 1712 1713 emu->iommu_workaround = false; 1714 1715 domain = iommu_get_domain_for_dev(emu->card->dev); 1716 if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY) 1717 return; 1718 1719 dev_notice(emu->card->dev, 1720 "non-passthrough IOMMU detected, widening DMA allocations"); 1721 emu->iommu_workaround = true; 1722 } 1723 1724 int snd_emu10k1_create(struct snd_card *card, 1725 struct pci_dev *pci, 1726 unsigned short extin_mask, 1727 unsigned short extout_mask, 1728 long max_cache_bytes, 1729 int enable_ir, 1730 uint subsystem) 1731 { 1732 struct snd_emu10k1 *emu = card->private_data; 1733 int idx, err; 1734 int is_audigy; 1735 size_t page_table_size; 1736 __le32 *pgtbl; 1737 unsigned int silent_page; 1738 const struct snd_emu_chip_details *c; 1739 1740 /* enable PCI device */ 1741 err = pcim_enable_device(pci); 1742 if (err < 0) 1743 return err; 1744 1745 card->private_free = snd_emu10k1_free; 1746 emu->card = card; 1747 spin_lock_init(&emu->reg_lock); 1748 spin_lock_init(&emu->emu_lock); 1749 spin_lock_init(&emu->spi_lock); 1750 spin_lock_init(&emu->i2c_lock); 1751 spin_lock_init(&emu->voice_lock); 1752 spin_lock_init(&emu->synth_lock); 1753 spin_lock_init(&emu->memblk_lock); 1754 mutex_init(&emu->fx8010.lock); 1755 INIT_LIST_HEAD(&emu->mapped_link_head); 1756 INIT_LIST_HEAD(&emu->mapped_order_link_head); 1757 emu->pci = pci; 1758 emu->irq = -1; 1759 emu->synth = NULL; 1760 emu->get_synth_voice = NULL; 1761 INIT_DELAYED_WORK(&emu->emu1010.firmware_work, emu1010_firmware_work); 1762 /* read revision & serial */ 1763 emu->revision = pci->revision; 1764 pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &emu->serial); 1765 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &emu->model); 1766 dev_dbg(card->dev, 1767 "vendor = 0x%x, device = 0x%x, subsystem_vendor_id = 0x%x, subsystem_id = 0x%x\n", 1768 pci->vendor, pci->device, emu->serial, emu->model); 1769 1770 for (c = emu_chip_details; c->vendor; c++) { 1771 if (c->vendor == pci->vendor && c->device == pci->device) { 1772 if (subsystem) { 1773 if (c->subsystem && (c->subsystem == subsystem)) 1774 break; 1775 else 1776 continue; 1777 } else { 1778 if (c->subsystem && (c->subsystem != emu->serial)) 1779 continue; 1780 if (c->revision && c->revision != emu->revision) 1781 continue; 1782 } 1783 break; 1784 } 1785 } 1786 if (c->vendor == 0) { 1787 dev_err(card->dev, "emu10k1: Card not recognised\n"); 1788 return -ENOENT; 1789 } 1790 emu->card_capabilities = c; 1791 if (c->subsystem && !subsystem) 1792 dev_dbg(card->dev, "Sound card name = %s\n", c->name); 1793 else if (subsystem) 1794 dev_dbg(card->dev, "Sound card name = %s, " 1795 "vendor = 0x%x, device = 0x%x, subsystem = 0x%x. " 1796 "Forced to subsystem = 0x%x\n", c->name, 1797 pci->vendor, pci->device, emu->serial, c->subsystem); 1798 else 1799 dev_dbg(card->dev, "Sound card name = %s, " 1800 "vendor = 0x%x, device = 0x%x, subsystem = 0x%x.\n", 1801 c->name, pci->vendor, pci->device, 1802 emu->serial); 1803 1804 if (!*card->id && c->id) 1805 strscpy(card->id, c->id, sizeof(card->id)); 1806 1807 is_audigy = emu->audigy = c->emu10k2_chip; 1808 1809 snd_emu10k1_detect_iommu(emu); 1810 1811 /* set addressing mode */ 1812 emu->address_mode = is_audigy ? 0 : 1; 1813 /* set the DMA transfer mask */ 1814 emu->dma_mask = emu->address_mode ? EMU10K1_DMA_MASK : AUDIGY_DMA_MASK; 1815 if (dma_set_mask_and_coherent(&pci->dev, emu->dma_mask) < 0) { 1816 dev_err(card->dev, 1817 "architecture does not support PCI busmaster DMA with mask 0x%lx\n", 1818 emu->dma_mask); 1819 return -ENXIO; 1820 } 1821 if (is_audigy) 1822 emu->gpr_base = A_FXGPREGBASE; 1823 else 1824 emu->gpr_base = FXGPREGBASE; 1825 1826 err = pci_request_regions(pci, "EMU10K1"); 1827 if (err < 0) 1828 return err; 1829 emu->port = pci_resource_start(pci, 0); 1830 1831 emu->max_cache_pages = max_cache_bytes >> PAGE_SHIFT; 1832 1833 page_table_size = sizeof(u32) * (emu->address_mode ? MAXPAGES1 : 1834 MAXPAGES0); 1835 if (snd_emu10k1_alloc_pages_maybe_wider(emu, page_table_size, 1836 &emu->ptb_pages) < 0) 1837 return -ENOMEM; 1838 dev_dbg(card->dev, "page table address range is %.8lx:%.8lx\n", 1839 (unsigned long)emu->ptb_pages.addr, 1840 (unsigned long)(emu->ptb_pages.addr + emu->ptb_pages.bytes)); 1841 1842 emu->page_ptr_table = vmalloc(array_size(sizeof(void *), 1843 emu->max_cache_pages)); 1844 emu->page_addr_table = vmalloc(array_size(sizeof(unsigned long), 1845 emu->max_cache_pages)); 1846 if (!emu->page_ptr_table || !emu->page_addr_table) 1847 return -ENOMEM; 1848 1849 if (snd_emu10k1_alloc_pages_maybe_wider(emu, EMUPAGESIZE, 1850 &emu->silent_page) < 0) 1851 return -ENOMEM; 1852 dev_dbg(card->dev, "silent page range is %.8lx:%.8lx\n", 1853 (unsigned long)emu->silent_page.addr, 1854 (unsigned long)(emu->silent_page.addr + 1855 emu->silent_page.bytes)); 1856 1857 emu->memhdr = snd_util_memhdr_new(emu->max_cache_pages * PAGE_SIZE); 1858 if (!emu->memhdr) 1859 return -ENOMEM; 1860 emu->memhdr->block_extra_size = sizeof(struct snd_emu10k1_memblk) - 1861 sizeof(struct snd_util_memblk); 1862 1863 pci_set_master(pci); 1864 1865 // The masks are not used for Audigy. 1866 // FIXME: these should come from the card_capabilites table. 1867 if (extin_mask == 0) 1868 extin_mask = 0x3fcf; // EXTIN_* 1869 if (extout_mask == 0) 1870 extout_mask = 0x7fff; // EXTOUT_* 1871 emu->fx8010.extin_mask = extin_mask; 1872 emu->fx8010.extout_mask = extout_mask; 1873 emu->enable_ir = enable_ir; 1874 1875 if (emu->card_capabilities->ca_cardbus_chip) { 1876 err = snd_emu10k1_cardbus_init(emu); 1877 if (err < 0) 1878 return err; 1879 } 1880 if (emu->card_capabilities->ecard) { 1881 err = snd_emu10k1_ecard_init(emu); 1882 if (err < 0) 1883 return err; 1884 } else if (emu->card_capabilities->emu_model) { 1885 err = snd_emu10k1_emu1010_init(emu); 1886 if (err < 0) 1887 return err; 1888 } else { 1889 /* 5.1: Enable the additional AC97 Slots. If the emu10k1 version 1890 does not support this, it shouldn't do any harm */ 1891 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, 1892 AC97SLOT_CNTR|AC97SLOT_LFE); 1893 } 1894 1895 /* initialize TRAM setup */ 1896 emu->fx8010.itram_size = (16 * 1024)/2; 1897 emu->fx8010.etram_pages.area = NULL; 1898 emu->fx8010.etram_pages.bytes = 0; 1899 1900 /* irq handler must be registered after I/O ports are activated */ 1901 if (devm_request_irq(&pci->dev, pci->irq, snd_emu10k1_interrupt, 1902 IRQF_SHARED, KBUILD_MODNAME, emu)) 1903 return -EBUSY; 1904 emu->irq = pci->irq; 1905 card->sync_irq = emu->irq; 1906 1907 /* 1908 * Init to 0x02109204 : 1909 * Clock accuracy = 0 (1000ppm) 1910 * Sample Rate = 2 (48kHz) 1911 * Audio Channel = 1 (Left of 2) 1912 * Source Number = 0 (Unspecified) 1913 * Generation Status = 1 (Original for Cat Code 12) 1914 * Cat Code = 12 (Digital Signal Mixer) 1915 * Mode = 0 (Mode 0) 1916 * Emphasis = 0 (None) 1917 * CP = 1 (Copyright unasserted) 1918 * AN = 0 (Audio data) 1919 * P = 0 (Consumer) 1920 */ 1921 emu->spdif_bits[0] = emu->spdif_bits[1] = 1922 emu->spdif_bits[2] = SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 | 1923 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC | 1924 SPCS_GENERATIONSTATUS | 0x00001200 | 1925 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT; 1926 1927 /* Clear silent pages and set up pointers */ 1928 memset(emu->silent_page.area, 0, emu->silent_page.bytes); 1929 silent_page = emu->silent_page.addr << emu->address_mode; 1930 pgtbl = (__le32 *)emu->ptb_pages.area; 1931 for (idx = 0; idx < (emu->address_mode ? MAXPAGES1 : MAXPAGES0); idx++) 1932 pgtbl[idx] = cpu_to_le32(silent_page | idx); 1933 1934 /* set up voice indices */ 1935 for (idx = 0; idx < NUM_G; idx++) 1936 emu->voices[idx].number = idx; 1937 1938 err = snd_emu10k1_init(emu, enable_ir, 0); 1939 if (err < 0) 1940 return err; 1941 #ifdef CONFIG_PM_SLEEP 1942 err = alloc_pm_buffer(emu); 1943 if (err < 0) 1944 return err; 1945 #endif 1946 1947 /* Initialize the effect engine */ 1948 err = snd_emu10k1_init_efx(emu); 1949 if (err < 0) 1950 return err; 1951 snd_emu10k1_audio_enable(emu); 1952 1953 #ifdef CONFIG_SND_PROC_FS 1954 snd_emu10k1_proc_init(emu); 1955 #endif 1956 return 0; 1957 } 1958 1959 #ifdef CONFIG_PM_SLEEP 1960 static const unsigned char saved_regs[] = { 1961 CPF, PTRX, CVCF, VTFT, Z1, Z2, PSST, DSL, CCCA, CCR, CLP, 1962 FXRT, MAPA, MAPB, ENVVOL, ATKHLDV, DCYSUSV, LFOVAL1, ENVVAL, 1963 ATKHLDM, DCYSUSM, LFOVAL2, IP, IFATN, PEFE, FMMOD, TREMFRQ, FM2FRQ2, 1964 TEMPENV, ADCCR, FXWC, MICBA, ADCBA, FXBA, 1965 MICBS, ADCBS, FXBS, CDCS, GPSCS, SPCS0, SPCS1, SPCS2, 1966 SPBYPASS, AC97SLOT, CDSRCS, GPSRCS, ZVSRCS, MICIDX, ADCIDX, FXIDX, 1967 0xff /* end */ 1968 }; 1969 static const unsigned char saved_regs_audigy[] = { 1970 A_ADCIDX, A_MICIDX, A_FXWC1, A_FXWC2, A_SAMPLE_RATE, 1971 A_FXRT2, A_SENDAMOUNTS, A_FXRT1, 1972 0xff /* end */ 1973 }; 1974 1975 static int alloc_pm_buffer(struct snd_emu10k1 *emu) 1976 { 1977 int size; 1978 1979 size = ARRAY_SIZE(saved_regs); 1980 if (emu->audigy) 1981 size += ARRAY_SIZE(saved_regs_audigy); 1982 emu->saved_ptr = vmalloc(array3_size(4, NUM_G, size)); 1983 if (!emu->saved_ptr) 1984 return -ENOMEM; 1985 if (snd_emu10k1_efx_alloc_pm_buffer(emu) < 0) 1986 return -ENOMEM; 1987 if (emu->card_capabilities->ca0151_chip && 1988 snd_p16v_alloc_pm_buffer(emu) < 0) 1989 return -ENOMEM; 1990 return 0; 1991 } 1992 1993 static void free_pm_buffer(struct snd_emu10k1 *emu) 1994 { 1995 vfree(emu->saved_ptr); 1996 snd_emu10k1_efx_free_pm_buffer(emu); 1997 if (emu->card_capabilities->ca0151_chip) 1998 snd_p16v_free_pm_buffer(emu); 1999 } 2000 2001 void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu) 2002 { 2003 int i; 2004 const unsigned char *reg; 2005 unsigned int *val; 2006 2007 val = emu->saved_ptr; 2008 for (reg = saved_regs; *reg != 0xff; reg++) 2009 for (i = 0; i < NUM_G; i++, val++) 2010 *val = snd_emu10k1_ptr_read(emu, *reg, i); 2011 if (emu->audigy) { 2012 for (reg = saved_regs_audigy; *reg != 0xff; reg++) 2013 for (i = 0; i < NUM_G; i++, val++) 2014 *val = snd_emu10k1_ptr_read(emu, *reg, i); 2015 } 2016 if (emu->audigy) 2017 emu->saved_a_iocfg = inw(emu->port + A_IOCFG); 2018 emu->saved_hcfg = inl(emu->port + HCFG); 2019 } 2020 2021 void snd_emu10k1_resume_init(struct snd_emu10k1 *emu) 2022 { 2023 if (emu->card_capabilities->ca_cardbus_chip) 2024 snd_emu10k1_cardbus_init(emu); 2025 if (emu->card_capabilities->ecard) 2026 snd_emu10k1_ecard_init(emu); 2027 else if (emu->card_capabilities->emu_model) 2028 snd_emu10k1_emu1010_init(emu); 2029 else 2030 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_CNTR|AC97SLOT_LFE); 2031 snd_emu10k1_init(emu, emu->enable_ir, 1); 2032 } 2033 2034 void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu) 2035 { 2036 int i; 2037 const unsigned char *reg; 2038 unsigned int *val; 2039 2040 snd_emu10k1_audio_enable(emu); 2041 2042 /* resore for spdif */ 2043 if (emu->audigy) 2044 outw(emu->saved_a_iocfg, emu->port + A_IOCFG); 2045 outl(emu->saved_hcfg, emu->port + HCFG); 2046 2047 val = emu->saved_ptr; 2048 for (reg = saved_regs; *reg != 0xff; reg++) 2049 for (i = 0; i < NUM_G; i++, val++) 2050 snd_emu10k1_ptr_write(emu, *reg, i, *val); 2051 if (emu->audigy) { 2052 for (reg = saved_regs_audigy; *reg != 0xff; reg++) 2053 for (i = 0; i < NUM_G; i++, val++) 2054 snd_emu10k1_ptr_write(emu, *reg, i, *val); 2055 } 2056 } 2057 #endif 2058