1*2ad6d71aSHal Feng// SPDX-License-Identifier: GPL-2.0 OR MIT 2*2ad6d71aSHal Feng/* 3*2ad6d71aSHal Feng * Copyright (C) 2025 StarFive Technology Co., Ltd. 4*2ad6d71aSHal Feng * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com> 5*2ad6d71aSHal Feng */ 6*2ad6d71aSHal Feng 7*2ad6d71aSHal Feng/dts-v1/; 8*2ad6d71aSHal Feng#include "jh7110-common.dtsi" 9*2ad6d71aSHal Feng 10*2ad6d71aSHal Feng/ { 11*2ad6d71aSHal Feng vcc_3v3_pcie: regulator-vcc-3v3-pcie { 12*2ad6d71aSHal Feng compatible = "regulator-fixed"; 13*2ad6d71aSHal Feng enable-active-high; 14*2ad6d71aSHal Feng gpio = <&sysgpio 27 GPIO_ACTIVE_HIGH>; 15*2ad6d71aSHal Feng regulator-name = "vcc_3v3_pcie"; 16*2ad6d71aSHal Feng regulator-min-microvolt = <3300000>; 17*2ad6d71aSHal Feng regulator-max-microvolt = <3300000>; 18*2ad6d71aSHal Feng }; 19*2ad6d71aSHal Feng}; 20*2ad6d71aSHal Feng 21*2ad6d71aSHal Feng&cpu_opp { 22*2ad6d71aSHal Feng /delete-node/ opp-375000000; 23*2ad6d71aSHal Feng /delete-node/ opp-500000000; 24*2ad6d71aSHal Feng /delete-node/ opp-750000000; 25*2ad6d71aSHal Feng /delete-node/ opp-1500000000; 26*2ad6d71aSHal Feng 27*2ad6d71aSHal Feng opp-312500000 { 28*2ad6d71aSHal Feng opp-hz = /bits/ 64 <312500000>; 29*2ad6d71aSHal Feng opp-microvolt = <800000>; 30*2ad6d71aSHal Feng }; 31*2ad6d71aSHal Feng opp-417000000 { 32*2ad6d71aSHal Feng opp-hz = /bits/ 64 <417000000>; 33*2ad6d71aSHal Feng opp-microvolt = <800000>; 34*2ad6d71aSHal Feng }; 35*2ad6d71aSHal Feng opp-625000000 { 36*2ad6d71aSHal Feng opp-hz = /bits/ 64 <625000000>; 37*2ad6d71aSHal Feng opp-microvolt = <800000>; 38*2ad6d71aSHal Feng }; 39*2ad6d71aSHal Feng opp-1250000000 { 40*2ad6d71aSHal Feng opp-hz = /bits/ 64 <1250000000>; 41*2ad6d71aSHal Feng opp-microvolt = <1000000>; 42*2ad6d71aSHal Feng }; 43*2ad6d71aSHal Feng}; 44*2ad6d71aSHal Feng 45*2ad6d71aSHal Feng&gmac0 { 46*2ad6d71aSHal Feng starfive,tx-use-rgmii-clk; 47*2ad6d71aSHal Feng assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; 48*2ad6d71aSHal Feng assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; 49*2ad6d71aSHal Feng status = "okay"; 50*2ad6d71aSHal Feng}; 51*2ad6d71aSHal Feng 52*2ad6d71aSHal Feng&i2c0 { 53*2ad6d71aSHal Feng status = "okay"; 54*2ad6d71aSHal Feng}; 55*2ad6d71aSHal Feng 56*2ad6d71aSHal Feng&mmc1 { 57*2ad6d71aSHal Feng max-frequency = <50000000>; 58*2ad6d71aSHal Feng keep-power-in-suspend; 59*2ad6d71aSHal Feng non-removable; 60*2ad6d71aSHal Feng}; 61*2ad6d71aSHal Feng 62*2ad6d71aSHal Feng&pcie1 { 63*2ad6d71aSHal Feng vpcie3v3-supply = <&vcc_3v3_pcie>; 64*2ad6d71aSHal Feng status = "okay"; 65*2ad6d71aSHal Feng}; 66*2ad6d71aSHal Feng 67*2ad6d71aSHal Feng&phy0 { 68*2ad6d71aSHal Feng motorcomm,tx-clk-adj-enabled; 69*2ad6d71aSHal Feng motorcomm,tx-clk-100-inverted; 70*2ad6d71aSHal Feng motorcomm,tx-clk-1000-inverted; 71*2ad6d71aSHal Feng motorcomm,rx-clk-drv-microamp = <3970>; 72*2ad6d71aSHal Feng motorcomm,rx-data-drv-microamp = <2910>; 73*2ad6d71aSHal Feng rx-internal-delay-ps = <1500>; 74*2ad6d71aSHal Feng tx-internal-delay-ps = <1500>; 75*2ad6d71aSHal Feng}; 76*2ad6d71aSHal Feng 77*2ad6d71aSHal Feng&pwm { 78*2ad6d71aSHal Feng status = "okay"; 79*2ad6d71aSHal Feng}; 80*2ad6d71aSHal Feng 81*2ad6d71aSHal Feng&spi0 { 82*2ad6d71aSHal Feng status = "okay"; 83*2ad6d71aSHal Feng}; 84*2ad6d71aSHal Feng 85*2ad6d71aSHal Feng&syscrg { 86*2ad6d71aSHal Feng assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1250000000>; 87*2ad6d71aSHal Feng}; 88*2ad6d71aSHal Feng 89*2ad6d71aSHal Feng&sysgpio { 90*2ad6d71aSHal Feng uart1_pins: uart1-0 { 91*2ad6d71aSHal Feng tx-pins { 92*2ad6d71aSHal Feng pinmux = <GPIOMUX(22, GPOUT_SYS_UART1_TX, 93*2ad6d71aSHal Feng GPOEN_ENABLE, 94*2ad6d71aSHal Feng GPI_NONE)>; 95*2ad6d71aSHal Feng bias-disable; 96*2ad6d71aSHal Feng drive-strength = <12>; 97*2ad6d71aSHal Feng input-disable; 98*2ad6d71aSHal Feng input-schmitt-disable; 99*2ad6d71aSHal Feng slew-rate = <0>; 100*2ad6d71aSHal Feng }; 101*2ad6d71aSHal Feng 102*2ad6d71aSHal Feng rx-pins { 103*2ad6d71aSHal Feng pinmux = <GPIOMUX(23, GPOUT_LOW, 104*2ad6d71aSHal Feng GPOEN_DISABLE, 105*2ad6d71aSHal Feng GPI_SYS_UART1_RX)>; 106*2ad6d71aSHal Feng bias-pull-up; 107*2ad6d71aSHal Feng drive-strength = <2>; 108*2ad6d71aSHal Feng input-enable; 109*2ad6d71aSHal Feng input-schmitt-enable; 110*2ad6d71aSHal Feng slew-rate = <0>; 111*2ad6d71aSHal Feng }; 112*2ad6d71aSHal Feng 113*2ad6d71aSHal Feng cts-pins { 114*2ad6d71aSHal Feng pinmux = <GPIOMUX(24, GPOUT_LOW, 115*2ad6d71aSHal Feng GPOEN_DISABLE, 116*2ad6d71aSHal Feng GPI_SYS_UART1_CTS)>; 117*2ad6d71aSHal Feng input-enable; 118*2ad6d71aSHal Feng }; 119*2ad6d71aSHal Feng 120*2ad6d71aSHal Feng rts-pins { 121*2ad6d71aSHal Feng pinmux = <GPIOMUX(25, GPOUT_SYS_UART1_RTS, 122*2ad6d71aSHal Feng GPOEN_ENABLE, 123*2ad6d71aSHal Feng GPI_NONE)>; 124*2ad6d71aSHal Feng input-enable; 125*2ad6d71aSHal Feng }; 126*2ad6d71aSHal Feng }; 127*2ad6d71aSHal Feng 128*2ad6d71aSHal Feng usb0_pins: usb0-0 { 129*2ad6d71aSHal Feng power-pins { 130*2ad6d71aSHal Feng pinmux = <GPIOMUX(26, GPOUT_HIGH, 131*2ad6d71aSHal Feng GPOEN_ENABLE, 132*2ad6d71aSHal Feng GPI_NONE)>; 133*2ad6d71aSHal Feng input-disable; 134*2ad6d71aSHal Feng }; 135*2ad6d71aSHal Feng 136*2ad6d71aSHal Feng switch-pins { 137*2ad6d71aSHal Feng pinmux = <GPIOMUX(62, GPOUT_LOW, 138*2ad6d71aSHal Feng GPOEN_ENABLE, 139*2ad6d71aSHal Feng GPI_NONE)>; 140*2ad6d71aSHal Feng input-disable; 141*2ad6d71aSHal Feng }; 142*2ad6d71aSHal Feng }; 143*2ad6d71aSHal Feng}; 144*2ad6d71aSHal Feng 145*2ad6d71aSHal Feng&uart1 { 146*2ad6d71aSHal Feng pinctrl-names = "default"; 147*2ad6d71aSHal Feng pinctrl-0 = <&uart1_pins>; 148*2ad6d71aSHal Feng status = "okay"; 149*2ad6d71aSHal Feng}; 150*2ad6d71aSHal Feng 151*2ad6d71aSHal Feng&usb0 { 152*2ad6d71aSHal Feng dr_mode = "host"; 153*2ad6d71aSHal Feng pinctrl-names = "default"; 154*2ad6d71aSHal Feng pinctrl-0 = <&usb0_pins>; 155*2ad6d71aSHal Feng status = "okay"; 156*2ad6d71aSHal Feng}; 157*2ad6d71aSHal Feng 158*2ad6d71aSHal Feng&usb_cdns3 { 159*2ad6d71aSHal Feng phys = <&usbphy0>, <&pciephy0>; 160*2ad6d71aSHal Feng phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy"; 161*2ad6d71aSHal Feng}; 162