xref: /linux/scripts/dtc/include-prefixes/riscv/starfive/jh7110-starfive-visionfive-2-lite.dtsi (revision 0cac5ce06e524755b3dac1e0a060b05992076d93) 
1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright (C) 2025 StarFive Technology Co., Ltd.
4 * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
5 */
6
7/dts-v1/;
8#include "jh7110-common.dtsi"
9
10/ {
11	vcc_3v3_pcie: regulator-vcc-3v3-pcie {
12		compatible = "regulator-fixed";
13		enable-active-high;
14		gpio = <&sysgpio 27 GPIO_ACTIVE_HIGH>;
15		regulator-name = "vcc_3v3_pcie";
16		regulator-min-microvolt = <3300000>;
17		regulator-max-microvolt = <3300000>;
18	};
19};
20
21&cpu_opp {
22	/delete-node/ opp-375000000;
23	/delete-node/ opp-500000000;
24	/delete-node/ opp-750000000;
25	/delete-node/ opp-1500000000;
26
27	opp-312500000 {
28		opp-hz = /bits/ 64 <312500000>;
29		opp-microvolt = <800000>;
30	};
31	opp-417000000 {
32		opp-hz = /bits/ 64 <417000000>;
33		opp-microvolt = <800000>;
34	};
35	opp-625000000 {
36		opp-hz = /bits/ 64 <625000000>;
37		opp-microvolt = <800000>;
38	};
39	opp-1250000000 {
40		opp-hz = /bits/ 64 <1250000000>;
41		opp-microvolt = <1000000>;
42	};
43};
44
45&gmac0 {
46	starfive,tx-use-rgmii-clk;
47	assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
48	assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
49	status = "okay";
50};
51
52&i2c0 {
53	status = "okay";
54};
55
56&mmc1 {
57	max-frequency = <50000000>;
58	keep-power-in-suspend;
59	non-removable;
60};
61
62&pcie1 {
63	vpcie3v3-supply = <&vcc_3v3_pcie>;
64	status = "okay";
65};
66
67&phy0 {
68	motorcomm,tx-clk-adj-enabled;
69	motorcomm,tx-clk-100-inverted;
70	motorcomm,tx-clk-1000-inverted;
71	motorcomm,rx-clk-drv-microamp = <3970>;
72	motorcomm,rx-data-drv-microamp = <2910>;
73	rx-internal-delay-ps = <1500>;
74	tx-internal-delay-ps = <1500>;
75};
76
77&pwm {
78	status = "okay";
79};
80
81&spi0 {
82	status = "okay";
83};
84
85&syscrg {
86	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1250000000>;
87};
88
89&sysgpio {
90	uart1_pins: uart1-0 {
91		tx-pins {
92			pinmux = <GPIOMUX(22, GPOUT_SYS_UART1_TX,
93					      GPOEN_ENABLE,
94					      GPI_NONE)>;
95			bias-disable;
96			drive-strength = <12>;
97			input-disable;
98			input-schmitt-disable;
99			slew-rate = <0>;
100		};
101
102		rx-pins {
103			pinmux = <GPIOMUX(23, GPOUT_LOW,
104					      GPOEN_DISABLE,
105					      GPI_SYS_UART1_RX)>;
106			bias-pull-up;
107			drive-strength = <2>;
108			input-enable;
109			input-schmitt-enable;
110			slew-rate = <0>;
111		};
112
113		cts-pins {
114			pinmux = <GPIOMUX(24, GPOUT_LOW,
115					      GPOEN_DISABLE,
116					      GPI_SYS_UART1_CTS)>;
117			input-enable;
118		};
119
120		rts-pins {
121			pinmux = <GPIOMUX(25, GPOUT_SYS_UART1_RTS,
122					      GPOEN_ENABLE,
123					      GPI_NONE)>;
124			input-enable;
125		};
126	};
127
128	usb0_pins: usb0-0 {
129		power-pins {
130			pinmux = <GPIOMUX(26, GPOUT_HIGH,
131					      GPOEN_ENABLE,
132					      GPI_NONE)>;
133			input-disable;
134		};
135
136		switch-pins {
137			pinmux = <GPIOMUX(62, GPOUT_LOW,
138					      GPOEN_ENABLE,
139					      GPI_NONE)>;
140			input-disable;
141		};
142	};
143};
144
145&uart1 {
146	pinctrl-names = "default";
147	pinctrl-0 = <&uart1_pins>;
148	status = "okay";
149};
150
151&usb0 {
152	dr_mode = "host";
153	pinctrl-names = "default";
154	pinctrl-0 = <&usb0_pins>;
155	status = "okay";
156};
157
158&usb_cdns3 {
159	phys = <&usbphy0>, <&pciephy0>;
160	phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
161};
162