1*2606bf58SHenry Bell// SPDX-License-Identifier: GPL-2.0 OR MIT 2*2606bf58SHenry Bell/* 3*2606bf58SHenry Bell * Copyright (C) 2024 Henry Bell <dmoo_dv@protonmail.com> 4*2606bf58SHenry Bell */ 5*2606bf58SHenry Bell 6*2606bf58SHenry Bell/dts-v1/; 7*2606bf58SHenry Bell#include "jh7110-common.dtsi" 8*2606bf58SHenry Bell 9*2606bf58SHenry Bell/ { 10*2606bf58SHenry Bell model = "Pine64 Star64"; 11*2606bf58SHenry Bell compatible = "pine64,star64", "starfive,jh7110"; 12*2606bf58SHenry Bell aliases { 13*2606bf58SHenry Bell ethernet1 = &gmac1; 14*2606bf58SHenry Bell }; 15*2606bf58SHenry Bell}; 16*2606bf58SHenry Bell 17*2606bf58SHenry Bell&gmac0 { 18*2606bf58SHenry Bell starfive,tx-use-rgmii-clk; 19*2606bf58SHenry Bell assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; 20*2606bf58SHenry Bell assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; 21*2606bf58SHenry Bell}; 22*2606bf58SHenry Bell 23*2606bf58SHenry Bell&gmac1 { 24*2606bf58SHenry Bell phy-handle = <&phy1>; 25*2606bf58SHenry Bell phy-mode = "rgmii-id"; 26*2606bf58SHenry Bell starfive,tx-use-rgmii-clk; 27*2606bf58SHenry Bell assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>; 28*2606bf58SHenry Bell assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; 29*2606bf58SHenry Bell status = "okay"; 30*2606bf58SHenry Bell 31*2606bf58SHenry Bell mdio { 32*2606bf58SHenry Bell #address-cells = <1>; 33*2606bf58SHenry Bell #size-cells = <0>; 34*2606bf58SHenry Bell compatible = "snps,dwmac-mdio"; 35*2606bf58SHenry Bell 36*2606bf58SHenry Bell phy1: ethernet-phy@1 { 37*2606bf58SHenry Bell reg = <1>; 38*2606bf58SHenry Bell }; 39*2606bf58SHenry Bell }; 40*2606bf58SHenry Bell}; 41*2606bf58SHenry Bell 42*2606bf58SHenry Bell&phy0 { 43*2606bf58SHenry Bell rx-internal-delay-ps = <1900>; 44*2606bf58SHenry Bell tx-internal-delay-ps = <1500>; 45*2606bf58SHenry Bell motorcomm,rx-clk-drv-microamp = <2910>; 46*2606bf58SHenry Bell motorcomm,rx-data-drv-microamp = <2910>; 47*2606bf58SHenry Bell motorcomm,tx-clk-adj-enabled; 48*2606bf58SHenry Bell motorcomm,tx-clk-10-inverted; 49*2606bf58SHenry Bell motorcomm,tx-clk-100-inverted; 50*2606bf58SHenry Bell motorcomm,tx-clk-1000-inverted; 51*2606bf58SHenry Bell}; 52*2606bf58SHenry Bell 53*2606bf58SHenry Bell&phy1 { 54*2606bf58SHenry Bell rx-internal-delay-ps = <0>; 55*2606bf58SHenry Bell tx-internal-delay-ps = <300>; 56*2606bf58SHenry Bell motorcomm,rx-clk-drv-microamp = <2910>; 57*2606bf58SHenry Bell motorcomm,rx-data-drv-microamp = <2910>; 58*2606bf58SHenry Bell motorcomm,tx-clk-adj-enabled; 59*2606bf58SHenry Bell motorcomm,tx-clk-10-inverted; 60*2606bf58SHenry Bell motorcomm,tx-clk-100-inverted; 61*2606bf58SHenry Bell}; 62