1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (C) 2024 Henry Bell <dmoo_dv@protonmail.com> 4 */ 5 6/dts-v1/; 7#include "jh7110-common.dtsi" 8 9/ { 10 model = "Pine64 Star64"; 11 compatible = "pine64,star64", "starfive,jh7110"; 12 aliases { 13 ethernet1 = &gmac1; 14 }; 15}; 16 17&gmac0 { 18 starfive,tx-use-rgmii-clk; 19 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; 20 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; 21 status = "okay"; 22}; 23 24&gmac1 { 25 phy-handle = <&phy1>; 26 phy-mode = "rgmii-id"; 27 starfive,tx-use-rgmii-clk; 28 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>; 29 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; 30 status = "okay"; 31 32 mdio { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 compatible = "snps,dwmac-mdio"; 36 37 phy1: ethernet-phy@1 { 38 reg = <1>; 39 }; 40 }; 41}; 42 43&i2c0 { 44 status = "okay"; 45}; 46 47&pcie1 { 48 status = "okay"; 49}; 50 51&phy0 { 52 rx-internal-delay-ps = <1500>; 53 motorcomm,rx-clk-drv-microamp = <2910>; 54 motorcomm,rx-data-drv-microamp = <2910>; 55 motorcomm,tx-clk-adj-enabled; 56 motorcomm,tx-clk-10-inverted; 57 motorcomm,tx-clk-100-inverted; 58 motorcomm,tx-clk-1000-inverted; 59}; 60 61&phy1 { 62 rx-internal-delay-ps = <0>; 63 tx-internal-delay-ps = <300>; 64 motorcomm,rx-clk-drv-microamp = <2910>; 65 motorcomm,rx-data-drv-microamp = <2910>; 66 motorcomm,tx-clk-adj-enabled; 67 motorcomm,tx-clk-10-inverted; 68 motorcomm,tx-clk-100-inverted; 69}; 70 71&pwm { 72 status = "okay"; 73}; 74 75&pwmdac { 76 status = "okay"; 77}; 78 79&spi0 { 80 status = "okay"; 81}; 82 83&usb0 { 84 dr_mode = "peripheral"; 85 status = "okay"; 86}; 87