1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd 4 * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com> 5 */ 6 7#include <dt-bindings/clock/spacemit,k3-clocks.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/reset/spacemit,k3-resets.h> 10#include <dt-bindings/phy/phy.h> 11 12#include "k3-pdma.h" 13 14/dts-v1/; 15 16/ { 17 #address-cells = <2>; 18 #size-cells = <2>; 19 model = "SpacemiT K3"; 20 compatible = "spacemit,k3"; 21 22 cpus: cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 timebase-frequency = <24000000>; 26 27 cpu_0: cpu@0 { 28 compatible = "spacemit,x100", "riscv"; 29 device_type = "cpu"; 30 reg = <0>; 31 riscv,isa-base = "rv64i"; 32 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 33 "sha", "shcounterenw", "shgatpa", "shtvala", 34 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 35 "smstateen", "ssaia", "ssccptr", "sscofpmf", 36 "sscounterenw", "ssnpm", "ssstateen", "sstc", 37 "sstvala", "sstvecd", "ssu64xl", "svade", 38 "svinval", "svnapot", "svpbmt", "za64rs", 39 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 40 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 41 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 42 "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", 43 "zicond", "zicsr", "zifencei", "zihintntl", 44 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 45 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 46 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 47 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 48 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 49 riscv,cbom-block-size = <64>; 50 riscv,cbop-block-size = <64>; 51 riscv,cboz-block-size = <64>; 52 i-cache-block-size = <64>; 53 i-cache-size = <65536>; 54 i-cache-sets = <256>; 55 d-cache-block-size = <64>; 56 d-cache-size = <65536>; 57 d-cache-sets = <256>; 58 next-level-cache = <&l2_cache0>; 59 mmu-type = "riscv,sv39"; 60 61 cpu0_intc: interrupt-controller { 62 compatible = "riscv,cpu-intc"; 63 #interrupt-cells = <1>; 64 interrupt-controller; 65 }; 66 }; 67 68 cpu_1: cpu@1 { 69 compatible = "spacemit,x100", "riscv"; 70 device_type = "cpu"; 71 reg = <1>; 72 riscv,isa-base = "rv64i"; 73 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 74 "sha", "shcounterenw", "shgatpa", "shtvala", 75 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 76 "smstateen", "ssaia", "ssccptr", "sscofpmf", 77 "sscounterenw", "ssnpm", "ssstateen", "sstc", 78 "sstvala", "sstvecd", "ssu64xl", "svade", 79 "svinval", "svnapot", "svpbmt", "za64rs", 80 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 81 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 82 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 83 "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", 84 "zicond", "zicsr", "zifencei", "zihintntl", 85 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 86 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 87 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 88 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 89 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 90 riscv,cbom-block-size = <64>; 91 riscv,cbop-block-size = <64>; 92 riscv,cboz-block-size = <64>; 93 i-cache-block-size = <64>; 94 i-cache-size = <65536>; 95 i-cache-sets = <256>; 96 d-cache-block-size = <64>; 97 d-cache-size = <65536>; 98 d-cache-sets = <256>; 99 next-level-cache = <&l2_cache0>; 100 mmu-type = "riscv,sv39"; 101 102 cpu1_intc: interrupt-controller { 103 compatible = "riscv,cpu-intc"; 104 #interrupt-cells = <1>; 105 interrupt-controller; 106 }; 107 }; 108 109 cpu_2: cpu@2 { 110 compatible = "spacemit,x100", "riscv"; 111 device_type = "cpu"; 112 reg = <2>; 113 riscv,isa-base = "rv64i"; 114 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 115 "sha", "shcounterenw", "shgatpa", "shtvala", 116 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 117 "smstateen", "ssaia", "ssccptr", "sscofpmf", 118 "sscounterenw", "ssnpm", "ssstateen", "sstc", 119 "sstvala", "sstvecd", "ssu64xl", "svade", 120 "svinval", "svnapot", "svpbmt", "za64rs", 121 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 122 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 123 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 124 "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", 125 "zicond", "zicsr", "zifencei", "zihintntl", 126 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 127 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 128 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 129 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 130 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 131 riscv,cbom-block-size = <64>; 132 riscv,cbop-block-size = <64>; 133 riscv,cboz-block-size = <64>; 134 i-cache-block-size = <64>; 135 i-cache-size = <65536>; 136 i-cache-sets = <256>; 137 d-cache-block-size = <64>; 138 d-cache-size = <65536>; 139 d-cache-sets = <256>; 140 next-level-cache = <&l2_cache0>; 141 mmu-type = "riscv,sv39"; 142 143 cpu2_intc: interrupt-controller { 144 compatible = "riscv,cpu-intc"; 145 #interrupt-cells = <1>; 146 interrupt-controller; 147 }; 148 }; 149 150 cpu_3: cpu@3 { 151 compatible = "spacemit,x100", "riscv"; 152 device_type = "cpu"; 153 reg = <3>; 154 riscv,isa-base = "rv64i"; 155 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 156 "sha", "shcounterenw", "shgatpa", "shtvala", 157 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 158 "smstateen", "ssaia", "ssccptr", "sscofpmf", 159 "sscounterenw", "ssnpm", "ssstateen", "sstc", 160 "sstvala", "sstvecd", "ssu64xl", "svade", 161 "svinval", "svnapot", "svpbmt", "za64rs", 162 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 163 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 164 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 165 "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", 166 "zicond", "zicsr", "zifencei", "zihintntl", 167 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 168 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 169 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 170 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 171 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 172 riscv,cbom-block-size = <64>; 173 riscv,cbop-block-size = <64>; 174 riscv,cboz-block-size = <64>; 175 i-cache-block-size = <64>; 176 i-cache-size = <65536>; 177 i-cache-sets = <256>; 178 d-cache-block-size = <64>; 179 d-cache-size = <65536>; 180 d-cache-sets = <256>; 181 next-level-cache = <&l2_cache0>; 182 mmu-type = "riscv,sv39"; 183 184 cpu3_intc: interrupt-controller { 185 compatible = "riscv,cpu-intc"; 186 #interrupt-cells = <1>; 187 interrupt-controller; 188 }; 189 }; 190 191 cpu_4: cpu@4 { 192 compatible = "spacemit,x100", "riscv"; 193 device_type = "cpu"; 194 reg = <4>; 195 riscv,isa-base = "rv64i"; 196 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 197 "sha", "shcounterenw", "shgatpa", "shtvala", 198 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 199 "smstateen", "ssaia", "ssccptr", "sscofpmf", 200 "sscounterenw", "ssnpm", "ssstateen", "sstc", 201 "sstvala", "sstvecd", "ssu64xl", "svade", 202 "svinval", "svnapot", "svpbmt", "za64rs", 203 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 204 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 205 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 206 "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", 207 "zicond", "zicsr", "zifencei", "zihintntl", 208 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 209 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 210 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 211 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 212 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 213 riscv,cbom-block-size = <64>; 214 riscv,cbop-block-size = <64>; 215 riscv,cboz-block-size = <64>; 216 i-cache-block-size = <64>; 217 i-cache-size = <65536>; 218 i-cache-sets = <256>; 219 d-cache-block-size = <64>; 220 d-cache-size = <65536>; 221 d-cache-sets = <256>; 222 next-level-cache = <&l2_cache1>; 223 mmu-type = "riscv,sv39"; 224 225 cpu4_intc: interrupt-controller { 226 compatible = "riscv,cpu-intc"; 227 #interrupt-cells = <1>; 228 interrupt-controller; 229 }; 230 }; 231 232 cpu_5: cpu@5 { 233 compatible = "spacemit,x100", "riscv"; 234 device_type = "cpu"; 235 reg = <5>; 236 riscv,isa-base = "rv64i"; 237 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 238 "sha", "shcounterenw", "shgatpa", "shtvala", 239 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 240 "smstateen", "ssaia", "ssccptr", "sscofpmf", 241 "sscounterenw", "ssnpm", "ssstateen", "sstc", 242 "sstvala", "sstvecd", "ssu64xl", "svade", 243 "svinval", "svnapot", "svpbmt", "za64rs", 244 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 245 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 246 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 247 "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", 248 "zicond", "zicsr", "zifencei", "zihintntl", 249 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 250 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 251 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 252 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 253 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 254 riscv,cbom-block-size = <64>; 255 riscv,cbop-block-size = <64>; 256 riscv,cboz-block-size = <64>; 257 i-cache-block-size = <64>; 258 i-cache-size = <65536>; 259 i-cache-sets = <256>; 260 d-cache-block-size = <64>; 261 d-cache-size = <65536>; 262 d-cache-sets = <256>; 263 next-level-cache = <&l2_cache1>; 264 mmu-type = "riscv,sv39"; 265 266 cpu5_intc: interrupt-controller { 267 compatible = "riscv,cpu-intc"; 268 #interrupt-cells = <1>; 269 interrupt-controller; 270 }; 271 }; 272 273 cpu_6: cpu@6 { 274 compatible = "spacemit,x100", "riscv"; 275 device_type = "cpu"; 276 reg = <6>; 277 riscv,isa-base = "rv64i"; 278 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 279 "sha", "shcounterenw", "shgatpa", "shtvala", 280 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 281 "smstateen", "ssaia", "ssccptr", "sscofpmf", 282 "sscounterenw", "ssnpm", "ssstateen", "sstc", 283 "sstvala", "sstvecd", "ssu64xl", "svade", 284 "svinval", "svnapot", "svpbmt", "za64rs", 285 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 286 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 287 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 288 "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", 289 "zicond", "zicsr", "zifencei", "zihintntl", 290 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 291 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 292 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 293 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 294 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 295 riscv,cbom-block-size = <64>; 296 riscv,cbop-block-size = <64>; 297 riscv,cboz-block-size = <64>; 298 i-cache-block-size = <64>; 299 i-cache-size = <65536>; 300 i-cache-sets = <256>; 301 d-cache-block-size = <64>; 302 d-cache-size = <65536>; 303 d-cache-sets = <256>; 304 next-level-cache = <&l2_cache1>; 305 mmu-type = "riscv,sv39"; 306 307 cpu6_intc: interrupt-controller { 308 compatible = "riscv,cpu-intc"; 309 #interrupt-cells = <1>; 310 interrupt-controller; 311 }; 312 }; 313 314 cpu_7: cpu@7 { 315 compatible = "spacemit,x100", "riscv"; 316 device_type = "cpu"; 317 reg = <7>; 318 riscv,isa-base = "rv64i"; 319 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 320 "sha", "shcounterenw", "shgatpa", "shtvala", 321 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 322 "smstateen", "ssaia", "ssccptr", "sscofpmf", 323 "sscounterenw", "ssnpm", "ssstateen", "sstc", 324 "sstvala", "sstvecd", "ssu64xl", "svade", 325 "svinval", "svnapot", "svpbmt", "za64rs", 326 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 327 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 328 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 329 "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", 330 "zicond", "zicsr", "zifencei", "zihintntl", 331 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 332 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 333 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 334 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 335 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 336 riscv,cbom-block-size = <64>; 337 riscv,cbop-block-size = <64>; 338 riscv,cboz-block-size = <64>; 339 i-cache-block-size = <64>; 340 i-cache-size = <65536>; 341 i-cache-sets = <256>; 342 d-cache-block-size = <64>; 343 d-cache-size = <65536>; 344 d-cache-sets = <256>; 345 next-level-cache = <&l2_cache1>; 346 mmu-type = "riscv,sv39"; 347 348 cpu7_intc: interrupt-controller { 349 compatible = "riscv,cpu-intc"; 350 #interrupt-cells = <1>; 351 interrupt-controller; 352 }; 353 }; 354 355 l2_cache0: cache-controller-0 { 356 compatible = "cache"; 357 cache-block-size = <64>; 358 cache-level = <2>; 359 cache-size = <4194304>; 360 cache-sets = <4096>; 361 cache-unified; 362 }; 363 364 l2_cache1: cache-controller-1 { 365 compatible = "cache"; 366 cache-block-size = <64>; 367 cache-level = <2>; 368 cache-size = <4194304>; 369 cache-sets = <4096>; 370 cache-unified; 371 }; 372 373 cpu-map { 374 cluster0 { 375 core0 { 376 cpu = <&cpu_0>; 377 }; 378 core1 { 379 cpu = <&cpu_1>; 380 }; 381 core2 { 382 cpu = <&cpu_2>; 383 }; 384 core3 { 385 cpu = <&cpu_3>; 386 }; 387 }; 388 389 cluster1 { 390 core0 { 391 cpu = <&cpu_4>; 392 }; 393 core1 { 394 cpu = <&cpu_5>; 395 }; 396 core2 { 397 cpu = <&cpu_6>; 398 }; 399 core3 { 400 cpu = <&cpu_7>; 401 }; 402 }; 403 }; 404 }; 405 406 clocks { 407 vctcxo_1m: clock-1m { 408 compatible = "fixed-clock"; 409 clock-frequency = <1000000>; 410 clock-output-names = "vctcxo_1m"; 411 #clock-cells = <0>; 412 }; 413 414 vctcxo_24m: clock-24m { 415 compatible = "fixed-clock"; 416 clock-frequency = <24000000>; 417 clock-output-names = "vctcxo_24m"; 418 #clock-cells = <0>; 419 }; 420 421 vctcxo_3m: clock-3m { 422 compatible = "fixed-clock"; 423 clock-frequency = <3000000>; 424 clock-output-names = "vctcxo_3m"; 425 #clock-cells = <0>; 426 }; 427 428 osc_32k: clock-32k { 429 compatible = "fixed-clock"; 430 clock-frequency = <32768>; 431 clock-output-names = "osc_32k"; 432 #clock-cells = <0>; 433 }; 434 }; 435 436 soc: soc { 437 compatible = "simple-bus"; 438 interrupt-parent = <&saplic>; 439 #address-cells = <2>; 440 #size-cells = <2>; 441 dma-noncoherent; 442 ranges; 443 444 usb3d: usb@81a00000 { 445 compatible = "spacemit,k3-dwc3"; 446 reg = <0x0 0x81a00000 0x0 0x10000>; 447 interrupts = <149 IRQ_TYPE_LEVEL_HIGH>; 448 interrupt-parent = <&saplic>; 449 clocks = <&syscon_apmu CLK_APMU_USB3_PORTD_BUS>; 450 clock-names = "usbdrd30"; 451 resets = <&syscon_apmu RESET_APMU_USB3_D_AHB>, 452 <&syscon_apmu RESET_APMU_USB3_D_VCC>, 453 <&syscon_apmu RESET_APMU_USB3_D_PHY>; 454 reset-names = "ahb", "vcc", "phy"; 455 phys = <&usb3d_u2phy>, 456 <&combophy 4 PHY_TYPE_USB3>; 457 phy-names = "usb2-phy", "usb3-phy"; 458 phy_type = "utmi"; 459 snps,dis_enblslpm_quirk; 460 snps,dis_u2_susphy_quirk; 461 snps,dis_u3_susphy_quirk; 462 snps,dis-del-phy-power-chg-quirk; 463 snps,dis-tx-ipgap-linecheck-quirk; 464 snps,parkmode-disable-ss-quirk; 465 dr_mode = "host"; 466 status = "disabled"; 467 }; 468 469 usb3d_u2phy: phy@81b00000 { 470 compatible = "spacemit,k3-usb2-phy"; 471 reg = <0x0 0x81b00000 0x0 0x200>; 472 clocks = <&syscon_apmu CLK_APMU_USB3_PORTD_BUS>; 473 #phy-cells = <0>; 474 status = "disabled"; 475 }; 476 477 combophy: phy@81d00000 { 478 compatible = "spacemit,k3-combo-phy"; 479 reg = <0x0 0x81d00000 0x0 0x600000>; 480 #phy-cells = <2>; 481 spacemit,apb-spare = <&pll>; 482 status = "disabled"; 483 }; 484 485 usb2_host: usb@c0a00000 { 486 compatible = "spacemit,k3-dwc3"; 487 reg = <0x0 0xc0a00000 0x0 0x10000>; 488 clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; 489 clock-names = "usbdrd30"; 490 resets = <&syscon_apmu RESET_APMU_USB2_AHB>, 491 <&syscon_apmu RESET_APMU_USB2_VCC>, 492 <&syscon_apmu RESET_APMU_USB2_PHY>; 493 reset-names = "ahb", "vcc", "phy"; 494 interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; 495 interrupt-parent = <&saplic>; 496 phys = <&usb2_phy>; 497 phy-names = "usb2-phy"; 498 phy_type = "utmi"; 499 snps,dis_enblslpm_quirk; 500 snps,dis_u2_susphy_quirk; 501 snps,dis-del-phy-power-chg-quirk; 502 snps,dis-tx-ipgap-linecheck-quirk; 503 dr_mode = "host"; 504 maximum-speed = "high-speed"; 505 status = "disabled"; 506 }; 507 508 usb2_phy: phy@c0a20000 { 509 compatible = "spacemit,k3-usb2-phy"; 510 reg = <0x0 0xc0a20000 0x0 0x200>; 511 clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; 512 #phy-cells = <0>; 513 status = "disabled"; 514 }; 515 516 eth0: ethernet@cac80000 { 517 compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; 518 reg = <0x0 0xcac80000 0x0 0x2000>; 519 clocks = <&syscon_apmu CLK_APMU_EMAC0_BUS>, 520 <&syscon_apmu CLK_APMU_EMAC0_1588>, 521 <&syscon_apmu CLK_APMU_EMAC0_RGMII_TX>; 522 clock-names = "stmmaceth", "ptp_ref", "tx"; 523 interrupts = <131 IRQ_TYPE_LEVEL_HIGH>, 524 <276 IRQ_TYPE_LEVEL_HIGH>; 525 interrupt-names = "macirq", "eth_wake_irq"; 526 resets = <&syscon_apmu RESET_APMU_EMAC0>; 527 reset-names = "stmmaceth"; 528 rx-fifo-depth = <8192>; 529 tx-fifo-depth = <8192>; 530 snps,multicast-filter-bins = <64>; 531 snps,perfect-filter-entries = <32>; 532 snps,aal; 533 snps,tso; 534 snps,txpbl = <8>; 535 snps,rxpbl = <8>; 536 snps,force_sf_dma_mode; 537 snps,axi-config = <&gmac0_axi_setup>; 538 spacemit,apmu = <&syscon_apmu 0x3e4 0x3e8>; 539 status = "disabled"; 540 541 mdio { 542 compatible = "snps,dwmac-mdio"; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 }; 546 547 gmac0_axi_setup: stmmac-axi-config { 548 snps,wr_osr_lmt = <0xf>; 549 snps,rd_osr_lmt = <0xf>; 550 /* max axi burst len is 256 */ 551 snps,blen = <256 128 64 32 16 0 0>; 552 }; 553 }; 554 555 eth1: ethernet@cac82000 { 556 compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; 557 reg = <0x0 0xcac82000 0x0 0x2000>; 558 clocks = <&syscon_apmu CLK_APMU_EMAC1_BUS>, 559 <&syscon_apmu CLK_APMU_EMAC1_1588>, 560 <&syscon_apmu CLK_APMU_EMAC1_RGMII_TX>; 561 clock-names = "stmmaceth", "ptp_ref", "tx"; 562 interrupts = <133 IRQ_TYPE_LEVEL_HIGH>, 563 <277 IRQ_TYPE_LEVEL_HIGH>; 564 interrupt-names = "macirq", "eth_wake_irq"; 565 resets = <&syscon_apmu RESET_APMU_EMAC1>; 566 reset-names = "stmmaceth"; 567 rx-fifo-depth = <8192>; 568 tx-fifo-depth = <8192>; 569 snps,multicast-filter-bins = <64>; 570 snps,perfect-filter-entries = <32>; 571 snps,aal; 572 snps,tso; 573 snps,txpbl = <8>; 574 snps,rxpbl = <8>; 575 snps,force_sf_dma_mode; 576 snps,axi-config = <&gmac1_axi_setup>; 577 spacemit,apmu = <&syscon_apmu 0x3ec 0x3f0>; 578 status = "disabled"; 579 580 mdio { 581 compatible = "snps,dwmac-mdio"; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 }; 585 586 gmac1_axi_setup: stmmac-axi-config { 587 snps,wr_osr_lmt = <0xf>; 588 snps,rd_osr_lmt = <0xf>; 589 /* max axi burst len is 256 */ 590 snps,blen = <256 128 64 32 16 0 0>; 591 }; 592 }; 593 594 eth2: ethernet@cac8e000 { 595 compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; 596 reg = <0x0 0xcac8e000 0x0 0x2000>; 597 clocks = <&syscon_apmu CLK_APMU_EMAC2_BUS>, 598 <&syscon_apmu CLK_APMU_EMAC2_1588>, 599 <&syscon_apmu CLK_APMU_EMAC2_RGMII_TX>; 600 clock-names = "stmmaceth", "ptp_ref", "tx"; 601 interrupts = <130 IRQ_TYPE_LEVEL_HIGH>, 602 <278 IRQ_TYPE_LEVEL_HIGH>; 603 interrupt-names = "macirq", "eth_wake_irq"; 604 resets = <&syscon_apmu RESET_APMU_EMAC2>; 605 reset-names = "stmmaceth"; 606 rx-fifo-depth = <4096>; 607 tx-fifo-depth = <4096>; 608 snps,multicast-filter-bins = <64>; 609 snps,perfect-filter-entries = <32>; 610 snps,aal; 611 snps,tso; 612 snps,txpbl = <8>; 613 snps,rxpbl = <8>; 614 snps,force_sf_dma_mode; 615 snps,axi-config = <&gmac2_axi_setup>; 616 spacemit,apmu = <&syscon_apmu 0x248 0x24c>; 617 status = "disabled"; 618 619 mdio { 620 compatible = "snps,dwmac-mdio"; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 }; 624 625 gmac2_axi_setup: stmmac-axi-config { 626 snps,wr_osr_lmt = <0xf>; 627 snps,rd_osr_lmt = <0xf>; 628 /* max axi burst len is 256 */ 629 snps,blen = <256 128 64 32 16 0 0>; 630 }; 631 }; 632 633 pdma: dma-controller@d4000000 { 634 compatible = "spacemit,k3-pdma"; 635 reg = <0x0 0xd4000000 0x0 0x4000>; 636 clocks = <&syscon_apmu CLK_APMU_DMA>; 637 resets = <&syscon_apmu RESET_APMU_DMA>; 638 interrupts = <72 IRQ_TYPE_LEVEL_HIGH>; 639 dma-channels = <16>; 640 #dma-cells = <1>; 641 status = "disabled"; 642 }; 643 644 i2c0: i2c@d4010800 { 645 compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; 646 reg = <0x0 0xd4010800 0x0 0x38>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&syscon_apbc CLK_APBC_TWSI0>, 651 <&syscon_apbc CLK_APBC_TWSI0_BUS>; 652 clock-names = "func", "bus"; 653 clock-frequency = <400000>; 654 resets = <&syscon_apbc RESET_APBC_TWSI0>; 655 status = "disabled"; 656 }; 657 658 i2c1: i2c@d4011000 { 659 compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; 660 reg = <0x0 0xd4011000 0x0 0x38>; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&syscon_apbc CLK_APBC_TWSI1>, 665 <&syscon_apbc CLK_APBC_TWSI1_BUS>; 666 clock-names = "func", "bus"; 667 clock-frequency = <400000>; 668 resets = <&syscon_apbc RESET_APBC_TWSI1>; 669 status = "disabled"; 670 }; 671 672 i2c2: i2c@d4012000 { 673 compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; 674 reg = <0x0 0xd4012000 0x0 0x38>; 675 #address-cells = <1>; 676 #size-cells = <0>; 677 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&syscon_apbc CLK_APBC_TWSI2>, 679 <&syscon_apbc CLK_APBC_TWSI2_BUS>; 680 clock-names = "func", "bus"; 681 clock-frequency = <400000>; 682 resets = <&syscon_apbc RESET_APBC_TWSI2>; 683 status = "disabled"; 684 }; 685 686 i2c4: i2c@d4012800 { 687 compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; 688 reg = <0x0 0xd4012800 0x0 0x38>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&syscon_apbc CLK_APBC_TWSI4>, 693 <&syscon_apbc CLK_APBC_TWSI4_BUS>; 694 clock-names = "func", "bus"; 695 clock-frequency = <400000>; 696 resets = <&syscon_apbc RESET_APBC_TWSI4>; 697 status = "disabled"; 698 }; 699 700 i2c5: i2c@d4013800 { 701 compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; 702 reg = <0x0 0xd4013800 0x0 0x38>; 703 #address-cells = <1>; 704 #size-cells = <0>; 705 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&syscon_apbc CLK_APBC_TWSI5>, 707 <&syscon_apbc CLK_APBC_TWSI5_BUS>; 708 clock-names = "func", "bus"; 709 clock-frequency = <400000>; 710 resets = <&syscon_apbc RESET_APBC_TWSI5>; 711 status = "disabled"; 712 }; 713 714 syscon_apbc: system-controller@d4015000 { 715 compatible = "spacemit,k3-syscon-apbc"; 716 reg = <0x0 0xd4015000 0x0 0x1000>; 717 clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; 718 clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; 719 #clock-cells = <1>; 720 #reset-cells = <1>; 721 }; 722 723 uart0: serial@d4017000 { 724 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 725 reg = <0x0 0xd4017000 0x0 0x100>; 726 reg-shift = <2>; 727 reg-io-width = <4>; 728 clocks = <&syscon_apbc CLK_APBC_UART0>, 729 <&syscon_apbc CLK_APBC_UART0_BUS>; 730 clock-names = "core", "bus"; 731 resets = <&syscon_apbc RESET_APBC_UART0>; 732 interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; 733 status = "disabled"; 734 }; 735 736 uart2: serial@d4017100 { 737 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 738 reg = <0x0 0xd4017100 0x0 0x100>; 739 reg-shift = <2>; 740 reg-io-width = <4>; 741 clocks = <&syscon_apbc CLK_APBC_UART2>, 742 <&syscon_apbc CLK_APBC_UART2_BUS>; 743 clock-names = "core", "bus"; 744 resets = <&syscon_apbc RESET_APBC_UART2>; 745 interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; 746 status = "disabled"; 747 }; 748 749 uart3: serial@d4017200 { 750 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 751 reg = <0x0 0xd4017200 0x0 0x100>; 752 reg-shift = <2>; 753 reg-io-width = <4>; 754 clocks = <&syscon_apbc CLK_APBC_UART3>, 755 <&syscon_apbc CLK_APBC_UART3_BUS>; 756 clock-names = "core", "bus"; 757 resets = <&syscon_apbc RESET_APBC_UART3>; 758 interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; 759 status = "disabled"; 760 }; 761 762 uart4: serial@d4017300 { 763 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 764 reg = <0x0 0xd4017300 0x0 0x100>; 765 reg-shift = <2>; 766 reg-io-width = <4>; 767 clocks = <&syscon_apbc CLK_APBC_UART4>, 768 <&syscon_apbc CLK_APBC_UART4_BUS>; 769 clock-names = "core", "bus"; 770 resets = <&syscon_apbc RESET_APBC_UART4>; 771 interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; 772 status = "disabled"; 773 }; 774 775 uart5: serial@d4017400 { 776 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 777 reg = <0x0 0xd4017400 0x0 0x100>; 778 reg-shift = <2>; 779 reg-io-width = <4>; 780 clocks = <&syscon_apbc CLK_APBC_UART5>, 781 <&syscon_apbc CLK_APBC_UART5_BUS>; 782 clock-names = "core", "bus"; 783 resets = <&syscon_apbc RESET_APBC_UART5>; 784 interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; 785 status = "disabled"; 786 }; 787 788 uart6: serial@d4017500 { 789 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 790 reg = <0x0 0xd4017500 0x0 0x100>; 791 reg-shift = <2>; 792 reg-io-width = <4>; 793 clocks = <&syscon_apbc CLK_APBC_UART6>, 794 <&syscon_apbc CLK_APBC_UART6_BUS>; 795 clock-names = "core", "bus"; 796 resets = <&syscon_apbc RESET_APBC_UART6>; 797 interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; 798 status = "disabled"; 799 }; 800 801 uart7: serial@d4017600 { 802 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 803 reg = <0x0 0xd4017600 0x0 0x100>; 804 reg-shift = <2>; 805 reg-io-width = <4>; 806 clocks = <&syscon_apbc CLK_APBC_UART7>, 807 <&syscon_apbc CLK_APBC_UART7_BUS>; 808 clock-names = "core", "bus"; 809 resets = <&syscon_apbc RESET_APBC_UART7>; 810 interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; 811 status = "disabled"; 812 }; 813 814 uart8: serial@d4017700 { 815 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 816 reg = <0x0 0xd4017700 0x0 0x100>; 817 reg-shift = <2>; 818 reg-io-width = <4>; 819 clocks = <&syscon_apbc CLK_APBC_UART8>, 820 <&syscon_apbc CLK_APBC_UART8_BUS>; 821 clock-names = "core", "bus"; 822 resets = <&syscon_apbc RESET_APBC_UART8>; 823 interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; 824 status = "disabled"; 825 }; 826 827 uart9: serial@d4017800 { 828 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 829 reg = <0x0 0xd4017800 0x0 0x100>; 830 reg-shift = <2>; 831 reg-io-width = <4>; 832 clocks = <&syscon_apbc CLK_APBC_UART9>, 833 <&syscon_apbc CLK_APBC_UART9_BUS>; 834 clock-names = "core", "bus"; 835 resets = <&syscon_apbc RESET_APBC_UART9>; 836 interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; 837 status = "disabled"; 838 }; 839 840 i2c6: i2c@d4018800 { 841 compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; 842 reg = <0x0 0xd4018800 0x0 0x38>; 843 #address-cells = <1>; 844 #size-cells = <0>; 845 interrupts = <70 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&syscon_apbc CLK_APBC_TWSI6>, 847 <&syscon_apbc CLK_APBC_TWSI6_BUS>; 848 clock-names = "func", "bus"; 849 clock-frequency = <400000>; 850 resets = <&syscon_apbc RESET_APBC_TWSI6>; 851 status = "disabled"; 852 }; 853 854 gpio: gpio@d4019000 { 855 compatible = "spacemit,k3-gpio"; 856 reg = <0x0 0xd4019000 0x0 0x100>; 857 clocks = <&syscon_apbc CLK_APBC_GPIO>, 858 <&syscon_apbc CLK_APBC_GPIO_BUS>; 859 clock-names = "core", "bus"; 860 gpio-controller; 861 #gpio-cells = <3>; 862 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; 863 interrupt-parent = <&saplic>; 864 interrupt-controller; 865 #interrupt-cells = <3>; 866 gpio-ranges = <&pinctrl 0 0 0 32>, 867 <&pinctrl 1 0 32 32>, 868 <&pinctrl 2 0 64 32>, 869 <&pinctrl 3 0 96 32>; 870 }; 871 872 i2c8: i2c@d401d800 { 873 compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; 874 reg = <0x0 0xd401d800 0x0 0x38>; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&syscon_apbc CLK_APBC_TWSI8>, 879 <&syscon_apbc CLK_APBC_TWSI8_BUS>; 880 clock-names = "func", "bus"; 881 clock-frequency = <400000>; 882 resets = <&syscon_apbc RESET_APBC_TWSI8>; 883 status = "disabled"; 884 }; 885 886 pwm0: pwm@d401a000 { 887 compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; 888 reg = <0x0 0xd401a000 0x0 0x10>; 889 clocks = <&syscon_apbc CLK_APBC_PWM0>, 890 <&syscon_apbc CLK_APBC_PWM0_BUS>; 891 clock-names = "func", "bus"; 892 resets = <&syscon_apbc RESET_APBC_PWM0>; 893 #pwm-cells = <3>; 894 status = "disabled"; 895 }; 896 897 pwm1: pwm@d401a400 { 898 compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; 899 reg = <0x0 0xd401a400 0x0 0x10>; 900 clocks = <&syscon_apbc CLK_APBC_PWM1>, 901 <&syscon_apbc CLK_APBC_PWM1_BUS>; 902 clock-names = "func", "bus"; 903 resets = <&syscon_apbc RESET_APBC_PWM1>; 904 #pwm-cells = <3>; 905 status = "disabled"; 906 }; 907 908 pwm2: pwm@d401a800 { 909 compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; 910 reg = <0x0 0xd401a800 0x0 0x10>; 911 clocks = <&syscon_apbc CLK_APBC_PWM2>, 912 <&syscon_apbc CLK_APBC_PWM2_BUS>; 913 clock-names = "func", "bus"; 914 resets = <&syscon_apbc RESET_APBC_PWM2>; 915 #pwm-cells = <3>; 916 status = "disabled"; 917 }; 918 919 pwm3: pwm@d401ac00 { 920 compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; 921 reg = <0x0 0xd401ac00 0x0 0x10>; 922 clocks = <&syscon_apbc CLK_APBC_PWM3>, 923 <&syscon_apbc CLK_APBC_PWM3_BUS>; 924 clock-names = "func", "bus"; 925 resets = <&syscon_apbc RESET_APBC_PWM3>; 926 #pwm-cells = <3>; 927 status = "disabled"; 928 }; 929 930 pwm4: pwm@d401b000 { 931 compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; 932 reg = <0x0 0xd401b000 0x0 0x10>; 933 clocks = <&syscon_apbc CLK_APBC_PWM4>, 934 <&syscon_apbc CLK_APBC_PWM4_BUS>; 935 clock-names = "func", "bus"; 936 resets = <&syscon_apbc RESET_APBC_PWM4>; 937 #pwm-cells = <3>; 938 status = "disabled"; 939 }; 940 941 pwm5: pwm@d401b400 { 942 compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; 943 reg = <0x0 0xd401b400 0x0 0x10>; 944 clocks = <&syscon_apbc CLK_APBC_PWM5>, 945 <&syscon_apbc CLK_APBC_PWM5_BUS>; 946 clock-names = "func", "bus"; 947 resets = <&syscon_apbc RESET_APBC_PWM5>; 948 #pwm-cells = <3>; 949 status = "disabled"; 950 }; 951 952 pwm6: pwm@d401b800 { 953 compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; 954 reg = <0x0 0xd401b800 0x0 0x10>; 955 clocks = <&syscon_apbc CLK_APBC_PWM6>, 956 <&syscon_apbc CLK_APBC_PWM6_BUS>; 957 clock-names = "func", "bus"; 958 resets = <&syscon_apbc RESET_APBC_PWM6>; 959 #pwm-cells = <3>; 960 status = "disabled"; 961 }; 962 963 pwm7: pwm@d401bc00 { 964 compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; 965 reg = <0x0 0xd401bc00 0x0 0x10>; 966 clocks = <&syscon_apbc CLK_APBC_PWM7>, 967 <&syscon_apbc CLK_APBC_PWM7_BUS>; 968 clock-names = "func", "bus"; 969 resets = <&syscon_apbc RESET_APBC_PWM7>; 970 #pwm-cells = <3>; 971 status = "disabled"; 972 }; 973 974 spi3: spi@d401c000 { 975 compatible = "spacemit,k3-spi", "spacemit,k1-spi"; 976 reg = <0x0 0xd401c000 0x0 0x30>; 977 #address-cells = <1>; 978 #size-cells = <0>; 979 clocks = <&syscon_apbc CLK_APBC_SPI3>, 980 <&syscon_apbc CLK_APBC_SPI3_BUS>; 981 clock-names = "core", "bus"; 982 resets = <&syscon_apbc RESET_APBC_SPI3>; 983 interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; 984 dmas = <&pdma K3_PDMA_SSP3_RX>, <&pdma K3_PDMA_SSP3_TX>; 985 dma-names = "rx", "tx"; 986 status = "disabled"; 987 }; 988 989 pwm8: pwm@d4020000 { 990 compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; 991 reg = <0x0 0xd4020000 0x0 0x10>; 992 clocks = <&syscon_apbc CLK_APBC_PWM8>, 993 <&syscon_apbc CLK_APBC_PWM8_BUS>; 994 clock-names = "func", "bus"; 995 resets = <&syscon_apbc RESET_APBC_PWM8>; 996 #pwm-cells = <3>; 997 status = "disabled"; 998 }; 999 1000 pwm9: pwm@d4020400 { 1001 compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; 1002 reg = <0x0 0xd4020400 0x0 0x10>; 1003 clocks = <&syscon_apbc CLK_APBC_PWM9>, 1004 <&syscon_apbc CLK_APBC_PWM9_BUS>; 1005 clock-names = "func", "bus"; 1006 resets = <&syscon_apbc RESET_APBC_PWM9>; 1007 #pwm-cells = <3>; 1008 status = "disabled"; 1009 }; 1010 1011 pwm10: pwm@d4020800 { 1012 compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; 1013 reg = <0x0 0xd4020800 0x0 0x10>; 1014 clocks = <&syscon_apbc CLK_APBC_PWM10>, 1015 <&syscon_apbc CLK_APBC_PWM10_BUS>; 1016 clock-names = "func", "bus"; 1017 resets = <&syscon_apbc RESET_APBC_PWM10>; 1018 #pwm-cells = <3>; 1019 status = "disabled"; 1020 }; 1021 1022 pwm11: pwm@d4020c00 { 1023 compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; 1024 reg = <0x0 0xd4020c00 0x0 0x10>; 1025 clocks = <&syscon_apbc CLK_APBC_PWM11>, 1026 <&syscon_apbc CLK_APBC_PWM11_BUS>; 1027 clock-names = "func", "bus"; 1028 resets = <&syscon_apbc RESET_APBC_PWM11>; 1029 #pwm-cells = <3>; 1030 status = "disabled"; 1031 }; 1032 1033 pwm12: pwm@d4021000 { 1034 compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; 1035 reg = <0x0 0xd4021000 0x0 0x10>; 1036 clocks = <&syscon_apbc CLK_APBC_PWM12>, 1037 <&syscon_apbc CLK_APBC_PWM12_BUS>; 1038 clock-names = "func", "bus"; 1039 resets = <&syscon_apbc RESET_APBC_PWM12>; 1040 #pwm-cells = <3>; 1041 status = "disabled"; 1042 }; 1043 1044 pwm13: pwm@d4021400 { 1045 compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; 1046 reg = <0x0 0xd4021400 0x0 0x10>; 1047 clocks = <&syscon_apbc CLK_APBC_PWM13>, 1048 <&syscon_apbc CLK_APBC_PWM13_BUS>; 1049 clock-names = "func", "bus"; 1050 resets = <&syscon_apbc RESET_APBC_PWM13>; 1051 #pwm-cells = <3>; 1052 status = "disabled"; 1053 }; 1054 1055 pwm14: pwm@d4021800 { 1056 compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; 1057 reg = <0x0 0xd4021800 0x0 0x10>; 1058 clocks = <&syscon_apbc CLK_APBC_PWM14>, 1059 <&syscon_apbc CLK_APBC_PWM14_BUS>; 1060 clock-names = "func", "bus"; 1061 resets = <&syscon_apbc RESET_APBC_PWM14>; 1062 #pwm-cells = <3>; 1063 status = "disabled"; 1064 }; 1065 1066 pwm15: pwm@d4021c00 { 1067 compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; 1068 reg = <0x0 0xd4021c00 0x0 0x10>; 1069 clocks = <&syscon_apbc CLK_APBC_PWM15>, 1070 <&syscon_apbc CLK_APBC_PWM15_BUS>; 1071 clock-names = "func", "bus"; 1072 resets = <&syscon_apbc RESET_APBC_PWM15>; 1073 #pwm-cells = <3>; 1074 status = "disabled"; 1075 }; 1076 1077 pwm16: pwm@d4022000 { 1078 compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; 1079 reg = <0x0 0xd4022000 0x0 0x10>; 1080 clocks = <&syscon_apbc CLK_APBC_PWM16>, 1081 <&syscon_apbc CLK_APBC_PWM16_BUS>; 1082 clock-names = "func", "bus"; 1083 resets = <&syscon_apbc RESET_APBC_PWM16>; 1084 #pwm-cells = <3>; 1085 status = "disabled"; 1086 }; 1087 1088 pwm17: pwm@d4022400 { 1089 compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; 1090 reg = <0x0 0xd4022400 0x0 0x10>; 1091 clocks = <&syscon_apbc CLK_APBC_PWM17>, 1092 <&syscon_apbc CLK_APBC_PWM17_BUS>; 1093 clock-names = "func", "bus"; 1094 resets = <&syscon_apbc RESET_APBC_PWM17>; 1095 #pwm-cells = <3>; 1096 status = "disabled"; 1097 }; 1098 1099 pwm18: pwm@d4022800 { 1100 compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; 1101 reg = <0x0 0xd4022800 0x0 0x10>; 1102 clocks = <&syscon_apbc CLK_APBC_PWM18>, 1103 <&syscon_apbc CLK_APBC_PWM18_BUS>; 1104 clock-names = "func", "bus"; 1105 resets = <&syscon_apbc RESET_APBC_PWM18>; 1106 #pwm-cells = <3>; 1107 status = "disabled"; 1108 }; 1109 1110 pwm19: pwm@d4022c00 { 1111 compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; 1112 reg = <0x0 0xd4022c00 0x0 0x10>; 1113 clocks = <&syscon_apbc CLK_APBC_PWM19>, 1114 <&syscon_apbc CLK_APBC_PWM19_BUS>; 1115 clock-names = "func", "bus"; 1116 resets = <&syscon_apbc RESET_APBC_PWM19>; 1117 #pwm-cells = <3>; 1118 status = "disabled"; 1119 }; 1120 1121 pinctrl: pinctrl@d401e000 { 1122 compatible = "spacemit,k3-pinctrl"; 1123 reg = <0x0 0xd401e000 0x0 0x1000>; 1124 clocks = <&syscon_apbc CLK_APBC_AIB>, 1125 <&syscon_apbc CLK_APBC_AIB_BUS>; 1126 clock-names = "func", "bus"; 1127 spacemit,apbc = <&syscon_apbc>; 1128 }; 1129 1130 uart10: serial@d401f000 { 1131 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 1132 reg = <0x0 0xd401f000 0x0 0x100>; 1133 reg-shift = <2>; 1134 reg-io-width = <4>; 1135 clocks = <&syscon_apbc CLK_APBC_UART10>, 1136 <&syscon_apbc CLK_APBC_UART10_BUS>; 1137 clock-names = "core", "bus"; 1138 resets = <&syscon_apbc RESET_APBC_UART10>; 1139 interrupts = <281 IRQ_TYPE_LEVEL_HIGH>; 1140 status = "disabled"; 1141 }; 1142 1143 spi0: spi@d4040000 { 1144 compatible = "spacemit,k3-spi", "spacemit,k1-spi"; 1145 reg = <0x0 0xd4040000 0x0 0x30>; 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 clocks = <&syscon_apbc CLK_APBC_SPI0>, 1149 <&syscon_apbc CLK_APBC_SPI0_BUS>; 1150 clock-names = "core", "bus"; 1151 resets = <&syscon_apbc RESET_APBC_SPI0>; 1152 interrupts = <283 IRQ_TYPE_LEVEL_HIGH>; 1153 dmas = <&pdma K3_PDMA_SSP0_RX>, <&pdma K3_PDMA_SSP0_TX>; 1154 dma-names = "rx", "tx"; 1155 status = "disabled"; 1156 }; 1157 1158 spi1: spi@d4040800 { 1159 compatible = "spacemit,k3-spi", "spacemit,k1-spi"; 1160 reg = <0x0 0xd4040800 0x0 0x30>; 1161 #address-cells = <1>; 1162 #size-cells = <0>; 1163 clocks = <&syscon_apbc CLK_APBC_SPI1>, 1164 <&syscon_apbc CLK_APBC_SPI1_BUS>; 1165 clock-names = "core", "bus"; 1166 resets = <&syscon_apbc RESET_APBC_SPI1>; 1167 interrupts = <282 IRQ_TYPE_LEVEL_HIGH>; 1168 dmas = <&pdma K3_PDMA_SSP1_RX>, <&pdma K3_PDMA_SSP1_TX>; 1169 dma-names = "rx", "tx"; 1170 status = "disabled"; 1171 }; 1172 1173 syscon_mpmu: system-controller@d4050000 { 1174 compatible = "spacemit,k3-syscon-mpmu"; 1175 reg = <0x0 0xd4050000 0x0 0x10000>; 1176 clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; 1177 clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; 1178 #clock-cells = <1>; 1179 #power-domain-cells = <1>; 1180 #reset-cells = <1>; 1181 }; 1182 1183 pll: clock-controller@d4090000 { 1184 compatible = "spacemit,k3-pll"; 1185 reg = <0x0 0xd4090000 0x0 0x10000>; 1186 clocks = <&vctcxo_24m>; 1187 spacemit,mpmu = <&syscon_mpmu>; 1188 #clock-cells = <1>; 1189 }; 1190 1191 qspi: spi@d420c000 { 1192 compatible = "spacemit,k3-qspi", 1193 "spacemit,k1-qspi"; 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 reg = <0x0 0xd420c000 0x0 0x1000>, 1197 <0x0 0xb8000000 0x0 0xc00000>; 1198 reg-names = "QuadSPI", "QuadSPI-memory"; 1199 clocks = <&syscon_apmu CLK_APMU_QSPI_BUS>, 1200 <&syscon_apmu CLK_APMU_QSPI>; 1201 clock-names = "qspi_en", "qspi"; 1202 resets = <&syscon_apmu RESET_APMU_QSPI>, 1203 <&syscon_apmu RESET_APMU_QSPI_BUS>; 1204 interrupts = <117 IRQ_TYPE_LEVEL_HIGH>; 1205 status = "disabled"; 1206 }; 1207 1208 sdhci0: mmc@d4280000 { 1209 compatible = "spacemit,k3-sdhci"; 1210 reg = <0x0 0xd4280000 0x0 0x200>; 1211 clocks = <&syscon_apmu CLK_APMU_SDH_AXI>, 1212 <&syscon_apmu CLK_APMU_SDH0>; 1213 clock-names = "core", "io"; 1214 resets = <&syscon_apmu RESET_APMU_SDH_AXI>, 1215 <&syscon_apmu RESET_APMU_SDH0>; 1216 reset-names = "axi", "sdh"; 1217 interrupts = <99 IRQ_TYPE_LEVEL_HIGH>; 1218 status = "disabled"; 1219 }; 1220 1221 syscon_apmu: system-controller@d4282800 { 1222 compatible = "spacemit,k3-syscon-apmu"; 1223 reg = <0x0 0xd4282800 0x0 0x400>; 1224 clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; 1225 clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; 1226 #clock-cells = <1>; 1227 #power-domain-cells = <1>; 1228 #reset-cells = <1>; 1229 }; 1230 1231 syscon_dciu: system-controller@d8440000 { 1232 compatible = "spacemit,k3-syscon-dciu"; 1233 reg = <0x0 0xd8440000 0x0 0xc000>; 1234 #clock-cells = <1>; 1235 #reset-cells = <1>; 1236 }; 1237 1238 simsic: interrupt-controller@e0400000 { 1239 compatible = "spacemit,k3-imsics", "riscv,imsics"; 1240 reg = <0x0 0xe0400000 0x0 0x200000>; 1241 #interrupt-cells = <0>; 1242 #msi-cells = <0>; 1243 interrupt-controller; 1244 interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>, 1245 <&cpu2_intc 9>, <&cpu3_intc 9>, 1246 <&cpu4_intc 9>, <&cpu5_intc 9>, 1247 <&cpu6_intc 9>, <&cpu7_intc 9>; 1248 msi-controller; 1249 riscv,guest-index-bits = <6>; 1250 riscv,hart-index-bits = <4>; 1251 riscv,num-guest-ids = <511>; 1252 riscv,num-ids = <511>; 1253 }; 1254 1255 saplic: interrupt-controller@e0804000 { 1256 compatible = "spacemit,k3-aplic", "riscv,aplic"; 1257 reg = <0x0 0xe0804000 0x0 0x4000>; 1258 #interrupt-cells = <2>; 1259 interrupt-controller; 1260 msi-parent = <&simsic>; 1261 riscv,num-sources = <512>; 1262 }; 1263 1264 clint: timer@e081c000 { 1265 compatible = "spacemit,k3-clint", "sifive,clint0"; 1266 reg = <0x0 0xe081c000 0x0 0x4000>; 1267 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 1268 <&cpu1_intc 3>, <&cpu1_intc 7>, 1269 <&cpu2_intc 3>, <&cpu2_intc 7>, 1270 <&cpu3_intc 3>, <&cpu3_intc 7>, 1271 <&cpu4_intc 3>, <&cpu4_intc 7>, 1272 <&cpu5_intc 3>, <&cpu5_intc 7>, 1273 <&cpu6_intc 3>, <&cpu6_intc 7>, 1274 <&cpu7_intc 3>, <&cpu7_intc 7>; 1275 }; 1276 1277 /* sec_i2c3: 0xf0614000, not available from Linux */ 1278 1279 mimsic: interrupt-controller@f1000000 { 1280 compatible = "spacemit,k3-imsics", "riscv,imsics"; 1281 reg = <0x0 0xf1000000 0x0 0x10000>; 1282 #interrupt-cells = <0>; 1283 #msi-cells = <0>; 1284 interrupt-controller; 1285 interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>, 1286 <&cpu2_intc 11>, <&cpu3_intc 11>, 1287 <&cpu4_intc 11>, <&cpu5_intc 11>, 1288 <&cpu6_intc 11>, <&cpu7_intc 11>; 1289 msi-controller; 1290 riscv,guest-index-bits = <6>; 1291 riscv,hart-index-bits = <4>; 1292 riscv,num-guest-ids = <511>; 1293 riscv,num-ids = <511>; 1294 status = "reserved"; 1295 }; 1296 1297 maplic: interrupt-controller@f1800000 { 1298 compatible = "spacemit,k3-aplic", "riscv,aplic"; 1299 reg = <0x0 0xf1800000 0x0 0x4000>; 1300 #interrupt-cells = <2>; 1301 interrupt-controller; 1302 msi-parent = <&mimsic>; 1303 riscv,children = <&saplic>; 1304 riscv,delegation = <&saplic 1 512>; 1305 riscv,num-sources = <512>; 1306 status = "reserved"; 1307 }; 1308 }; 1309}; 1310