1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* 3 * Copyright (C) 2025 Inochi Amaoto <inochiama@outlook.com> 4 */ 5 6 #ifndef _SOPHGO_CV18XX_RESET 7 #define _SOPHGO_CV18XX_RESET 8 9 #define RST_DDR 2 10 #define RST_H264C 3 11 #define RST_JPEG 4 12 #define RST_H265C 5 13 #define RST_VIPSYS 6 14 #define RST_TDMA 7 15 #define RST_TPU 8 16 #define RST_TPUSYS 9 17 #define RST_USB 11 18 #define RST_ETH0 12 19 #define RST_ETH1 13 20 #define RST_NAND 14 21 #define RST_EMMC 15 22 #define RST_SD0 16 23 #define RST_SDMA 18 24 #define RST_I2S0 19 25 #define RST_I2S1 20 26 #define RST_I2S2 21 27 #define RST_I2S3 22 28 #define RST_UART0 23 29 #define RST_UART1 24 30 #define RST_UART2 25 31 #define RST_UART3 26 32 #define RST_I2C0 27 33 #define RST_I2C1 28 34 #define RST_I2C2 29 35 #define RST_I2C3 30 36 #define RST_I2C4 31 37 #define RST_PWM0 32 38 #define RST_PWM1 33 39 #define RST_PWM2 34 40 #define RST_PWM3 35 41 #define RST_SPI0 40 42 #define RST_SPI1 41 43 #define RST_SPI2 42 44 #define RST_SPI3 43 45 #define RST_GPIO0 44 46 #define RST_GPIO1 45 47 #define RST_GPIO2 46 48 #define RST_EFUSE 47 49 #define RST_WDT 48 50 #define RST_AHB_ROM 49 51 #define RST_SPIC 50 52 #define RST_TEMPSEN 51 53 #define RST_SARADC 52 54 #define RST_COMBO_PHY0 58 55 #define RST_SPI_NAND 61 56 #define RST_SE 62 57 #define RST_UART4 74 58 #define RST_GPIO3 75 59 #define RST_SYSTEM 76 60 #define RST_TIMER 77 61 #define RST_TIMER0 78 62 #define RST_TIMER1 79 63 #define RST_TIMER2 80 64 #define RST_TIMER3 81 65 #define RST_TIMER4 82 66 #define RST_TIMER5 83 67 #define RST_TIMER6 84 68 #define RST_TIMER7 85 69 #define RST_WGN0 86 70 #define RST_WGN1 87 71 #define RST_WGN2 88 72 #define RST_KEYSCAN 89 73 #define RST_AUDDAC 91 74 #define RST_AUDDAC_APB 92 75 #define RST_AUDADC 93 76 #define RST_VCSYS 95 77 #define RST_ETHPHY 96 78 #define RST_ETHPHY_APB 97 79 #define RST_AUDSRC 98 80 #define RST_VIP_CAM0 99 81 #define RST_WDT1 100 82 #define RST_WDT2 101 83 #define RST_AUTOCLEAR_CPUCORE0 256 84 #define RST_AUTOCLEAR_CPUCORE1 257 85 #define RST_AUTOCLEAR_CPUCORE2 258 86 #define RST_AUTOCLEAR_CPUCORE3 259 87 #define RST_AUTOCLEAR_CPUSYS0 260 88 #define RST_AUTOCLEAR_CPUSYS1 261 89 #define RST_AUTOCLEAR_CPUSYS2 262 90 #define RST_CPUCORE0 288 91 #define RST_CPUCORE1 289 92 #define RST_CPUCORE2 290 93 #define RST_CPUCORE3 291 94 #define RST_CPUSYS0 292 95 #define RST_CPUSYS1 293 96 #define RST_CPUSYS2 294 97 98 #endif /* _SOPHGO_CV18XX_RESET */ 99