1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2024 Beijing ESWIN Computing Technology Co., Ltd. 4 */ 5 6/dts-v1/; 7 8/ { 9 #address-cells = <2>; 10 #size-cells = <2>; 11 12 cpus { 13 #address-cells = <1>; 14 #size-cells = <0>; 15 timebase-frequency = <1000000>; 16 17 cpu0: cpu@0 { 18 compatible = "sifive,p550", "riscv"; 19 device_type = "cpu"; 20 d-cache-block-size = <64>; 21 d-cache-sets = <128>; 22 d-cache-size = <32768>; 23 d-tlb-sets = <1>; 24 d-tlb-size = <32>; 25 i-cache-block-size = <64>; 26 i-cache-sets = <128>; 27 i-cache-size = <32768>; 28 i-tlb-sets = <1>; 29 i-tlb-size = <32>; 30 mmu-type = "riscv,sv48"; 31 next-level-cache = <&l2_cache_0>; 32 reg = <0x0>; 33 riscv,isa-base = "rv64i"; 34 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf", 35 "zba", "zbb", "zicsr", "zifencei"; 36 tlb-split; 37 38 cpu0_intc: interrupt-controller { 39 compatible = "riscv,cpu-intc"; 40 #interrupt-cells = <1>; 41 interrupt-controller; 42 }; 43 }; 44 45 cpu1: cpu@1 { 46 compatible = "sifive,p550", "riscv"; 47 d-cache-block-size = <64>; 48 d-cache-sets = <128>; 49 d-cache-size = <32768>; 50 d-tlb-sets = <1>; 51 d-tlb-size = <32>; 52 device_type = "cpu"; 53 i-cache-block-size = <64>; 54 i-cache-sets = <128>; 55 i-cache-size = <32768>; 56 i-tlb-sets = <1>; 57 i-tlb-size = <32>; 58 mmu-type = "riscv,sv48"; 59 next-level-cache = <&l2_cache_1>; 60 reg = <0x1>; 61 riscv,isa-base = "rv64i"; 62 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf", 63 "zba", "zbb", "zicsr", "zifencei"; 64 tlb-split; 65 66 cpu1_intc: interrupt-controller { 67 compatible = "riscv,cpu-intc"; 68 #interrupt-cells = <1>; 69 interrupt-controller; 70 }; 71 }; 72 73 cpu2: cpu@2 { 74 compatible = "sifive,p550", "riscv"; 75 d-cache-block-size = <64>; 76 d-cache-sets = <128>; 77 d-cache-size = <32768>; 78 d-tlb-sets = <1>; 79 d-tlb-size = <32>; 80 device_type = "cpu"; 81 i-cache-block-size = <64>; 82 i-cache-sets = <128>; 83 i-cache-size = <32768>; 84 i-tlb-sets = <1>; 85 i-tlb-size = <32>; 86 mmu-type = "riscv,sv48"; 87 next-level-cache = <&l2_cache_2>; 88 reg = <0x2>; 89 riscv,isa-base = "rv64i"; 90 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf", 91 "zba", "zbb", "zicsr", "zifencei"; 92 tlb-split; 93 94 cpu2_intc: interrupt-controller { 95 compatible = "riscv,cpu-intc"; 96 #interrupt-cells = <1>; 97 interrupt-controller; 98 }; 99 }; 100 101 cpu3: cpu@3 { 102 compatible = "sifive,p550", "riscv"; 103 d-cache-block-size = <64>; 104 d-cache-sets = <128>; 105 d-cache-size = <32768>; 106 d-tlb-sets = <1>; 107 d-tlb-size = <32>; 108 device_type = "cpu"; 109 i-cache-block-size = <64>; 110 i-cache-sets = <128>; 111 i-cache-size = <32768>; 112 i-tlb-sets = <1>; 113 i-tlb-size = <32>; 114 mmu-type = "riscv,sv48"; 115 next-level-cache = <&l2_cache_3>; 116 reg = <0x3>; 117 riscv,isa-base = "rv64i"; 118 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf", 119 "zba", "zbb", "zicsr", "zifencei"; 120 tlb-split; 121 122 cpu3_intc: interrupt-controller { 123 compatible = "riscv,cpu-intc"; 124 #interrupt-cells = <1>; 125 interrupt-controller; 126 }; 127 }; 128 129 l2_cache_0: l2-cache0 { 130 compatible = "cache"; 131 cache-block-size = <64>; 132 cache-level = <2>; 133 cache-sets = <512>; 134 cache-size = <262144>; 135 cache-unified; 136 next-level-cache = <&ccache>; 137 }; 138 139 l2_cache_1: l2-cache1 { 140 compatible = "cache"; 141 cache-block-size = <64>; 142 cache-level = <2>; 143 cache-sets = <512>; 144 cache-size = <262144>; 145 cache-unified; 146 next-level-cache = <&ccache>; 147 }; 148 149 l2_cache_2: l2-cache2 { 150 compatible = "cache"; 151 cache-block-size = <64>; 152 cache-level = <2>; 153 cache-sets = <512>; 154 cache-size = <262144>; 155 cache-unified; 156 next-level-cache = <&ccache>; 157 }; 158 159 l2_cache_3: l2-cache3 { 160 compatible = "cache"; 161 cache-block-size = <64>; 162 cache-level = <2>; 163 cache-sets = <512>; 164 cache-size = <262144>; 165 cache-unified; 166 next-level-cache = <&ccache>; 167 }; 168 }; 169 170 pmu { 171 compatible = "riscv,pmu"; 172 riscv,event-to-mhpmcounters = 173 <0x00001 0x00001 0x00000001>, 174 <0x00002 0x00002 0x00000004>, 175 <0x00004 0x00006 0x00000078>, 176 <0x10009 0x10009 0x00000078>, 177 <0x10019 0x10019 0x00000078>, 178 <0x10021 0x10021 0x00000078>; 179 riscv,event-to-mhpmevent = 180 <0x00004 0x00000000 0x00000202>, 181 <0x00005 0x00000000 0x00004000>, 182 <0x00006 0x00000000 0x00002001>, 183 <0x10009 0x00000000 0x00000102>, 184 <0x10019 0x00000000 0x00001002>, 185 <0x10021 0x00000000 0x00000802>; 186 riscv,raw-event-to-mhpmcounters = 187 <0x00000000 0x00000000 0xffffffff 0xfc0000ff 0x00000078>, 188 <0x00000000 0x00000001 0xffffffff 0xfffe07ff 0x00000078>, 189 <0x00000000 0x00000002 0xffffffff 0xfffe00ff 0x00000078>, 190 <0x00000000 0x00000003 0xfffffffc 0x000000ff 0x00000078>, 191 <0x00000000 0x00000004 0xffffffc0 0x000000ff 0x00000078>, 192 <0x00000000 0x00000005 0xffffffff 0xfffffdff 0x00000078>, 193 <0x00000000 0x00000006 0xfffffe00 0x110204ff 0x00000078>, 194 <0x00000000 0x00000007 0xffffffff 0xf00000ff 0x00000078>, 195 <0x00000000 0x00000008 0xfffffe04 0x000000ff 0x00000078>, 196 <0x00000000 0x00000009 0xffffffff 0xffffc0ff 0x00000078>, 197 <0x00000000 0x0000000a 0xffffffff 0xf00000ff 0x00000078>, 198 <0x00000000 0x0000000b 0xffffffff 0xfffffcff 0x00000078>, 199 <0x00000000 0x0000000c 0xfffffff0 0x000000ff 0x00000078>, 200 <0x00000000 0x0000000d 0xffffffff 0x800000ff 0x00000078>, 201 <0x00000000 0x0000000e 0xffffffff 0xf80000ff 0x00000078>, 202 <0x00000000 0x0000000f 0xfffffffc 0x000000ff 0x00000078>; 203 }; 204 205 soc { 206 compatible = "simple-bus"; 207 ranges; 208 interrupt-parent = <&plic>; 209 #address-cells = <2>; 210 #size-cells = <2>; 211 dma-noncoherent; 212 213 clint: timer@2000000 { 214 compatible = "eswin,eic7700-clint", "sifive,clint0"; 215 reg = <0x0 0x02000000 0x0 0x10000>; 216 interrupts-extended = 217 <&cpu0_intc 3>, <&cpu0_intc 7>, 218 <&cpu1_intc 3>, <&cpu1_intc 7>, 219 <&cpu2_intc 3>, <&cpu2_intc 7>, 220 <&cpu3_intc 3>, <&cpu3_intc 7>; 221 }; 222 223 ccache: cache-controller@2010000 { 224 compatible = "eswin,eic7700-l3-cache", "sifive,ccache0", "cache"; 225 reg = <0x0 0x2010000 0x0 0x4000>; 226 interrupts = <1>, <3>, <4>, <2>; 227 cache-block-size = <64>; 228 cache-level = <3>; 229 cache-sets = <4096>; 230 cache-size = <4194304>; 231 cache-unified; 232 }; 233 234 plic: interrupt-controller@c000000 { 235 compatible = "eswin,eic7700-plic", "sifive,plic-1.0.0"; 236 reg = <0x0 0xc000000 0x0 0x4000000>; 237 interrupt-controller; 238 interrupts-extended = 239 <&cpu0_intc 11>, <&cpu0_intc 9>, 240 <&cpu1_intc 11>, <&cpu1_intc 9>, 241 <&cpu2_intc 11>, <&cpu2_intc 9>, 242 <&cpu3_intc 11>, <&cpu3_intc 9>; 243 riscv,ndev = <520>; 244 #address-cells = <0>; 245 #interrupt-cells = <1>; 246 }; 247 248 uart0: serial@50900000 { 249 compatible = "snps,dw-apb-uart"; 250 reg = <0x0 0x50900000 0x0 0x10000>; 251 interrupts = <100>; 252 clock-frequency = <200000000>; 253 reg-io-width = <4>; 254 reg-shift = <2>; 255 status = "disabled"; 256 }; 257 258 uart1: serial@50910000 { 259 compatible = "snps,dw-apb-uart"; 260 reg = <0x0 0x50910000 0x0 0x10000>; 261 interrupts = <101>; 262 clock-frequency = <200000000>; 263 reg-io-width = <4>; 264 reg-shift = <2>; 265 status = "disabled"; 266 }; 267 268 uart2: serial@50920000 { 269 compatible = "snps,dw-apb-uart"; 270 reg = <0x0 0x50920000 0x0 0x10000>; 271 interrupts = <102>; 272 clock-frequency = <200000000>; 273 reg-io-width = <4>; 274 reg-shift = <2>; 275 status = "disabled"; 276 }; 277 278 uart3: serial@50930000 { 279 compatible = "snps,dw-apb-uart"; 280 reg = <0x0 0x50930000 0x0 0x10000>; 281 interrupts = <103>; 282 clock-frequency = <200000000>; 283 reg-io-width = <4>; 284 reg-shift = <2>; 285 status = "disabled"; 286 }; 287 288 uart4: serial@50940000 { 289 compatible = "snps,dw-apb-uart"; 290 reg = <0x0 0x50940000 0x0 0x10000>; 291 interrupts = <104>; 292 clock-frequency = <200000000>; 293 reg-io-width = <4>; 294 reg-shift = <2>; 295 status = "disabled"; 296 }; 297 298 gpio@51600000 { 299 compatible = "snps,dw-apb-gpio"; 300 reg = <0x0 0x51600000 0x0 0x80>; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 304 gpioA: gpio-port@0 { 305 compatible = "snps,dw-apb-gpio-port"; 306 reg = <0>; 307 interrupt-controller; 308 #interrupt-cells = <2>; 309 interrupts = 310 <303>, <304>, <305>, <306>, <307>, <308>, <309>, 311 <310>, <311>, <312>, <313>, <314>, <315>, <316>, 312 <317>, <318>, <319>, <320>, <321>, <322>, <323>, 313 <324>, <325>, <326>, <327>, <328>, <329>, <330>, 314 <331>, <332>, <333>, <334>; 315 gpio-controller; 316 ngpios = <32>; 317 #gpio-cells = <2>; 318 }; 319 320 gpioB: gpio-port@1 { 321 compatible = "snps,dw-apb-gpio-port"; 322 reg = <1>; 323 gpio-controller; 324 ngpios = <32>; 325 #gpio-cells = <2>; 326 }; 327 328 gpioC: gpio-port@2 { 329 compatible = "snps,dw-apb-gpio-port"; 330 reg = <2>; 331 gpio-controller; 332 ngpios = <32>; 333 #gpio-cells = <2>; 334 }; 335 336 gpioD: gpio-port@3 { 337 compatible = "snps,dw-apb-gpio-port"; 338 reg = <3>; 339 gpio-controller; 340 ngpios = <16>; 341 #gpio-cells = <2>; 342 }; 343 }; 344 }; 345}; 346