177874ebdSJunhui Liu// SPDX-License-Identifier: GPL-2.0 OR MIT 277874ebdSJunhui Liu/* 377874ebdSJunhui Liu * Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech> 477874ebdSJunhui Liu */ 577874ebdSJunhui Liu 677874ebdSJunhui Liu/dts-v1/; 777874ebdSJunhui Liu/ { 877874ebdSJunhui Liu #address-cells = <2>; 977874ebdSJunhui Liu #size-cells = <2>; 1077874ebdSJunhui Liu model = "Anlogic DR1V90"; 1177874ebdSJunhui Liu compatible = "anlogic,dr1v90"; 1277874ebdSJunhui Liu 1377874ebdSJunhui Liu cpus { 1477874ebdSJunhui Liu #address-cells = <1>; 1577874ebdSJunhui Liu #size-cells = <0>; 1677874ebdSJunhui Liu timebase-frequency = <800000000>; 1777874ebdSJunhui Liu 1877874ebdSJunhui Liu cpu@0 { 1977874ebdSJunhui Liu compatible = "nuclei,ux900", "riscv"; 2077874ebdSJunhui Liu d-cache-block-size = <64>; 2177874ebdSJunhui Liu d-cache-sets = <256>; 2277874ebdSJunhui Liu d-cache-size = <32768>; 2377874ebdSJunhui Liu device_type = "cpu"; 2477874ebdSJunhui Liu i-cache-block-size = <64>; 2577874ebdSJunhui Liu i-cache-sets = <256>; 2677874ebdSJunhui Liu i-cache-size = <32768>; 2777874ebdSJunhui Liu mmu-type = "riscv,sv39"; 2877874ebdSJunhui Liu reg = <0>; 2977874ebdSJunhui Liu riscv,isa-base = "rv64i"; 30*18649ffbSGuodong Xu riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", 31*18649ffbSGuodong Xu "zba", "zbb", "zbc", "zbkc", "zbs", 32*18649ffbSGuodong Xu "zicntr", "zicsr", "zifencei", 3377874ebdSJunhui Liu "zihintpause", "zihpm"; 3477874ebdSJunhui Liu 3577874ebdSJunhui Liu cpu0_intc: interrupt-controller { 3677874ebdSJunhui Liu compatible = "riscv,cpu-intc"; 3777874ebdSJunhui Liu #interrupt-cells = <1>; 3877874ebdSJunhui Liu interrupt-controller; 3977874ebdSJunhui Liu }; 4077874ebdSJunhui Liu }; 4177874ebdSJunhui Liu }; 4277874ebdSJunhui Liu 4377874ebdSJunhui Liu soc { 4477874ebdSJunhui Liu compatible = "simple-bus"; 4577874ebdSJunhui Liu interrupt-parent = <&plic>; 4677874ebdSJunhui Liu #address-cells = <2>; 4777874ebdSJunhui Liu #size-cells = <2>; 4877874ebdSJunhui Liu ranges; 4977874ebdSJunhui Liu 5077874ebdSJunhui Liu aclint_mswi: interrupt-controller@68031000 { 5177874ebdSJunhui Liu compatible = "anlogic,dr1v90-aclint-mswi", "nuclei,ux900-aclint-mswi"; 5277874ebdSJunhui Liu reg = <0x0 0x68031000 0x0 0x4000>; 5377874ebdSJunhui Liu interrupts-extended = <&cpu0_intc 3>; 5477874ebdSJunhui Liu }; 5577874ebdSJunhui Liu 5677874ebdSJunhui Liu aclint_mtimer: timer@68035000 { 5777874ebdSJunhui Liu compatible = "anlogic,dr1v90-aclint-mtimer", "nuclei,ux900-aclint-mtimer"; 5877874ebdSJunhui Liu reg = <0x0 0x68035000 0x0 0x8000>; 5977874ebdSJunhui Liu reg-names = "mtimecmp"; 6077874ebdSJunhui Liu interrupts-extended = <&cpu0_intc 7>; 6177874ebdSJunhui Liu }; 6277874ebdSJunhui Liu 6377874ebdSJunhui Liu aclint_sswi: interrupt-controller@6803d000 { 6477874ebdSJunhui Liu compatible = "anlogic,dr1v90-aclint-sswi", "nuclei,ux900-aclint-sswi"; 6577874ebdSJunhui Liu reg = <0x0 0x6803d000 0x0 0x3000>; 6677874ebdSJunhui Liu #interrupt-cells = <0>; 6777874ebdSJunhui Liu interrupt-controller; 6877874ebdSJunhui Liu interrupts-extended = <&cpu0_intc 1>; 6977874ebdSJunhui Liu }; 7077874ebdSJunhui Liu 7177874ebdSJunhui Liu plic: interrupt-controller@6c000000 { 7277874ebdSJunhui Liu compatible = "anlogic,dr1v90-plic", "sifive,plic-1.0.0"; 7377874ebdSJunhui Liu reg = <0x0 0x6c000000 0x0 0x4000000>; 7477874ebdSJunhui Liu #address-cells = <0>; 7577874ebdSJunhui Liu #interrupt-cells = <1>; 7677874ebdSJunhui Liu interrupt-controller; 7777874ebdSJunhui Liu interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; 7877874ebdSJunhui Liu riscv,ndev = <150>; 7977874ebdSJunhui Liu }; 8077874ebdSJunhui Liu 8177874ebdSJunhui Liu uart0: serial@f8400000 { 8277874ebdSJunhui Liu compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart"; 8377874ebdSJunhui Liu reg = <0x0 0xf8400000 0x0 0x1000>; 8477874ebdSJunhui Liu clock-frequency = <50000000>; 8577874ebdSJunhui Liu interrupts = <71>; 8677874ebdSJunhui Liu reg-io-width = <4>; 8777874ebdSJunhui Liu reg-shift = <2>; 8877874ebdSJunhui Liu status = "disabled"; 8977874ebdSJunhui Liu }; 9077874ebdSJunhui Liu 9177874ebdSJunhui Liu uart1: serial@f8401000 { 9277874ebdSJunhui Liu compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart"; 9377874ebdSJunhui Liu reg = <0x0 0xf8401000 0x0 0x1000>; 9477874ebdSJunhui Liu clock-frequency = <50000000>; 9577874ebdSJunhui Liu interrupts = <72>; 9677874ebdSJunhui Liu reg-io-width = <4>; 9777874ebdSJunhui Liu reg-shift = <2>; 9877874ebdSJunhui Liu status = "disabled"; 9977874ebdSJunhui Liu }; 10077874ebdSJunhui Liu }; 10177874ebdSJunhui Liu}; 102