1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech> 4 */ 5 6/dts-v1/; 7/ { 8 #address-cells = <2>; 9 #size-cells = <2>; 10 model = "Anlogic DR1V90"; 11 compatible = "anlogic,dr1v90"; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 timebase-frequency = <800000000>; 17 18 cpu@0 { 19 compatible = "nuclei,ux900", "riscv"; 20 d-cache-block-size = <64>; 21 d-cache-sets = <256>; 22 d-cache-size = <32768>; 23 device_type = "cpu"; 24 i-cache-block-size = <64>; 25 i-cache-sets = <256>; 26 i-cache-size = <32768>; 27 mmu-type = "riscv,sv39"; 28 reg = <0>; 29 riscv,isa-base = "rv64i"; 30 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", 31 "zba", "zbb", "zbc", "zbkc", "zbs", 32 "zicntr", "zicsr", "zifencei", 33 "zihintpause", "zihpm"; 34 35 cpu0_intc: interrupt-controller { 36 compatible = "riscv,cpu-intc"; 37 #interrupt-cells = <1>; 38 interrupt-controller; 39 }; 40 }; 41 }; 42 43 soc { 44 compatible = "simple-bus"; 45 interrupt-parent = <&plic>; 46 #address-cells = <2>; 47 #size-cells = <2>; 48 ranges; 49 50 aclint_mswi: interrupt-controller@68031000 { 51 compatible = "anlogic,dr1v90-aclint-mswi", "nuclei,ux900-aclint-mswi"; 52 reg = <0x0 0x68031000 0x0 0x4000>; 53 interrupts-extended = <&cpu0_intc 3>; 54 }; 55 56 aclint_mtimer: timer@68035000 { 57 compatible = "anlogic,dr1v90-aclint-mtimer", "nuclei,ux900-aclint-mtimer"; 58 reg = <0x0 0x68035000 0x0 0x8000>; 59 reg-names = "mtimecmp"; 60 interrupts-extended = <&cpu0_intc 7>; 61 }; 62 63 aclint_sswi: interrupt-controller@6803d000 { 64 compatible = "anlogic,dr1v90-aclint-sswi", "nuclei,ux900-aclint-sswi"; 65 reg = <0x0 0x6803d000 0x0 0x3000>; 66 #interrupt-cells = <0>; 67 interrupt-controller; 68 interrupts-extended = <&cpu0_intc 1>; 69 }; 70 71 plic: interrupt-controller@6c000000 { 72 compatible = "anlogic,dr1v90-plic", "sifive,plic-1.0.0"; 73 reg = <0x0 0x6c000000 0x0 0x4000000>; 74 #address-cells = <0>; 75 #interrupt-cells = <1>; 76 interrupt-controller; 77 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; 78 riscv,ndev = <150>; 79 }; 80 81 uart0: serial@f8400000 { 82 compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart"; 83 reg = <0x0 0xf8400000 0x0 0x1000>; 84 clock-frequency = <50000000>; 85 interrupts = <71>; 86 reg-io-width = <4>; 87 reg-shift = <2>; 88 status = "disabled"; 89 }; 90 91 uart1: serial@f8401000 { 92 compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart"; 93 reg = <0x0 0xf8401000 0x0 0x1000>; 94 clock-frequency = <50000000>; 95 interrupts = <72>; 96 reg-io-width = <4>; 97 reg-shift = <2>; 98 status = "disabled"; 99 }; 100 }; 101}; 102