1/ { 2 compatible = "opencores,or1ksim"; 3 #address-cells = <1>; 4 #size-cells = <1>; 5 interrupt-parent = <&pic>; 6 7 aliases { 8 uart0 = &serial0; 9 }; 10 11 chosen { 12 bootargs = "earlycon"; 13 stdout-path = "uart0:115200"; 14 }; 15 16 memory@0 { 17 device_type = "memory"; 18 reg = <0x00000000 0x02000000>; 19 }; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 compatible = "opencores,or1200-rtlsvn481"; 27 reg = <0>; 28 }; 29 30 cpu1: cpu@1 { 31 compatible = "opencores,or1200-rtlsvn481"; 32 reg = <1>; 33 }; 34 }; 35 36 ompic: ompic@98000000 { 37 compatible = "openrisc,ompic"; 38 reg = <0x98000000 16>; 39 interrupt-controller; 40 #interrupt-cells = <0>; 41 interrupts = <1>; 42 }; 43 44 /* 45 * OR1K PIC is built into CPU and accessed via special purpose 46 * registers. It is not addressable and, hence, has no 'reg' 47 * property. 48 */ 49 pic: pic { 50 compatible = "opencores,or1k-pic-level"; 51 #interrupt-cells = <1>; 52 interrupt-controller; 53 }; 54 55 serial0: serial@90000000 { 56 compatible = "opencores,uart16550-rtlsvn105", "ns16550a"; 57 reg = <0x90000000 0x100>; 58 interrupts = <2>; 59 }; 60 61 enet0: ethoc@92000000 { 62 compatible = "opencores,ethoc"; 63 reg = <0x92000000 0x800>; 64 interrupts = <4>; 65 big-endian; 66 status = "disabled"; 67 }; 68}; 69