1// SPDX-License-Identifier: GPL-2.0-or-later 2/dts-v1/; 3 4#include "rtl9302c.dtsi" 5 6#include <dt-bindings/input/input.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/leds/common.h> 9#include <dt-bindings/thermal/thermal.h> 10 11/ { 12 compatible = "cameo,rtl9302c-2x-rtl8224-2xge", "realtek,rtl9302-soc"; 13 model = "RTL9302C Development Board"; 14 15 memory@0 { 16 device_type = "memory"; 17 reg = <0x0 0x8000000>; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23}; 24 25&uart0 { 26 status = "okay"; 27}; 28 29&spi0 { 30 status = "okay"; 31 flash@0 { 32 compatible = "jedec,spi-nor"; 33 reg = <0>; 34 spi-max-frequency = <10000000>; 35 36 partitions { 37 compatible = "fixed-partitions"; 38 #address-cells = <1>; 39 #size-cells = <1>; 40 41 partition@0 { 42 label = "LOADER"; 43 reg = <0x0 0xe0000>; 44 read-only; 45 }; 46 partition@e0000 { 47 label = "BDINFO"; 48 reg = <0xe0000 0x10000>; 49 }; 50 partition@f0000 { 51 label = "SYSINFO"; 52 reg = <0xf0000 0x10000>; 53 read-only; 54 }; 55 partition@100000 { 56 label = "JFFS2 CFG"; 57 reg = <0x100000 0x100000>; 58 }; 59 partition@200000 { 60 label = "JFFS2 LOG"; 61 reg = <0x200000 0x100000>; 62 }; 63 partition@300000 { 64 label = "RUNTIME"; 65 reg = <0x300000 0xe80000>; 66 }; 67 partition@1180000 { 68 label = "RUNTIME2"; 69 reg = <0x1180000 0xe80000>; 70 }; 71 }; 72 }; 73}; 74 75&mdio0 { 76 /* External RTL8224 */ 77 phy0: ethernet-phy@0 { 78 reg = <0>; 79 compatible = "ethernet-phy-ieee802.3-c45"; 80 }; 81 phy1: ethernet-phy@1 { 82 reg = <1>; 83 compatible = "ethernet-phy-ieee802.3-c45"; 84 }; 85 phy2: ethernet-phy@2 { 86 reg = <2>; 87 compatible = "ethernet-phy-ieee802.3-c45"; 88 }; 89 phy3: ethernet-phy@3 { 90 reg = <3>; 91 compatible = "ethernet-phy-ieee802.3-c45"; 92 }; 93}; 94 95&mdio1 { 96 /* External RTL8224 */ 97 phy4: ethernet-phy@0 { 98 reg = <0>; 99 compatible = "ethernet-phy-ieee802.3-c45"; 100 }; 101 phy5: ethernet-phy@1 { 102 reg = <1>; 103 compatible = "ethernet-phy-ieee802.3-c45"; 104 }; 105 phy6: ethernet-phy@2 { 106 reg = <2>; 107 compatible = "ethernet-phy-ieee802.3-c45"; 108 }; 109 phy7: ethernet-phy@3 { 110 reg = <3>; 111 compatible = "ethernet-phy-ieee802.3-c45"; 112 }; 113}; 114 115&switch0 { 116 ethernet-ports { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 120 port@0 { 121 reg = <0>; 122 phy-handle = <&phy0>; 123 phy-mode = "usxgmii"; 124 }; 125 port@1 { 126 reg = <1>; 127 phy-handle = <&phy1>; 128 phy-mode = "usxgmii"; 129 }; 130 port@2 { 131 reg = <2>; 132 phy-handle = <&phy2>; 133 phy-mode = "usxgmii"; 134 }; 135 port@3 { 136 reg = <3>; 137 phy-handle = <&phy3>; 138 phy-mode = "usxgmii"; 139 }; 140 port@16 { 141 reg = <16>; 142 phy-handle = <&phy4>; 143 phy-mode = "usxgmii"; 144 }; 145 port@17 { 146 reg = <17>; 147 phy-handle = <&phy5>; 148 phy-mode = "usxgmii"; 149 }; 150 port@18 { 151 reg = <18>; 152 phy-handle = <&phy6>; 153 phy-mode = "usxgmii"; 154 }; 155 port@19 { 156 reg = <19>; 157 phy-handle = <&phy7>; 158 phy-mode = "usxgmii"; 159 }; 160 port@24{ 161 reg = <24>; 162 phy-mode = "10gbase-r"; 163 }; 164 port@25{ 165 reg = <25>; 166 phy-mode = "10gbase-r"; 167 }; 168 }; 169}; 170