1// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2/* 3 * Copyright 2025 Mobileye Vision Technologies Ltd. 4 */ 5 6#include <dt-bindings/interrupt-controller/mips-gic.h> 7 8#include <dt-bindings/clock/mobileye,eyeq6lplus-clk.h> 9 10/ { 11 #address-cells = <2>; 12 #size-cells = <2>; 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 cpu@0 { 17 device_type = "cpu"; 18 compatible = "img,i6500"; 19 reg = <0>; 20 clocks = <&olb EQ6LPC_CPU_OCC>; 21 }; 22 }; 23 24 cpu_intc: interrupt-controller { 25 compatible = "mti,cpu-interrupt-controller"; 26 interrupt-controller; 27 #address-cells = <0>; 28 #interrupt-cells = <1>; 29 }; 30 31 coherency-manager { 32 compatible = "mobileye,eyeq6-cm"; 33 }; 34 35 xtal: clock-30000000 { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <30000000>; 39 }; 40 41 soc: soc { 42 compatible = "simple-bus"; 43 #address-cells = <2>; 44 #size-cells = <2>; 45 ranges; 46 47 olb: system-controller@e8400000 { 48 compatible = "mobileye,eyeq6lplus-olb", "syscon"; 49 reg = <0 0xe8400000 0x0 0x80000>; 50 #reset-cells = <2>; 51 #clock-cells = <1>; 52 clocks = <&xtal>; 53 clock-names = "ref"; 54 }; 55 56 ospi: spi@e8800000 { 57 compatible = "mobileye,eyeq5-ospi", "cdns,qspi-nor"; 58 #address-cells = <1>; 59 #size-cells = <0>; 60 reg = <0 0xe8800000 0x0 0x100000>, 61 <0 0xb0000000 0x0 0x30000000>; 62 interrupt-parent = <&gic>; 63 interrupts = <GIC_SHARED 10 IRQ_TYPE_LEVEL_HIGH>; 64 cdns,fifo-depth = <128>; 65 cdns,fifo-width = <4>; 66 cdns,trigger-address = <0x00000000>; 67 clocks = <&olb EQ6LPC_PER_OSPI>; 68 status = "disabled"; 69 }; 70 71 spi0: spi@eac0d000 { 72 compatible = "snps,dw-apb-ssi"; 73 reg = <0 0xeac0d000 0x0 0x1000>; 74 clocks = <&olb EQ6LPC_PER_SPI>; 75 interrupt-parent = <&gic>; 76 interrupts = <GIC_SHARED 11 IRQ_TYPE_LEVEL_HIGH>; 77 resets = <&olb 0 0>; 78 reset-names = "spi"; 79 #address-cells = <1>; 80 #size-cells = <0>; 81 status = "disabled"; 82 }; 83 84 spi1: spi@eac0e000 { 85 compatible = "snps,dw-apb-ssi"; 86 reg = <0 0xeac0e000 0x0 0x1000>; 87 spi-slave; 88 clocks = <&olb EQ6LPC_PER_SPI>; 89 interrupt-parent = <&gic>; 90 interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>; 91 resets = <&olb 0 1>; 92 reset-names = "spi"; 93 #address-cells = <0>; 94 #size-cells = <0>; 95 status = "disabled"; 96 }; 97 98 uart0: serial@eac10000 { 99 compatible = "snps,dw-apb-uart"; 100 reg-shift = <2>; 101 reg-io-width = <4>; 102 clocks = <&olb EQ6LPC_PER_UART>; 103 clock-frequency = <15625000>; 104 reg = <0 0xeac10000 0x0 0x1000>; 105 interrupt-parent = <&gic>; 106 interrupts = <GIC_SHARED 8 IRQ_TYPE_LEVEL_HIGH>; 107 resets = <&olb 0 2>; 108 status = "disabled"; 109 }; 110 111 i2c0: i2c@eac11000 { 112 compatible = "mobileye,eyeq6lplus-i2c", "snps,designware-i2c"; 113 reg = <0 0xeac11000 0x0 0x1000>; 114 interrupt-parent = <&gic>; 115 interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; 116 clock-frequency = <400000>; 117 clocks = <&olb EQ6LPC_PER_I2C_SER>; 118 resets = <&olb 0 3>; 119 i2c-sda-hold-time-ns = <50>; 120 status = "disabled"; 121 }; 122 123 i2c1: i2c@eac12000 { 124 compatible = "mobileye,eyeq6lplus-i2c", "snps,designware-i2c"; 125 reg = <0 0xeac12000 0x0 0x1000>; 126 interrupt-parent = <&gic>; 127 interrupts = <GIC_SHARED 7 IRQ_TYPE_LEVEL_HIGH>; 128 clock-frequency = <400000>; 129 clocks = <&olb EQ6LPC_PER_I2C_SER>; 130 resets = <&olb 0 4>; 131 i2c-sda-hold-time-ns = <50>; 132 status = "disabled"; 133 }; 134 135 gpio: gpio@eac14000 { 136 compatible = "snps,dw-apb-gpio"; 137 reg = <0x0 0xeac14000 0x0 0x1000>; 138 #address-cells = <1>; 139 #size-cells = <0>; 140 resets = <&olb 0 13>; 141 porta: gpio-port@0 { 142 compatible = "snps,dw-apb-gpio-port"; 143 gpio-controller; 144 #gpio-cells = <2>; 145 snps,nr-gpios = <32>; 146 gpio-ranges = <&olb 0 0 32>; 147 reg = <0>; 148 interrupt-controller; 149 #interrupt-cells = <2>; 150 interrupt-parent = <&gic>; 151 interrupts = <GIC_SHARED 13 IRQ_TYPE_LEVEL_HIGH>; 152 }; 153 }; 154 155 gic: interrupt-controller@f0920000 { 156 compatible = "mti,gic"; 157 reg = <0x0 0xf0920000 0x0 0x20000>; 158 interrupt-controller; 159 #interrupt-cells = <3>; 160 interrupt-parent = <&cpu_intc>; 161 timer { 162 compatible = "mti,gic-timer"; 163 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; 164 clocks = <&olb EQ6LPC_CPU_OCC>; 165 }; 166 }; 167 }; 168}; 169 170#include "eyeq6lplus-pins.dtsi" 171