xref: /linux/scripts/dtc/include-prefixes/dt-bindings/reset/qcom,ipq9650-gcc.h (revision b2128290c29902315e632ea59e0504d6bc9e9b42)
1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /*
3  * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4  */
5 
6 #ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ9650_H
7 #define _DT_BINDINGS_RESET_IPQ_GCC_IPQ9650_H
8 
9 #define GCC_ADSS_BCR						0
10 #define GCC_ADSS_PWM_CLK_ARES					1
11 #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR			2
12 #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES		3
13 #define GCC_APSS_AHB_CLK_ARES					4
14 #define GCC_APSS_ATB_CLK_ARES					5
15 #define GCC_APSS_AXI_CLK_ARES					6
16 #define GCC_APSS_TS_CLK_ARES					7
17 #define GCC_BOOT_ROM_AHB_CLK_ARES				8
18 #define GCC_BOOT_ROM_BCR					9
19 #define GCC_CMN_12GPLL_AHB_CLK_ARES				10
20 #define GCC_CMN_12GPLL_APU_CLK_ARES				11
21 #define GCC_CMN_12GPLL_SYS_CLK_ARES				12
22 #define GCC_CMN_BLK_BCR						13
23 #define GCC_CMN_LDO_CLK_ARES					14
24 #define GCC_CPUSS_TRIG_CLK_ARES					15
25 #define GCC_GP1_CLK_ARES					16
26 #define GCC_GP2_CLK_ARES					17
27 #define GCC_GP3_CLK_ARES					18
28 #define GCC_MDIO_AHB_CLK_ARES					19
29 #define GCC_MDIO_BCR						20
30 #define GCC_NSSCC_CLK_ARES					21
31 #define GCC_NSSCFG_CLK_ARES					22
32 #define GCC_NSSNOC_ATB_CLK_ARES					23
33 #define GCC_NSSNOC_MEMNOC_1_CLK_ARES				24
34 #define GCC_NSSNOC_MEMNOC_CLK_ARES				25
35 #define GCC_NSSNOC_NSSCC_CLK_ARES				26
36 #define GCC_NSSNOC_PCNOC_1_CLK_ARES				27
37 #define GCC_NSSNOC_QOSGEN_REF_CLK_ARES				28
38 #define GCC_NSSNOC_SNOC_1_CLK_ARES				29
39 #define GCC_NSSNOC_SNOC_CLK_ARES				30
40 #define GCC_NSSNOC_TIMEOUT_REF_CLK_ARES				31
41 #define GCC_NSSNOC_XO_DCD_CLK_ARES				32
42 #define GCC_NSS_BCR						33
43 #define GCC_NSS_TS_CLK_ARES					34
44 #define GCC_PCIE0PHY_PHY_BCR					35
45 #define GCC_PCIE0_AHB_CLK_ARES					36
46 #define GCC_PCIE0_AHB_RESET					37
47 #define GCC_PCIE0_AUX_CLK_ARES					38
48 #define GCC_PCIE0_AUX_RESET					39
49 #define GCC_PCIE0_AXI_M_CLK_ARES				40
50 #define GCC_PCIE0_AXI_M_RESET					41
51 #define GCC_PCIE0_AXI_M_STICKY_RESET				42
52 #define GCC_PCIE0_AXI_S_BRIDGE_CLK_ARES				43
53 #define GCC_PCIE0_AXI_S_CLK_ARES				44
54 #define GCC_PCIE0_AXI_S_RESET					45
55 #define GCC_PCIE0_AXI_S_STICKY_RESET				46
56 #define GCC_PCIE0_BCR						47
57 #define GCC_PCIE0_CORE_STICKY_RESET				48
58 #define GCC_PCIE0_LINK_DOWN_BCR					49
59 #define GCC_PCIE0_PHY_BCR					50
60 #define GCC_PCIE0_PIPE_CLK_ARES					51
61 #define GCC_PCIE0_PIPE_RESET					52
62 #define GCC_PCIE1PHY_PHY_BCR					53
63 #define GCC_PCIE1_AHB_CLK_ARES					54
64 #define GCC_PCIE1_AHB_RESET					55
65 #define GCC_PCIE1_AUX_CLK_ARES					56
66 #define GCC_PCIE1_AUX_RESET					57
67 #define GCC_PCIE1_AXI_M_CLK_ARES				58
68 #define GCC_PCIE1_AXI_M_RESET					59
69 #define GCC_PCIE1_AXI_M_STICKY_RESET				60
70 #define GCC_PCIE1_AXI_S_BRIDGE_CLK_ARES				61
71 #define GCC_PCIE1_AXI_S_CLK_ARES				62
72 #define GCC_PCIE1_AXI_S_RESET					63
73 #define GCC_PCIE1_AXI_S_STICKY_RESET				64
74 #define GCC_PCIE1_BCR						65
75 #define GCC_PCIE1_CORE_STICKY_RESET				66
76 #define GCC_PCIE1_LINK_DOWN_BCR					67
77 #define GCC_PCIE1_PHY_BCR					68
78 #define GCC_PCIE1_PIPE_CLK_ARES					69
79 #define GCC_PCIE1_PIPE_RESET					70
80 #define GCC_PCIE2PHY_PHY_BCR					71
81 #define GCC_PCIE2_AHB_CLK_ARES					72
82 #define GCC_PCIE2_AHB_RESET					73
83 #define GCC_PCIE2_AUX_CLK_ARES					74
84 #define GCC_PCIE2_AUX_RESET					75
85 #define GCC_PCIE2_AXI_M_CLK_ARES				76
86 #define GCC_PCIE2_AXI_M_RESET					77
87 #define GCC_PCIE2_AXI_M_STICKY_RESET				78
88 #define GCC_PCIE2_AXI_S_BRIDGE_CLK_ARES				79
89 #define GCC_PCIE2_AXI_S_CLK_ARES				80
90 #define GCC_PCIE2_AXI_S_RESET					81
91 #define GCC_PCIE2_AXI_S_STICKY_RESET				82
92 #define GCC_PCIE2_BCR						83
93 #define GCC_PCIE2_CORE_STICKY_RESET				84
94 #define GCC_PCIE2_LINK_DOWN_BCR					85
95 #define GCC_PCIE2_PHY_BCR					86
96 #define GCC_PCIE2_PIPE_CLK_ARES					87
97 #define GCC_PCIE2_PIPE_RESET					88
98 #define GCC_PCIE3PHY_PHY_BCR					89
99 #define GCC_PCIE3_AHB_CLK_ARES					90
100 #define GCC_PCIE3_AHB_RESET					91
101 #define GCC_PCIE3_AUX_CLK_ARES					92
102 #define GCC_PCIE3_AUX_RESET					93
103 #define GCC_PCIE3_AXI_M_CLK_ARES				94
104 #define GCC_PCIE3_AXI_M_RESET					95
105 #define GCC_PCIE3_AXI_M_STICKY_RESET				96
106 #define GCC_PCIE3_AXI_S_BRIDGE_CLK_ARES				97
107 #define GCC_PCIE3_AXI_S_CLK_ARES				98
108 #define GCC_PCIE3_AXI_S_RESET					99
109 #define GCC_PCIE3_AXI_S_STICKY_RESET				100
110 #define GCC_PCIE3_BCR						101
111 #define GCC_PCIE3_CORE_STICKY_RESET				102
112 #define GCC_PCIE3_LINK_DOWN_BCR					103
113 #define GCC_PCIE3_PHY_BCR					104
114 #define GCC_PCIE3_PIPE_CLK_ARES					105
115 #define GCC_PCIE3_PIPE_RESET					106
116 #define GCC_PCIE4PHY_PHY_BCR					107
117 #define GCC_PCIE4_AHB_CLK_ARES					108
118 #define GCC_PCIE4_AHB_RESET					109
119 #define GCC_PCIE4_AUX_CLK_ARES					110
120 #define GCC_PCIE4_AUX_RESET					111
121 #define GCC_PCIE4_AXI_M_CLK_ARES				112
122 #define GCC_PCIE4_AXI_M_RESET					113
123 #define GCC_PCIE4_AXI_M_STICKY_RESET				114
124 #define GCC_PCIE4_AXI_S_BRIDGE_CLK_ARES				115
125 #define GCC_PCIE4_AXI_S_CLK_ARES				116
126 #define GCC_PCIE4_AXI_S_RESET					117
127 #define GCC_PCIE4_AXI_S_STICKY_RESET				118
128 #define GCC_PCIE4_BCR						119
129 #define GCC_PCIE4_CORE_STICKY_RESET				120
130 #define GCC_PCIE4_LINK_DOWN_BCR					121
131 #define GCC_PCIE4_PHY_BCR					122
132 #define GCC_PCIE4_PIPE_CLK_ARES					123
133 #define GCC_PCIE4_PIPE_RESET					124
134 #define GCC_QDSS_APB2JTAG_CLK_ARES				125
135 #define GCC_QDSS_AT_CLK_ARES					126
136 #define GCC_QDSS_BCR						127
137 #define GCC_QDSS_CFG_AHB_CLK_ARES				128
138 #define GCC_QDSS_DAP_AHB_CLK_ARES				129
139 #define GCC_QDSS_DAP_CLK_ARES					130
140 #define GCC_QDSS_ETR_USB_CLK_ARES				131
141 #define GCC_QDSS_EUD_AT_CLK_ARES				132
142 #define GCC_QDSS_STM_CLK_ARES					133
143 #define GCC_QDSS_TRACECLKIN_CLK_ARES				134
144 #define GCC_QDSS_TSCTR_DIV16_CLK_ARES				135
145 #define GCC_QDSS_TSCTR_DIV2_CLK_ARES				136
146 #define GCC_QDSS_TSCTR_DIV3_CLK_ARES				137
147 #define GCC_QDSS_TSCTR_DIV4_CLK_ARES				138
148 #define GCC_QDSS_TSCTR_DIV8_CLK_ARES				139
149 #define GCC_QDSS_TS_CLK_ARES					140
150 #define GCC_QPIC_AHB_CLK_ARES					141
151 #define GCC_QPIC_BCR						142
152 #define GCC_QPIC_CLK_ARES					143
153 #define GCC_QPIC_IO_MACRO_CLK_ARES				144
154 #define GCC_QPIC_SLEEP_CLK_ARES					145
155 #define GCC_QUPV3_2X_CORE_CLK_ARES				146
156 #define GCC_QUPV3_AHB_MST_CLK_ARES				147
157 #define GCC_QUPV3_AHB_SLV_CLK_ARES				148
158 #define GCC_QUPV3_BCR						149
159 #define GCC_QUPV3_CORE_CLK_ARES					150
160 #define GCC_QUPV3_WRAP_SE0_BCR					151
161 #define GCC_QUPV3_WRAP_SE0_CLK_ARES				152
162 #define GCC_QUPV3_WRAP_SE1_BCR					153
163 #define GCC_QUPV3_WRAP_SE1_CLK_ARES				154
164 #define GCC_QUPV3_WRAP_SE2_BCR					155
165 #define GCC_QUPV3_WRAP_SE2_CLK_ARES				156
166 #define GCC_QUPV3_WRAP_SE3_BCR					157
167 #define GCC_QUPV3_WRAP_SE3_CLK_ARES				158
168 #define GCC_QUPV3_WRAP_SE4_BCR					159
169 #define GCC_QUPV3_WRAP_SE4_CLK_ARES				160
170 #define GCC_QUPV3_WRAP_SE5_BCR					161
171 #define GCC_QUPV3_WRAP_SE5_CLK_ARES				162
172 #define GCC_QUPV3_WRAP_SE6_BCR					163
173 #define GCC_QUPV3_WRAP_SE6_CLK_ARES				164
174 #define GCC_QUPV3_WRAP_SE7_BCR					165
175 #define GCC_QUPV3_WRAP_SE7_CLK_ARES				166
176 #define GCC_QUSB2_0_PHY_BCR					167
177 #define GCC_QUSB2_1_PHY_BCR					168
178 #define GCC_SDCC1_APPS_CLK_ARES					169
179 #define GCC_SDCC1_ICE_CORE_CLK_ARES				170
180 #define GCC_SDCC_BCR						171
181 #define GCC_TLMM_AHB_CLK_ARES					172
182 #define GCC_TLMM_BCR						173
183 #define GCC_TLMM_CLK_ARES					174
184 #define GCC_UNIPHY0_AHB_CLK_ARES				175
185 #define GCC_UNIPHY0_BCR						176
186 #define GCC_UNIPHY0_PMA_BCR					177
187 #define GCC_UNIPHY0_SYS_CLK_ARES				178
188 #define GCC_UNIPHY0_XPCS_ARES					179
189 #define GCC_UNIPHY1_AHB_CLK_ARES				180
190 #define GCC_UNIPHY1_BCR						181
191 #define GCC_UNIPHY1_PMA_BCR					182
192 #define GCC_UNIPHY1_SYS_CLK_ARES				183
193 #define GCC_UNIPHY1_XPCS_ARES					184
194 #define GCC_UNIPHY2_AHB_CLK_ARES				185
195 #define GCC_UNIPHY2_BCR						186
196 #define GCC_UNIPHY2_PMA_BCR					187
197 #define GCC_UNIPHY2_SYS_CLK_ARES				188
198 #define GCC_UNIPHY2_XPCS_ARES					189
199 #define GCC_USB0_AUX_CLK_ARES					190
200 #define GCC_USB0_MASTER_CLK_ARES				191
201 #define GCC_USB0_MOCK_UTMI_CLK_ARES				192
202 #define GCC_USB0_PHY_BCR					193
203 #define GCC_USB0_PHY_CFG_AHB_CLK_ARES				194
204 #define GCC_USB0_PIPE_CLK_ARES					195
205 #define GCC_USB0_SLEEP_CLK_ARES					196
206 #define GCC_USB1_BCR						197
207 #define GCC_USB1_MASTER_CLK_ARES				198
208 #define GCC_USB1_MOCK_UTMI_CLK_ARES				199
209 #define GCC_USB1_PHY_CFG_AHB_CLK_ARES				200
210 #define GCC_USB1_SLEEP_CLK_ARES					201
211 #define GCC_USB3PHY_0_PHY_BCR					202
212 #define GCC_USB_BCR						203
213 #define GCC_UNIPHY1_XLGPCS_ARES					204
214 #define GCC_UNIPHY2_XLGPCS_ARES					205
215 #endif
216