1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H 7 #define _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H 8 9 #define EDMA_HW_RESET 0 10 #define NSS_CC_CE_BCR 1 11 #define NSS_CC_CLC_BCR 2 12 #define NSS_CC_EIP197_BCR 3 13 #define NSS_CC_HAQ_BCR 4 14 #define NSS_CC_IMEM_BCR 5 15 #define NSS_CC_MAC_BCR 6 16 #define NSS_CC_PPE_BCR 7 17 #define NSS_CC_UBI_BCR 8 18 #define NSS_CC_UNIPHY_BCR 9 19 #define UBI3_CLKRST_CLAMP_ENABLE 10 20 #define UBI3_CORE_CLAMP_ENABLE 11 21 #define UBI2_CLKRST_CLAMP_ENABLE 12 22 #define UBI2_CORE_CLAMP_ENABLE 13 23 #define UBI1_CLKRST_CLAMP_ENABLE 14 24 #define UBI1_CORE_CLAMP_ENABLE 15 25 #define UBI0_CLKRST_CLAMP_ENABLE 16 26 #define UBI0_CORE_CLAMP_ENABLE 17 27 #define NSSNOC_NSS_CSR_ARES 18 28 #define NSS_CSR_ARES 19 29 #define PPE_BTQ_ARES 20 30 #define PPE_IPE_ARES 21 31 #define PPE_ARES 22 32 #define PPE_CFG_ARES 23 33 #define PPE_EDMA_ARES 24 34 #define PPE_EDMA_CFG_ARES 25 35 #define CRY_PPE_ARES 26 36 #define NSSNOC_PPE_ARES 27 37 #define NSSNOC_PPE_CFG_ARES 28 38 #define PORT1_MAC_ARES 29 39 #define PORT2_MAC_ARES 30 40 #define PORT3_MAC_ARES 31 41 #define PORT4_MAC_ARES 32 42 #define PORT5_MAC_ARES 33 43 #define PORT6_MAC_ARES 34 44 #define XGMAC0_PTP_REF_ARES 35 45 #define XGMAC1_PTP_REF_ARES 36 46 #define XGMAC2_PTP_REF_ARES 37 47 #define XGMAC3_PTP_REF_ARES 38 48 #define XGMAC4_PTP_REF_ARES 39 49 #define XGMAC5_PTP_REF_ARES 40 50 #define HAQ_AHB_ARES 41 51 #define HAQ_AXI_ARES 42 52 #define NSSNOC_HAQ_AHB_ARES 43 53 #define NSSNOC_HAQ_AXI_ARES 44 54 #define CE_APB_ARES 45 55 #define CE_AXI_ARES 46 56 #define NSSNOC_CE_APB_ARES 47 57 #define NSSNOC_CE_AXI_ARES 48 58 #define CRYPTO_ARES 49 59 #define NSSNOC_CRYPTO_ARES 50 60 #define NSSNOC_NC_AXI0_1_ARES 51 61 #define UBI0_CORE_ARES 52 62 #define UBI1_CORE_ARES 53 63 #define UBI2_CORE_ARES 54 64 #define UBI3_CORE_ARES 55 65 #define NC_AXI0_ARES 56 66 #define UTCM0_ARES 57 67 #define NC_AXI1_ARES 58 68 #define UTCM1_ARES 59 69 #define NC_AXI2_ARES 60 70 #define UTCM2_ARES 61 71 #define NC_AXI3_ARES 62 72 #define UTCM3_ARES 63 73 #define NSSNOC_NC_AXI0_ARES 64 74 #define AHB0_ARES 65 75 #define INTR0_AHB_ARES 66 76 #define AHB1_ARES 67 77 #define INTR1_AHB_ARES 68 78 #define AHB2_ARES 69 79 #define INTR2_AHB_ARES 70 80 #define AHB3_ARES 71 81 #define INTR3_AHB_ARES 72 82 #define NSSNOC_AHB0_ARES 73 83 #define NSSNOC_INT0_AHB_ARES 74 84 #define AXI0_ARES 75 85 #define AXI1_ARES 76 86 #define AXI2_ARES 77 87 #define AXI3_ARES 78 88 #define NSSNOC_AXI0_ARES 79 89 #define IMEM_QSB_ARES 80 90 #define NSSNOC_IMEM_QSB_ARES 81 91 #define IMEM_AHB_ARES 82 92 #define NSSNOC_IMEM_AHB_ARES 83 93 #define UNIPHY_PORT1_RX_ARES 84 94 #define UNIPHY_PORT1_TX_ARES 85 95 #define UNIPHY_PORT2_RX_ARES 86 96 #define UNIPHY_PORT2_TX_ARES 87 97 #define UNIPHY_PORT3_RX_ARES 88 98 #define UNIPHY_PORT3_TX_ARES 89 99 #define UNIPHY_PORT4_RX_ARES 90 100 #define UNIPHY_PORT4_TX_ARES 91 101 #define UNIPHY_PORT5_RX_ARES 92 102 #define UNIPHY_PORT5_TX_ARES 93 103 #define UNIPHY_PORT6_RX_ARES 94 104 #define UNIPHY_PORT6_TX_ARES 95 105 #define PORT1_RX_ARES 96 106 #define PORT1_TX_ARES 97 107 #define PORT2_RX_ARES 98 108 #define PORT2_TX_ARES 99 109 #define PORT3_RX_ARES 100 110 #define PORT3_TX_ARES 101 111 #define PORT4_RX_ARES 102 112 #define PORT4_TX_ARES 103 113 #define PORT5_RX_ARES 104 114 #define PORT5_TX_ARES 105 115 #define PORT6_RX_ARES 106 116 #define PORT6_TX_ARES 107 117 #define PPE_FULL_RESET 108 118 #define UNIPHY0_SOFT_RESET 109 119 #define UNIPHY1_SOFT_RESET 110 120 #define UNIPHY2_SOFT_RESET 111 121 #define UNIPHY_PORT1_ARES 112 122 #define UNIPHY_PORT2_ARES 113 123 #define UNIPHY_PORT3_ARES 114 124 #define UNIPHY_PORT4_ARES 115 125 #define UNIPHY_PORT5_ARES 116 126 #define UNIPHY_PORT6_ARES 117 127 #define NSSPORT1_RESET 118 128 #define NSSPORT2_RESET 119 129 #define NSSPORT3_RESET 120 130 #define NSSPORT4_RESET 121 131 #define NSSPORT5_RESET 122 132 #define NSSPORT6_RESET 123 133 134 #endif 135