1*2798cf48SFinley Xiao /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*2798cf48SFinley Xiao /* 3*2798cf48SFinley Xiao * Copyright (c) 2022-2024 Rockchip Electronics Co., Ltd. 4*2798cf48SFinley Xiao */ 5*2798cf48SFinley Xiao #ifndef __DT_BINDINGS_POWER_RK3562_POWER_H__ 6*2798cf48SFinley Xiao #define __DT_BINDINGS_POWER_RK3562_POWER_H__ 7*2798cf48SFinley Xiao 8*2798cf48SFinley Xiao /* VD_CORE */ 9*2798cf48SFinley Xiao #define RK3562_PD_CPU_0 0 10*2798cf48SFinley Xiao #define RK3562_PD_CPU_1 1 11*2798cf48SFinley Xiao #define RK3562_PD_CPU_2 2 12*2798cf48SFinley Xiao #define RK3562_PD_CPU_3 3 13*2798cf48SFinley Xiao #define RK3562_PD_CORE_ALIVE 4 14*2798cf48SFinley Xiao 15*2798cf48SFinley Xiao /* VD_PMU */ 16*2798cf48SFinley Xiao #define RK3562_PD_PMU 5 17*2798cf48SFinley Xiao #define RK3562_PD_PMU_ALIVE 6 18*2798cf48SFinley Xiao 19*2798cf48SFinley Xiao /* VD_NPU */ 20*2798cf48SFinley Xiao #define RK3562_PD_NPU 7 21*2798cf48SFinley Xiao 22*2798cf48SFinley Xiao /* VD_GPU */ 23*2798cf48SFinley Xiao #define RK3562_PD_GPU 8 24*2798cf48SFinley Xiao 25*2798cf48SFinley Xiao /* VD_LOGIC */ 26*2798cf48SFinley Xiao #define RK3562_PD_DDR 9 27*2798cf48SFinley Xiao #define RK3562_PD_VEPU 10 28*2798cf48SFinley Xiao #define RK3562_PD_VDPU 11 29*2798cf48SFinley Xiao #define RK3562_PD_VI 12 30*2798cf48SFinley Xiao #define RK3562_PD_VO 13 31*2798cf48SFinley Xiao #define RK3562_PD_RGA 14 32*2798cf48SFinley Xiao #define RK3562_PD_PHP 15 33*2798cf48SFinley Xiao #define RK3562_PD_LOGIC_ALIVE 16 34*2798cf48SFinley Xiao 35*2798cf48SFinley Xiao #endif 36