1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8750_H 7 #define __DT_BINDINGS_INTERCONNECT_QCOM_SM8750_H 8 9 #define MASTER_QSPI_0 0 10 #define MASTER_QUP_1 1 11 #define MASTER_QUP_3 2 12 #define MASTER_SDCC_4 3 13 #define MASTER_UFS_MEM 4 14 #define MASTER_USB3_0 5 15 #define SLAVE_A1NOC_SNOC 6 16 17 #define MASTER_QDSS_BAM 0 18 #define MASTER_QUP_2 1 19 #define MASTER_CRYPTO 2 20 #define MASTER_IPA 3 21 #define MASTER_SOCCP_AGGR_NOC 4 22 #define MASTER_SP 5 23 #define MASTER_QDSS_ETR 6 24 #define MASTER_QDSS_ETR_1 7 25 #define MASTER_SDCC_2 8 26 #define SLAVE_A2NOC_SNOC 9 27 28 #define MASTER_QUP_CORE_0 0 29 #define MASTER_QUP_CORE_1 1 30 #define MASTER_QUP_CORE_2 2 31 #define SLAVE_QUP_CORE_0 3 32 #define SLAVE_QUP_CORE_1 4 33 #define SLAVE_QUP_CORE_2 5 34 35 #define MASTER_CNOC_CFG 0 36 #define SLAVE_AHB2PHY_SOUTH 1 37 #define SLAVE_AHB2PHY_NORTH 2 38 #define SLAVE_CAMERA_CFG 3 39 #define SLAVE_CLK_CTL 4 40 #define SLAVE_CRYPTO_0_CFG 5 41 #define SLAVE_DISPLAY_CFG 6 42 #define SLAVE_EVA_CFG 7 43 #define SLAVE_GFX3D_CFG 8 44 #define SLAVE_I2C 9 45 #define SLAVE_I3C_IBI0_CFG 10 46 #define SLAVE_I3C_IBI1_CFG 11 47 #define SLAVE_IMEM_CFG 12 48 #define SLAVE_CNOC_MSS 13 49 #define SLAVE_PCIE_CFG 14 50 #define SLAVE_PRNG 15 51 #define SLAVE_QDSS_CFG 16 52 #define SLAVE_QSPI_0 17 53 #define SLAVE_QUP_3 18 54 #define SLAVE_QUP_1 19 55 #define SLAVE_QUP_2 20 56 #define SLAVE_SDCC_2 21 57 #define SLAVE_SDCC_4 22 58 #define SLAVE_SPSS_CFG 23 59 #define SLAVE_TCSR 24 60 #define SLAVE_TLMM 25 61 #define SLAVE_UFS_MEM_CFG 26 62 #define SLAVE_USB3_0 27 63 #define SLAVE_VENUS_CFG 28 64 #define SLAVE_VSENSE_CTRL_CFG 29 65 #define SLAVE_CNOC_MNOC_CFG 30 66 #define SLAVE_PCIE_ANOC_CFG 31 67 #define SLAVE_QDSS_STM 32 68 #define SLAVE_TCU 33 69 70 #define MASTER_GEM_NOC_CNOC 0 71 #define MASTER_GEM_NOC_PCIE_SNOC 1 72 #define SLAVE_AOSS 2 73 #define SLAVE_IPA_CFG 3 74 #define SLAVE_IPC_ROUTER_CFG 4 75 #define SLAVE_SOCCP 5 76 #define SLAVE_TME_CFG 6 77 #define SLAVE_APPSS 7 78 #define SLAVE_CNOC_CFG 8 79 #define SLAVE_DDRSS_CFG 9 80 #define SLAVE_BOOT_IMEM 10 81 #define SLAVE_IMEM 11 82 #define SLAVE_BOOT_IMEM_2 12 83 #define SLAVE_SERVICE_CNOC 13 84 #define SLAVE_PCIE_0 14 85 86 #define MASTER_GPU_TCU 0 87 #define MASTER_SYS_TCU 1 88 #define MASTER_APPSS_PROC 2 89 #define MASTER_GFX3D 3 90 #define MASTER_LPASS_GEM_NOC 4 91 #define MASTER_MSS_PROC 5 92 #define MASTER_MNOC_HF_MEM_NOC 6 93 #define MASTER_MNOC_SF_MEM_NOC 7 94 #define MASTER_COMPUTE_NOC 8 95 #define MASTER_ANOC_PCIE_GEM_NOC 9 96 #define MASTER_SNOC_SF_MEM_NOC 10 97 #define MASTER_UBWC_P 11 98 #define MASTER_GIC 12 99 #define SLAVE_UBWC_P 13 100 #define SLAVE_GEM_NOC_CNOC 14 101 #define SLAVE_LLCC 15 102 #define SLAVE_MEM_NOC_PCIE_SNOC 16 103 104 #define MASTER_LPIAON_NOC 0 105 #define SLAVE_LPASS_GEM_NOC 1 106 107 #define MASTER_LPASS_LPINOC 0 108 #define SLAVE_LPIAON_NOC_LPASS_AG_NOC 1 109 110 #define MASTER_LPASS_PROC 0 111 #define SLAVE_LPICX_NOC_LPIAON_NOC 1 112 113 #define MASTER_LLCC 0 114 #define SLAVE_EBI1 1 115 116 #define MASTER_CAMNOC_HF 0 117 #define MASTER_CAMNOC_NRT_ICP_SF 1 118 #define MASTER_CAMNOC_RT_CDM_SF 2 119 #define MASTER_CAMNOC_SF 3 120 #define MASTER_MDP 4 121 #define MASTER_CDSP_HCP 5 122 #define MASTER_VIDEO_CV_PROC 6 123 #define MASTER_VIDEO_EVA 7 124 #define MASTER_VIDEO_MVP 8 125 #define MASTER_VIDEO_V_PROC 9 126 #define MASTER_CNOC_MNOC_CFG 10 127 #define SLAVE_MNOC_HF_MEM_NOC 11 128 #define SLAVE_MNOC_SF_MEM_NOC 12 129 #define SLAVE_SERVICE_MNOC 13 130 131 #define MASTER_CDSP_PROC 0 132 #define SLAVE_CDSP_MEM_NOC 1 133 134 #define MASTER_PCIE_ANOC_CFG 0 135 #define MASTER_PCIE_0 1 136 #define SLAVE_ANOC_PCIE_GEM_NOC 2 137 #define SLAVE_SERVICE_PCIE_ANOC 3 138 139 #define MASTER_A1NOC_SNOC 0 140 #define MASTER_A2NOC_SNOC 1 141 #define SLAVE_SNOC_GEM_NOC_SF 2 142 143 #endif 144